1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a7792 Clock Pulse Generator / Module Standby and Software Reset |
4 | * |
5 | * Copyright (C) 2017 Glider bvba |
6 | * |
7 | * Based on clk-rcar-gen2.c |
8 | * |
9 | * Copyright (C) 2013 Ideas On Board SPRL |
10 | */ |
11 | |
12 | #include <linux/device.h> |
13 | #include <linux/init.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/soc/renesas/rcar-rst.h> |
16 | |
17 | #include <dt-bindings/clock/r8a7792-cpg-mssr.h> |
18 | |
19 | #include "renesas-cpg-mssr.h" |
20 | #include "rcar-gen2-cpg.h" |
21 | |
22 | enum clk_ids { |
23 | /* Core Clock Outputs exported to DT */ |
24 | LAST_DT_CORE_CLK = R8A7792_CLK_OSC, |
25 | |
26 | /* External Input Clocks */ |
27 | CLK_EXTAL, |
28 | |
29 | /* Internal Core Clocks */ |
30 | CLK_MAIN, |
31 | CLK_PLL0, |
32 | CLK_PLL1, |
33 | CLK_PLL3, |
34 | CLK_PLL1_DIV2, |
35 | |
36 | /* Module Clocks */ |
37 | MOD_CLK_BASE |
38 | }; |
39 | |
40 | static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { |
41 | /* External Clock Inputs */ |
42 | DEF_INPUT("extal" , CLK_EXTAL), |
43 | |
44 | /* Internal Core Clocks */ |
45 | DEF_BASE(".main" , CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), |
46 | DEF_BASE(".pll0" , CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), |
47 | DEF_BASE(".pll1" , CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), |
48 | DEF_BASE(".pll3" , CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), |
49 | |
50 | DEF_FIXED(".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2, 1), |
51 | |
52 | /* Core Clock Outputs */ |
53 | DEF_BASE("qspi" , R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), |
54 | |
55 | DEF_FIXED("z" , R8A7792_CLK_Z, CLK_PLL0, 1, 1), |
56 | DEF_FIXED("zg" , R8A7792_CLK_ZG, CLK_PLL1, 5, 1), |
57 | DEF_FIXED("zx" , R8A7792_CLK_ZX, CLK_PLL1, 3, 1), |
58 | DEF_FIXED("zs" , R8A7792_CLK_ZS, CLK_PLL1, 6, 1), |
59 | DEF_FIXED("hp" , R8A7792_CLK_HP, CLK_PLL1, 12, 1), |
60 | DEF_FIXED("i" , R8A7792_CLK_I, CLK_PLL1, 3, 1), |
61 | DEF_FIXED("b" , R8A7792_CLK_B, CLK_PLL1, 12, 1), |
62 | DEF_FIXED("lb" , R8A7792_CLK_LB, CLK_PLL1, 24, 1), |
63 | DEF_FIXED("p" , R8A7792_CLK_P, CLK_PLL1, 24, 1), |
64 | DEF_FIXED("cl" , R8A7792_CLK_CL, CLK_PLL1, 48, 1), |
65 | DEF_FIXED("m2" , R8A7792_CLK_M2, CLK_PLL1, 8, 1), |
66 | DEF_FIXED("imp" , R8A7792_CLK_IMP, CLK_PLL1, 4, 1), |
67 | DEF_FIXED("zb3" , R8A7792_CLK_ZB3, CLK_PLL3, 4, 1), |
68 | DEF_FIXED("zb3d2" , R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1), |
69 | DEF_FIXED("ddr" , R8A7792_CLK_DDR, CLK_PLL3, 8, 1), |
70 | DEF_FIXED("sd" , R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1), |
71 | DEF_FIXED("mp" , R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1), |
72 | DEF_FIXED("cp" , R8A7792_CLK_CP, CLK_PLL1, 48, 1), |
73 | DEF_FIXED("cpex" , R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1), |
74 | DEF_FIXED("rcan" , R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1), |
75 | DEF_FIXED("r" , R8A7792_CLK_R, CLK_PLL1, 49152, 1), |
76 | DEF_FIXED("osc" , R8A7792_CLK_OSC, CLK_PLL1, 12288, 1), |
77 | }; |
78 | |
79 | static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { |
80 | DEF_MOD("msiof0" , 0, R8A7792_CLK_MP), |
81 | DEF_MOD("jpu" , 106, R8A7792_CLK_M2), |
82 | DEF_MOD("tmu1" , 111, R8A7792_CLK_P), |
83 | DEF_MOD("3dg" , 112, R8A7792_CLK_ZG), |
84 | DEF_MOD("2d-dmac" , 115, R8A7792_CLK_ZS), |
85 | DEF_MOD("tmu3" , 121, R8A7792_CLK_P), |
86 | DEF_MOD("tmu2" , 122, R8A7792_CLK_P), |
87 | DEF_MOD("cmt0" , 124, R8A7792_CLK_R), |
88 | DEF_MOD("tmu0" , 125, R8A7792_CLK_CP), |
89 | DEF_MOD("vsp1du1" , 127, R8A7792_CLK_ZS), |
90 | DEF_MOD("vsp1du0" , 128, R8A7792_CLK_ZS), |
91 | DEF_MOD("vsps" , 131, R8A7792_CLK_ZS), |
92 | DEF_MOD("msiof1" , 208, R8A7792_CLK_MP), |
93 | DEF_MOD("sys-dmac1" , 218, R8A7792_CLK_ZS), |
94 | DEF_MOD("sys-dmac0" , 219, R8A7792_CLK_ZS), |
95 | DEF_MOD("tpu0" , 304, R8A7792_CLK_CP), |
96 | DEF_MOD("sdhi0" , 314, R8A7792_CLK_SD), |
97 | DEF_MOD("cmt1" , 329, R8A7792_CLK_R), |
98 | DEF_MOD("rwdt" , 402, R8A7792_CLK_R), |
99 | DEF_MOD("irqc" , 407, R8A7792_CLK_CP), |
100 | DEF_MOD("intc-sys" , 408, R8A7792_CLK_ZS), |
101 | DEF_MOD("audio-dmac0" , 502, R8A7792_CLK_HP), |
102 | DEF_MOD("thermal" , 522, CLK_EXTAL), |
103 | DEF_MOD("pwm" , 523, R8A7792_CLK_P), |
104 | DEF_MOD("hscif1" , 716, R8A7792_CLK_ZS), |
105 | DEF_MOD("hscif0" , 717, R8A7792_CLK_ZS), |
106 | DEF_MOD("scif3" , 718, R8A7792_CLK_P), |
107 | DEF_MOD("scif2" , 719, R8A7792_CLK_P), |
108 | DEF_MOD("scif1" , 720, R8A7792_CLK_P), |
109 | DEF_MOD("scif0" , 721, R8A7792_CLK_P), |
110 | DEF_MOD("du1" , 723, R8A7792_CLK_ZX), |
111 | DEF_MOD("du0" , 724, R8A7792_CLK_ZX), |
112 | DEF_MOD("vin5" , 804, R8A7792_CLK_ZG), |
113 | DEF_MOD("vin4" , 805, R8A7792_CLK_ZG), |
114 | DEF_MOD("vin3" , 808, R8A7792_CLK_ZG), |
115 | DEF_MOD("vin2" , 809, R8A7792_CLK_ZG), |
116 | DEF_MOD("vin1" , 810, R8A7792_CLK_ZG), |
117 | DEF_MOD("vin0" , 811, R8A7792_CLK_ZG), |
118 | DEF_MOD("etheravb" , 812, R8A7792_CLK_HP), |
119 | DEF_MOD("imr-lx3" , 821, R8A7792_CLK_ZG), |
120 | DEF_MOD("imr-lsx3-1" , 822, R8A7792_CLK_ZG), |
121 | DEF_MOD("imr-lsx3-0" , 823, R8A7792_CLK_ZG), |
122 | DEF_MOD("imr-lsx3-5" , 825, R8A7792_CLK_ZG), |
123 | DEF_MOD("imr-lsx3-4" , 826, R8A7792_CLK_ZG), |
124 | DEF_MOD("imr-lsx3-3" , 827, R8A7792_CLK_ZG), |
125 | DEF_MOD("imr-lsx3-2" , 828, R8A7792_CLK_ZG), |
126 | DEF_MOD("gyro-adc" , 901, R8A7792_CLK_P), |
127 | DEF_MOD("gpio7" , 904, R8A7792_CLK_CP), |
128 | DEF_MOD("gpio6" , 905, R8A7792_CLK_CP), |
129 | DEF_MOD("gpio5" , 907, R8A7792_CLK_CP), |
130 | DEF_MOD("gpio4" , 908, R8A7792_CLK_CP), |
131 | DEF_MOD("gpio3" , 909, R8A7792_CLK_CP), |
132 | DEF_MOD("gpio2" , 910, R8A7792_CLK_CP), |
133 | DEF_MOD("gpio1" , 911, R8A7792_CLK_CP), |
134 | DEF_MOD("gpio0" , 912, R8A7792_CLK_CP), |
135 | DEF_MOD("gpio11" , 913, R8A7792_CLK_CP), |
136 | DEF_MOD("gpio10" , 914, R8A7792_CLK_CP), |
137 | DEF_MOD("can1" , 915, R8A7792_CLK_P), |
138 | DEF_MOD("can0" , 916, R8A7792_CLK_P), |
139 | DEF_MOD("qspi_mod" , 917, R8A7792_CLK_QSPI), |
140 | DEF_MOD("gpio9" , 919, R8A7792_CLK_CP), |
141 | DEF_MOD("gpio8" , 921, R8A7792_CLK_CP), |
142 | DEF_MOD("i2c5" , 925, R8A7792_CLK_HP), |
143 | DEF_MOD("iicdvfs" , 926, R8A7792_CLK_CP), |
144 | DEF_MOD("i2c4" , 927, R8A7792_CLK_HP), |
145 | DEF_MOD("i2c3" , 928, R8A7792_CLK_HP), |
146 | DEF_MOD("i2c2" , 929, R8A7792_CLK_HP), |
147 | DEF_MOD("i2c1" , 930, R8A7792_CLK_HP), |
148 | DEF_MOD("i2c0" , 931, R8A7792_CLK_HP), |
149 | DEF_MOD("ssi-all" , 1005, R8A7792_CLK_P), |
150 | DEF_MOD("ssi4" , 1011, MOD_CLK_ID(1005)), |
151 | DEF_MOD("ssi3" , 1012, MOD_CLK_ID(1005)), |
152 | }; |
153 | |
154 | static const unsigned int r8a7792_crit_mod_clks[] __initconst = { |
155 | MOD_CLK_ID(402), /* RWDT */ |
156 | MOD_CLK_ID(408), /* INTC-SYS (GIC) */ |
157 | }; |
158 | |
159 | /* |
160 | * CPG Clock Data |
161 | */ |
162 | |
163 | /* |
164 | * MD EXTAL PLL0 PLL1 PLL3 |
165 | * 14 13 19 (MHz) *1 *2 |
166 | *--------------------------------------------------- |
167 | * 0 0 0 15 x200/3 x208/2 x106 |
168 | * 0 0 1 15 x200/3 x208/2 x88 |
169 | * 0 1 0 20 x150/3 x156/2 x80 |
170 | * 0 1 1 20 x150/3 x156/2 x66 |
171 | * 1 0 0 26 / 2 x230/3 x240/2 x122 |
172 | * 1 0 1 26 / 2 x230/3 x240/2 x102 |
173 | * 1 1 0 30 / 2 x200/3 x208/2 x106 |
174 | * 1 1 1 30 / 2 x200/3 x208/2 x88 |
175 | * |
176 | * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3) |
177 | * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2) |
178 | */ |
179 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ |
180 | (((md) & BIT(13)) >> 12) | \ |
181 | (((md) & BIT(19)) >> 19)) |
182 | static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { |
183 | { 1, 208, 106, 200 }, |
184 | { 1, 208, 88, 200 }, |
185 | { 1, 156, 80, 150 }, |
186 | { 1, 156, 66, 150 }, |
187 | { 2, 240, 122, 230 }, |
188 | { 2, 240, 102, 230 }, |
189 | { 2, 208, 106, 200 }, |
190 | { 2, 208, 88, 200 }, |
191 | }; |
192 | |
193 | static int __init r8a7792_cpg_mssr_init(struct device *dev) |
194 | { |
195 | const struct rcar_gen2_cpg_pll_config *cpg_pll_config; |
196 | u32 cpg_mode; |
197 | int error; |
198 | |
199 | error = rcar_rst_read_mode_pins(mode: &cpg_mode); |
200 | if (error) |
201 | return error; |
202 | |
203 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
204 | |
205 | return rcar_gen2_cpg_init(config: cpg_pll_config, pll0_div: 3, mode: cpg_mode); |
206 | } |
207 | |
208 | const struct cpg_mssr_info r8a7792_cpg_mssr_info __initconst = { |
209 | /* Core Clocks */ |
210 | .core_clks = r8a7792_core_clks, |
211 | .num_core_clks = ARRAY_SIZE(r8a7792_core_clks), |
212 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
213 | .num_total_core_clks = MOD_CLK_BASE, |
214 | |
215 | /* Module Clocks */ |
216 | .mod_clks = r8a7792_mod_clks, |
217 | .num_mod_clks = ARRAY_SIZE(r8a7792_mod_clks), |
218 | .num_hw_mod_clks = 12 * 32, |
219 | |
220 | /* Critical Module Clocks */ |
221 | .crit_mod_clks = r8a7792_crit_mod_clks, |
222 | .num_crit_mod_clks = ARRAY_SIZE(r8a7792_crit_mod_clks), |
223 | |
224 | /* Callbacks */ |
225 | .init = r8a7792_cpg_mssr_init, |
226 | .cpg_clk_register = rcar_gen2_cpg_clk_register, |
227 | }; |
228 | |