1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (c) 2021 Rockchip Electronics Co., Ltd. |
4 | * Copyright (c) 2022 Collabora Ltd. |
5 | * Author: Sebastian Reichel <sebastian.reichel@collabora.com> |
6 | */ |
7 | |
8 | #include <linux/module.h> |
9 | #include <linux/of.h> |
10 | #include <dt-bindings/reset/rockchip,rk3588-cru.h> |
11 | #include "clk.h" |
12 | |
13 | /* 0xFD7C0000 + 0x0A00 */ |
14 | #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) |
15 | |
16 | /* 0xFD7C8000 + 0x0A00 */ |
17 | #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) |
18 | |
19 | /* 0xFD7D0000 + 0x0A00 */ |
20 | #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) |
21 | |
22 | /* 0xFD7F0000 + 0x0A00 */ |
23 | #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) |
24 | |
25 | /* mapping table for reset ID to register offset */ |
26 | static const int rk3588_register_offset[] = { |
27 | /* SOFTRST_CON01 */ |
28 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), |
29 | RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), |
30 | RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), |
31 | RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM |
32 | RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), |
33 | RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM |
34 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), |
35 | |
36 | /* SOFTRST_CON02 */ |
37 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), |
38 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), |
39 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), |
40 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), |
41 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), |
42 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), |
43 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), |
44 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), |
45 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), |
46 | |
47 | /* SOFTRST_CON03 */ |
48 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), |
49 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), |
50 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), |
51 | RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM |
52 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), |
53 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), |
54 | |
55 | /* SOFTRST_CON04 */ |
56 | RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM |
57 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), |
58 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), |
59 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), |
60 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), |
61 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), |
62 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), |
63 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), |
64 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), |
65 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), |
66 | |
67 | /* SOFTRST_CON05 */ |
68 | RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), |
69 | RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), |
70 | RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), |
71 | RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), |
72 | RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), |
73 | |
74 | /* SOFTRST_CON06 */ |
75 | RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), |
76 | RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), |
77 | |
78 | /* SOFTRST_CON07 */ |
79 | RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), |
80 | RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), |
81 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), |
82 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), |
83 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), |
84 | RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), |
85 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), |
86 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), |
87 | |
88 | /* SOFTRST_CON08 */ |
89 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), |
90 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), |
91 | RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), |
92 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), |
93 | |
94 | /* SOFTRST_CON09 */ |
95 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), |
96 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), |
97 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), |
98 | RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), |
99 | RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), |
100 | |
101 | /* SOFTRST_CON10 */ |
102 | RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), |
103 | RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), |
104 | RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), |
105 | RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), |
106 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), |
107 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), |
108 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), |
109 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), |
110 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), |
111 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), |
112 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), |
113 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), |
114 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), |
115 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), |
116 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), |
117 | |
118 | /* SOFTRST_CON11 */ |
119 | RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), |
120 | RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), |
121 | RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), |
122 | RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), |
123 | RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), |
124 | RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), |
125 | RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), |
126 | RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), |
127 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), |
128 | RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), |
129 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), |
130 | RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), |
131 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), |
132 | RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), |
133 | RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), |
134 | |
135 | /* SOFTRST_CON12 */ |
136 | RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), |
137 | RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), |
138 | RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), |
139 | RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), |
140 | RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), |
141 | RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), |
142 | RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), |
143 | RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), |
144 | RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), |
145 | RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), |
146 | RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), |
147 | RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), |
148 | |
149 | /* SOFTRST_CON13 */ |
150 | RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), |
151 | RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), |
152 | RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), |
153 | RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), |
154 | RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), |
155 | RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), |
156 | |
157 | /* SOFTRST_CON14 */ |
158 | RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), |
159 | RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), |
160 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), |
161 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), |
162 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), |
163 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), |
164 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), |
165 | RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), |
166 | RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), |
167 | RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), |
168 | RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), |
169 | RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), |
170 | |
171 | /* SOFTRST_CON15 */ |
172 | RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), |
173 | RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), |
174 | RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), |
175 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), |
176 | RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), |
177 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), |
178 | RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), |
179 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), |
180 | RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), |
181 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), |
182 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), |
183 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), |
184 | |
185 | /* SOFTRST_CON16 */ |
186 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), |
187 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), |
188 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), |
189 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), |
190 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), |
191 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), |
192 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), |
193 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), |
194 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), |
195 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), |
196 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), |
197 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), |
198 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), |
199 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), |
200 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), |
201 | RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), |
202 | |
203 | /* SOFTRST_CON17 */ |
204 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), |
205 | RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), |
206 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), |
207 | RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), |
208 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), |
209 | RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), |
210 | RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), |
211 | RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), |
212 | RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), |
213 | RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), |
214 | RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), |
215 | RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), |
216 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), |
217 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), |
218 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), |
219 | |
220 | /* SOFTRST_CON18 */ |
221 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), |
222 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), |
223 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), |
224 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), |
225 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), |
226 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), |
227 | RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), |
228 | RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), |
229 | RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), |
230 | RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), |
231 | |
232 | /* SOFTRST_CON19 */ |
233 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), |
234 | RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), |
235 | RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), |
236 | |
237 | /* SOFTRST_CON20 */ |
238 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), |
239 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), |
240 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), |
241 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), |
242 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), |
243 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), |
244 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), |
245 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), |
246 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), |
247 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), |
248 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), |
249 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), |
250 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), |
251 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), |
252 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), |
253 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), |
254 | |
255 | /* SOFTRST_CON21 */ |
256 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), |
257 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), |
258 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), |
259 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), |
260 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), |
261 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), |
262 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), |
263 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), |
264 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), |
265 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), |
266 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), |
267 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), |
268 | |
269 | /* SOFTRST_CON22 */ |
270 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), |
271 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), |
272 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), |
273 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), |
274 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), |
275 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), |
276 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), |
277 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), |
278 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), |
279 | |
280 | /* SOFTRST_CON23 */ |
281 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), |
282 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), |
283 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), |
284 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), |
285 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), |
286 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), |
287 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), |
288 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), |
289 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), |
290 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), |
291 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), |
292 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), |
293 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), |
294 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), |
295 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), |
296 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), |
297 | |
298 | /* SOFTRST_CON24 */ |
299 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), |
300 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), |
301 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), |
302 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), |
303 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), |
304 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), |
305 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), |
306 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), |
307 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), |
308 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), |
309 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), |
310 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), |
311 | |
312 | /* SOFTRST_CON25 */ |
313 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), |
314 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), |
315 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), |
316 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), |
317 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), |
318 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), |
319 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), |
320 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), |
321 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), |
322 | |
323 | /* SOFTRST_CON26 */ |
324 | RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), |
325 | RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), |
326 | RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), |
327 | RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), |
328 | |
329 | /* SOFTRST_CON27 */ |
330 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), |
331 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), |
332 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), |
333 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), |
334 | |
335 | /* SOFTRST_CON28 */ |
336 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), |
337 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), |
338 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), |
339 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), |
340 | |
341 | /* SOFTRST_CON29 */ |
342 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), |
343 | RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), |
344 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), |
345 | RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), |
346 | RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), |
347 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), |
348 | RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), |
349 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), |
350 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), |
351 | RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), |
352 | |
353 | /* SOFTRST_CON30 */ |
354 | RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), |
355 | RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), |
356 | RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), |
357 | RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), |
358 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), |
359 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), |
360 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), |
361 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), |
362 | |
363 | /* SOFTRST_CON31 */ |
364 | RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), |
365 | RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), |
366 | RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), |
367 | RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), |
368 | RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), |
369 | RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), |
370 | RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), |
371 | RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), |
372 | RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), |
373 | RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), |
374 | |
375 | /* SOFTRST_CON32 */ |
376 | RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), |
377 | RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), |
378 | RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), |
379 | RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), |
380 | RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), |
381 | RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), |
382 | RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), |
383 | RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), |
384 | RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), |
385 | RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), |
386 | RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), |
387 | |
388 | /* SOFTRST_CON33 */ |
389 | RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), |
390 | RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), |
391 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), |
392 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), |
393 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), |
394 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), |
395 | |
396 | /* SOFTRST_CON34 */ |
397 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), |
398 | RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), |
399 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), |
400 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), |
401 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), |
402 | |
403 | /* SOFTRST_CON35 */ |
404 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), |
405 | |
406 | /* SOFTRST_CON37 */ |
407 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), |
408 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), |
409 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), |
410 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), |
411 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), |
412 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), |
413 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), |
414 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), |
415 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), |
416 | RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), |
417 | RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), |
418 | RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), |
419 | |
420 | /* SOFTRST_CON40 */ |
421 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), |
422 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), |
423 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), |
424 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), |
425 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), |
426 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), |
427 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), |
428 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), |
429 | |
430 | /* SOFTRST_CON41 */ |
431 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), |
432 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), |
433 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), |
434 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), |
435 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), |
436 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), |
437 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), |
438 | |
439 | /* SOFTRST_CON42 */ |
440 | RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), |
441 | RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), |
442 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), |
443 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), |
444 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), |
445 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), |
446 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), |
447 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), |
448 | RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), |
449 | RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), |
450 | |
451 | /* SOFTRST_CON43 */ |
452 | RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), |
453 | RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), |
454 | RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), |
455 | |
456 | /* SOFTRST_CON44 */ |
457 | RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), |
458 | RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), |
459 | RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), |
460 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), |
461 | RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), |
462 | RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), |
463 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), |
464 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), |
465 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), |
466 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), |
467 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), |
468 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), |
469 | |
470 | /* SOFTRST_CON45 */ |
471 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), |
472 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), |
473 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), |
474 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), |
475 | RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), |
476 | RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), |
477 | RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), |
478 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), |
479 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), |
480 | RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), |
481 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), |
482 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), |
483 | RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), |
484 | |
485 | /* SOFTRST_CON47 */ |
486 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), |
487 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), |
488 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), |
489 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), |
490 | RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), |
491 | |
492 | /* SOFTRST_CON48 */ |
493 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), |
494 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), |
495 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), |
496 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), |
497 | RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), |
498 | |
499 | /* SOFTRST_CON49 */ |
500 | RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), |
501 | RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), |
502 | RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), |
503 | RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), |
504 | RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), |
505 | RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), |
506 | RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), |
507 | RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), |
508 | |
509 | /* SOFTRST_CON50 */ |
510 | RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), |
511 | RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), |
512 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), |
513 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), |
514 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), |
515 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), |
516 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), |
517 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), |
518 | |
519 | /* SOFTRST_CON51 */ |
520 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), |
521 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), |
522 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), |
523 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), |
524 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), |
525 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), |
526 | RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), |
527 | |
528 | /* SOFTRST_CON52 */ |
529 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), |
530 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), |
531 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), |
532 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), |
533 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), |
534 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), |
535 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), |
536 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), |
537 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), |
538 | |
539 | /* SOFTRST_CON53 */ |
540 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), |
541 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), |
542 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), |
543 | RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), |
544 | RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), |
545 | RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), |
546 | RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), |
547 | RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), |
548 | RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), |
549 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), |
550 | |
551 | /* SOFTRST_CON55 */ |
552 | RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), |
553 | RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), |
554 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), |
555 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), |
556 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), |
557 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), |
558 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), |
559 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), |
560 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), |
561 | RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), |
562 | |
563 | /* SOFTRST_CON56 */ |
564 | RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), |
565 | RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), |
566 | RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), |
567 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), |
568 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), |
569 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), |
570 | |
571 | /* SOFTRST_CON57 */ |
572 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), |
573 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), |
574 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), |
575 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), |
576 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), |
577 | |
578 | /* SOFTRST_CON59 */ |
579 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), |
580 | RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), |
581 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), |
582 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), |
583 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), |
584 | RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), |
585 | RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), |
586 | |
587 | /* SOFTRST_CON60 */ |
588 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), |
589 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), |
590 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), |
591 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), |
592 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), |
593 | RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), |
594 | RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), |
595 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), |
596 | |
597 | /* SOFTRST_CON61 */ |
598 | RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), |
599 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), |
600 | RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), |
601 | RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), |
602 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), |
603 | RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), |
604 | |
605 | /* SOFTRST_CON62 */ |
606 | RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), |
607 | RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), |
608 | RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), |
609 | RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), |
610 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), |
611 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), |
612 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), |
613 | |
614 | /* SOFTRST_CON63 */ |
615 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), |
616 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), |
617 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), |
618 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), |
619 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), |
620 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), |
621 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), |
622 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), |
623 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), |
624 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), |
625 | |
626 | /* SOFTRST_CON64 */ |
627 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), |
628 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), |
629 | RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), |
630 | RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), |
631 | RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), |
632 | RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), |
633 | |
634 | /* SOFTRST_CON65 */ |
635 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), |
636 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), |
637 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), |
638 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), |
639 | RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), |
640 | |
641 | /* SOFTRST_CON66 */ |
642 | RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), |
643 | RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), |
644 | RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), |
645 | RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), |
646 | RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), |
647 | RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), |
648 | RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), |
649 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), |
650 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), |
651 | |
652 | /* SOFTRST_CON67 */ |
653 | RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), |
654 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), |
655 | RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), |
656 | RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), |
657 | |
658 | /* SOFTRST_CON68 */ |
659 | RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), |
660 | RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), |
661 | RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), |
662 | RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), |
663 | |
664 | /* SOFTRST_CON69 */ |
665 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), |
666 | RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), |
667 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), |
668 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), |
669 | RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), |
670 | RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), |
671 | RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), |
672 | RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), |
673 | RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), |
674 | |
675 | /* SOFTRST_CON70 */ |
676 | RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), |
677 | RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), |
678 | RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), |
679 | RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), |
680 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), |
681 | RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), |
682 | RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), |
683 | RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), |
684 | RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), |
685 | RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), |
686 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), |
687 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), |
688 | |
689 | /* SOFTRST_CON72 */ |
690 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), |
691 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), |
692 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), |
693 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), |
694 | RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), |
695 | RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), |
696 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), |
697 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), |
698 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), |
699 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), |
700 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), |
701 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM |
702 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM |
703 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM |
704 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM |
705 | |
706 | /* SOFTRST_CON73 */ |
707 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM |
708 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM |
709 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM |
710 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM |
711 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM |
712 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM |
713 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM |
714 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM |
715 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM |
716 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM |
717 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM |
718 | RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), |
719 | RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), |
720 | |
721 | /* SOFTRST_CON74 */ |
722 | RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), |
723 | RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), |
724 | |
725 | /* SOFTRST_CON75 */ |
726 | RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), |
727 | RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), |
728 | RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), |
729 | |
730 | /* SOFTRST_CON76 */ |
731 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), |
732 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), |
733 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), |
734 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), |
735 | RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), |
736 | |
737 | /* SOFTRST_CON77 */ |
738 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), |
739 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), |
740 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), |
741 | |
742 | /* PHPTOPCRU_SOFTRST_CON00 */ |
743 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), |
744 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), |
745 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), |
746 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), |
747 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), |
748 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), |
749 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), |
750 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), |
751 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), |
752 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), |
753 | |
754 | /* PMU1CRU_SOFTRST_CON00 */ |
755 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), |
756 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), |
757 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), |
758 | RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), |
759 | RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), |
760 | |
761 | /* PMU1CRU_SOFTRST_CON01 */ |
762 | RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), |
763 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), |
764 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), |
765 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), |
766 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), |
767 | RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), |
768 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), |
769 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), |
770 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), |
771 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), |
772 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), |
773 | |
774 | /* PMU1CRU_SOFTRST_CON02 */ |
775 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), |
776 | RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), |
777 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), |
778 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), |
779 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), |
780 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), |
781 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), |
782 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), |
783 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), |
784 | |
785 | /* PMU1CRU_SOFTRST_CON03 */ |
786 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), |
787 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), |
788 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), |
789 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), |
790 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), |
791 | |
792 | /* PMU1CRU_SOFTRST_CON04 */ |
793 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), |
794 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), |
795 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), |
796 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), |
797 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), |
798 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), |
799 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), |
800 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), |
801 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), |
802 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), |
803 | |
804 | /* PMU1CRU_SOFTRST_CON05 */ |
805 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), |
806 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), |
807 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), |
808 | RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), |
809 | |
810 | /* SECURECRU_SOFTRST_CON00 */ |
811 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), |
812 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), |
813 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), |
814 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), |
815 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), |
816 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), |
817 | |
818 | /* SECURECRU_SOFTRST_CON01 */ |
819 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), |
820 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), |
821 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), |
822 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), |
823 | RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), |
824 | RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), |
825 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), |
826 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), |
827 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), |
828 | RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), |
829 | RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), |
830 | |
831 | /* SECURECRU_SOFTRST_CON02 */ |
832 | RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), |
833 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), |
834 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), |
835 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), |
836 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), |
837 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), |
838 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), |
839 | |
840 | /* SECURECRU_SOFTRST_CON03 */ |
841 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), |
842 | RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), |
843 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), |
844 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), |
845 | RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), |
846 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), |
847 | RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), |
848 | }; |
849 | |
850 | void rk3588_rst_init(struct device_node *np, void __iomem *reg_base) |
851 | { |
852 | rockchip_register_softrst_lut(np, |
853 | lookup_table: rk3588_register_offset, |
854 | ARRAY_SIZE(rk3588_register_offset), |
855 | base: reg_base + RK3588_SOFTRST_CON(0), |
856 | ROCKCHIP_SOFTRST_HIWORD_MASK); |
857 | } |
858 | |