| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _CCU_SUN50I_A100_H_ |
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| 7 | #define _CCU_SUN50I_A100_H_ |
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| 8 | |
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| 9 | #include <dt-bindings/clock/sun50i-a100-ccu.h> |
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| 10 | #include <dt-bindings/reset/sun50i-a100-ccu.h> |
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| 11 | |
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| 12 | #define CLK_OSC12M 0 |
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| 13 | #define CLK_PLL_CPUX 1 |
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| 14 | #define CLK_PLL_DDR0 2 |
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| 15 | |
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| 16 | /* PLL_PERIPH0 exported for PRCM */ |
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| 17 | |
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| 18 | #define CLK_PLL_PERIPH0_2X 4 |
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| 19 | #define CLK_PLL_PERIPH1 5 |
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| 20 | #define CLK_PLL_PERIPH1_2X 6 |
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| 21 | #define CLK_PLL_GPU 7 |
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| 22 | #define CLK_PLL_VIDEO0 8 |
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| 23 | #define CLK_PLL_VIDEO0_2X 9 |
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| 24 | #define CLK_PLL_VIDEO0_4X 10 |
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| 25 | #define CLK_PLL_VIDEO1 11 |
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| 26 | #define CLK_PLL_VIDEO1_2X 12 |
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| 27 | #define CLK_PLL_VIDEO1_4X 13 |
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| 28 | #define CLK_PLL_VIDEO2 14 |
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| 29 | #define CLK_PLL_VIDEO2_2X 15 |
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| 30 | #define CLK_PLL_VIDEO2_4X 16 |
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| 31 | #define CLK_PLL_VIDEO3 17 |
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| 32 | #define CLK_PLL_VIDEO3_2X 18 |
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| 33 | #define CLK_PLL_VIDEO3_4X 19 |
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| 34 | #define CLK_PLL_VE 20 |
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| 35 | #define CLK_PLL_COM 21 |
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| 36 | #define CLK_PLL_COM_AUDIO 22 |
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| 37 | #define CLK_PLL_AUDIO 23 |
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| 38 | |
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| 39 | /* CPUX clock exported for DVFS */ |
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| 40 | |
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| 41 | #define CLK_AXI 25 |
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| 42 | #define CLK_CPUX_APB 26 |
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| 43 | #define CLK_PSI_AHB1_AHB2 27 |
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| 44 | #define CLK_AHB3 28 |
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| 45 | |
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| 46 | /* APB1 clock exported for PIO */ |
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| 47 | |
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| 48 | #define CLK_APB2 30 |
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| 49 | |
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| 50 | /* All module clocks and bus gates are exported except DRAM */ |
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| 51 | |
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| 52 | #define CLK_BUS_DRAM 58 |
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| 53 | |
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| 54 | #define CLK_NUMBER (CLK_CSI_ISP + 1) |
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| 55 | |
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| 56 | #endif /* _CCU_SUN50I_A100_H_ */ |
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| 57 | |
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