1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Reset controller portions for the U8500 PRCC |
4 | * Copyright (C) 2021 Linus Walleij <linus.walleij@linaro.org> |
5 | */ |
6 | #include <linux/of.h> |
7 | #include <linux/of_address.h> |
8 | #include <linux/slab.h> |
9 | #include <linux/io.h> |
10 | #include <linux/err.h> |
11 | #include <linux/types.h> |
12 | #include <linux/reset-controller.h> |
13 | #include <linux/bits.h> |
14 | #include <linux/delay.h> |
15 | |
16 | #include "prcc.h" |
17 | #include "reset-prcc.h" |
18 | |
19 | #define to_u8500_prcc_reset(p) container_of((p), struct u8500_prcc_reset, rcdev) |
20 | |
21 | /* This macro flattens the 2-dimensional PRCC numberspace */ |
22 | #define PRCC_RESET_LINE(prcc_num, bit) \ |
23 | (((prcc_num) * PRCC_PERIPHS_PER_CLUSTER) + (bit)) |
24 | |
25 | /* |
26 | * Reset registers in each PRCC - the reset lines are active low |
27 | * so what you need to do is write a bit for the peripheral you |
28 | * want to put into reset into the CLEAR register, this will assert |
29 | * the reset by pulling the line low. SET take the device out of |
30 | * reset. The status reflects the actual state of the line. |
31 | */ |
32 | #define PRCC_K_SOFTRST_SET 0x018 |
33 | #define PRCC_K_SOFTRST_CLEAR 0x01c |
34 | #define PRCC_K_RST_STATUS 0x020 |
35 | |
36 | static int prcc_num_to_index(unsigned int num) |
37 | { |
38 | switch (num) { |
39 | case 1: |
40 | return CLKRST1_INDEX; |
41 | case 2: |
42 | return CLKRST2_INDEX; |
43 | case 3: |
44 | return CLKRST3_INDEX; |
45 | case 5: |
46 | return CLKRST5_INDEX; |
47 | case 6: |
48 | return CLKRST6_INDEX; |
49 | } |
50 | return -EINVAL; |
51 | } |
52 | |
53 | static void __iomem *u8500_prcc_reset_base(struct u8500_prcc_reset *ur, |
54 | unsigned long id) |
55 | { |
56 | unsigned int prcc_num, index; |
57 | |
58 | prcc_num = id / PRCC_PERIPHS_PER_CLUSTER; |
59 | index = prcc_num_to_index(num: prcc_num); |
60 | |
61 | if (index >= ARRAY_SIZE(ur->base)) |
62 | return NULL; |
63 | |
64 | return ur->base[index]; |
65 | } |
66 | |
67 | static int u8500_prcc_reset(struct reset_controller_dev *rcdev, |
68 | unsigned long id) |
69 | { |
70 | struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
71 | void __iomem *base = u8500_prcc_reset_base(ur, id); |
72 | unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
73 | |
74 | pr_debug("PRCC cycle reset id %lu, bit %u\n" , id, bit); |
75 | |
76 | /* |
77 | * Assert reset and then release it. The one microsecond |
78 | * delay is found in the vendor reference code. |
79 | */ |
80 | writel(BIT(bit), addr: base + PRCC_K_SOFTRST_CLEAR); |
81 | udelay(1); |
82 | writel(BIT(bit), addr: base + PRCC_K_SOFTRST_SET); |
83 | udelay(1); |
84 | |
85 | return 0; |
86 | } |
87 | |
88 | static int u8500_prcc_reset_assert(struct reset_controller_dev *rcdev, |
89 | unsigned long id) |
90 | { |
91 | struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
92 | void __iomem *base = u8500_prcc_reset_base(ur, id); |
93 | unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
94 | |
95 | pr_debug("PRCC assert reset id %lu, bit %u\n" , id, bit); |
96 | writel(BIT(bit), addr: base + PRCC_K_SOFTRST_CLEAR); |
97 | |
98 | return 0; |
99 | } |
100 | |
101 | static int u8500_prcc_reset_deassert(struct reset_controller_dev *rcdev, |
102 | unsigned long id) |
103 | { |
104 | struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
105 | void __iomem *base = u8500_prcc_reset_base(ur, id); |
106 | unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
107 | |
108 | pr_debug("PRCC deassert reset id %lu, bit %u\n" , id, bit); |
109 | writel(BIT(bit), addr: base + PRCC_K_SOFTRST_SET); |
110 | |
111 | return 0; |
112 | } |
113 | |
114 | static int u8500_prcc_reset_status(struct reset_controller_dev *rcdev, |
115 | unsigned long id) |
116 | { |
117 | struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev); |
118 | void __iomem *base = u8500_prcc_reset_base(ur, id); |
119 | unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER; |
120 | u32 val; |
121 | |
122 | pr_debug("PRCC check status on reset line id %lu, bit %u\n" , id, bit); |
123 | val = readl(addr: base + PRCC_K_RST_STATUS); |
124 | |
125 | /* Active low so return the inverse value of the bit */ |
126 | return !(val & BIT(bit)); |
127 | } |
128 | |
129 | static const struct reset_control_ops u8500_prcc_reset_ops = { |
130 | .reset = u8500_prcc_reset, |
131 | .assert = u8500_prcc_reset_assert, |
132 | .deassert = u8500_prcc_reset_deassert, |
133 | .status = u8500_prcc_reset_status, |
134 | }; |
135 | |
136 | static int u8500_prcc_reset_xlate(struct reset_controller_dev *rcdev, |
137 | const struct of_phandle_args *reset_spec) |
138 | { |
139 | unsigned int prcc_num, bit; |
140 | |
141 | if (reset_spec->args_count != 2) |
142 | return -EINVAL; |
143 | |
144 | prcc_num = reset_spec->args[0]; |
145 | bit = reset_spec->args[1]; |
146 | |
147 | if (prcc_num != 1 && prcc_num != 2 && prcc_num != 3 && |
148 | prcc_num != 5 && prcc_num != 6) { |
149 | pr_err("%s: invalid PRCC %d\n" , __func__, prcc_num); |
150 | return -EINVAL; |
151 | } |
152 | |
153 | pr_debug("located reset line %d at PRCC %d bit %d\n" , |
154 | PRCC_RESET_LINE(prcc_num, bit), prcc_num, bit); |
155 | |
156 | return PRCC_RESET_LINE(prcc_num, bit); |
157 | } |
158 | |
159 | void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur) |
160 | { |
161 | struct reset_controller_dev *rcdev = &ur->rcdev; |
162 | int ret; |
163 | int i; |
164 | |
165 | for (i = 0; i < CLKRST_MAX; i++) { |
166 | ur->base[i] = ioremap(offset: ur->phy_base[i], size: SZ_4K); |
167 | if (!ur->base[i]) |
168 | pr_err("PRCC failed to remap for reset base %d (%08x)\n" , |
169 | i, ur->phy_base[i]); |
170 | } |
171 | |
172 | rcdev->owner = THIS_MODULE; |
173 | rcdev->ops = &u8500_prcc_reset_ops; |
174 | rcdev->of_node = np; |
175 | rcdev->of_reset_n_cells = 2; |
176 | rcdev->of_xlate = u8500_prcc_reset_xlate; |
177 | |
178 | ret = reset_controller_register(rcdev); |
179 | if (ret) |
180 | pr_err("PRCC failed to register reset controller\n" ); |
181 | } |
182 | |