1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - TMU
4 *
5 * Copyright (C) 2009 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pm_domain.h>
22#include <linux/pm_runtime.h>
23#include <linux/sh_timer.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26
27enum sh_tmu_model {
28 SH_TMU,
29 SH_TMU_SH3,
30};
31
32struct sh_tmu_device;
33
34struct sh_tmu_channel {
35 struct sh_tmu_device *tmu;
36 unsigned int index;
37
38 void __iomem *base;
39 int irq;
40
41 unsigned long periodic;
42 struct clock_event_device ced;
43 struct clocksource cs;
44 bool cs_enabled;
45 unsigned int enable_count;
46};
47
48struct sh_tmu_device {
49 struct platform_device *pdev;
50
51 void __iomem *mapbase;
52 struct clk *clk;
53 unsigned long rate;
54
55 enum sh_tmu_model model;
56
57 raw_spinlock_t lock; /* Protect the shared start/stop register */
58
59 struct sh_tmu_channel *channels;
60 unsigned int num_channels;
61
62 bool has_clockevent;
63 bool has_clocksource;
64};
65
66#define TSTR -1 /* shared register */
67#define TCOR 0 /* channel register */
68#define TCNT 1 /* channel register */
69#define TCR 2 /* channel register */
70
71#define TCR_UNF (1 << 8)
72#define TCR_UNIE (1 << 5)
73#define TCR_TPSC_CLK4 (0 << 0)
74#define TCR_TPSC_CLK16 (1 << 0)
75#define TCR_TPSC_CLK64 (2 << 0)
76#define TCR_TPSC_CLK256 (3 << 0)
77#define TCR_TPSC_CLK1024 (4 << 0)
78#define TCR_TPSC_MASK (7 << 0)
79
80static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
81{
82 unsigned long offs;
83
84 if (reg_nr == TSTR) {
85 switch (ch->tmu->model) {
86 case SH_TMU_SH3:
87 return ioread8(ch->tmu->mapbase + 2);
88 case SH_TMU:
89 return ioread8(ch->tmu->mapbase + 4);
90 }
91 }
92
93 offs = reg_nr << 2;
94
95 if (reg_nr == TCR)
96 return ioread16(ch->base + offs);
97 else
98 return ioread32(ch->base + offs);
99}
100
101static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
102 unsigned long value)
103{
104 unsigned long offs;
105
106 if (reg_nr == TSTR) {
107 switch (ch->tmu->model) {
108 case SH_TMU_SH3:
109 return iowrite8(value, ch->tmu->mapbase + 2);
110 case SH_TMU:
111 return iowrite8(value, ch->tmu->mapbase + 4);
112 }
113 }
114
115 offs = reg_nr << 2;
116
117 if (reg_nr == TCR)
118 iowrite16(value, ch->base + offs);
119 else
120 iowrite32(value, ch->base + offs);
121}
122
123static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
124{
125 unsigned long flags, value;
126
127 /* start stop register shared by multiple timer channels */
128 raw_spin_lock_irqsave(&ch->tmu->lock, flags);
129 value = sh_tmu_read(ch, TSTR);
130
131 if (start)
132 value |= 1 << ch->index;
133 else
134 value &= ~(1 << ch->index);
135
136 sh_tmu_write(ch, TSTR, value);
137 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
138}
139
140static int __sh_tmu_enable(struct sh_tmu_channel *ch)
141{
142 int ret;
143
144 /* enable clock */
145 ret = clk_enable(ch->tmu->clk);
146 if (ret) {
147 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
148 ch->index);
149 return ret;
150 }
151
152 /* make sure channel is disabled */
153 sh_tmu_start_stop_ch(ch, 0);
154
155 /* maximum timeout */
156 sh_tmu_write(ch, TCOR, 0xffffffff);
157 sh_tmu_write(ch, TCNT, 0xffffffff);
158
159 /* configure channel to parent clock / 4, irq off */
160 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
161
162 /* enable channel */
163 sh_tmu_start_stop_ch(ch, 1);
164
165 return 0;
166}
167
168static int sh_tmu_enable(struct sh_tmu_channel *ch)
169{
170 if (ch->enable_count++ > 0)
171 return 0;
172
173 pm_runtime_get_sync(&ch->tmu->pdev->dev);
174 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
175
176 return __sh_tmu_enable(ch);
177}
178
179static void __sh_tmu_disable(struct sh_tmu_channel *ch)
180{
181 /* disable channel */
182 sh_tmu_start_stop_ch(ch, 0);
183
184 /* disable interrupts in TMU block */
185 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
186
187 /* stop clock */
188 clk_disable(ch->tmu->clk);
189}
190
191static void sh_tmu_disable(struct sh_tmu_channel *ch)
192{
193 if (WARN_ON(ch->enable_count == 0))
194 return;
195
196 if (--ch->enable_count > 0)
197 return;
198
199 __sh_tmu_disable(ch);
200
201 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
202 pm_runtime_put(&ch->tmu->pdev->dev);
203}
204
205static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
206 int periodic)
207{
208 /* stop timer */
209 sh_tmu_start_stop_ch(ch, 0);
210
211 /* acknowledge interrupt */
212 sh_tmu_read(ch, TCR);
213
214 /* enable interrupt */
215 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
216
217 /* reload delta value in case of periodic timer */
218 if (periodic)
219 sh_tmu_write(ch, TCOR, delta);
220 else
221 sh_tmu_write(ch, TCOR, 0xffffffff);
222
223 sh_tmu_write(ch, TCNT, delta);
224
225 /* start timer */
226 sh_tmu_start_stop_ch(ch, 1);
227}
228
229static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
230{
231 struct sh_tmu_channel *ch = dev_id;
232
233 /* disable or acknowledge interrupt */
234 if (clockevent_state_oneshot(&ch->ced))
235 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
236 else
237 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
238
239 /* notify clockevent layer */
240 ch->ced.event_handler(&ch->ced);
241 return IRQ_HANDLED;
242}
243
244static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
245{
246 return container_of(cs, struct sh_tmu_channel, cs);
247}
248
249static u64 sh_tmu_clocksource_read(struct clocksource *cs)
250{
251 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
252
253 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
254}
255
256static int sh_tmu_clocksource_enable(struct clocksource *cs)
257{
258 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
259 int ret;
260
261 if (WARN_ON(ch->cs_enabled))
262 return 0;
263
264 ret = sh_tmu_enable(ch);
265 if (!ret)
266 ch->cs_enabled = true;
267
268 return ret;
269}
270
271static void sh_tmu_clocksource_disable(struct clocksource *cs)
272{
273 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
274
275 if (WARN_ON(!ch->cs_enabled))
276 return;
277
278 sh_tmu_disable(ch);
279 ch->cs_enabled = false;
280}
281
282static void sh_tmu_clocksource_suspend(struct clocksource *cs)
283{
284 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
285
286 if (!ch->cs_enabled)
287 return;
288
289 if (--ch->enable_count == 0) {
290 __sh_tmu_disable(ch);
291 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
292 }
293}
294
295static void sh_tmu_clocksource_resume(struct clocksource *cs)
296{
297 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
298
299 if (!ch->cs_enabled)
300 return;
301
302 if (ch->enable_count++ == 0) {
303 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
304 __sh_tmu_enable(ch);
305 }
306}
307
308static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
309 const char *name)
310{
311 struct clocksource *cs = &ch->cs;
312
313 cs->name = name;
314 cs->rating = 200;
315 cs->read = sh_tmu_clocksource_read;
316 cs->enable = sh_tmu_clocksource_enable;
317 cs->disable = sh_tmu_clocksource_disable;
318 cs->suspend = sh_tmu_clocksource_suspend;
319 cs->resume = sh_tmu_clocksource_resume;
320 cs->mask = CLOCKSOURCE_MASK(32);
321 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
322
323 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
324 ch->index);
325
326 clocksource_register_hz(cs, ch->tmu->rate);
327 return 0;
328}
329
330static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
331{
332 return container_of(ced, struct sh_tmu_channel, ced);
333}
334
335static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
336{
337 sh_tmu_enable(ch);
338
339 if (periodic) {
340 ch->periodic = (ch->tmu->rate + HZ/2) / HZ;
341 sh_tmu_set_next(ch, ch->periodic, 1);
342 }
343}
344
345static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced)
346{
347 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
348
349 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
350 sh_tmu_disable(ch);
351 return 0;
352}
353
354static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,
355 int periodic)
356{
357 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
358
359 /* deal with old setting first */
360 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
361 sh_tmu_disable(ch);
362
363 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
364 ch->index, periodic ? "periodic" : "oneshot");
365 sh_tmu_clock_event_start(ch, periodic);
366 return 0;
367}
368
369static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced)
370{
371 return sh_tmu_clock_event_set_state(ced, 0);
372}
373
374static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced)
375{
376 return sh_tmu_clock_event_set_state(ced, 1);
377}
378
379static int sh_tmu_clock_event_next(unsigned long delta,
380 struct clock_event_device *ced)
381{
382 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
383
384 BUG_ON(!clockevent_state_oneshot(ced));
385
386 /* program new delta value */
387 sh_tmu_set_next(ch, delta, 0);
388 return 0;
389}
390
391static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
392{
393 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
394}
395
396static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
397{
398 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
399}
400
401static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
402 const char *name)
403{
404 struct clock_event_device *ced = &ch->ced;
405 int ret;
406
407 ced->name = name;
408 ced->features = CLOCK_EVT_FEAT_PERIODIC;
409 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
410 ced->rating = 200;
411 ced->cpumask = cpu_possible_mask;
412 ced->set_next_event = sh_tmu_clock_event_next;
413 ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
414 ced->set_state_periodic = sh_tmu_clock_event_set_periodic;
415 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot;
416 ced->suspend = sh_tmu_clock_event_suspend;
417 ced->resume = sh_tmu_clock_event_resume;
418
419 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
420 ch->index);
421
422 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
423
424 ret = request_irq(ch->irq, sh_tmu_interrupt,
425 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
426 dev_name(&ch->tmu->pdev->dev), ch);
427 if (ret) {
428 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
429 ch->index, ch->irq);
430 return;
431 }
432}
433
434static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
435 bool clockevent, bool clocksource)
436{
437 if (clockevent) {
438 ch->tmu->has_clockevent = true;
439 sh_tmu_register_clockevent(ch, name);
440 } else if (clocksource) {
441 ch->tmu->has_clocksource = true;
442 sh_tmu_register_clocksource(ch, name);
443 }
444
445 return 0;
446}
447
448static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
449 bool clockevent, bool clocksource,
450 struct sh_tmu_device *tmu)
451{
452 /* Skip unused channels. */
453 if (!clockevent && !clocksource)
454 return 0;
455
456 ch->tmu = tmu;
457 ch->index = index;
458
459 if (tmu->model == SH_TMU_SH3)
460 ch->base = tmu->mapbase + 4 + ch->index * 12;
461 else
462 ch->base = tmu->mapbase + 8 + ch->index * 12;
463
464 ch->irq = platform_get_irq(tmu->pdev, index);
465 if (ch->irq < 0) {
466 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
467 ch->index);
468 return ch->irq;
469 }
470
471 ch->cs_enabled = false;
472 ch->enable_count = 0;
473
474 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
475 clockevent, clocksource);
476}
477
478static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
479{
480 struct resource *res;
481
482 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
483 if (!res) {
484 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
485 return -ENXIO;
486 }
487
488 tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
489 if (tmu->mapbase == NULL)
490 return -ENXIO;
491
492 return 0;
493}
494
495static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
496{
497 struct device_node *np = tmu->pdev->dev.of_node;
498
499 tmu->model = SH_TMU;
500 tmu->num_channels = 3;
501
502 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
503
504 if (tmu->num_channels != 2 && tmu->num_channels != 3) {
505 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
506 tmu->num_channels);
507 return -EINVAL;
508 }
509
510 return 0;
511}
512
513static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
514{
515 unsigned int i;
516 int ret;
517
518 tmu->pdev = pdev;
519
520 raw_spin_lock_init(&tmu->lock);
521
522 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
523 ret = sh_tmu_parse_dt(tmu);
524 if (ret < 0)
525 return ret;
526 } else if (pdev->dev.platform_data) {
527 const struct platform_device_id *id = pdev->id_entry;
528 struct sh_timer_config *cfg = pdev->dev.platform_data;
529
530 tmu->model = id->driver_data;
531 tmu->num_channels = hweight8(cfg->channels_mask);
532 } else {
533 dev_err(&tmu->pdev->dev, "missing platform data\n");
534 return -ENXIO;
535 }
536
537 /* Get hold of clock. */
538 tmu->clk = clk_get(&tmu->pdev->dev, "fck");
539 if (IS_ERR(tmu->clk)) {
540 dev_err(&tmu->pdev->dev, "cannot get clock\n");
541 return PTR_ERR(tmu->clk);
542 }
543
544 ret = clk_prepare(tmu->clk);
545 if (ret < 0)
546 goto err_clk_put;
547
548 /* Determine clock rate. */
549 ret = clk_enable(tmu->clk);
550 if (ret < 0)
551 goto err_clk_unprepare;
552
553 tmu->rate = clk_get_rate(tmu->clk) / 4;
554 clk_disable(tmu->clk);
555
556 /* Map the memory resource. */
557 ret = sh_tmu_map_memory(tmu);
558 if (ret < 0) {
559 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
560 goto err_clk_unprepare;
561 }
562
563 /* Allocate and setup the channels. */
564 tmu->channels = kcalloc(tmu->num_channels, sizeof(*tmu->channels),
565 GFP_KERNEL);
566 if (tmu->channels == NULL) {
567 ret = -ENOMEM;
568 goto err_unmap;
569 }
570
571 /*
572 * Use the first channel as a clock event device and the second channel
573 * as a clock source.
574 */
575 for (i = 0; i < tmu->num_channels; ++i) {
576 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
577 i == 0, i == 1, tmu);
578 if (ret < 0)
579 goto err_unmap;
580 }
581
582 platform_set_drvdata(pdev, tmu);
583
584 return 0;
585
586err_unmap:
587 kfree(tmu->channels);
588 iounmap(tmu->mapbase);
589err_clk_unprepare:
590 clk_unprepare(tmu->clk);
591err_clk_put:
592 clk_put(tmu->clk);
593 return ret;
594}
595
596static int sh_tmu_probe(struct platform_device *pdev)
597{
598 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
599 int ret;
600
601 if (!is_early_platform_device(pdev)) {
602 pm_runtime_set_active(&pdev->dev);
603 pm_runtime_enable(&pdev->dev);
604 }
605
606 if (tmu) {
607 dev_info(&pdev->dev, "kept as earlytimer\n");
608 goto out;
609 }
610
611 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
612 if (tmu == NULL)
613 return -ENOMEM;
614
615 ret = sh_tmu_setup(tmu, pdev);
616 if (ret) {
617 kfree(tmu);
618 pm_runtime_idle(&pdev->dev);
619 return ret;
620 }
621 if (is_early_platform_device(pdev))
622 return 0;
623
624 out:
625 if (tmu->has_clockevent || tmu->has_clocksource)
626 pm_runtime_irq_safe(&pdev->dev);
627 else
628 pm_runtime_idle(&pdev->dev);
629
630 return 0;
631}
632
633static int sh_tmu_remove(struct platform_device *pdev)
634{
635 return -EBUSY; /* cannot unregister clockevent and clocksource */
636}
637
638static const struct platform_device_id sh_tmu_id_table[] = {
639 { "sh-tmu", SH_TMU },
640 { "sh-tmu-sh3", SH_TMU_SH3 },
641 { }
642};
643MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
644
645static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
646 { .compatible = "renesas,tmu" },
647 { }
648};
649MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
650
651static struct platform_driver sh_tmu_device_driver = {
652 .probe = sh_tmu_probe,
653 .remove = sh_tmu_remove,
654 .driver = {
655 .name = "sh_tmu",
656 .of_match_table = of_match_ptr(sh_tmu_of_table),
657 },
658 .id_table = sh_tmu_id_table,
659};
660
661static int __init sh_tmu_init(void)
662{
663 return platform_driver_register(&sh_tmu_device_driver);
664}
665
666static void __exit sh_tmu_exit(void)
667{
668 platform_driver_unregister(&sh_tmu_device_driver);
669}
670
671early_platform_init("earlytimer", &sh_tmu_device_driver);
672subsys_initcall(sh_tmu_init);
673module_exit(sh_tmu_exit);
674
675MODULE_AUTHOR("Magnus Damm");
676MODULE_DESCRIPTION("SuperH TMU Timer Driver");
677MODULE_LICENSE("GPL v2");
678