1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * AMCC SoC PPC4xx Crypto Driver
4 *
5 * Copyright (c) 2008 Applied Micro Circuits Corporation.
6 * All rights reserved. James Hsiao <jhsiao@amcc.com>
7 *
8 * This filr defines the register set for Security Subsystem
9 */
10
11#ifndef __CRYPTO4XX_REG_DEF_H__
12#define __CRYPTO4XX_REG_DEF_H__
13
14/* CRYPTO4XX Register offset */
15#define CRYPTO4XX_DESCRIPTOR 0x00000000
16#define CRYPTO4XX_CTRL_STAT 0x00000000
17#define CRYPTO4XX_SOURCE 0x00000004
18#define CRYPTO4XX_DEST 0x00000008
19#define CRYPTO4XX_SA 0x0000000C
20#define CRYPTO4XX_SA_LENGTH 0x00000010
21#define CRYPTO4XX_LENGTH 0x00000014
22
23#define CRYPTO4XX_PE_DMA_CFG 0x00000040
24#define CRYPTO4XX_PE_DMA_STAT 0x00000044
25#define CRYPTO4XX_PDR_BASE 0x00000048
26#define CRYPTO4XX_RDR_BASE 0x0000004c
27#define CRYPTO4XX_RING_SIZE 0x00000050
28#define CRYPTO4XX_RING_CTRL 0x00000054
29#define CRYPTO4XX_INT_RING_STAT 0x00000058
30#define CRYPTO4XX_EXT_RING_STAT 0x0000005c
31#define CRYPTO4XX_IO_THRESHOLD 0x00000060
32#define CRYPTO4XX_GATH_RING_BASE 0x00000064
33#define CRYPTO4XX_SCAT_RING_BASE 0x00000068
34#define CRYPTO4XX_PART_RING_SIZE 0x0000006c
35#define CRYPTO4XX_PART_RING_CFG 0x00000070
36
37#define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
38#define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
39#define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
40#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
41#define CRYPTO4XX_SA_UADDR 0x00000090
42#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
43#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
44
45#define CRYPTO4XX_SEQ_RD 0x00000408
46#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
47
48#define CRYPTO4XX_SA_CMD_0 0x00010600
49#define CRYPTO4XX_SA_CMD_1 0x00010604
50
51#define CRYPTO4XX_STATE_PTR 0x000106dc
52#define CRYPTO4XX_STATE_IV 0x00010700
53#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
54#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
55
56#define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
57#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
58
59#define CRYPTO4XX_DATA_IN 0x00018000
60#define CRYPTO4XX_DATA_OUT 0x0001c000
61
62#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
63#define CRYPTO4XX_INT_MASK_STAT 0x000500a4
64#define CRYPTO4XX_INT_CLR 0x000500a4
65#define CRYPTO4XX_INT_EN 0x000500a8
66
67#define CRYPTO4XX_INT_PKA 0x00000002
68#define CRYPTO4XX_INT_PDR_DONE 0x00008000
69#define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
70#define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
71#define CRYPTO4XX_INT_PE_ERR 0x00000200
72#define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
73#define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
74#define CRYPTO4XX_INT_MASTER_ERR 0x00000008
75#define CRYPTO4XX_INT_ERROR 0x00030258
76
77#define CRYPTO4XX_INT_CFG 0x000500ac
78#define CRYPTO4XX_INT_DESCR_RD 0x000500b0
79#define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
80#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
81
82#define CRYPTO4XX_DEVICE_CTRL 0x00060080
83#define CRYPTO4XX_DEVICE_ID 0x00060084
84#define CRYPTO4XX_DEVICE_INFO 0x00060088
85#define CRYPTO4XX_DMA_USER_SRC 0x00060094
86#define CRYPTO4XX_DMA_USER_DEST 0x00060098
87#define CRYPTO4XX_DMA_USER_CMD 0x0006009C
88
89#define CRYPTO4XX_DMA_CFG 0x000600d4
90#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
91#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
92
93#define CRYPTO4XX_PRNG_STAT 0x00070000
94#define CRYPTO4XX_PRNG_STAT_BUSY 0x1
95#define CRYPTO4XX_PRNG_CTRL 0x00070004
96#define CRYPTO4XX_PRNG_SEED_L 0x00070008
97#define CRYPTO4XX_PRNG_SEED_H 0x0007000c
98
99#define CRYPTO4XX_PRNG_RES_0 0x00070020
100#define CRYPTO4XX_PRNG_RES_1 0x00070024
101#define CRYPTO4XX_PRNG_RES_2 0x00070028
102#define CRYPTO4XX_PRNG_RES_3 0x0007002C
103
104#define CRYPTO4XX_PRNG_LFSR_L 0x00070030
105#define CRYPTO4XX_PRNG_LFSR_H 0x00070034
106
107/*
108 * Initialize CRYPTO ENGINE registers, and memory bases.
109 */
110#define PPC4XX_PDR_POLL 0x3ff
111#define PPC4XX_OUTPUT_THRESHOLD 2
112#define PPC4XX_INPUT_THRESHOLD 2
113#define PPC4XX_PD_SIZE 6
114#define PPC4XX_CTX_DONE_INT 0x2000
115#define PPC4XX_PD_DONE_INT 0x8000
116#define PPC4XX_TMO_ERR_INT 0x40000
117#define PPC4XX_BYTE_ORDER 0x22222
118#define PPC4XX_INTERRUPT_CLR 0x3ffff
119#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
120#define PPC4XX_DC_3DES_EN 1
121#define PPC4XX_TRNG_EN 0x00020000
122#define PPC4XX_INT_DESCR_CNT 7
123#define PPC4XX_INT_TIMEOUT_CNT 0
124#define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF
125#define PPC4XX_INT_CFG 1
126/*
127 * all follow define are ad hoc
128 */
129#define PPC4XX_RING_RETRY 100
130#define PPC4XX_RING_POLL 100
131#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD
132#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD
133
134/*
135 * Generic Security Association (SA) with all possible fields. These will
136 * never likely used except for reference purpose. These structure format
137 * can be not changed as the hardware expects them to be layout as defined.
138 * Field can be removed or reduced but ordering can not be changed.
139 */
140#define CRYPTO4XX_DMA_CFG_OFFSET 0x40
141union ce_pe_dma_cfg {
142 struct {
143 u32 rsv:7;
144 u32 dir_host:1;
145 u32 rsv1:2;
146 u32 bo_td_en:1;
147 u32 dis_pdr_upd:1;
148 u32 bo_sgpd_en:1;
149 u32 bo_data_en:1;
150 u32 bo_sa_en:1;
151 u32 bo_pd_en:1;
152 u32 rsv2:4;
153 u32 dynamic_sa_en:1;
154 u32 pdr_mode:2;
155 u32 pe_mode:1;
156 u32 rsv3:5;
157 u32 reset_sg:1;
158 u32 reset_pdr:1;
159 u32 reset_pe:1;
160 } bf;
161 u32 w;
162} __attribute__((packed));
163
164#define CRYPTO4XX_PDR_BASE_OFFSET 0x48
165#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
166#define CRYPTO4XX_RING_SIZE_OFFSET 0x50
167union ce_ring_size {
168 struct {
169 u32 ring_offset:16;
170 u32 rsv:6;
171 u32 ring_size:10;
172 } bf;
173 u32 w;
174} __attribute__((packed));
175
176#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
177union ce_ring_control {
178 struct {
179 u32 continuous:1;
180 u32 rsv:5;
181 u32 ring_retry_divisor:10;
182 u32 rsv1:4;
183 u32 ring_poll_divisor:10;
184 } bf;
185 u32 w;
186} __attribute__((packed));
187
188#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
189union ce_io_threshold {
190 struct {
191 u32 rsv:6;
192 u32 output_threshold:10;
193 u32 rsv1:6;
194 u32 input_threshold:10;
195 } bf;
196 u32 w;
197} __attribute__((packed));
198
199#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
200#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
201
202union ce_part_ring_size {
203 struct {
204 u32 sdr_size:16;
205 u32 gdr_size:16;
206 } bf;
207 u32 w;
208} __attribute__((packed));
209
210#define MAX_BURST_SIZE_32 0
211#define MAX_BURST_SIZE_64 1
212#define MAX_BURST_SIZE_128 2
213#define MAX_BURST_SIZE_256 3
214
215/* gather descriptor control length */
216struct gd_ctl_len {
217 u32 len:16;
218 u32 rsv:14;
219 u32 done:1;
220 u32 ready:1;
221} __attribute__((packed));
222
223struct ce_gd {
224 u32 ptr;
225 struct gd_ctl_len ctl_len;
226} __attribute__((packed));
227
228struct sd_ctl {
229 u32 ctl:30;
230 u32 done:1;
231 u32 rdy:1;
232} __attribute__((packed));
233
234struct ce_sd {
235 u32 ptr;
236 struct sd_ctl ctl;
237} __attribute__((packed));
238
239#define PD_PAD_CTL_32 0x10
240#define PD_PAD_CTL_64 0x20
241#define PD_PAD_CTL_128 0x40
242#define PD_PAD_CTL_256 0x80
243union ce_pd_ctl {
244 struct {
245 u32 pd_pad_ctl:8;
246 u32 status:8;
247 u32 next_hdr:8;
248 u32 rsv:2;
249 u32 cached_sa:1;
250 u32 hash_final:1;
251 u32 init_arc4:1;
252 u32 rsv1:1;
253 u32 pe_done:1;
254 u32 host_ready:1;
255 } bf;
256 u32 w;
257} __attribute__((packed));
258#define PD_CTL_HASH_FINAL BIT(4)
259#define PD_CTL_PE_DONE BIT(1)
260#define PD_CTL_HOST_READY BIT(0)
261
262union ce_pd_ctl_len {
263 struct {
264 u32 bypass:8;
265 u32 pe_done:1;
266 u32 host_ready:1;
267 u32 rsv:2;
268 u32 pkt_len:20;
269 } bf;
270 u32 w;
271} __attribute__((packed));
272
273struct ce_pd {
274 union ce_pd_ctl pd_ctl;
275 u32 src;
276 u32 dest;
277 u32 sa; /* get from ctx->sa_dma_addr */
278 u32 sa_len; /* only if dynamic sa is used */
279 union ce_pd_ctl_len pd_ctl_len;
280
281} __attribute__((packed));
282#endif
283

source code of linux/drivers/crypto/amcc/crypto4xx_reg_def.h