1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright 2016 Broadcom |
4 | */ |
5 | |
6 | /* |
7 | * This file contains SPU message definitions specific to SPU-M. |
8 | */ |
9 | |
10 | #ifndef _SPUM_H_ |
11 | #define _SPUM_H_ |
12 | |
13 | #define SPU_CRYPTO_OPERATION_GENERIC 0x1 |
14 | |
15 | /* Length of STATUS field in tx and rx packets */ |
16 | #define SPU_TX_STATUS_LEN 4 |
17 | |
18 | /* SPU-M error codes */ |
19 | #define SPU_STATUS_MASK 0x0000FF00 |
20 | #define SPU_STATUS_SUCCESS 0x00000000 |
21 | #define SPU_STATUS_INVALID_ICV 0x00000100 |
22 | |
23 | #define SPU_STATUS_ERROR_FLAG 0x00020000 |
24 | |
25 | /* Request message. MH + EMH + BDESC + BD header */ |
26 | #define SPU_REQ_FIXED_LEN 24 |
27 | |
28 | /* |
29 | * Max length of a SPU message header. Used to allocate a buffer where |
30 | * the SPU message header is constructed. Can be used for either a SPU-M |
31 | * header or a SPU2 header. |
32 | * For SPU-M, sum of the following: |
33 | * MH - 4 bytes |
34 | * EMH - 4 |
35 | * SCTX - 3 + |
36 | * max auth key len - 64 |
37 | * max cipher key len - 264 (RC4) |
38 | * max IV len - 16 |
39 | * BDESC - 12 |
40 | * BD header - 4 |
41 | * Total: 371 |
42 | * |
43 | * For SPU2, FMD_SIZE (32) plus lengths of hash and cipher keys, |
44 | * hash and cipher IVs. If SPU2 does not support RC4, then |
45 | */ |
46 | #define (SPU_REQ_FIXED_LEN + MAX_KEY_SIZE + \ |
47 | MAX_KEY_SIZE + MAX_IV_SIZE) |
48 | |
49 | /* |
50 | * Response message header length. Normally MH, EMH, BD header, but when |
51 | * BD_SUPPRESS is used for hash requests, there is no BD header. |
52 | */ |
53 | #define SPU_RESP_HDR_LEN 12 |
54 | #define SPU_HASH_RESP_HDR_LEN 8 |
55 | |
56 | /* |
57 | * Max value that can be represented in the Payload Length field of the BD |
58 | * header. This is a 16-bit field. |
59 | */ |
60 | #define SPUM_NS2_MAX_PAYLOAD (BIT(16) - 1) |
61 | |
62 | /* |
63 | * NSP SPU is limited to ~9KB because of FA2 FIFO size limitations; |
64 | * Set MAX_PAYLOAD to 8k to allow for addition of header, digest, etc. |
65 | * and stay within limitation. |
66 | */ |
67 | |
68 | #define SPUM_NSP_MAX_PAYLOAD 8192 |
69 | |
70 | /* Buffer Descriptor Header [BDESC]. SPU in big-endian mode. */ |
71 | struct { |
72 | __be16 ; /* word 0 [31-16] */ |
73 | __be16 ; /* word 0 [15-0] */ |
74 | __be16 ; /* word 1 [31-16] */ |
75 | __be16 ; /* word 1 [15-0] */ |
76 | __be16 ; /* word 2 [31-16] */ |
77 | __be16 ; /* word 2 [15-0] */ |
78 | }; |
79 | |
80 | /* Buffer Data Header [BD]. SPU in big-endian mode. */ |
81 | struct { |
82 | __be16 ; |
83 | __be16 ; |
84 | }; |
85 | |
86 | /* Command Context Header. SPU-M in big endian mode. */ |
87 | struct { |
88 | u8 ; /* [31:24] */ |
89 | u8 ; /* [23:16] */ |
90 | u16 ; /* [15:0] */ |
91 | }; |
92 | |
93 | /* MH header flags bits */ |
94 | #define MH_SUPDT_PRES BIT(0) |
95 | #define MH_HASH_PRES BIT(2) |
96 | #define MH_BD_PRES BIT(3) |
97 | #define MH_MFM_PRES BIT(4) |
98 | #define MH_BDESC_PRES BIT(5) |
99 | #define MH_SCTX_PRES BIT(7) |
100 | |
101 | /* SCTX word 0 bit offsets and fields masks */ |
102 | #define SCTX_SIZE 0x000000FF |
103 | |
104 | /* SCTX word 1 bit shifts and field masks */ |
105 | #define UPDT_OFST 0x000000FF /* offset of SCTX updateable fld */ |
106 | #define HASH_TYPE 0x00000300 /* hash alg operation type */ |
107 | #define HASH_TYPE_SHIFT 8 |
108 | #define HASH_MODE 0x00001C00 /* one of spu2_hash_mode */ |
109 | #define HASH_MODE_SHIFT 10 |
110 | #define HASH_ALG 0x0000E000 /* hash algorithm */ |
111 | #define HASH_ALG_SHIFT 13 |
112 | #define CIPHER_TYPE 0x00030000 /* encryption operation type */ |
113 | #define CIPHER_TYPE_SHIFT 16 |
114 | #define CIPHER_MODE 0x001C0000 /* encryption mode */ |
115 | #define CIPHER_MODE_SHIFT 18 |
116 | #define CIPHER_ALG 0x00E00000 /* encryption algo */ |
117 | #define CIPHER_ALG_SHIFT 21 |
118 | #define ICV_IS_512 BIT(27) |
119 | #define ICV_IS_512_SHIFT 27 |
120 | #define CIPHER_ORDER BIT(30) |
121 | #define CIPHER_ORDER_SHIFT 30 |
122 | #define CIPHER_INBOUND BIT(31) |
123 | #define CIPHER_INBOUND_SHIFT 31 |
124 | |
125 | /* SCTX word 2 bit shifts and field masks */ |
126 | #define EXP_IV_SIZE 0x7 |
127 | #define IV_OFFSET BIT(3) |
128 | #define IV_OFFSET_SHIFT 3 |
129 | #define GEN_IV BIT(5) |
130 | #define GEN_IV_SHIFT 5 |
131 | #define EXPLICIT_IV BIT(6) |
132 | #define EXPLICIT_IV_SHIFT 6 |
133 | #define SCTX_IV BIT(7) |
134 | #define SCTX_IV_SHIFT 7 |
135 | #define ICV_SIZE 0x0F00 |
136 | #define ICV_SIZE_SHIFT 8 |
137 | #define CHECK_ICV BIT(12) |
138 | #define CHECK_ICV_SHIFT 12 |
139 | #define INSERT_ICV BIT(13) |
140 | #define INSERT_ICV_SHIFT 13 |
141 | #define BD_SUPPRESS BIT(19) |
142 | #define BD_SUPPRESS_SHIFT 19 |
143 | |
144 | /* Generic Mode Security Context Structure [SCTX] */ |
145 | struct SCTX { |
146 | /* word 0: protocol flags */ |
147 | __be32 proto_flags; |
148 | |
149 | /* word 1: cipher flags */ |
150 | __be32 cipher_flags; |
151 | |
152 | /* word 2: Extended cipher flags */ |
153 | __be32 ecf; |
154 | |
155 | }; |
156 | |
157 | struct { |
158 | struct MHEADER ; |
159 | u32 ; |
160 | struct SCTX ; |
161 | }; |
162 | |
163 | #endif /* _SPUM_H_ */ |
164 | |