1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ |
3 | |
4 | /* \file cc_aead.h |
5 | * ARM CryptoCell AEAD Crypto API |
6 | */ |
7 | |
8 | #ifndef __CC_AEAD_H__ |
9 | #define __CC_AEAD_H__ |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <crypto/algapi.h> |
13 | #include <crypto/ctr.h> |
14 | |
15 | /* mac_cmp - HW writes 8 B but all bytes hold the same value */ |
16 | #define ICV_CMP_SIZE 8 |
17 | #define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3) |
18 | #define MAX_MAC_SIZE SHA256_DIGEST_SIZE |
19 | |
20 | /* defines for AES GCM configuration buffer */ |
21 | #define GCM_BLOCK_LEN_SIZE 8 |
22 | |
23 | #define GCM_BLOCK_RFC4_IV_OFFSET 4 |
24 | #define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */ |
25 | #define GCM_BLOCK_RFC4_NONCE_OFFSET 0 |
26 | #define GCM_BLOCK_RFC4_NONCE_SIZE 4 |
27 | |
28 | /* Offsets into AES CCM configuration buffer */ |
29 | #define CCM_B0_OFFSET 0 |
30 | #define CCM_A0_OFFSET 16 |
31 | #define CCM_CTR_COUNT_0_OFFSET 32 |
32 | /* CCM B0 and CTR_COUNT constants. */ |
33 | #define CCM_BLOCK_NONCE_OFFSET 1 /* Nonce offset inside B0 and CTR_COUNT */ |
34 | #define CCM_BLOCK_NONCE_SIZE 3 /* Nonce size inside B0 and CTR_COUNT */ |
35 | #define CCM_BLOCK_IV_OFFSET 4 /* IV offset inside B0 and CTR_COUNT */ |
36 | #define CCM_BLOCK_IV_SIZE 8 /* IV size inside B0 and CTR_COUNT */ |
37 | |
38 | enum { |
39 | = -1, |
40 | = 0, |
41 | = 2, |
42 | = 6, |
43 | = S32_MAX |
44 | }; |
45 | |
46 | struct aead_req_ctx { |
47 | /* Allocate cache line although only 4 bytes are needed to |
48 | * assure next field falls @ cache line |
49 | * Used for both: digest HW compare and CCM/GCM MAC value |
50 | */ |
51 | u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned; |
52 | u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned; |
53 | |
54 | //used in gcm |
55 | u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned; |
56 | u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned; |
57 | u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned; |
58 | struct { |
59 | u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned; |
60 | u8 len_c[GCM_BLOCK_LEN_SIZE]; |
61 | } gcm_len_block; |
62 | |
63 | u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; |
64 | /* HW actual size input */ |
65 | unsigned int hw_iv_size ____cacheline_aligned; |
66 | /* used to prevent cache coherence problem */ |
67 | u8 backup_mac[MAX_MAC_SIZE]; |
68 | u8 *backup_iv; /* store orig iv */ |
69 | u32 assoclen; /* size of AAD buffer to authenticate */ |
70 | dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */ |
71 | /* buffer for internal ccm configurations */ |
72 | dma_addr_t ccm_iv0_dma_addr; |
73 | dma_addr_t icv_dma_addr; /* Phys. address of ICV */ |
74 | |
75 | //used in gcm |
76 | /* buffer for internal gcm configurations */ |
77 | dma_addr_t gcm_iv_inc1_dma_addr; |
78 | /* buffer for internal gcm configurations */ |
79 | dma_addr_t gcm_iv_inc2_dma_addr; |
80 | dma_addr_t hkey_dma_addr; /* Phys. address of hkey */ |
81 | dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */ |
82 | |
83 | u8 *icv_virt_addr; /* Virt. address of ICV */ |
84 | struct async_gen_req_ctx gen_ctx; |
85 | struct cc_mlli assoc; |
86 | struct cc_mlli src; |
87 | struct cc_mlli dst; |
88 | struct scatterlist *src_sgl; |
89 | struct scatterlist *dst_sgl; |
90 | unsigned int src_offset; |
91 | unsigned int dst_offset; |
92 | enum cc_req_dma_buf_type assoc_buff_type; |
93 | enum cc_req_dma_buf_type data_buff_type; |
94 | struct mlli_params mlli_params; |
95 | unsigned int cryptlen; |
96 | struct scatterlist ccm_adata_sg; |
97 | enum aead_ccm_header_size ccm_hdr_size; |
98 | unsigned int req_authsize; |
99 | enum drv_cipher_mode cipher_mode; |
100 | bool is_icv_fragmented; |
101 | bool is_single_pass; |
102 | bool plaintext_authenticate_only; //for gcm_rfc4543 |
103 | }; |
104 | |
105 | int cc_aead_alloc(struct cc_drvdata *drvdata); |
106 | int cc_aead_free(struct cc_drvdata *drvdata); |
107 | |
108 | #endif /*__CC_AEAD_H__*/ |
109 | |