1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ |
3 | |
4 | /* \file cc_hash.h |
5 | * ARM CryptoCell Hash Crypto API |
6 | */ |
7 | |
8 | #ifndef __CC_HASH_H__ |
9 | #define __CC_HASH_H__ |
10 | |
11 | #include "cc_buffer_mgr.h" |
12 | |
13 | #define HMAC_IPAD_CONST 0x36363636 |
14 | #define HMAC_OPAD_CONST 0x5C5C5C5C |
15 | #define HASH_LEN_SIZE_712 16 |
16 | #define HASH_LEN_SIZE_630 8 |
17 | #define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712 |
18 | #define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE |
19 | #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE |
20 | |
21 | #define XCBC_MAC_K1_OFFSET 0 |
22 | #define XCBC_MAC_K2_OFFSET 16 |
23 | #define XCBC_MAC_K3_OFFSET 32 |
24 | |
25 | #define CC_EXPORT_MAGIC 0xC2EE1070U |
26 | |
27 | /* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used |
28 | * for xcbc/cmac statesize |
29 | */ |
30 | struct aeshash_state { |
31 | u8 state[AES_BLOCK_SIZE]; |
32 | unsigned int count; |
33 | u8 buffer[AES_BLOCK_SIZE]; |
34 | }; |
35 | |
36 | /* ahash state */ |
37 | struct ahash_req_ctx { |
38 | u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned; |
39 | u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; |
40 | u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; |
41 | u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; |
42 | u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned; |
43 | struct async_gen_req_ctx gen_ctx ____cacheline_aligned; |
44 | enum cc_req_dma_buf_type data_dma_buf_type; |
45 | dma_addr_t opad_digest_dma_addr; |
46 | dma_addr_t digest_buff_dma_addr; |
47 | dma_addr_t digest_bytes_len_dma_addr; |
48 | dma_addr_t digest_result_dma_addr; |
49 | u32 buf_cnt[2]; |
50 | u32 buff_index; |
51 | u32 xcbc_count; /* count xcbc update operatations */ |
52 | struct scatterlist buff_sg[2]; |
53 | struct scatterlist *curr_sg; |
54 | u32 in_nents; |
55 | u32 mlli_nents; |
56 | struct mlli_params mlli_params; |
57 | }; |
58 | |
59 | static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state) |
60 | { |
61 | return &state->buf_cnt[state->buff_index]; |
62 | } |
63 | |
64 | static inline u8 *cc_hash_buf(struct ahash_req_ctx *state) |
65 | { |
66 | return state->buffers[state->buff_index]; |
67 | } |
68 | |
69 | static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state) |
70 | { |
71 | return &state->buf_cnt[state->buff_index ^ 1]; |
72 | } |
73 | |
74 | static inline u8 *cc_next_buf(struct ahash_req_ctx *state) |
75 | { |
76 | return state->buffers[state->buff_index ^ 1]; |
77 | } |
78 | |
79 | int cc_hash_alloc(struct cc_drvdata *drvdata); |
80 | int cc_init_hash_sram(struct cc_drvdata *drvdata); |
81 | int cc_hash_free(struct cc_drvdata *drvdata); |
82 | |
83 | /** |
84 | * cc_digest_len_addr() - Gets the initial digest length |
85 | * |
86 | * @drvdata: Associated device driver context |
87 | * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512 |
88 | * |
89 | * Return: |
90 | * Returns the address of the initial digest length in SRAM |
91 | */ |
92 | u32 cc_digest_len_addr(void *drvdata, u32 mode); |
93 | |
94 | /** |
95 | * cc_larval_digest_addr() - Gets the address of the initial digest in SRAM |
96 | * according to the given hash mode |
97 | * |
98 | * @drvdata: Associated device driver context |
99 | * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512 |
100 | * |
101 | * Return: |
102 | * The address of the initial digest in SRAM |
103 | */ |
104 | u32 cc_larval_digest_addr(void *drvdata, u32 mode); |
105 | |
106 | #endif /*__CC_HASH_H__*/ |
107 |