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1/*
2 * GPIO driver for LPC32xx SoC
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio/driver.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/module.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30
31#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
32#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
33#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
34#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
35#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
36#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
37#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
38#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
39#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
40#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
41#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
42#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
43#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
44#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
45#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
46#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
47#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
48#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
49#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
50#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
51#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
52#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
53#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
54#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
55#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
56#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
57#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
58
59#define GPIO012_PIN_TO_BIT(x) (1 << (x))
60#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
61#define GPO3_PIN_TO_BIT(x) (1 << (x))
62#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
63#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
64#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
65#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
66#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
67#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
68
69#define LPC32XX_GPIO_P0_MAX 8
70#define LPC32XX_GPIO_P1_MAX 24
71#define LPC32XX_GPIO_P2_MAX 13
72#define LPC32XX_GPIO_P3_MAX 6
73#define LPC32XX_GPI_P3_MAX 29
74#define LPC32XX_GPO_P3_MAX 24
75
76#define LPC32XX_GPIO_P0_GRP 0
77#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
78#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
79#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
80#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
81#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
82
83struct gpio_regs {
84 void __iomem *inp_state;
85 void __iomem *outp_state;
86 void __iomem *outp_set;
87 void __iomem *outp_clr;
88 void __iomem *dir_set;
89 void __iomem *dir_clr;
90};
91
92/*
93 * GPIO names
94 */
95static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
96 "p0.0", "p0.1", "p0.2", "p0.3",
97 "p0.4", "p0.5", "p0.6", "p0.7"
98};
99
100static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
101 "p1.0", "p1.1", "p1.2", "p1.3",
102 "p1.4", "p1.5", "p1.6", "p1.7",
103 "p1.8", "p1.9", "p1.10", "p1.11",
104 "p1.12", "p1.13", "p1.14", "p1.15",
105 "p1.16", "p1.17", "p1.18", "p1.19",
106 "p1.20", "p1.21", "p1.22", "p1.23",
107};
108
109static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
110 "p2.0", "p2.1", "p2.2", "p2.3",
111 "p2.4", "p2.5", "p2.6", "p2.7",
112 "p2.8", "p2.9", "p2.10", "p2.11",
113 "p2.12"
114};
115
116static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
117 "gpio00", "gpio01", "gpio02", "gpio03",
118 "gpio04", "gpio05"
119};
120
121static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
122 "gpi00", "gpi01", "gpi02", "gpi03",
123 "gpi04", "gpi05", "gpi06", "gpi07",
124 "gpi08", "gpi09", NULL, NULL,
125 NULL, NULL, NULL, "gpi15",
126 "gpi16", "gpi17", "gpi18", "gpi19",
127 "gpi20", "gpi21", "gpi22", "gpi23",
128 "gpi24", "gpi25", "gpi26", "gpi27",
129 "gpi28"
130};
131
132static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
133 "gpo00", "gpo01", "gpo02", "gpo03",
134 "gpo04", "gpo05", "gpo06", "gpo07",
135 "gpo08", "gpo09", "gpo10", "gpo11",
136 "gpo12", "gpo13", "gpo14", "gpo15",
137 "gpo16", "gpo17", "gpo18", "gpo19",
138 "gpo20", "gpo21", "gpo22", "gpo23"
139};
140
141static struct gpio_regs gpio_grp_regs_p0 = {
142 .inp_state = LPC32XX_GPIO_P0_INP_STATE,
143 .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
144 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
145 .dir_set = LPC32XX_GPIO_P0_DIR_SET,
146 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
147};
148
149static struct gpio_regs gpio_grp_regs_p1 = {
150 .inp_state = LPC32XX_GPIO_P1_INP_STATE,
151 .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
152 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
153 .dir_set = LPC32XX_GPIO_P1_DIR_SET,
154 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
155};
156
157static struct gpio_regs gpio_grp_regs_p2 = {
158 .inp_state = LPC32XX_GPIO_P2_INP_STATE,
159 .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
160 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
161 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
162 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
163};
164
165static struct gpio_regs gpio_grp_regs_p3 = {
166 .inp_state = LPC32XX_GPIO_P3_INP_STATE,
167 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
168 .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
169 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
170 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
171 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
172};
173
174struct lpc32xx_gpio_chip {
175 struct gpio_chip chip;
176 struct gpio_regs *gpio_grp;
177};
178
179static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
180 unsigned pin, int input)
181{
182 if (input)
183 __raw_writel(GPIO012_PIN_TO_BIT(pin),
184 group->gpio_grp->dir_clr);
185 else
186 __raw_writel(GPIO012_PIN_TO_BIT(pin),
187 group->gpio_grp->dir_set);
188}
189
190static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
191 unsigned pin, int input)
192{
193 u32 u = GPIO3_PIN_TO_BIT(pin);
194
195 if (input)
196 __raw_writel(u, group->gpio_grp->dir_clr);
197 else
198 __raw_writel(u, group->gpio_grp->dir_set);
199}
200
201static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
202 unsigned pin, int high)
203{
204 if (high)
205 __raw_writel(GPIO012_PIN_TO_BIT(pin),
206 group->gpio_grp->outp_set);
207 else
208 __raw_writel(GPIO012_PIN_TO_BIT(pin),
209 group->gpio_grp->outp_clr);
210}
211
212static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
213 unsigned pin, int high)
214{
215 u32 u = GPIO3_PIN_TO_BIT(pin);
216
217 if (high)
218 __raw_writel(u, group->gpio_grp->outp_set);
219 else
220 __raw_writel(u, group->gpio_grp->outp_clr);
221}
222
223static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
224 unsigned pin, int high)
225{
226 if (high)
227 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
228 else
229 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
230}
231
232static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
233 unsigned pin)
234{
235 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
236 pin);
237}
238
239static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
240 unsigned pin)
241{
242 int state = __raw_readl(group->gpio_grp->inp_state);
243
244 /*
245 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
246 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
247 */
248 return GPIO3_PIN_IN_SEL(state, pin);
249}
250
251static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
252 unsigned pin)
253{
254 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
255}
256
257static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
258 unsigned pin)
259{
260 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
261}
262
263/*
264 * GPIO primitives.
265 */
266static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
267 unsigned pin)
268{
269 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
270
271 __set_gpio_dir_p012(group, pin, 1);
272
273 return 0;
274}
275
276static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
277 unsigned pin)
278{
279 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
280
281 __set_gpio_dir_p3(group, pin, 1);
282
283 return 0;
284}
285
286static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
287 unsigned pin)
288{
289 return 0;
290}
291
292static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
293{
294 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
295
296 return !!__get_gpio_state_p012(group, pin);
297}
298
299static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
300{
301 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
302
303 return !!__get_gpio_state_p3(group, pin);
304}
305
306static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
307{
308 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
309
310 return !!__get_gpi_state_p3(group, pin);
311}
312
313static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
314 int value)
315{
316 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
317
318 __set_gpio_level_p012(group, pin, value);
319 __set_gpio_dir_p012(group, pin, 0);
320
321 return 0;
322}
323
324static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
325 int value)
326{
327 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
328
329 __set_gpio_level_p3(group, pin, value);
330 __set_gpio_dir_p3(group, pin, 0);
331
332 return 0;
333}
334
335static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
336 int value)
337{
338 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
339
340 __set_gpo_level_p3(group, pin, value);
341 return 0;
342}
343
344static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
345 int value)
346{
347 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
348
349 __set_gpio_level_p012(group, pin, value);
350}
351
352static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
353 int value)
354{
355 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
356
357 __set_gpio_level_p3(group, pin, value);
358}
359
360static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
361 int value)
362{
363 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
364
365 __set_gpo_level_p3(group, pin, value);
366}
367
368static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
369{
370 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
371
372 return !!__get_gpo_state_p3(group, pin);
373}
374
375static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
376{
377 if (pin < chip->ngpio)
378 return 0;
379
380 return -EINVAL;
381}
382
383static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
384{
385 return -ENXIO;
386}
387
388static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
389{
390 return -ENXIO;
391}
392
393static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
394{
395 return -ENXIO;
396}
397
398static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
399 {
400 .chip = {
401 .label = "gpio_p0",
402 .direction_input = lpc32xx_gpio_dir_input_p012,
403 .get = lpc32xx_gpio_get_value_p012,
404 .direction_output = lpc32xx_gpio_dir_output_p012,
405 .set = lpc32xx_gpio_set_value_p012,
406 .request = lpc32xx_gpio_request,
407 .to_irq = lpc32xx_gpio_to_irq_p01,
408 .base = LPC32XX_GPIO_P0_GRP,
409 .ngpio = LPC32XX_GPIO_P0_MAX,
410 .names = gpio_p0_names,
411 .can_sleep = false,
412 },
413 .gpio_grp = &gpio_grp_regs_p0,
414 },
415 {
416 .chip = {
417 .label = "gpio_p1",
418 .direction_input = lpc32xx_gpio_dir_input_p012,
419 .get = lpc32xx_gpio_get_value_p012,
420 .direction_output = lpc32xx_gpio_dir_output_p012,
421 .set = lpc32xx_gpio_set_value_p012,
422 .request = lpc32xx_gpio_request,
423 .to_irq = lpc32xx_gpio_to_irq_p01,
424 .base = LPC32XX_GPIO_P1_GRP,
425 .ngpio = LPC32XX_GPIO_P1_MAX,
426 .names = gpio_p1_names,
427 .can_sleep = false,
428 },
429 .gpio_grp = &gpio_grp_regs_p1,
430 },
431 {
432 .chip = {
433 .label = "gpio_p2",
434 .direction_input = lpc32xx_gpio_dir_input_p012,
435 .get = lpc32xx_gpio_get_value_p012,
436 .direction_output = lpc32xx_gpio_dir_output_p012,
437 .set = lpc32xx_gpio_set_value_p012,
438 .request = lpc32xx_gpio_request,
439 .base = LPC32XX_GPIO_P2_GRP,
440 .ngpio = LPC32XX_GPIO_P2_MAX,
441 .names = gpio_p2_names,
442 .can_sleep = false,
443 },
444 .gpio_grp = &gpio_grp_regs_p2,
445 },
446 {
447 .chip = {
448 .label = "gpio_p3",
449 .direction_input = lpc32xx_gpio_dir_input_p3,
450 .get = lpc32xx_gpio_get_value_p3,
451 .direction_output = lpc32xx_gpio_dir_output_p3,
452 .set = lpc32xx_gpio_set_value_p3,
453 .request = lpc32xx_gpio_request,
454 .to_irq = lpc32xx_gpio_to_irq_gpio_p3,
455 .base = LPC32XX_GPIO_P3_GRP,
456 .ngpio = LPC32XX_GPIO_P3_MAX,
457 .names = gpio_p3_names,
458 .can_sleep = false,
459 },
460 .gpio_grp = &gpio_grp_regs_p3,
461 },
462 {
463 .chip = {
464 .label = "gpi_p3",
465 .direction_input = lpc32xx_gpio_dir_in_always,
466 .get = lpc32xx_gpi_get_value,
467 .request = lpc32xx_gpio_request,
468 .to_irq = lpc32xx_gpio_to_irq_gpi_p3,
469 .base = LPC32XX_GPI_P3_GRP,
470 .ngpio = LPC32XX_GPI_P3_MAX,
471 .names = gpi_p3_names,
472 .can_sleep = false,
473 },
474 .gpio_grp = &gpio_grp_regs_p3,
475 },
476 {
477 .chip = {
478 .label = "gpo_p3",
479 .direction_output = lpc32xx_gpio_dir_out_always,
480 .set = lpc32xx_gpo_set_value,
481 .get = lpc32xx_gpo_get_value,
482 .request = lpc32xx_gpio_request,
483 .base = LPC32XX_GPO_P3_GRP,
484 .ngpio = LPC32XX_GPO_P3_MAX,
485 .names = gpo_p3_names,
486 .can_sleep = false,
487 },
488 .gpio_grp = &gpio_grp_regs_p3,
489 },
490};
491
492static int lpc32xx_of_xlate(struct gpio_chip *gc,
493 const struct of_phandle_args *gpiospec, u32 *flags)
494{
495 /* Is this the correct bank? */
496 u32 bank = gpiospec->args[0];
497 if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
498 (gc != &lpc32xx_gpiochip[bank].chip)))
499 return -EINVAL;
500
501 if (flags)
502 *flags = gpiospec->args[2];
503 return gpiospec->args[1];
504}
505
506static int lpc32xx_gpio_probe(struct platform_device *pdev)
507{
508 int i;
509
510 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
511 if (pdev->dev.of_node) {
512 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
513 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
514 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
515 }
516 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
517 &lpc32xx_gpiochip[i]);
518 }
519
520 return 0;
521}
522
523#ifdef CONFIG_OF
524static const struct of_device_id lpc32xx_gpio_of_match[] = {
525 { .compatible = "nxp,lpc3220-gpio", },
526 { },
527};
528#endif
529
530static struct platform_driver lpc32xx_gpio_driver = {
531 .driver = {
532 .name = "lpc32xx-gpio",
533 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
534 },
535 .probe = lpc32xx_gpio_probe,
536};
537
538module_platform_driver(lpc32xx_gpio_driver);
539

Warning: That file was not part of the compilation database. It may have many parsing errors.