1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * linux/drivers/gpio/gpio-mb86s7x.c |
4 | * |
5 | * Copyright (C) 2015 Fujitsu Semiconductor Limited |
6 | * Copyright (C) 2015 Linaro Ltd. |
7 | */ |
8 | |
9 | #include <linux/acpi.h> |
10 | #include <linux/io.h> |
11 | #include <linux/init.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/mod_devicetable.h> |
14 | #include <linux/module.h> |
15 | #include <linux/err.h> |
16 | #include <linux/errno.h> |
17 | #include <linux/ioport.h> |
18 | #include <linux/gpio/driver.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/spinlock.h> |
21 | #include <linux/slab.h> |
22 | |
23 | #include "gpiolib-acpi.h" |
24 | |
25 | /* |
26 | * Only first 8bits of a register correspond to each pin, |
27 | * so there are 4 registers for 32 pins. |
28 | */ |
29 | #define PDR(x) (0x0 + x / 8 * 4) |
30 | #define DDR(x) (0x10 + x / 8 * 4) |
31 | #define PFR(x) (0x20 + x / 8 * 4) |
32 | |
33 | #define OFFSET(x) BIT((x) % 8) |
34 | |
35 | struct mb86s70_gpio_chip { |
36 | struct gpio_chip gc; |
37 | void __iomem *base; |
38 | struct clk *clk; |
39 | spinlock_t lock; |
40 | }; |
41 | |
42 | static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) |
43 | { |
44 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
45 | unsigned long flags; |
46 | u32 val; |
47 | |
48 | spin_lock_irqsave(&gchip->lock, flags); |
49 | |
50 | val = readl(addr: gchip->base + PFR(gpio)); |
51 | val &= ~OFFSET(gpio); |
52 | writel(val, addr: gchip->base + PFR(gpio)); |
53 | |
54 | spin_unlock_irqrestore(lock: &gchip->lock, flags); |
55 | |
56 | return 0; |
57 | } |
58 | |
59 | static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio) |
60 | { |
61 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
62 | unsigned long flags; |
63 | u32 val; |
64 | |
65 | spin_lock_irqsave(&gchip->lock, flags); |
66 | |
67 | val = readl(addr: gchip->base + PFR(gpio)); |
68 | val |= OFFSET(gpio); |
69 | writel(val, addr: gchip->base + PFR(gpio)); |
70 | |
71 | spin_unlock_irqrestore(lock: &gchip->lock, flags); |
72 | } |
73 | |
74 | static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) |
75 | { |
76 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
77 | unsigned long flags; |
78 | unsigned char val; |
79 | |
80 | spin_lock_irqsave(&gchip->lock, flags); |
81 | |
82 | val = readl(addr: gchip->base + DDR(gpio)); |
83 | val &= ~OFFSET(gpio); |
84 | writel(val, addr: gchip->base + DDR(gpio)); |
85 | |
86 | spin_unlock_irqrestore(lock: &gchip->lock, flags); |
87 | |
88 | return 0; |
89 | } |
90 | |
91 | static int mb86s70_gpio_direction_output(struct gpio_chip *gc, |
92 | unsigned gpio, int value) |
93 | { |
94 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
95 | unsigned long flags; |
96 | unsigned char val; |
97 | |
98 | spin_lock_irqsave(&gchip->lock, flags); |
99 | |
100 | val = readl(addr: gchip->base + PDR(gpio)); |
101 | if (value) |
102 | val |= OFFSET(gpio); |
103 | else |
104 | val &= ~OFFSET(gpio); |
105 | writel(val, addr: gchip->base + PDR(gpio)); |
106 | |
107 | val = readl(addr: gchip->base + DDR(gpio)); |
108 | val |= OFFSET(gpio); |
109 | writel(val, addr: gchip->base + DDR(gpio)); |
110 | |
111 | spin_unlock_irqrestore(lock: &gchip->lock, flags); |
112 | |
113 | return 0; |
114 | } |
115 | |
116 | static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio) |
117 | { |
118 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
119 | |
120 | return !!(readl(addr: gchip->base + PDR(gpio)) & OFFSET(gpio)); |
121 | } |
122 | |
123 | static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) |
124 | { |
125 | struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); |
126 | unsigned long flags; |
127 | unsigned char val; |
128 | |
129 | spin_lock_irqsave(&gchip->lock, flags); |
130 | |
131 | val = readl(addr: gchip->base + PDR(gpio)); |
132 | if (value) |
133 | val |= OFFSET(gpio); |
134 | else |
135 | val &= ~OFFSET(gpio); |
136 | writel(val, addr: gchip->base + PDR(gpio)); |
137 | |
138 | spin_unlock_irqrestore(lock: &gchip->lock, flags); |
139 | } |
140 | |
141 | static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) |
142 | { |
143 | int irq, index; |
144 | |
145 | for (index = 0;; index++) { |
146 | irq = platform_get_irq(to_platform_device(gc->parent), index); |
147 | if (irq < 0) |
148 | return irq; |
149 | if (irq == 0) |
150 | break; |
151 | if (irq_get_irq_data(irq)->hwirq == offset) |
152 | return irq; |
153 | } |
154 | return -EINVAL; |
155 | } |
156 | |
157 | static int mb86s70_gpio_probe(struct platform_device *pdev) |
158 | { |
159 | struct mb86s70_gpio_chip *gchip; |
160 | int ret; |
161 | |
162 | gchip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*gchip), GFP_KERNEL); |
163 | if (gchip == NULL) |
164 | return -ENOMEM; |
165 | |
166 | platform_set_drvdata(pdev, data: gchip); |
167 | |
168 | gchip->base = devm_platform_ioremap_resource(pdev, index: 0); |
169 | if (IS_ERR(ptr: gchip->base)) |
170 | return PTR_ERR(ptr: gchip->base); |
171 | |
172 | gchip->clk = devm_clk_get_optional(dev: &pdev->dev, NULL); |
173 | if (IS_ERR(ptr: gchip->clk)) |
174 | return PTR_ERR(ptr: gchip->clk); |
175 | |
176 | ret = clk_prepare_enable(clk: gchip->clk); |
177 | if (ret) |
178 | return ret; |
179 | |
180 | spin_lock_init(&gchip->lock); |
181 | |
182 | gchip->gc.direction_output = mb86s70_gpio_direction_output; |
183 | gchip->gc.direction_input = mb86s70_gpio_direction_input; |
184 | gchip->gc.request = mb86s70_gpio_request; |
185 | gchip->gc.free = mb86s70_gpio_free; |
186 | gchip->gc.get = mb86s70_gpio_get; |
187 | gchip->gc.set = mb86s70_gpio_set; |
188 | gchip->gc.to_irq = mb86s70_gpio_to_irq; |
189 | gchip->gc.label = dev_name(dev: &pdev->dev); |
190 | gchip->gc.ngpio = 32; |
191 | gchip->gc.owner = THIS_MODULE; |
192 | gchip->gc.parent = &pdev->dev; |
193 | gchip->gc.base = -1; |
194 | |
195 | ret = gpiochip_add_data(&gchip->gc, gchip); |
196 | if (ret) { |
197 | dev_err(&pdev->dev, "couldn't register gpio driver\n" ); |
198 | clk_disable_unprepare(clk: gchip->clk); |
199 | return ret; |
200 | } |
201 | |
202 | acpi_gpiochip_request_interrupts(chip: &gchip->gc); |
203 | |
204 | return 0; |
205 | } |
206 | |
207 | static void mb86s70_gpio_remove(struct platform_device *pdev) |
208 | { |
209 | struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); |
210 | |
211 | acpi_gpiochip_free_interrupts(chip: &gchip->gc); |
212 | gpiochip_remove(gc: &gchip->gc); |
213 | clk_disable_unprepare(clk: gchip->clk); |
214 | } |
215 | |
216 | static const struct of_device_id mb86s70_gpio_dt_ids[] = { |
217 | { .compatible = "fujitsu,mb86s70-gpio" }, |
218 | { /* sentinel */ } |
219 | }; |
220 | MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); |
221 | |
222 | #ifdef CONFIG_ACPI |
223 | static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = { |
224 | { "SCX0007" }, |
225 | { /* sentinel */ } |
226 | }; |
227 | MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids); |
228 | #endif |
229 | |
230 | static struct platform_driver mb86s70_gpio_driver = { |
231 | .driver = { |
232 | .name = "mb86s70-gpio" , |
233 | .of_match_table = mb86s70_gpio_dt_ids, |
234 | .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids), |
235 | }, |
236 | .probe = mb86s70_gpio_probe, |
237 | .remove_new = mb86s70_gpio_remove, |
238 | }; |
239 | module_platform_driver(mb86s70_gpio_driver); |
240 | |
241 | MODULE_DESCRIPTION("MB86S7x GPIO Driver" ); |
242 | MODULE_ALIAS("platform:mb86s70-gpio" ); |
243 | MODULE_LICENSE("GPL" ); |
244 | |