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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale vf610 GPIO support through PORT and GPIO
4 *
5 * Copyright (c) 2014 Toradex AG.
6 *
7 * Author: Stefan Agner <stefan@agner.ch>.
8 */
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/of_irq.h>
22
23#define VF610_GPIO_PER_PORT 32
24
25struct fsl_gpio_soc_data {
26 /* SoCs has a Port Data Direction Register (PDDR) */
27 bool have_paddr;
28};
29
30struct vf610_gpio_port {
31 struct gpio_chip gc;
32 void __iomem *base;
33 void __iomem *gpio_base;
34 const struct fsl_gpio_soc_data *sdata;
35 u8 irqc[VF610_GPIO_PER_PORT];
36 struct clk *clk_port;
37 struct clk *clk_gpio;
38 int irq;
39};
40
41#define GPIO_PDOR 0x00
42#define GPIO_PSOR 0x04
43#define GPIO_PCOR 0x08
44#define GPIO_PTOR 0x0c
45#define GPIO_PDIR 0x10
46#define GPIO_PDDR 0x14
47
48#define PORT_PCR(n) ((n) * 0x4)
49#define PORT_PCR_IRQC_OFFSET 16
50
51#define PORT_ISFR 0xa0
52#define PORT_DFER 0xc0
53#define PORT_DFCR 0xc4
54#define PORT_DFWR 0xc8
55
56#define PORT_INT_OFF 0x0
57#define PORT_INT_LOGIC_ZERO 0x8
58#define PORT_INT_RISING_EDGE 0x9
59#define PORT_INT_FALLING_EDGE 0xa
60#define PORT_INT_EITHER_EDGE 0xb
61#define PORT_INT_LOGIC_ONE 0xc
62
63static struct irq_chip vf610_gpio_irq_chip;
64
65static const struct fsl_gpio_soc_data imx_data = {
66 .have_paddr = true,
67};
68
69static const struct of_device_id vf610_gpio_dt_ids[] = {
70 { .compatible = "fsl,vf610-gpio", .data = NULL, },
71 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
72 { /* sentinel */ }
73};
74
75static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
76{
77 writel_relaxed(val, reg);
78}
79
80static inline u32 vf610_gpio_readl(void __iomem *reg)
81{
82 return readl_relaxed(reg);
83}
84
85static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
86{
87 struct vf610_gpio_port *port = gpiochip_get_data(gc);
88 unsigned long mask = BIT(gpio);
89 void __iomem *addr;
90
91 if (port->sdata && port->sdata->have_paddr) {
92 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
93 addr = mask ? port->gpio_base + GPIO_PDOR :
94 port->gpio_base + GPIO_PDIR;
95 return !!(vf610_gpio_readl(addr) & BIT(gpio));
96 } else {
97 return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR)
98 & BIT(gpio));
99 }
100}
101
102static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
103{
104 struct vf610_gpio_port *port = gpiochip_get_data(gc);
105 unsigned long mask = BIT(gpio);
106
107 if (val)
108 vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
109 else
110 vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
111}
112
113static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
114{
115 struct vf610_gpio_port *port = gpiochip_get_data(chip);
116 unsigned long mask = BIT(gpio);
117 u32 val;
118
119 if (port->sdata && port->sdata->have_paddr) {
120 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
121 val &= ~mask;
122 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
123 }
124
125 return pinctrl_gpio_direction_input(chip->base + gpio);
126}
127
128static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
129 int value)
130{
131 struct vf610_gpio_port *port = gpiochip_get_data(chip);
132 unsigned long mask = BIT(gpio);
133
134 if (port->sdata && port->sdata->have_paddr)
135 vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR);
136
137 vf610_gpio_set(chip, gpio, value);
138
139 return pinctrl_gpio_direction_output(chip->base + gpio);
140}
141
142static void vf610_gpio_irq_handler(struct irq_desc *desc)
143{
144 struct vf610_gpio_port *port =
145 gpiochip_get_data(irq_desc_get_handler_data(desc));
146 struct irq_chip *chip = irq_desc_get_chip(desc);
147 int pin;
148 unsigned long irq_isfr;
149
150 chained_irq_enter(chip, desc);
151
152 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
153
154 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
155 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
156
157 generic_handle_irq(irq_find_mapping(port->gc.irq.domain, pin));
158 }
159
160 chained_irq_exit(chip, desc);
161}
162
163static void vf610_gpio_irq_ack(struct irq_data *d)
164{
165 struct vf610_gpio_port *port =
166 gpiochip_get_data(irq_data_get_irq_chip_data(d));
167 int gpio = d->hwirq;
168
169 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
170}
171
172static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
173{
174 struct vf610_gpio_port *port =
175 gpiochip_get_data(irq_data_get_irq_chip_data(d));
176 u8 irqc;
177
178 switch (type) {
179 case IRQ_TYPE_EDGE_RISING:
180 irqc = PORT_INT_RISING_EDGE;
181 break;
182 case IRQ_TYPE_EDGE_FALLING:
183 irqc = PORT_INT_FALLING_EDGE;
184 break;
185 case IRQ_TYPE_EDGE_BOTH:
186 irqc = PORT_INT_EITHER_EDGE;
187 break;
188 case IRQ_TYPE_LEVEL_LOW:
189 irqc = PORT_INT_LOGIC_ZERO;
190 break;
191 case IRQ_TYPE_LEVEL_HIGH:
192 irqc = PORT_INT_LOGIC_ONE;
193 break;
194 default:
195 return -EINVAL;
196 }
197
198 port->irqc[d->hwirq] = irqc;
199
200 if (type & IRQ_TYPE_LEVEL_MASK)
201 irq_set_handler_locked(d, handle_level_irq);
202 else
203 irq_set_handler_locked(d, handle_edge_irq);
204
205 return 0;
206}
207
208static void vf610_gpio_irq_mask(struct irq_data *d)
209{
210 struct vf610_gpio_port *port =
211 gpiochip_get_data(irq_data_get_irq_chip_data(d));
212 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
213
214 vf610_gpio_writel(0, pcr_base);
215}
216
217static void vf610_gpio_irq_unmask(struct irq_data *d)
218{
219 struct vf610_gpio_port *port =
220 gpiochip_get_data(irq_data_get_irq_chip_data(d));
221 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
222
223 vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
224 pcr_base);
225}
226
227static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
228{
229 struct vf610_gpio_port *port =
230 gpiochip_get_data(irq_data_get_irq_chip_data(d));
231
232 if (enable)
233 enable_irq_wake(port->irq);
234 else
235 disable_irq_wake(port->irq);
236
237 return 0;
238}
239
240static struct irq_chip vf610_gpio_irq_chip = {
241 .name = "gpio-vf610",
242 .irq_ack = vf610_gpio_irq_ack,
243 .irq_mask = vf610_gpio_irq_mask,
244 .irq_unmask = vf610_gpio_irq_unmask,
245 .irq_set_type = vf610_gpio_irq_set_type,
246 .irq_set_wake = vf610_gpio_irq_set_wake,
247};
248
249static int vf610_gpio_probe(struct platform_device *pdev)
250{
251 struct device *dev = &pdev->dev;
252 struct device_node *np = dev->of_node;
253 struct vf610_gpio_port *port;
254 struct resource *iores;
255 struct gpio_chip *gc;
256 int i;
257 int ret;
258
259 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
260 if (!port)
261 return -ENOMEM;
262
263 port->sdata = of_device_get_match_data(dev);
264 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 port->base = devm_ioremap_resource(dev, iores);
266 if (IS_ERR(port->base))
267 return PTR_ERR(port->base);
268
269 iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
270 port->gpio_base = devm_ioremap_resource(dev, iores);
271 if (IS_ERR(port->gpio_base))
272 return PTR_ERR(port->gpio_base);
273
274 port->irq = platform_get_irq(pdev, 0);
275 if (port->irq < 0)
276 return port->irq;
277
278 port->clk_port = devm_clk_get(&pdev->dev, "port");
279 if (!IS_ERR(port->clk_port)) {
280 ret = clk_prepare_enable(port->clk_port);
281 if (ret)
282 return ret;
283 } else if (port->clk_port == ERR_PTR(-EPROBE_DEFER)) {
284 /*
285 * Percolate deferrals, for anything else,
286 * just live without the clocking.
287 */
288 return PTR_ERR(port->clk_port);
289 }
290
291 port->clk_gpio = devm_clk_get(&pdev->dev, "gpio");
292 if (!IS_ERR(port->clk_gpio)) {
293 ret = clk_prepare_enable(port->clk_gpio);
294 if (ret) {
295 clk_disable_unprepare(port->clk_port);
296 return ret;
297 }
298 } else if (port->clk_gpio == ERR_PTR(-EPROBE_DEFER)) {
299 clk_disable_unprepare(port->clk_port);
300 return PTR_ERR(port->clk_gpio);
301 }
302
303 platform_set_drvdata(pdev, port);
304
305 gc = &port->gc;
306 gc->of_node = np;
307 gc->parent = dev;
308 gc->label = "vf610-gpio";
309 gc->ngpio = VF610_GPIO_PER_PORT;
310 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
311
312 gc->request = gpiochip_generic_request;
313 gc->free = gpiochip_generic_free;
314 gc->direction_input = vf610_gpio_direction_input;
315 gc->get = vf610_gpio_get;
316 gc->direction_output = vf610_gpio_direction_output;
317 gc->set = vf610_gpio_set;
318
319 ret = gpiochip_add_data(gc, port);
320 if (ret < 0)
321 return ret;
322
323 /* Mask all GPIO interrupts */
324 for (i = 0; i < gc->ngpio; i++)
325 vf610_gpio_writel(0, port->base + PORT_PCR(i));
326
327 /* Clear the interrupt status register for all GPIO's */
328 vf610_gpio_writel(~0, port->base + PORT_ISFR);
329
330 ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0,
331 handle_edge_irq, IRQ_TYPE_NONE);
332 if (ret) {
333 dev_err(dev, "failed to add irqchip\n");
334 gpiochip_remove(gc);
335 return ret;
336 }
337 gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq,
338 vf610_gpio_irq_handler);
339
340 return 0;
341}
342
343static int vf610_gpio_remove(struct platform_device *pdev)
344{
345 struct vf610_gpio_port *port = platform_get_drvdata(pdev);
346
347 gpiochip_remove(&port->gc);
348 if (!IS_ERR(port->clk_port))
349 clk_disable_unprepare(port->clk_port);
350 if (!IS_ERR(port->clk_gpio))
351 clk_disable_unprepare(port->clk_gpio);
352
353 return 0;
354}
355
356static struct platform_driver vf610_gpio_driver = {
357 .driver = {
358 .name = "gpio-vf610",
359 .of_match_table = vf610_gpio_dt_ids,
360 },
361 .probe = vf610_gpio_probe,
362 .remove = vf610_gpio_remove,
363};
364
365builtin_platform_driver(vf610_gpio_driver);
366

Warning: That file was not part of the compilation database. It may have many parsing errors.