| 1 | /* |
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| 2 | * Copyright 2019 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef _AMDGPU_PMU_H_ |
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| 25 | #define _AMDGPU_PMU_H_ |
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| 26 | |
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| 27 | /* PMU types. */ |
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| 28 | enum amdgpu_pmu_perf_type { |
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| 29 | AMDGPU_PMU_PERF_TYPE_NONE = 0, |
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| 30 | AMDGPU_PMU_PERF_TYPE_DF, |
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| 31 | AMDGPU_PMU_PERF_TYPE_ALL |
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| 32 | }; |
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| 33 | |
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| 34 | /* |
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| 35 | * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type" |
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| 36 | * configurations. Event config types are parsed from the 64-bit raw |
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| 37 | * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and |
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| 38 | * are registered into the HW perf events config_base. |
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| 39 | * |
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| 40 | * PMU types with only a single event configuration type |
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| 41 | * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated |
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| 42 | * when the performance counter is added. |
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| 43 | */ |
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| 44 | enum amdgpu_pmu_event_config_type { |
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| 45 | AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0, |
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| 46 | AMDGPU_PMU_EVENT_CONFIG_TYPE_DF, |
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| 47 | AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI, |
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| 48 | AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX |
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| 49 | }; |
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| 50 | |
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| 51 | #define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT 56 |
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| 52 | #define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK 0xff |
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| 53 | |
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| 54 | int amdgpu_pmu_init(struct amdgpu_device *adev); |
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| 55 | void amdgpu_pmu_fini(struct amdgpu_device *adev); |
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| 56 | |
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| 57 | #endif /* _AMDGPU_PMU_H_ */ |
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| 58 | |
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