1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef _TA_RAS_IF_H |
25 | #define _TA_RAS_IF_H |
26 | |
27 | #define RAS_TA_HOST_IF_VER 0 |
28 | |
29 | /* Responses have bit 31 set */ |
30 | #define RSP_ID_MASK (1U << 31) |
31 | #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) |
32 | |
33 | /* RAS related enumerations */ |
34 | /**********************************************************/ |
35 | enum ras_command { |
36 | TA_RAS_COMMAND__ENABLE_FEATURES = 0, |
37 | TA_RAS_COMMAND__DISABLE_FEATURES, |
38 | TA_RAS_COMMAND__TRIGGER_ERROR, |
39 | TA_RAS_COMMAND__QUERY_BLOCK_INFO, |
40 | TA_RAS_COMMAND__QUERY_SUB_BLOCK_INFO, |
41 | TA_RAS_COMMAND__QUERY_ADDRESS, |
42 | }; |
43 | |
44 | enum ta_ras_status { |
45 | TA_RAS_STATUS__SUCCESS = 0x0000, |
46 | TA_RAS_STATUS__RESET_NEEDED = 0xA001, |
47 | TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002, |
48 | TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003, |
49 | TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004, |
50 | TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005, |
51 | TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006, |
52 | TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007, |
53 | TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008, |
54 | TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009, |
55 | TA_RAS_STATUS__ERROR_GENERIC = 0xA00A, |
56 | TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B, |
57 | TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C, |
58 | TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D, |
59 | TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E, |
60 | TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F, |
61 | TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010, |
62 | TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011, |
63 | TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012, |
64 | TA_RAS_STATUS__ERROR_NULL_PTR = 0xA013, |
65 | TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014, |
66 | TA_RAS_STATUS__ERROR_PCS_STATE_QUIET = 0xA015, |
67 | TA_RAS_STATUS__ERROR_PCS_STATE_ERROR = 0xA016, |
68 | TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017, |
69 | TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018, |
70 | TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019, |
71 | TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A |
72 | }; |
73 | |
74 | enum ta_ras_block { |
75 | TA_RAS_BLOCK__UMC = 0, |
76 | TA_RAS_BLOCK__SDMA, |
77 | TA_RAS_BLOCK__GFX, |
78 | TA_RAS_BLOCK__MMHUB, |
79 | TA_RAS_BLOCK__ATHUB, |
80 | TA_RAS_BLOCK__PCIE_BIF, |
81 | TA_RAS_BLOCK__HDP, |
82 | TA_RAS_BLOCK__XGMI_WAFL, |
83 | TA_RAS_BLOCK__DF, |
84 | TA_RAS_BLOCK__SMN, |
85 | TA_RAS_BLOCK__SEM, |
86 | TA_RAS_BLOCK__MP0, |
87 | TA_RAS_BLOCK__MP1, |
88 | TA_RAS_BLOCK__FUSE, |
89 | TA_RAS_BLOCK__MCA, |
90 | TA_RAS_BLOCK__VCN, |
91 | TA_RAS_BLOCK__JPEG, |
92 | TA_NUM_BLOCK_MAX |
93 | }; |
94 | |
95 | enum ta_ras_mca_block { |
96 | TA_RAS_MCA_BLOCK__MP0 = 0, |
97 | TA_RAS_MCA_BLOCK__MP1 = 1, |
98 | TA_RAS_MCA_BLOCK__MPIO = 2, |
99 | TA_RAS_MCA_BLOCK__IOHC = 3, |
100 | TA_MCA_NUM_BLOCK_MAX |
101 | }; |
102 | |
103 | enum ta_ras_error_type { |
104 | TA_RAS_ERROR__NONE = 0, |
105 | TA_RAS_ERROR__PARITY = 1, |
106 | TA_RAS_ERROR__SINGLE_CORRECTABLE = 2, |
107 | TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4, |
108 | TA_RAS_ERROR__POISON = 8, |
109 | }; |
110 | |
111 | enum ta_ras_address_type { |
112 | TA_RAS_MCA_TO_PA, |
113 | TA_RAS_PA_TO_MCA, |
114 | }; |
115 | |
116 | /* Input/output structures for RAS commands */ |
117 | /**********************************************************/ |
118 | |
119 | struct ta_ras_enable_features_input { |
120 | enum ta_ras_block block_id; |
121 | enum ta_ras_error_type error_type; |
122 | }; |
123 | |
124 | struct ta_ras_disable_features_input { |
125 | enum ta_ras_block block_id; |
126 | enum ta_ras_error_type error_type; |
127 | }; |
128 | |
129 | struct ta_ras_trigger_error_input { |
130 | enum ta_ras_block block_id; // ras-block. i.e. umc, gfx |
131 | enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable |
132 | uint32_t sub_block_index; // mem block. i.e. hbm, sram etc. |
133 | uint64_t address; // explicit address of error |
134 | uint64_t value; // method if error injection. i.e persistent, coherent etc. |
135 | }; |
136 | |
137 | struct ta_ras_init_flags { |
138 | uint8_t poison_mode_en; |
139 | uint8_t dgpu_mode; |
140 | uint16_t xcc_mask; |
141 | uint8_t channel_dis_num; |
142 | }; |
143 | |
144 | struct ta_ras_mca_addr { |
145 | uint64_t err_addr; |
146 | uint32_t ch_inst; |
147 | uint32_t umc_inst; |
148 | uint32_t node_inst; |
149 | }; |
150 | |
151 | struct ta_ras_phy_addr { |
152 | uint64_t pa; |
153 | uint32_t bank; |
154 | uint32_t channel_idx; |
155 | }; |
156 | |
157 | struct ta_ras_query_address_input { |
158 | enum ta_ras_address_type addr_type; |
159 | struct ta_ras_mca_addr ma; |
160 | struct ta_ras_phy_addr pa; |
161 | }; |
162 | |
163 | struct ta_ras_output_flags { |
164 | uint8_t ras_init_success_flag; |
165 | uint8_t err_inject_switch_disable_flag; |
166 | uint8_t reg_access_failure_flag; |
167 | }; |
168 | |
169 | struct ta_ras_query_address_output { |
170 | /* don't use the flags here */ |
171 | struct ta_ras_output_flags flags; |
172 | struct ta_ras_mca_addr ma; |
173 | struct ta_ras_phy_addr pa; |
174 | }; |
175 | |
176 | /* Common input structure for RAS callbacks */ |
177 | /**********************************************************/ |
178 | union ta_ras_cmd_input { |
179 | struct ta_ras_init_flags init_flags; |
180 | struct ta_ras_enable_features_input enable_features; |
181 | struct ta_ras_disable_features_input disable_features; |
182 | struct ta_ras_trigger_error_input trigger_error; |
183 | struct ta_ras_query_address_input address; |
184 | |
185 | uint32_t reserve_pad[256]; |
186 | }; |
187 | |
188 | union ta_ras_cmd_output { |
189 | struct ta_ras_output_flags flags; |
190 | struct ta_ras_query_address_output address; |
191 | |
192 | uint32_t reserve_pad[256]; |
193 | }; |
194 | |
195 | /* Shared Memory structures */ |
196 | /**********************************************************/ |
197 | struct ta_ras_shared_memory { |
198 | uint32_t cmd_id; |
199 | uint32_t resp_id; |
200 | uint32_t ras_status; |
201 | uint32_t if_version; |
202 | union ta_ras_cmd_input ras_in_message; |
203 | union ta_ras_cmd_output ras_out_message; |
204 | }; |
205 | |
206 | #endif // TL_RAS_IF_H_ |
207 | |