1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __KFD_TOPOLOGY_H__
24#define __KFD_TOPOLOGY_H__
25
26#include <linux/types.h>
27#include <linux/list.h>
28#include "kfd_crat.h"
29
30#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
31
32#define HSA_CAP_HOT_PLUGGABLE 0x00000001
33#define HSA_CAP_ATS_PRESENT 0x00000002
34#define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
35#define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
36#define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
37#define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
38#define HSA_CAP_VA_LIMIT 0x00000040
39#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
40#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
41#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
42#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
43#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
44#define HSA_CAP_RESERVED 0xffffc000
45
46#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
47#define HSA_CAP_DOORBELL_TYPE_1_0 0x1
48#define HSA_CAP_DOORBELL_TYPE_2_0 0x2
49#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
50
51struct kfd_node_properties {
52 uint64_t hive_id;
53 uint32_t cpu_cores_count;
54 uint32_t simd_count;
55 uint32_t mem_banks_count;
56 uint32_t caches_count;
57 uint32_t io_links_count;
58 uint32_t cpu_core_id_base;
59 uint32_t simd_id_base;
60 uint32_t capability;
61 uint32_t max_waves_per_simd;
62 uint32_t lds_size_in_kb;
63 uint32_t gds_size_in_kb;
64 uint32_t wave_front_size;
65 uint32_t array_count;
66 uint32_t simd_arrays_per_engine;
67 uint32_t cu_per_simd_array;
68 uint32_t simd_per_cu;
69 uint32_t max_slots_scratch_cu;
70 uint32_t engine_id;
71 uint32_t vendor_id;
72 uint32_t device_id;
73 uint32_t location_id;
74 uint32_t max_engine_clk_fcompute;
75 uint32_t max_engine_clk_ccompute;
76 int32_t drm_render_minor;
77 uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
78};
79
80#define HSA_MEM_HEAP_TYPE_SYSTEM 0
81#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
82#define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2
83#define HSA_MEM_HEAP_TYPE_GPU_GDS 3
84#define HSA_MEM_HEAP_TYPE_GPU_LDS 4
85#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5
86
87#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
88#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
89#define HSA_MEM_FLAGS_RESERVED 0xfffffffc
90
91struct kfd_mem_properties {
92 struct list_head list;
93 uint32_t heap_type;
94 uint64_t size_in_bytes;
95 uint32_t flags;
96 uint32_t width;
97 uint32_t mem_clk_max;
98 struct kobject *kobj;
99 struct attribute attr;
100};
101
102#define HSA_CACHE_TYPE_DATA 0x00000001
103#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
104#define HSA_CACHE_TYPE_CPU 0x00000004
105#define HSA_CACHE_TYPE_HSACU 0x00000008
106#define HSA_CACHE_TYPE_RESERVED 0xfffffff0
107
108struct kfd_cache_properties {
109 struct list_head list;
110 uint32_t processor_id_low;
111 uint32_t cache_level;
112 uint32_t cache_size;
113 uint32_t cacheline_size;
114 uint32_t cachelines_per_tag;
115 uint32_t cache_assoc;
116 uint32_t cache_latency;
117 uint32_t cache_type;
118 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
119 struct kobject *kobj;
120 struct attribute attr;
121};
122
123struct kfd_iolink_properties {
124 struct list_head list;
125 uint32_t iolink_type;
126 uint32_t ver_maj;
127 uint32_t ver_min;
128 uint32_t node_from;
129 uint32_t node_to;
130 uint32_t weight;
131 uint32_t min_latency;
132 uint32_t max_latency;
133 uint32_t min_bandwidth;
134 uint32_t max_bandwidth;
135 uint32_t rec_transfer_size;
136 uint32_t flags;
137 struct kobject *kobj;
138 struct attribute attr;
139};
140
141struct kfd_perf_properties {
142 struct list_head list;
143 char block_name[16];
144 uint32_t max_concurrent;
145 struct attribute_group *attr_group;
146};
147
148struct kfd_topology_device {
149 struct list_head list;
150 uint32_t gpu_id;
151 uint32_t proximity_domain;
152 struct kfd_node_properties node_props;
153 struct list_head mem_props;
154 uint32_t cache_count;
155 struct list_head cache_props;
156 uint32_t io_link_count;
157 struct list_head io_link_props;
158 struct list_head perf_props;
159 struct kfd_dev *gpu;
160 struct kobject *kobj_node;
161 struct kobject *kobj_mem;
162 struct kobject *kobj_cache;
163 struct kobject *kobj_iolink;
164 struct kobject *kobj_perf;
165 struct attribute attr_gpuid;
166 struct attribute attr_name;
167 struct attribute attr_props;
168 uint8_t oem_id[CRAT_OEMID_LENGTH];
169 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
170 uint32_t oem_revision;
171};
172
173struct kfd_system_properties {
174 uint32_t num_devices; /* Number of H-NUMA nodes */
175 uint32_t generation_count;
176 uint64_t platform_oem;
177 uint64_t platform_id;
178 uint64_t platform_rev;
179 struct kobject *kobj_topology;
180 struct kobject *kobj_nodes;
181 struct attribute attr_genid;
182 struct attribute attr_props;
183};
184
185struct kfd_topology_device *kfd_create_topology_device(
186 struct list_head *device_list);
187void kfd_release_topology_device_list(struct list_head *device_list);
188
189#endif /* __KFD_TOPOLOGY_H__ */
190