1 | /* |
2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DAL_DDC_SERVICE_H__ |
27 | #define __DAL_DDC_SERVICE_H__ |
28 | |
29 | #include "link.h" |
30 | |
31 | #define AUX_POWER_UP_WA_DELAY 500 |
32 | #define I2C_OVER_AUX_DEFER_WA_DELAY 70 |
33 | #define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40 |
34 | #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1 |
35 | #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ |
36 | #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/ |
37 | |
38 | #define EDID_SEGMENT_SIZE 256 |
39 | |
40 | struct ddc_service *link_create_ddc_service( |
41 | struct ddc_service_init_data *ddc_init_data); |
42 | |
43 | void link_destroy_ddc_service(struct ddc_service **ddc); |
44 | |
45 | void set_ddc_transaction_type( |
46 | struct ddc_service *ddc, |
47 | enum ddc_transaction_type type); |
48 | |
49 | uint32_t link_get_aux_defer_delay(struct ddc_service *ddc); |
50 | |
51 | bool link_is_in_aux_transaction_mode(struct ddc_service *ddc); |
52 | |
53 | bool try_to_configure_aux_timeout(struct ddc_service *ddc, |
54 | uint32_t timeout); |
55 | |
56 | bool link_query_ddc_data( |
57 | struct ddc_service *ddc, |
58 | uint32_t address, |
59 | uint8_t *write_buf, |
60 | uint32_t write_size, |
61 | uint8_t *read_buf, |
62 | uint32_t read_size); |
63 | |
64 | /* Attempt to submit an aux payload, retrying on timeouts, defers, and busy |
65 | * states as outlined in the DP spec. Returns true if the request was |
66 | * successful. |
67 | * |
68 | * NOTE: The function requires explicit mutex on DM side in order to prevent |
69 | * potential race condition. DC components should call the dpcd read/write |
70 | * function in dm_helpers in order to access dpcd safely |
71 | */ |
72 | bool link_aux_transfer_with_retries_no_mutex(struct ddc_service *ddc, |
73 | struct aux_payload *payload); |
74 | |
75 | bool link_configure_fixed_vs_pe_retimer( |
76 | struct ddc_service *ddc, |
77 | const uint8_t *data, |
78 | uint32_t length); |
79 | |
80 | bool link_query_fixed_vs_pe_retimer( |
81 | struct ddc_service *ddc, |
82 | uint8_t *data, |
83 | uint32_t length); |
84 | |
85 | uint32_t link_get_fixed_vs_pe_retimer_read_address(struct dc_link *link); |
86 | uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link); |
87 | |
88 | |
89 | void write_scdc_data( |
90 | struct ddc_service *ddc_service, |
91 | uint32_t pix_clk, |
92 | bool lte_340_scramble); |
93 | |
94 | void read_scdc_data( |
95 | struct ddc_service *ddc_service); |
96 | |
97 | void set_dongle_type(struct ddc_service *ddc, |
98 | enum display_dongle_type dongle_type); |
99 | |
100 | struct ddc *get_ddc_pin(struct ddc_service *ddc_service); |
101 | |
102 | int link_aux_transfer_raw(struct ddc_service *ddc, |
103 | struct aux_payload *payload, |
104 | enum aux_return_code_type *operation_result); |
105 | #endif /* __DAL_DDC_SERVICE_H__ */ |
106 | |
107 | |