| 1 | /* |
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| 2 | * Copyright 2012-15 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef __DC_TIMING_GENERATOR_DCN10_H__ |
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| 27 | #define __DC_TIMING_GENERATOR_DCN10_H__ |
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| 28 | |
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| 29 | #include "optc.h" |
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| 30 | |
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| 31 | #define DCN10TG_FROM_TG(tg)\ |
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| 32 | container_of(tg, struct optc, base) |
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| 33 | |
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| 34 | #define TG_COMMON_REG_LIST_DCN(inst) \ |
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| 35 | SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ |
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| 36 | SRI(OTG_VUPDATE_PARAM, OTG, inst),\ |
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| 37 | SRI(OTG_VREADY_PARAM, OTG, inst),\ |
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| 38 | SRI(OTG_BLANK_CONTROL, OTG, inst),\ |
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| 39 | SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ |
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| 40 | SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ |
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| 41 | SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ |
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| 42 | SRI(OTG_H_TOTAL, OTG, inst),\ |
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| 43 | SRI(OTG_H_BLANK_START_END, OTG, inst),\ |
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| 44 | SRI(OTG_H_SYNC_A, OTG, inst),\ |
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| 45 | SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ |
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| 46 | SRI(OTG_H_TIMING_CNTL, OTG, inst),\ |
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| 47 | SRI(OTG_V_TOTAL, OTG, inst),\ |
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| 48 | SRI(OTG_V_BLANK_START_END, OTG, inst),\ |
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| 49 | SRI(OTG_V_SYNC_A, OTG, inst),\ |
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| 50 | SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ |
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| 51 | SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ |
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| 52 | SRI(OTG_CONTROL, OTG, inst),\ |
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| 53 | SRI(OTG_STEREO_CONTROL, OTG, inst),\ |
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| 54 | SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ |
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| 55 | SRI(OTG_STEREO_STATUS, OTG, inst),\ |
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| 56 | SRI(OTG_V_TOTAL_MAX, OTG, inst),\ |
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| 57 | SRI(OTG_V_TOTAL_MID, OTG, inst),\ |
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| 58 | SRI(OTG_V_TOTAL_MIN, OTG, inst),\ |
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| 59 | SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ |
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| 60 | SRI(OTG_TRIGA_CNTL, OTG, inst),\ |
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| 61 | SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ |
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| 62 | SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ |
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| 63 | SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ |
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| 64 | SRI(OTG_STATUS, OTG, inst),\ |
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| 65 | SRI(OTG_STATUS_POSITION, OTG, inst),\ |
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| 66 | SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ |
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| 67 | SRI(OTG_BLACK_COLOR, OTG, inst),\ |
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| 68 | SRI(OTG_CLOCK_CONTROL, OTG, inst),\ |
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| 69 | SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ |
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| 70 | SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ |
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| 71 | SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ |
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| 72 | SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ |
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| 73 | SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ |
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| 74 | SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ |
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| 75 | SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ |
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| 76 | SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ |
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| 77 | SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ |
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| 78 | SRI(CONTROL, VTG, inst),\ |
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| 79 | SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ |
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| 80 | SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ |
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| 81 | SRI(OTG_GSL_CONTROL, OTG, inst),\ |
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| 82 | SRI(OTG_CRC_CNTL, OTG, inst),\ |
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| 83 | SRI(OTG_CRC0_DATA_RG, OTG, inst),\ |
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| 84 | SRI(OTG_CRC0_DATA_B, OTG, inst),\ |
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| 85 | SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ |
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| 86 | SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ |
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| 87 | SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ |
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| 88 | SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ |
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| 89 | SR(GSL_SOURCE_SELECT),\ |
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| 90 | SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ |
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| 91 | SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) |
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| 92 | |
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| 93 | #define TG_COMMON_REG_LIST_DCN1_0(inst) \ |
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| 94 | TG_COMMON_REG_LIST_DCN(inst),\ |
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| 95 | SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ |
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| 96 | SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ |
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| 97 | SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ |
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| 98 | SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) |
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| 99 | |
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| 100 | |
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| 101 | struct dcn_optc_registers { |
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| 102 | uint32_t OTG_GLOBAL_CONTROL1; |
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| 103 | uint32_t OTG_GLOBAL_CONTROL2; |
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| 104 | uint32_t OTG_VERT_SYNC_CONTROL; |
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| 105 | uint32_t OTG_MASTER_UPDATE_MODE; |
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| 106 | uint32_t OTG_GSL_CONTROL; |
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| 107 | uint32_t OTG_VSTARTUP_PARAM; |
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| 108 | uint32_t OTG_VUPDATE_PARAM; |
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| 109 | uint32_t OTG_VREADY_PARAM; |
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| 110 | uint32_t OTG_BLANK_CONTROL; |
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| 111 | uint32_t OTG_MASTER_UPDATE_LOCK; |
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| 112 | uint32_t OTG_GLOBAL_CONTROL0; |
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| 113 | uint32_t OTG_DOUBLE_BUFFER_CONTROL; |
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| 114 | uint32_t OTG_H_TOTAL; |
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| 115 | uint32_t OTG_H_BLANK_START_END; |
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| 116 | uint32_t OTG_H_SYNC_A; |
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| 117 | uint32_t OTG_H_SYNC_A_CNTL; |
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| 118 | uint32_t OTG_H_TIMING_CNTL; |
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| 119 | uint32_t OTG_V_TOTAL; |
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| 120 | uint32_t OTG_V_BLANK_START_END; |
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| 121 | uint32_t OTG_V_SYNC_A; |
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| 122 | uint32_t OTG_V_SYNC_A_CNTL; |
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| 123 | uint32_t OTG_INTERLACE_CONTROL; |
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| 124 | uint32_t OTG_CONTROL; |
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| 125 | uint32_t OTG_STEREO_CONTROL; |
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| 126 | uint32_t OTG_3D_STRUCTURE_CONTROL; |
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| 127 | uint32_t OTG_STEREO_STATUS; |
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| 128 | uint32_t OTG_V_TOTAL_MAX; |
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| 129 | uint32_t OTG_V_TOTAL_MID; |
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| 130 | uint32_t OTG_V_TOTAL_MIN; |
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| 131 | uint32_t OTG_V_TOTAL_CONTROL; |
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| 132 | uint32_t OTG_TRIGA_CNTL; |
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| 133 | uint32_t OTG_TRIGA_MANUAL_TRIG; |
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| 134 | uint32_t OTG_MANUAL_FLOW_CONTROL; |
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| 135 | uint32_t OTG_FORCE_COUNT_NOW_CNTL; |
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| 136 | uint32_t OTG_STATIC_SCREEN_CONTROL; |
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| 137 | uint32_t OTG_STATUS_FRAME_COUNT; |
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| 138 | uint32_t OTG_STATUS; |
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| 139 | uint32_t OTG_STATUS_POSITION; |
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| 140 | uint32_t OTG_NOM_VERT_POSITION; |
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| 141 | uint32_t OTG_BLACK_COLOR; |
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| 142 | uint32_t OTG_TEST_PATTERN_PARAMETERS; |
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| 143 | uint32_t OTG_TEST_PATTERN_CONTROL; |
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| 144 | uint32_t OTG_TEST_PATTERN_COLOR; |
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| 145 | uint32_t OTG_CLOCK_CONTROL; |
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| 146 | uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; |
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| 147 | uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; |
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| 148 | uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; |
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| 149 | uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; |
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| 150 | uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; |
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| 151 | uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; |
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| 152 | uint32_t OPTC_INPUT_CLOCK_CONTROL; |
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| 153 | uint32_t OPTC_DATA_SOURCE_SELECT; |
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| 154 | uint32_t OPTC_MEMORY_CONFIG; |
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| 155 | uint32_t OPTC_INPUT_GLOBAL_CONTROL; |
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| 156 | uint32_t CONTROL; |
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| 157 | uint32_t OTG_GSL_WINDOW_X; |
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| 158 | uint32_t OTG_GSL_WINDOW_Y; |
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| 159 | uint32_t OTG_VUPDATE_KEEPOUT; |
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| 160 | uint32_t OTG_CRC_CNTL; |
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| 161 | uint32_t OTG_CRC_CNTL2; |
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| 162 | uint32_t OTG_CRC0_DATA_RG; |
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| 163 | uint32_t OTG_CRC0_DATA_B; |
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| 164 | uint32_t OTG_CRC1_DATA_B; |
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| 165 | uint32_t OTG_CRC2_DATA_B; |
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| 166 | uint32_t OTG_CRC3_DATA_B; |
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| 167 | uint32_t OTG_CRC1_DATA_RG; |
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| 168 | uint32_t OTG_CRC2_DATA_RG; |
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| 169 | uint32_t OTG_CRC3_DATA_RG; |
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| 170 | uint32_t OTG_CRC0_WINDOWA_X_CONTROL; |
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| 171 | uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; |
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| 172 | uint32_t OTG_CRC0_WINDOWB_X_CONTROL; |
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| 173 | uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; |
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| 174 | uint32_t OTG_CRC1_WINDOWA_X_CONTROL; |
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| 175 | uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; |
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| 176 | uint32_t OTG_CRC1_WINDOWB_X_CONTROL; |
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| 177 | uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; |
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| 178 | uint32_t GSL_SOURCE_SELECT; |
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| 179 | uint32_t DWB_SOURCE_SELECT; |
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| 180 | uint32_t OTG_DSC_START_POSITION; |
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| 181 | uint32_t OPTC_DATA_FORMAT_CONTROL; |
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| 182 | uint32_t OPTC_BYTES_PER_PIXEL; |
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| 183 | uint32_t OPTC_WIDTH_CONTROL; |
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| 184 | uint32_t OTG_DRR_CONTROL; |
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| 185 | uint32_t OTG_BLANK_DATA_COLOR; |
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| 186 | uint32_t OTG_BLANK_DATA_COLOR_EXT; |
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| 187 | uint32_t OTG_DRR_TRIGGER_WINDOW; |
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| 188 | uint32_t OTG_M_CONST_DTO0; |
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| 189 | uint32_t OTG_M_CONST_DTO1; |
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| 190 | uint32_t OTG_DRR_V_TOTAL_CHANGE; |
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| 191 | uint32_t OTG_GLOBAL_CONTROL4; |
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| 192 | uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK; |
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| 193 | uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK; |
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| 194 | uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK; |
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| 195 | uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK; |
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| 196 | uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK; |
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| 197 | uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK; |
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| 198 | uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; |
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| 199 | uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; |
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| 200 | uint32_t OPTC_CLOCK_CONTROL; |
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| 201 | }; |
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| 202 | |
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| 203 | #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ |
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| 204 | SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ |
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| 205 | SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ |
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| 206 | SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ |
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| 207 | SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ |
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| 208 | SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ |
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| 209 | SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ |
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| 210 | SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ |
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| 211 | SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ |
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| 212 | SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ |
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| 213 | SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ |
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| 214 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ |
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| 215 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ |
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| 216 | SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ |
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| 217 | SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ |
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| 218 | SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ |
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| 219 | SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ |
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| 220 | SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ |
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| 221 | SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ |
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| 222 | SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ |
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| 223 | SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ |
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| 224 | SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ |
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| 225 | SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ |
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| 226 | SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ |
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| 227 | SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ |
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| 228 | SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ |
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| 229 | SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ |
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| 230 | SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ |
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| 231 | SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ |
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| 232 | SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ |
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| 233 | SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ |
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| 234 | SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ |
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| 235 | SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ |
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| 236 | SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ |
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| 237 | SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ |
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| 238 | SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ |
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| 239 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ |
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| 240 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ |
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| 241 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ |
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| 242 | SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ |
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| 243 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ |
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| 244 | SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ |
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| 245 | SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ |
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| 246 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ |
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| 247 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ |
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| 248 | SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ |
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| 249 | SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ |
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| 250 | SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ |
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| 251 | SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ |
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| 252 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ |
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| 253 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ |
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| 254 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ |
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| 255 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ |
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| 256 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ |
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| 257 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ |
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| 258 | SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ |
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| 259 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ |
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| 260 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ |
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| 261 | SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ |
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| 262 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ |
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| 263 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ |
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| 264 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ |
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| 265 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ |
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| 266 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ |
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| 267 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ |
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| 268 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ |
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| 269 | SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ |
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| 270 | SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ |
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| 271 | SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ |
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| 272 | SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ |
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| 273 | SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ |
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| 274 | SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ |
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| 275 | SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ |
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| 276 | SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ |
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| 277 | SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ |
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| 278 | SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ |
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| 279 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ |
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| 280 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ |
|---|
| 281 | SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ |
|---|
| 282 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ |
|---|
| 283 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ |
|---|
| 284 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ |
|---|
| 285 | SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ |
|---|
| 286 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ |
|---|
| 287 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ |
|---|
| 288 | SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ |
|---|
| 289 | SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ |
|---|
| 290 | SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ |
|---|
| 291 | SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ |
|---|
| 292 | SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ |
|---|
| 293 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ |
|---|
| 294 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ |
|---|
| 295 | SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ |
|---|
| 296 | SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ |
|---|
| 297 | SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ |
|---|
| 298 | SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ |
|---|
| 299 | SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ |
|---|
| 300 | SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ |
|---|
| 301 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ |
|---|
| 302 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ |
|---|
| 303 | SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ |
|---|
| 304 | SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ |
|---|
| 305 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ |
|---|
| 306 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ |
|---|
| 307 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ |
|---|
| 308 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ |
|---|
| 309 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ |
|---|
| 310 | SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ |
|---|
| 311 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ |
|---|
| 312 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ |
|---|
| 313 | SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ |
|---|
| 314 | SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ |
|---|
| 315 | SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ |
|---|
| 316 | SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ |
|---|
| 317 | SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ |
|---|
| 318 | SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ |
|---|
| 319 | SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ |
|---|
| 320 | SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ |
|---|
| 321 | SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ |
|---|
| 322 | SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ |
|---|
| 323 | SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ |
|---|
| 324 | SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ |
|---|
| 325 | SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ |
|---|
| 326 | SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ |
|---|
| 327 | SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ |
|---|
| 328 | SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) |
|---|
| 329 | |
|---|
| 330 | |
|---|
| 331 | |
|---|
| 332 | #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ |
|---|
| 333 | TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ |
|---|
| 334 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ |
|---|
| 335 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ |
|---|
| 336 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ |
|---|
| 337 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ |
|---|
| 338 | SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ |
|---|
| 339 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ |
|---|
| 340 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ |
|---|
| 341 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ |
|---|
| 342 | SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ |
|---|
| 343 | SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ |
|---|
| 344 | SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ |
|---|
| 345 | SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ |
|---|
| 346 | SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ |
|---|
| 347 | |
|---|
| 348 | #define TG_REG_FIELD_LIST_DCN1_0(type) \ |
|---|
| 349 | type VSTARTUP_START;\ |
|---|
| 350 | type VUPDATE_OFFSET;\ |
|---|
| 351 | type VUPDATE_WIDTH;\ |
|---|
| 352 | type VREADY_OFFSET;\ |
|---|
| 353 | type OTG_BLANK_DATA_EN;\ |
|---|
| 354 | type OTG_BLANK_DE_MODE;\ |
|---|
| 355 | type OTG_CURRENT_BLANK_STATE;\ |
|---|
| 356 | type OTG_MASTER_UPDATE_LOCK;\ |
|---|
| 357 | type UPDATE_LOCK_STATUS;\ |
|---|
| 358 | type OTG_UPDATE_PENDING;\ |
|---|
| 359 | type OTG_MASTER_UPDATE_LOCK_SEL;\ |
|---|
| 360 | type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ |
|---|
| 361 | type OTG_H_TOTAL;\ |
|---|
| 362 | type OTG_H_BLANK_START;\ |
|---|
| 363 | type OTG_H_BLANK_END;\ |
|---|
| 364 | type OTG_H_SYNC_A_START;\ |
|---|
| 365 | type OTG_H_SYNC_A_END;\ |
|---|
| 366 | type OTG_H_SYNC_A_POL;\ |
|---|
| 367 | type OTG_H_TIMING_DIV_BY2;\ |
|---|
| 368 | type OTG_V_TOTAL;\ |
|---|
| 369 | type OTG_V_BLANK_START;\ |
|---|
| 370 | type OTG_V_BLANK_END;\ |
|---|
| 371 | type OTG_V_SYNC_A_START;\ |
|---|
| 372 | type OTG_V_SYNC_A_END;\ |
|---|
| 373 | type OTG_V_SYNC_A_POL;\ |
|---|
| 374 | type OTG_INTERLACE_ENABLE;\ |
|---|
| 375 | type OTG_MASTER_EN;\ |
|---|
| 376 | type OTG_START_POINT_CNTL;\ |
|---|
| 377 | type OTG_DISABLE_POINT_CNTL;\ |
|---|
| 378 | type OTG_FIELD_NUMBER_CNTL;\ |
|---|
| 379 | type OTG_CURRENT_MASTER_EN_STATE;\ |
|---|
| 380 | type OTG_STEREO_EN;\ |
|---|
| 381 | type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ |
|---|
| 382 | type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ |
|---|
| 383 | type OTG_STEREO_EYE_FLAG_POLARITY;\ |
|---|
| 384 | type OTG_STEREO_CURRENT_EYE;\ |
|---|
| 385 | type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ |
|---|
| 386 | type OTG_3D_STRUCTURE_EN;\ |
|---|
| 387 | type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ |
|---|
| 388 | type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ |
|---|
| 389 | type OTG_V_TOTAL_MAX;\ |
|---|
| 390 | type OTG_V_TOTAL_MID;\ |
|---|
| 391 | type OTG_V_TOTAL_MIN;\ |
|---|
| 392 | type OTG_V_TOTAL_MIN_SEL;\ |
|---|
| 393 | type OTG_V_TOTAL_MAX_SEL;\ |
|---|
| 394 | type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ |
|---|
| 395 | type OTG_VTOTAL_MID_FRAME_NUM;\ |
|---|
| 396 | type OTG_FORCE_LOCK_ON_EVENT;\ |
|---|
| 397 | type OTG_SET_V_TOTAL_MIN_MASK_EN;\ |
|---|
| 398 | type OTG_SET_V_TOTAL_MIN_MASK;\ |
|---|
| 399 | type OTG_FORCE_COUNT_NOW_CLEAR;\ |
|---|
| 400 | type OTG_FORCE_COUNT_NOW_MODE;\ |
|---|
| 401 | type OTG_FORCE_COUNT_NOW_OCCURRED;\ |
|---|
| 402 | type OTG_TRIGA_SOURCE_SELECT;\ |
|---|
| 403 | type OTG_TRIGA_SOURCE_PIPE_SELECT;\ |
|---|
| 404 | type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ |
|---|
| 405 | type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ |
|---|
| 406 | type OTG_TRIGA_POLARITY_SELECT;\ |
|---|
| 407 | type OTG_TRIGA_FREQUENCY_SELECT;\ |
|---|
| 408 | type OTG_TRIGA_DELAY;\ |
|---|
| 409 | type OTG_TRIGA_CLEAR;\ |
|---|
| 410 | type OTG_TRIGA_MANUAL_TRIG;\ |
|---|
| 411 | type OTG_STATIC_SCREEN_EVENT_MASK;\ |
|---|
| 412 | type OTG_STATIC_SCREEN_FRAME_COUNT;\ |
|---|
| 413 | type OTG_FRAME_COUNT;\ |
|---|
| 414 | type OTG_V_BLANK;\ |
|---|
| 415 | type OTG_V_ACTIVE_DISP;\ |
|---|
| 416 | type OTG_HORZ_COUNT;\ |
|---|
| 417 | type OTG_VERT_COUNT;\ |
|---|
| 418 | type OTG_VERT_COUNT_NOM;\ |
|---|
| 419 | type OTG_BLACK_COLOR_B_CB;\ |
|---|
| 420 | type OTG_BLACK_COLOR_G_Y;\ |
|---|
| 421 | type OTG_BLACK_COLOR_R_CR;\ |
|---|
| 422 | type OTG_BLANK_DATA_COLOR_BLUE_CB;\ |
|---|
| 423 | type OTG_BLANK_DATA_COLOR_GREEN_Y;\ |
|---|
| 424 | type OTG_BLANK_DATA_COLOR_RED_CR;\ |
|---|
| 425 | type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\ |
|---|
| 426 | type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\ |
|---|
| 427 | type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\ |
|---|
| 428 | type OTG_VTOTAL_MID_REPLACING_MIN_EN;\ |
|---|
| 429 | type OTG_TEST_PATTERN_INC0;\ |
|---|
| 430 | type OTG_TEST_PATTERN_INC1;\ |
|---|
| 431 | type OTG_TEST_PATTERN_VRES;\ |
|---|
| 432 | type OTG_TEST_PATTERN_HRES;\ |
|---|
| 433 | type OTG_TEST_PATTERN_RAMP0_OFFSET;\ |
|---|
| 434 | type OTG_TEST_PATTERN_EN;\ |
|---|
| 435 | type OTG_TEST_PATTERN_MODE;\ |
|---|
| 436 | type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ |
|---|
| 437 | type OTG_TEST_PATTERN_COLOR_FORMAT;\ |
|---|
| 438 | type OTG_TEST_PATTERN_MASK;\ |
|---|
| 439 | type OTG_TEST_PATTERN_DATA;\ |
|---|
| 440 | type OTG_BUSY;\ |
|---|
| 441 | type OTG_CLOCK_EN;\ |
|---|
| 442 | type OTG_CLOCK_ON;\ |
|---|
| 443 | type OTG_CLOCK_GATE_DIS;\ |
|---|
| 444 | type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ |
|---|
| 445 | type OTG_VERTICAL_INTERRUPT0_LINE_START;\ |
|---|
| 446 | type OTG_VERTICAL_INTERRUPT0_LINE_END;\ |
|---|
| 447 | type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ |
|---|
| 448 | type OTG_VERTICAL_INTERRUPT1_LINE_START;\ |
|---|
| 449 | type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ |
|---|
| 450 | type OTG_VERTICAL_INTERRUPT2_LINE_START;\ |
|---|
| 451 | type OPTC_INPUT_CLK_EN;\ |
|---|
| 452 | type OPTC_INPUT_CLK_ON;\ |
|---|
| 453 | type OPTC_INPUT_CLK_GATE_DIS;\ |
|---|
| 454 | type OPTC_UNDERFLOW_OCCURRED_STATUS;\ |
|---|
| 455 | type OPTC_UNDERFLOW_CLEAR;\ |
|---|
| 456 | type OPTC_SRC_SEL;\ |
|---|
| 457 | type VTG0_ENABLE;\ |
|---|
| 458 | type VTG0_FP2;\ |
|---|
| 459 | type VTG0_VCOUNT_INIT;\ |
|---|
| 460 | type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ |
|---|
| 461 | type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ |
|---|
| 462 | type OTG_AUTO_FORCE_VSYNC_MODE;\ |
|---|
| 463 | type MASTER_UPDATE_INTERLACED_MODE;\ |
|---|
| 464 | type OTG_GSL0_EN;\ |
|---|
| 465 | type OTG_GSL1_EN;\ |
|---|
| 466 | type OTG_GSL2_EN;\ |
|---|
| 467 | type OTG_GSL_MASTER_EN;\ |
|---|
| 468 | type OTG_GSL_FORCE_DELAY;\ |
|---|
| 469 | type OTG_GSL_CHECK_ALL_FIELDS;\ |
|---|
| 470 | type OTG_GSL_WINDOW_START_X;\ |
|---|
| 471 | type OTG_GSL_WINDOW_END_X;\ |
|---|
| 472 | type OTG_GSL_WINDOW_START_Y;\ |
|---|
| 473 | type OTG_GSL_WINDOW_END_Y;\ |
|---|
| 474 | type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ |
|---|
| 475 | type OTG_GSL_MASTER_MODE;\ |
|---|
| 476 | type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ |
|---|
| 477 | type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ |
|---|
| 478 | type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ |
|---|
| 479 | type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ |
|---|
| 480 | type OTG_CRC_CONT_EN;\ |
|---|
| 481 | type OTG_CRC0_SELECT;\ |
|---|
| 482 | type OTG_CRC_EN;\ |
|---|
| 483 | type CRC0_R_CR;\ |
|---|
| 484 | type CRC0_G_Y;\ |
|---|
| 485 | type CRC0_B_CB;\ |
|---|
| 486 | type CRC1_R_CR;\ |
|---|
| 487 | type CRC1_G_Y;\ |
|---|
| 488 | type CRC1_B_CB;\ |
|---|
| 489 | type CRC2_R_CR;\ |
|---|
| 490 | type CRC2_G_Y;\ |
|---|
| 491 | type CRC2_B_CB;\ |
|---|
| 492 | type CRC3_R_CR;\ |
|---|
| 493 | type CRC3_G_Y;\ |
|---|
| 494 | type CRC3_B_CB;\ |
|---|
| 495 | type OTG_CRC0_WINDOWA_X_START;\ |
|---|
| 496 | type OTG_CRC0_WINDOWA_X_END;\ |
|---|
| 497 | type OTG_CRC0_WINDOWA_Y_START;\ |
|---|
| 498 | type OTG_CRC0_WINDOWA_Y_END;\ |
|---|
| 499 | type OTG_CRC0_WINDOWB_X_START;\ |
|---|
| 500 | type OTG_CRC0_WINDOWB_X_END;\ |
|---|
| 501 | type OTG_CRC0_WINDOWB_Y_START;\ |
|---|
| 502 | type OTG_CRC0_WINDOWB_Y_END;\ |
|---|
| 503 | type OTG_CRC_WINDOW_DB_EN;\ |
|---|
| 504 | type OTG_CRC1_WINDOWA_X_START;\ |
|---|
| 505 | type OTG_CRC1_WINDOWA_X_END;\ |
|---|
| 506 | type OTG_CRC1_WINDOWA_Y_START;\ |
|---|
| 507 | type OTG_CRC1_WINDOWA_Y_END;\ |
|---|
| 508 | type OTG_CRC1_WINDOWB_X_START;\ |
|---|
| 509 | type OTG_CRC1_WINDOWB_X_END;\ |
|---|
| 510 | type OTG_CRC1_WINDOWB_Y_START;\ |
|---|
| 511 | type OTG_CRC1_WINDOWB_Y_END;\ |
|---|
| 512 | type GSL0_READY_SOURCE_SEL;\ |
|---|
| 513 | type GSL1_READY_SOURCE_SEL;\ |
|---|
| 514 | type GSL2_READY_SOURCE_SEL;\ |
|---|
| 515 | type MANUAL_FLOW_CONTROL;\ |
|---|
| 516 | type MANUAL_FLOW_CONTROL_SEL; |
|---|
| 517 | |
|---|
| 518 | #define TG_REG_FIELD_LIST(type) \ |
|---|
| 519 | TG_REG_FIELD_LIST_DCN1_0(type)\ |
|---|
| 520 | type OTG_V_SYNC_MODE;\ |
|---|
| 521 | type OTG_DRR_TRIGGER_WINDOW_START_X;\ |
|---|
| 522 | type OTG_DRR_TRIGGER_WINDOW_END_X;\ |
|---|
| 523 | type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\ |
|---|
| 524 | type OTG_OUT_MUX;\ |
|---|
| 525 | type OTG_M_CONST_DTO_PHASE;\ |
|---|
| 526 | type OTG_M_CONST_DTO_MODULO;\ |
|---|
| 527 | type MASTER_UPDATE_LOCK_DB_X;\ |
|---|
| 528 | type MASTER_UPDATE_LOCK_DB_Y;\ |
|---|
| 529 | type MASTER_UPDATE_LOCK_DB_EN;\ |
|---|
| 530 | type GLOBAL_UPDATE_LOCK_EN;\ |
|---|
| 531 | type DIG_UPDATE_LOCATION;\ |
|---|
| 532 | type OTG_DSC_START_POSITION_X;\ |
|---|
| 533 | type OTG_DSC_START_POSITION_LINE_NUM;\ |
|---|
| 534 | type OPTC_NUM_OF_INPUT_SEGMENT;\ |
|---|
| 535 | type OPTC_SEG0_SRC_SEL;\ |
|---|
| 536 | type OPTC_SEG1_SRC_SEL;\ |
|---|
| 537 | type OPTC_SEG2_SRC_SEL;\ |
|---|
| 538 | type OPTC_SEG3_SRC_SEL;\ |
|---|
| 539 | type OPTC_MEM_SEL;\ |
|---|
| 540 | type OPTC_DATA_FORMAT;\ |
|---|
| 541 | type OPTC_DSC_MODE;\ |
|---|
| 542 | type OPTC_DSC_BYTES_PER_PIXEL;\ |
|---|
| 543 | type OPTC_DSC_SLICE_WIDTH;\ |
|---|
| 544 | type OPTC_SEGMENT_WIDTH;\ |
|---|
| 545 | type OPTC_DWB0_SOURCE_SELECT;\ |
|---|
| 546 | type OPTC_DWB1_SOURCE_SELECT;\ |
|---|
| 547 | type MASTER_UPDATE_LOCK_DB_START_X;\ |
|---|
| 548 | type MASTER_UPDATE_LOCK_DB_END_X;\ |
|---|
| 549 | type MASTER_UPDATE_LOCK_DB_START_Y;\ |
|---|
| 550 | type MASTER_UPDATE_LOCK_DB_END_Y;\ |
|---|
| 551 | type DIG_UPDATE_POSITION_X;\ |
|---|
| 552 | type DIG_UPDATE_POSITION_Y;\ |
|---|
| 553 | type OTG_H_TIMING_DIV_MODE;\ |
|---|
| 554 | type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ |
|---|
| 555 | type OTG_CRC_DSC_MODE;\ |
|---|
| 556 | type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ |
|---|
| 557 | type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ |
|---|
| 558 | type OTG_CRC_DATA_FORMAT;\ |
|---|
| 559 | type OTG_V_TOTAL_LAST_USED_BY_DRR;\ |
|---|
| 560 | type OTG_DRR_TIMING_DBUF_UPDATE_PENDING;\ |
|---|
| 561 | type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING; |
|---|
| 562 | |
|---|
| 563 | #define TG_REG_FIELD_LIST_DCN3_2(type) \ |
|---|
| 564 | type OTG_H_TIMING_DIV_MODE_MANUAL; |
|---|
| 565 | |
|---|
| 566 | |
|---|
| 567 | #define TG_REG_FIELD_LIST_DCN3_5(type) \ |
|---|
| 568 | type OTG_CRC0_WINDOWA_X_START_READBACK;\ |
|---|
| 569 | type OTG_CRC0_WINDOWA_X_END_READBACK;\ |
|---|
| 570 | type OTG_CRC0_WINDOWA_Y_START_READBACK;\ |
|---|
| 571 | type OTG_CRC0_WINDOWA_Y_END_READBACK;\ |
|---|
| 572 | type OTG_CRC0_WINDOWB_X_START_READBACK;\ |
|---|
| 573 | type OTG_CRC0_WINDOWB_X_END_READBACK;\ |
|---|
| 574 | type OTG_CRC0_WINDOWB_Y_START_READBACK;\ |
|---|
| 575 | type OTG_CRC0_WINDOWB_Y_END_READBACK; \ |
|---|
| 576 | type OTG_CRC1_WINDOWA_X_START_READBACK;\ |
|---|
| 577 | type OTG_CRC1_WINDOWA_X_END_READBACK;\ |
|---|
| 578 | type OTG_CRC1_WINDOWA_Y_START_READBACK;\ |
|---|
| 579 | type OTG_CRC1_WINDOWA_Y_END_READBACK;\ |
|---|
| 580 | type OTG_CRC1_WINDOWB_X_START_READBACK;\ |
|---|
| 581 | type OTG_CRC1_WINDOWB_X_END_READBACK;\ |
|---|
| 582 | type OTG_CRC1_WINDOWB_Y_START_READBACK;\ |
|---|
| 583 | type OTG_CRC1_WINDOWB_Y_END_READBACK;\ |
|---|
| 584 | type OPTC_FGCG_REP_DIS; |
|---|
| 585 | |
|---|
| 586 | struct dcn_optc_shift { |
|---|
| 587 | TG_REG_FIELD_LIST(uint8_t) |
|---|
| 588 | TG_REG_FIELD_LIST_DCN3_2(uint8_t) |
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| 589 | TG_REG_FIELD_LIST_DCN3_5(uint8_t) |
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| 590 | }; |
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| 591 | |
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| 592 | struct dcn_optc_mask { |
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| 593 | TG_REG_FIELD_LIST(uint32_t) |
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| 594 | TG_REG_FIELD_LIST_DCN3_2(uint32_t) |
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| 595 | TG_REG_FIELD_LIST_DCN3_5(uint32_t) |
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| 596 | }; |
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| 597 | |
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| 598 | void dcn10_timing_generator_init(struct optc *optc); |
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| 599 | |
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| 600 | #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ |
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| 601 | |
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