1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _athub_1_8_0_OFFSET_HEADER |
24 | #define |
25 | |
26 | |
27 | |
28 | // addressBlock: aid_athub_atsdec |
29 | // base address: 0x3080 |
30 | #define regATC_ATS_CNTL 0x0000 |
31 | #define regATC_ATS_CNTL_BASE_IDX 0 |
32 | #define regATC_ATS_CNTL2 0x0001 |
33 | #define regATC_ATS_CNTL2_BASE_IDX 0 |
34 | #define regATC_ATS_CNTL3 0x0002 |
35 | #define regATC_ATS_CNTL3_BASE_IDX 0 |
36 | #define regATC_ATS_CNTL4 0x0003 |
37 | #define regATC_ATS_CNTL4_BASE_IDX 0 |
38 | #define regATC_ATS_MISC_CNTL 0x0005 |
39 | #define regATC_ATS_MISC_CNTL_BASE_IDX 0 |
40 | #define regATC_ATS_STATUS 0x0009 |
41 | #define regATC_ATS_STATUS_BASE_IDX 0 |
42 | #define regATC_PERFCOUNTER0_CFG 0x000a |
43 | #define regATC_PERFCOUNTER0_CFG_BASE_IDX 0 |
44 | #define regATC_PERFCOUNTER1_CFG 0x000b |
45 | #define regATC_PERFCOUNTER1_CFG_BASE_IDX 0 |
46 | #define regATC_PERFCOUNTER2_CFG 0x000c |
47 | #define regATC_PERFCOUNTER2_CFG_BASE_IDX 0 |
48 | #define regATC_PERFCOUNTER3_CFG 0x000d |
49 | #define regATC_PERFCOUNTER3_CFG_BASE_IDX 0 |
50 | #define regATC_PERFCOUNTER_RSLT_CNTL 0x000e |
51 | #define regATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
52 | #define regATC_PERFCOUNTER_LO 0x000f |
53 | #define regATC_PERFCOUNTER_LO_BASE_IDX 0 |
54 | #define regATC_PERFCOUNTER_HI 0x0010 |
55 | #define regATC_PERFCOUNTER_HI_BASE_IDX 0 |
56 | #define regATC_ATS_FAULT_CNTL 0x0012 |
57 | #define regATC_ATS_FAULT_CNTL_BASE_IDX 0 |
58 | #define regATC_ATS_FAULT_STATUS_INFO 0x0013 |
59 | #define regATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 |
60 | #define regATC_ATS_FAULT_STATUS_INFO2 0x0014 |
61 | #define regATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 |
62 | #define regATC_ATS_FAULT_STATUS_INFO3 0x0015 |
63 | #define regATC_ATS_FAULT_STATUS_INFO3_BASE_IDX 0 |
64 | #define regATC_ATS_FAULT_STATUS_INFO4 0x0016 |
65 | #define regATC_ATS_FAULT_STATUS_INFO4_BASE_IDX 0 |
66 | #define regATC_ATS_FAULT_STATUS_ADDR 0x0017 |
67 | #define regATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 |
68 | #define regATC_ATS_DEFAULT_PAGE_LOW 0x0018 |
69 | #define regATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 |
70 | #define regATHUB_PCIE_ATS_CNTL 0x001f |
71 | #define regATHUB_PCIE_ATS_CNTL_BASE_IDX 0 |
72 | #define regATHUB_PCIE_PASID_CNTL 0x0020 |
73 | #define regATHUB_PCIE_PASID_CNTL_BASE_IDX 0 |
74 | #define regATHUB_PCIE_PAGE_REQ_CNTL 0x0021 |
75 | #define regATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 |
76 | #define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0022 |
77 | #define regATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 |
78 | #define regATHUB_COMMAND 0x0023 |
79 | #define regATHUB_COMMAND_BASE_IDX 0 |
80 | #define regATHUB_PCIE_ATS_CNTL_VF_0 0x0024 |
81 | #define regATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 |
82 | #define regATHUB_PCIE_ATS_CNTL_VF_1 0x0025 |
83 | #define regATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 |
84 | #define regATHUB_PCIE_ATS_CNTL_VF_2 0x0026 |
85 | #define regATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 |
86 | #define regATHUB_PCIE_ATS_CNTL_VF_3 0x0027 |
87 | #define regATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 |
88 | #define regATHUB_PCIE_ATS_CNTL_VF_4 0x0028 |
89 | #define regATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 |
90 | #define regATHUB_PCIE_ATS_CNTL_VF_5 0x0029 |
91 | #define regATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 |
92 | #define regATHUB_PCIE_ATS_CNTL_VF_6 0x002a |
93 | #define regATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 |
94 | #define regATHUB_PCIE_ATS_CNTL_VF_7 0x002b |
95 | #define regATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 |
96 | #define regATHUB_PCIE_ATS_CNTL_VF_8 0x002c |
97 | #define regATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 |
98 | #define regATHUB_PCIE_ATS_CNTL_VF_9 0x002d |
99 | #define regATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 |
100 | #define regATHUB_PCIE_ATS_CNTL_VF_10 0x002e |
101 | #define regATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 |
102 | #define regATHUB_PCIE_ATS_CNTL_VF_11 0x002f |
103 | #define regATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 |
104 | #define regATHUB_PCIE_ATS_CNTL_VF_12 0x0030 |
105 | #define regATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 |
106 | #define regATHUB_PCIE_ATS_CNTL_VF_13 0x0031 |
107 | #define regATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 |
108 | #define regATHUB_PCIE_ATS_CNTL_VF_14 0x0032 |
109 | #define regATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 |
110 | #define regATHUB_PCIE_ATS_CNTL_VF_15 0x0033 |
111 | #define regATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 |
112 | #define regATHUB_SHARED_VIRT_RESET_REQ 0x0034 |
113 | #define regATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 |
114 | #define regATHUB_SHARED_ACTIVE_FCN_ID 0x0036 |
115 | #define regATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 |
116 | #define regATC_ATS_SDPPORT_CNTL 0x0038 |
117 | #define regATC_ATS_SDPPORT_CNTL_BASE_IDX 0 |
118 | #define regATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x003e |
119 | #define regATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 |
120 | #define regATC_VMID0_PASID_MAPPING 0x003f |
121 | #define regATC_VMID0_PASID_MAPPING_BASE_IDX 0 |
122 | #define regATC_VMID1_PASID_MAPPING 0x0040 |
123 | #define regATC_VMID1_PASID_MAPPING_BASE_IDX 0 |
124 | #define regATC_VMID2_PASID_MAPPING 0x0041 |
125 | #define regATC_VMID2_PASID_MAPPING_BASE_IDX 0 |
126 | #define regATC_VMID3_PASID_MAPPING 0x0042 |
127 | #define regATC_VMID3_PASID_MAPPING_BASE_IDX 0 |
128 | #define regATC_VMID4_PASID_MAPPING 0x0043 |
129 | #define regATC_VMID4_PASID_MAPPING_BASE_IDX 0 |
130 | #define regATC_VMID5_PASID_MAPPING 0x0044 |
131 | #define regATC_VMID5_PASID_MAPPING_BASE_IDX 0 |
132 | #define regATC_VMID6_PASID_MAPPING 0x0045 |
133 | #define regATC_VMID6_PASID_MAPPING_BASE_IDX 0 |
134 | #define regATC_VMID7_PASID_MAPPING 0x0046 |
135 | #define regATC_VMID7_PASID_MAPPING_BASE_IDX 0 |
136 | #define regATC_VMID8_PASID_MAPPING 0x0047 |
137 | #define regATC_VMID8_PASID_MAPPING_BASE_IDX 0 |
138 | #define regATC_VMID9_PASID_MAPPING 0x0048 |
139 | #define regATC_VMID9_PASID_MAPPING_BASE_IDX 0 |
140 | #define regATC_VMID10_PASID_MAPPING 0x0049 |
141 | #define regATC_VMID10_PASID_MAPPING_BASE_IDX 0 |
142 | #define regATC_VMID11_PASID_MAPPING 0x004a |
143 | #define regATC_VMID11_PASID_MAPPING_BASE_IDX 0 |
144 | #define regATC_VMID12_PASID_MAPPING 0x004b |
145 | #define regATC_VMID12_PASID_MAPPING_BASE_IDX 0 |
146 | #define regATC_VMID13_PASID_MAPPING 0x004c |
147 | #define regATC_VMID13_PASID_MAPPING_BASE_IDX 0 |
148 | #define regATC_VMID14_PASID_MAPPING 0x004d |
149 | #define regATC_VMID14_PASID_MAPPING_BASE_IDX 0 |
150 | #define regATC_VMID15_PASID_MAPPING 0x004e |
151 | #define regATC_VMID15_PASID_MAPPING_BASE_IDX 0 |
152 | #define regATC_TRANS_FAULT_RSPCNTRL 0x0050 |
153 | #define regATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 |
154 | #define regATC_ATS_VMID_STATUS 0x0051 |
155 | #define regATC_ATS_VMID_STATUS_BASE_IDX 0 |
156 | #define regATHUB_MISC_CNTL 0x0055 |
157 | #define regATHUB_MISC_CNTL_BASE_IDX 0 |
158 | #define regATHUB_MEM_POWER_LS 0x0056 |
159 | #define regATHUB_MEM_POWER_LS_BASE_IDX 0 |
160 | #define regATHUB_IH_CREDIT 0x0057 |
161 | #define regATHUB_IH_CREDIT_BASE_IDX 0 |
162 | |
163 | |
164 | // addressBlock: aid_athub_xpbdec |
165 | // base address: 0x46000 |
166 | #define regXPB_RTR_SRC_APRTR0 0x0000 |
167 | #define regXPB_RTR_SRC_APRTR0_BASE_IDX 1 |
168 | #define regXPB_RTR_SRC_APRTR1 0x0001 |
169 | #define regXPB_RTR_SRC_APRTR1_BASE_IDX 1 |
170 | #define regXPB_RTR_SRC_APRTR2 0x0002 |
171 | #define regXPB_RTR_SRC_APRTR2_BASE_IDX 1 |
172 | #define regXPB_RTR_SRC_APRTR3 0x0003 |
173 | #define regXPB_RTR_SRC_APRTR3_BASE_IDX 1 |
174 | #define regXPB_RTR_SRC_APRTR4 0x0004 |
175 | #define regXPB_RTR_SRC_APRTR4_BASE_IDX 1 |
176 | #define regXPB_RTR_SRC_APRTR5 0x0005 |
177 | #define regXPB_RTR_SRC_APRTR5_BASE_IDX 1 |
178 | #define regXPB_RTR_SRC_APRTR6 0x0006 |
179 | #define regXPB_RTR_SRC_APRTR6_BASE_IDX 1 |
180 | #define regXPB_RTR_SRC_APRTR7 0x0007 |
181 | #define regXPB_RTR_SRC_APRTR7_BASE_IDX 1 |
182 | #define regXPB_RTR_SRC_APRTR8 0x0008 |
183 | #define regXPB_RTR_SRC_APRTR8_BASE_IDX 1 |
184 | #define regXPB_RTR_SRC_APRTR9 0x0009 |
185 | #define regXPB_RTR_SRC_APRTR9_BASE_IDX 1 |
186 | #define regXPB_XDMA_RTR_SRC_APRTR0 0x000a |
187 | #define regXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 1 |
188 | #define regXPB_XDMA_RTR_SRC_APRTR1 0x000b |
189 | #define regXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 1 |
190 | #define regXPB_XDMA_RTR_SRC_APRTR2 0x000c |
191 | #define regXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 1 |
192 | #define regXPB_XDMA_RTR_SRC_APRTR3 0x000d |
193 | #define regXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 1 |
194 | #define regXPB_RTR_DEST_MAP0 0x000e |
195 | #define regXPB_RTR_DEST_MAP0_BASE_IDX 1 |
196 | #define regXPB_RTR_DEST_MAP1 0x000f |
197 | #define regXPB_RTR_DEST_MAP1_BASE_IDX 1 |
198 | #define regXPB_RTR_DEST_MAP2 0x0010 |
199 | #define regXPB_RTR_DEST_MAP2_BASE_IDX 1 |
200 | #define regXPB_RTR_DEST_MAP3 0x0011 |
201 | #define regXPB_RTR_DEST_MAP3_BASE_IDX 1 |
202 | #define regXPB_RTR_DEST_MAP4 0x0012 |
203 | #define regXPB_RTR_DEST_MAP4_BASE_IDX 1 |
204 | #define regXPB_RTR_DEST_MAP5 0x0013 |
205 | #define regXPB_RTR_DEST_MAP5_BASE_IDX 1 |
206 | #define regXPB_RTR_DEST_MAP6 0x0014 |
207 | #define regXPB_RTR_DEST_MAP6_BASE_IDX 1 |
208 | #define regXPB_RTR_DEST_MAP7 0x0015 |
209 | #define regXPB_RTR_DEST_MAP7_BASE_IDX 1 |
210 | #define regXPB_RTR_DEST_MAP8 0x0016 |
211 | #define regXPB_RTR_DEST_MAP8_BASE_IDX 1 |
212 | #define regXPB_RTR_DEST_MAP9 0x0017 |
213 | #define regXPB_RTR_DEST_MAP9_BASE_IDX 1 |
214 | #define regXPB_XDMA_RTR_DEST_MAP0 0x0018 |
215 | #define regXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 1 |
216 | #define regXPB_XDMA_RTR_DEST_MAP1 0x0019 |
217 | #define regXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 1 |
218 | #define regXPB_XDMA_RTR_DEST_MAP2 0x001a |
219 | #define regXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 1 |
220 | #define regXPB_XDMA_RTR_DEST_MAP3 0x001b |
221 | #define regXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 1 |
222 | #define regXPB_CLG_CFG0 0x001c |
223 | #define regXPB_CLG_CFG0_BASE_IDX 1 |
224 | #define regXPB_CLG_CFG1 0x001d |
225 | #define regXPB_CLG_CFG1_BASE_IDX 1 |
226 | #define regXPB_CLG_CFG2 0x001e |
227 | #define regXPB_CLG_CFG2_BASE_IDX 1 |
228 | #define regXPB_CLG_CFG3 0x001f |
229 | #define regXPB_CLG_CFG3_BASE_IDX 1 |
230 | #define regXPB_CLG_CFG4 0x0020 |
231 | #define regXPB_CLG_CFG4_BASE_IDX 1 |
232 | #define regXPB_CLG_CFG5 0x0021 |
233 | #define regXPB_CLG_CFG5_BASE_IDX 1 |
234 | #define regXPB_CLG_CFG6 0x0022 |
235 | #define regXPB_CLG_CFG6_BASE_IDX 1 |
236 | #define regXPB_CLG_CFG7 0x0023 |
237 | #define regXPB_CLG_CFG7_BASE_IDX 1 |
238 | #define 0x0024 |
239 | #define 1 |
240 | #define 0x0025 |
241 | #define 1 |
242 | #define 0x0026 |
243 | #define 1 |
244 | #define regXPB_LB_ADDR 0x0027 |
245 | #define regXPB_LB_ADDR_BASE_IDX 1 |
246 | #define regXPB_WCB_STS 0x0028 |
247 | #define regXPB_WCB_STS_BASE_IDX 1 |
248 | #define regXPB_HST_CFG 0x0029 |
249 | #define regXPB_HST_CFG_BASE_IDX 1 |
250 | #define regXPB_P2P_BAR_CFG 0x002a |
251 | #define regXPB_P2P_BAR_CFG_BASE_IDX 1 |
252 | #define regXPB_P2P_BAR0 0x002b |
253 | #define regXPB_P2P_BAR0_BASE_IDX 1 |
254 | #define regXPB_P2P_BAR1 0x002c |
255 | #define regXPB_P2P_BAR1_BASE_IDX 1 |
256 | #define regXPB_P2P_BAR2 0x002d |
257 | #define regXPB_P2P_BAR2_BASE_IDX 1 |
258 | #define regXPB_P2P_BAR3 0x002e |
259 | #define regXPB_P2P_BAR3_BASE_IDX 1 |
260 | #define regXPB_P2P_BAR4 0x002f |
261 | #define regXPB_P2P_BAR4_BASE_IDX 1 |
262 | #define regXPB_P2P_BAR5 0x0030 |
263 | #define regXPB_P2P_BAR5_BASE_IDX 1 |
264 | #define regXPB_P2P_BAR6 0x0031 |
265 | #define regXPB_P2P_BAR6_BASE_IDX 1 |
266 | #define regXPB_P2P_BAR7 0x0032 |
267 | #define regXPB_P2P_BAR7_BASE_IDX 1 |
268 | #define regXPB_P2P_BAR_SETUP 0x0033 |
269 | #define regXPB_P2P_BAR_SETUP_BASE_IDX 1 |
270 | #define regXPB_P2P_BAR_DELTA_ABOVE 0x0035 |
271 | #define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 1 |
272 | #define regXPB_P2P_BAR_DELTA_BELOW 0x0036 |
273 | #define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 1 |
274 | #define regXPB_PEER_SYS_BAR0 0x0037 |
275 | #define regXPB_PEER_SYS_BAR0_BASE_IDX 1 |
276 | #define regXPB_PEER_SYS_BAR1 0x0038 |
277 | #define regXPB_PEER_SYS_BAR1_BASE_IDX 1 |
278 | #define regXPB_PEER_SYS_BAR2 0x0039 |
279 | #define regXPB_PEER_SYS_BAR2_BASE_IDX 1 |
280 | #define regXPB_PEER_SYS_BAR3 0x003a |
281 | #define regXPB_PEER_SYS_BAR3_BASE_IDX 1 |
282 | #define regXPB_PEER_SYS_BAR4 0x003b |
283 | #define regXPB_PEER_SYS_BAR4_BASE_IDX 1 |
284 | #define regXPB_PEER_SYS_BAR5 0x003c |
285 | #define regXPB_PEER_SYS_BAR5_BASE_IDX 1 |
286 | #define regXPB_PEER_SYS_BAR6 0x003d |
287 | #define regXPB_PEER_SYS_BAR6_BASE_IDX 1 |
288 | #define regXPB_PEER_SYS_BAR7 0x003e |
289 | #define regXPB_PEER_SYS_BAR7_BASE_IDX 1 |
290 | #define regXPB_PEER_SYS_BAR8 0x003f |
291 | #define regXPB_PEER_SYS_BAR8_BASE_IDX 1 |
292 | #define regXPB_PEER_SYS_BAR9 0x0040 |
293 | #define regXPB_PEER_SYS_BAR9_BASE_IDX 1 |
294 | #define regXPB_XDMA_PEER_SYS_BAR0 0x0041 |
295 | #define regXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 1 |
296 | #define regXPB_XDMA_PEER_SYS_BAR1 0x0042 |
297 | #define regXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 1 |
298 | #define regXPB_XDMA_PEER_SYS_BAR2 0x0043 |
299 | #define regXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 1 |
300 | #define regXPB_XDMA_PEER_SYS_BAR3 0x0044 |
301 | #define regXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 1 |
302 | #define regXPB_CLK_GAT 0x0045 |
303 | #define regXPB_CLK_GAT_BASE_IDX 1 |
304 | #define regXPB_INTF_CFG 0x0046 |
305 | #define regXPB_INTF_CFG_BASE_IDX 1 |
306 | #define regXPB_INTF_STS 0x0047 |
307 | #define regXPB_INTF_STS_BASE_IDX 1 |
308 | #define regXPB_PIPE_STS 0x0048 |
309 | #define regXPB_PIPE_STS_BASE_IDX 1 |
310 | #define regXPB_SUB_CTRL 0x0049 |
311 | #define regXPB_SUB_CTRL_BASE_IDX 1 |
312 | #define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x004a |
313 | #define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 1 |
314 | #define regXPB_PERF_KNOBS 0x004b |
315 | #define regXPB_PERF_KNOBS_BASE_IDX 1 |
316 | #define regXPB_STICKY 0x004c |
317 | #define regXPB_STICKY_BASE_IDX 1 |
318 | #define regXPB_STICKY_W1C 0x004d |
319 | #define regXPB_STICKY_W1C_BASE_IDX 1 |
320 | #define regXPB_MISC_CFG 0x004e |
321 | #define regXPB_MISC_CFG_BASE_IDX 1 |
322 | #define regXPB_INTF_CFG2 0x004f |
323 | #define regXPB_INTF_CFG2_BASE_IDX 1 |
324 | #define 0x0050 |
325 | #define 1 |
326 | #define 0x0051 |
327 | #define 1 |
328 | #define regXPB_CLG_GFX_MATCH 0x0052 |
329 | #define regXPB_CLG_GFX_MATCH_BASE_IDX 1 |
330 | #define regXPB_CLG_GFX_MATCH_VLD 0x0053 |
331 | #define regXPB_CLG_GFX_MATCH_VLD_BASE_IDX 1 |
332 | #define regXPB_CLG_GFX_MATCH_MSK 0x0054 |
333 | #define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 1 |
334 | #define regXPB_CLG_MM_MATCH 0x0055 |
335 | #define regXPB_CLG_MM_MATCH_BASE_IDX 1 |
336 | #define regXPB_CLG_MM_MATCH_VLD 0x0056 |
337 | #define regXPB_CLG_MM_MATCH_VLD_BASE_IDX 1 |
338 | #define regXPB_CLG_MM_MATCH_MSK 0x0057 |
339 | #define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 1 |
340 | #define regXPB_CLG_GFX_UNITID_MAPPING0 0x0058 |
341 | #define regXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 1 |
342 | #define regXPB_CLG_GFX_UNITID_MAPPING1 0x0059 |
343 | #define regXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 1 |
344 | #define regXPB_CLG_GFX_UNITID_MAPPING2 0x005a |
345 | #define regXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 1 |
346 | #define regXPB_CLG_GFX_UNITID_MAPPING3 0x005b |
347 | #define regXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 1 |
348 | #define regXPB_CLG_GFX_UNITID_MAPPING4 0x005c |
349 | #define regXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 1 |
350 | #define regXPB_CLG_GFX_UNITID_MAPPING5 0x005d |
351 | #define regXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 1 |
352 | #define regXPB_CLG_GFX_UNITID_MAPPING6 0x005e |
353 | #define regXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 1 |
354 | #define regXPB_CLG_GFX_UNITID_MAPPING7 0x005f |
355 | #define regXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 1 |
356 | #define regXPB_CLG_MM_UNITID_MAPPING0 0x0060 |
357 | #define regXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 1 |
358 | #define regXPB_CLG_MM_UNITID_MAPPING1 0x0061 |
359 | #define regXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 1 |
360 | #define regXPB_CLG_MM_UNITID_MAPPING2 0x0062 |
361 | #define regXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 1 |
362 | #define regXPB_CLG_MM_UNITID_MAPPING3 0x0063 |
363 | #define regXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 1 |
364 | |
365 | |
366 | // addressBlock: aid_athub_rpbdec |
367 | // base address: 0x46200 |
368 | #define regRPB_PASSPW_CONF 0x0080 |
369 | #define regRPB_PASSPW_CONF_BASE_IDX 1 |
370 | #define regRPB_BLOCKLEVEL_CONF 0x0081 |
371 | #define regRPB_BLOCKLEVEL_CONF_BASE_IDX 1 |
372 | #define regRPB_TAG_CONF 0x0082 |
373 | #define regRPB_TAG_CONF_BASE_IDX 1 |
374 | #define regRPB_TAG_CONF2 0x0083 |
375 | #define regRPB_TAG_CONF2_BASE_IDX 1 |
376 | #define regRPB_ARB_CNTL 0x0085 |
377 | #define regRPB_ARB_CNTL_BASE_IDX 1 |
378 | #define regRPB_ARB_CNTL2 0x0086 |
379 | #define regRPB_ARB_CNTL2_BASE_IDX 1 |
380 | #define regRPB_BIF_CNTL 0x0087 |
381 | #define regRPB_BIF_CNTL_BASE_IDX 1 |
382 | #define regRPB_BIF_CNTL2 0x0088 |
383 | #define regRPB_BIF_CNTL2_BASE_IDX 1 |
384 | #define regRPB_PERF_COUNTER_CNTL 0x008a |
385 | #define regRPB_PERF_COUNTER_CNTL_BASE_IDX 1 |
386 | #define regRPB_DEINTRLV_COMBINE_CNTL 0x008c |
387 | #define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 1 |
388 | #define regRPB_VC_SWITCH_RDWR 0x008d |
389 | #define regRPB_VC_SWITCH_RDWR_BASE_IDX 1 |
390 | #define regRPB_PERFCOUNTER_LO 0x008e |
391 | #define regRPB_PERFCOUNTER_LO_BASE_IDX 1 |
392 | #define regRPB_PERFCOUNTER_HI 0x008f |
393 | #define regRPB_PERFCOUNTER_HI_BASE_IDX 1 |
394 | #define regRPB_PERFCOUNTER0_CFG 0x0090 |
395 | #define regRPB_PERFCOUNTER0_CFG_BASE_IDX 1 |
396 | #define regRPB_PERFCOUNTER1_CFG 0x0091 |
397 | #define regRPB_PERFCOUNTER1_CFG_BASE_IDX 1 |
398 | #define regRPB_PERFCOUNTER2_CFG 0x0092 |
399 | #define regRPB_PERFCOUNTER2_CFG_BASE_IDX 1 |
400 | #define regRPB_PERFCOUNTER3_CFG 0x0093 |
401 | #define regRPB_PERFCOUNTER3_CFG_BASE_IDX 1 |
402 | #define regRPB_PERFCOUNTER_RSLT_CNTL 0x0094 |
403 | #define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 |
404 | #define regRPB_ATS_CNTL 0x0096 |
405 | #define regRPB_ATS_CNTL_BASE_IDX 1 |
406 | #define regRPB_ATS_CNTL2 0x0097 |
407 | #define regRPB_ATS_CNTL2_BASE_IDX 1 |
408 | #define regRPB_SDPPORT_CNTL 0x0098 |
409 | #define regRPB_SDPPORT_CNTL_BASE_IDX 1 |
410 | |
411 | #endif |
412 | |