1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _athub_1_8_0_SH_MASK_HEADER
24#define _athub_1_8_0_SH_MASK_HEADER
25
26
27// addressBlock: aid_athub_atsdec
28//ATC_ATS_CNTL
29#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
30#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
31#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
32#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
33#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
34#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16
35#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
36#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
37#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
38#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L
39#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000F0000L
40#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L
41//ATC_ATS_CNTL2
42#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR__SHIFT 0x0
43#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR__SHIFT 0x8
44#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV__SHIFT 0x10
45#define ATC_ATS_CNTL2__TRANSLATION_STALL__SHIFT 0x18
46#define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE__SHIFT 0x19
47#define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE__SHIFT 0x1a
48#define ATC_ATS_CNTL2__RESERVED__SHIFT 0x1b
49#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC5TR_MASK 0x000000FFL
50#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_VC0TR_MASK 0x0000FF00L
51#define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV_MASK 0x00FF0000L
52#define ATC_ATS_CNTL2__TRANSLATION_STALL_MASK 0x01000000L
53#define ATC_ATS_CNTL2__GC_TRANS_VC5_ENABLE_MASK 0x02000000L
54#define ATC_ATS_CNTL2__MM_TRANS_VC5_ENABLE_MASK 0x04000000L
55#define ATC_ATS_CNTL2__RESERVED_MASK 0xF8000000L
56//ATC_ATS_CNTL3
57#define ATC_ATS_CNTL3__RESERVED__SHIFT 0x0
58#define ATC_ATS_CNTL3__RESERVED_MASK 0xFFFFFFFFL
59//ATC_ATS_CNTL4
60#define ATC_ATS_CNTL4__RESERVED__SHIFT 0x0
61#define ATC_ATS_CNTL4__RESERVED_MASK 0xFFFFFFFFL
62//ATC_ATS_MISC_CNTL
63#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST__SHIFT 0x10
64#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST__SHIFT 0x11
65#define ATC_ATS_MISC_CNTL__DEBUG_COLLISION__SHIFT 0x12
66#define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE__SHIFT 0x13
67#define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL__SHIFT 0x1d
68#define ATC_ATS_MISC_CNTL__RESERVED__SHIFT 0x1e
69#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_HOST_MASK 0x00010000L
70#define ATC_ATS_MISC_CNTL__TRANS_RESP_IN_INV_COLLISION_GUEST_MASK 0x00020000L
71#define ATC_ATS_MISC_CNTL__DEBUG_COLLISION_MASK 0x00040000L
72#define ATC_ATS_MISC_CNTL__EFFECTIVE_TRANS_WORK_QUEUE_MASK 0x1FF80000L
73#define ATC_ATS_MISC_CNTL__TRANS_RESP_NULL_PASID_SEL_MASK 0x20000000L
74#define ATC_ATS_MISC_CNTL__RESERVED_MASK 0xC0000000L
75//ATC_ATS_STATUS
76#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
77#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
78#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
79#define ATC_ATS_STATUS__FED_IND__SHIFT 0x3
80#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
81#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
82#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
83#define ATC_ATS_STATUS__FED_IND_MASK 0x00000008L
84//ATC_PERFCOUNTER0_CFG
85#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
86#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
87#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
88#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
89#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
90#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
91#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
92#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
93#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
94#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
95//ATC_PERFCOUNTER1_CFG
96#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
97#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
98#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
99#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
100#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
101#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
102#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
103#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
104#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
105#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
106//ATC_PERFCOUNTER2_CFG
107#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
108#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
109#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
110#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
111#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
112#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
113#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
114#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
115#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
116#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
117//ATC_PERFCOUNTER3_CFG
118#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
119#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
120#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
121#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
122#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
123#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
124#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
125#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
126#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
127#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
128//ATC_PERFCOUNTER_RSLT_CNTL
129#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
130#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
131#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
132#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
133#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
134#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
135#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
136#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
137#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
138#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
139#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
140#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
141//ATC_PERFCOUNTER_LO
142#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
143#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
144//ATC_PERFCOUNTER_HI
145#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
146#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
147#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
148#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
149//ATC_ATS_FAULT_CNTL
150#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
151#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
152#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
153#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL
154#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L
155#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L
156//ATC_ATS_FAULT_STATUS_INFO
157#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
158#define ATC_ATS_FAULT_STATUS_INFO__VMID_ALL__SHIFT 0x9
159#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
160#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
161#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
162#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
163#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
164#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
165#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
166#define ATC_ATS_FAULT_STATUS_INFO__PHYSICAL_ADDR_HIGH__SHIFT 0x1c
167#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL
168#define ATC_ATS_FAULT_STATUS_INFO__VMID_ALL_MASK 0x00000200L
169#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L
170#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
171#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
172#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
173#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
174#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L
175#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L
176#define ATC_ATS_FAULT_STATUS_INFO__PHYSICAL_ADDR_HIGH_MASK 0xF0000000L
177//ATC_ATS_FAULT_STATUS_INFO2
178#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
179#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
180#define ATC_ATS_FAULT_STATUS_INFO2__L2NUM__SHIFT 0x9
181#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX1__SHIFT 0xd
182#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX2__SHIFT 0x13
183#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX3__SHIFT 0x19
184#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L
185#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL
186#define ATC_ATS_FAULT_STATUS_INFO2__L2NUM_MASK 0x00001E00L
187#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX1_MASK 0x0007E000L
188#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX2_MASK 0x01F80000L
189#define ATC_ATS_FAULT_STATUS_INFO2__INV_VMID_GFX3_MASK 0x7E000000L
190//ATC_ATS_FAULT_STATUS_INFO3
191#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX4__SHIFT 0x0
192#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX5__SHIFT 0x6
193#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX6__SHIFT 0xc
194#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX7__SHIFT 0x12
195#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_MM0__SHIFT 0x18
196#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX4_MASK 0x0000003FL
197#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX5_MASK 0x00000FC0L
198#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX6_MASK 0x0003F000L
199#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_GFX7_MASK 0x00FC0000L
200#define ATC_ATS_FAULT_STATUS_INFO3__INV_VMID_MM0_MASK 0x3F000000L
201//ATC_ATS_FAULT_STATUS_INFO4
202#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM1__SHIFT 0x0
203#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM2__SHIFT 0x6
204#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM3__SHIFT 0xc
205#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM1_MASK 0x0000003FL
206#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM2_MASK 0x00000FC0L
207#define ATC_ATS_FAULT_STATUS_INFO4__INV_VMID_MM3_MASK 0x0003F000L
208//ATC_ATS_FAULT_STATUS_ADDR
209#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
210#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL
211//ATC_ATS_DEFAULT_PAGE_LOW
212#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
213#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL
214//ATHUB_PCIE_ATS_CNTL
215#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10
216#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
217#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
218#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
219//ATHUB_PCIE_PASID_CNTL
220#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10
221#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11
222#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12
223#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L
224#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L
225#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L
226//ATHUB_PCIE_PAGE_REQ_CNTL
227#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
228#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
229#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L
230#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L
231//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC
232#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
233#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
234//ATHUB_COMMAND
235#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
236#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L
237//ATHUB_PCIE_ATS_CNTL_VF_0
238#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
239#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
240//ATHUB_PCIE_ATS_CNTL_VF_1
241#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
242#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
243//ATHUB_PCIE_ATS_CNTL_VF_2
244#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
245#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
246//ATHUB_PCIE_ATS_CNTL_VF_3
247#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
248#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
249//ATHUB_PCIE_ATS_CNTL_VF_4
250#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
251#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
252//ATHUB_PCIE_ATS_CNTL_VF_5
253#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
254#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
255//ATHUB_PCIE_ATS_CNTL_VF_6
256#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
257#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
258//ATHUB_PCIE_ATS_CNTL_VF_7
259#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
260#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
261//ATHUB_PCIE_ATS_CNTL_VF_8
262#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
263#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
264//ATHUB_PCIE_ATS_CNTL_VF_9
265#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
266#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
267//ATHUB_PCIE_ATS_CNTL_VF_10
268#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
269#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
270//ATHUB_PCIE_ATS_CNTL_VF_11
271#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
272#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
273//ATHUB_PCIE_ATS_CNTL_VF_12
274#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
275#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
276//ATHUB_PCIE_ATS_CNTL_VF_13
277#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
278#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
279//ATHUB_PCIE_ATS_CNTL_VF_14
280#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
281#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
282//ATHUB_PCIE_ATS_CNTL_VF_15
283#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
284#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
285//ATHUB_SHARED_VIRT_RESET_REQ
286#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
287#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
288#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
289#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
290//ATHUB_SHARED_ACTIVE_FCN_ID
291#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
292#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
293#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
294#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
295//ATC_ATS_SDPPORT_CNTL
296#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0
297#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1
298#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3
299#define ATC_ATS_SDPPORT_CNTL__ATS_INV_REISSUE_CREDIT__SHIFT 0x7
300#define ATC_ATS_SDPPORT_CNTL__ATS_INV_ENABLE_DISRUPT_FULLDIS__SHIFT 0x8
301#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x9
302#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0xa
303#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0xb
304#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xf
305#define ATC_ATS_SDPPORT_CNTL__UTCL2_RDY_MODE__SHIFT 0x10
306#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_REISSUE_CREDIT__SHIFT 0x11
307#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_ENABLE_DISRUPT_FULLDIS__SHIFT 0x12
308#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_INVALREQ_RDRSPSTATUS_CNTL__SHIFT 0x13
309#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x16
310#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
311#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
312#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
313#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
314#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
315#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x1c
316#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x1d
317#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x1e
318#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x1f
319#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L
320#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L
321#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L
322#define ATC_ATS_SDPPORT_CNTL__ATS_INV_REISSUE_CREDIT_MASK 0x00000080L
323#define ATC_ATS_SDPPORT_CNTL__ATS_INV_ENABLE_DISRUPT_FULLDIS_MASK 0x00000100L
324#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000200L
325#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000400L
326#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00007800L
327#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00008000L
328#define ATC_ATS_SDPPORT_CNTL__UTCL2_RDY_MODE_MASK 0x00010000L
329#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_REISSUE_CREDIT_MASK 0x00020000L
330#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_ENABLE_DISRUPT_FULLDIS_MASK 0x00040000L
331#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_INVALREQ_RDRSPSTATUS_CNTL_MASK 0x00380000L
332#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
333#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
334#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
335#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
336#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
337#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
338#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x10000000L
339#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x20000000L
340#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x40000000L
341#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x80000000L
342//ATC_VMID_PASID_MAPPING_UPDATE_STATUS
343#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
344#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
345#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
346#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
347#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
348#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
349#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
350#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
351#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
352#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
353#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
354#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
355#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
356#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
357#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
358#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
359#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
360#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
361#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
362#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
363#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
364#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
365#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
366#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
367#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
368#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
369#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
370#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
371#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
372#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
373#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
374#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
375//ATC_VMID0_PASID_MAPPING
376#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
377#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
378#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
379#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL
380#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
381#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
382//ATC_VMID1_PASID_MAPPING
383#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
384#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
385#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
386#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL
387#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
388#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
389//ATC_VMID2_PASID_MAPPING
390#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
391#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
392#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
393#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL
394#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
395#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
396//ATC_VMID3_PASID_MAPPING
397#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
398#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
399#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
400#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL
401#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
402#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
403//ATC_VMID4_PASID_MAPPING
404#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
405#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
406#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
407#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL
408#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
409#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
410//ATC_VMID5_PASID_MAPPING
411#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
412#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
413#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
414#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL
415#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
416#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
417//ATC_VMID6_PASID_MAPPING
418#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
419#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
420#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
421#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL
422#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
423#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
424//ATC_VMID7_PASID_MAPPING
425#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
426#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
427#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
428#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL
429#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
430#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
431//ATC_VMID8_PASID_MAPPING
432#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
433#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
434#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
435#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL
436#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
437#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
438//ATC_VMID9_PASID_MAPPING
439#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
440#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
441#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
442#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL
443#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
444#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
445//ATC_VMID10_PASID_MAPPING
446#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
447#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
448#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
449#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL
450#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
451#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
452//ATC_VMID11_PASID_MAPPING
453#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
454#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
455#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
456#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL
457#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
458#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
459//ATC_VMID12_PASID_MAPPING
460#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
461#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
462#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
463#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL
464#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
465#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
466//ATC_VMID13_PASID_MAPPING
467#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
468#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
469#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
470#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL
471#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
472#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
473//ATC_VMID14_PASID_MAPPING
474#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
475#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
476#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
477#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL
478#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
479#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
480//ATC_VMID15_PASID_MAPPING
481#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
482#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
483#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
484#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL
485#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L
486#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
487//ATC_TRANS_FAULT_RSPCNTRL
488#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0
489#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1
490#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2
491#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3
492#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4
493#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
494#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6
495#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7
496#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8
497#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9
498#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
499#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb
500#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc
501#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd
502#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
503#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf
504#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L
505#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L
506#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L
507#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L
508#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L
509#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L
510#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L
511#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L
512#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L
513#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L
514#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L
515#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L
516#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L
517#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L
518#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L
519#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L
520//ATC_ATS_VMID_STATUS
521#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
522#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
523#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
524#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
525#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
526#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
527#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
528#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
529#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
530#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
531#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
532#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
533#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
534#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
535#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
536#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
537#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L
538#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L
539#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L
540#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L
541#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L
542#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L
543#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L
544#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L
545#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L
546#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L
547#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L
548#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L
549#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L
550#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L
551#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L
552#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L
553//ATHUB_MISC_CNTL
554#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6
555#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12
556#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13
557#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14
558#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15
559#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b
560#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c
561#define ATHUB_MISC_CNTL__SRAM_FGCG_ENABLE__SHIFT 0x1d
562#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L
563#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L
564#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L
565#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L
566#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L
567#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L
568#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L
569#define ATHUB_MISC_CNTL__SRAM_FGCG_ENABLE_MASK 0x20000000L
570//ATHUB_MEM_POWER_LS
571#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
572#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
573#define ATHUB_MEM_POWER_LS__LS_DELAY_ENABLE__SHIFT 0x13
574#define ATHUB_MEM_POWER_LS__LS_DELAY_TIME__SHIFT 0x14
575#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
576#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x0007FFC0L
577#define ATHUB_MEM_POWER_LS__LS_DELAY_ENABLE_MASK 0x00080000L
578#define ATHUB_MEM_POWER_LS__LS_DELAY_TIME_MASK 0x03F00000L
579//ATHUB_IH_CREDIT
580#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
581#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
582#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
583#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
584
585
586// addressBlock: aid_athub_xpbdec
587//XPB_RTR_SRC_APRTR0
588#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
589#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
590//XPB_RTR_SRC_APRTR1
591#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
592#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
593//XPB_RTR_SRC_APRTR2
594#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
595#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
596//XPB_RTR_SRC_APRTR3
597#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
598#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
599//XPB_RTR_SRC_APRTR4
600#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
601#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
602//XPB_RTR_SRC_APRTR5
603#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
604#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
605//XPB_RTR_SRC_APRTR6
606#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
607#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
608//XPB_RTR_SRC_APRTR7
609#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
610#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
611//XPB_RTR_SRC_APRTR8
612#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
613#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
614//XPB_RTR_SRC_APRTR9
615#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
616#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
617//XPB_XDMA_RTR_SRC_APRTR0
618#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
619#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
620//XPB_XDMA_RTR_SRC_APRTR1
621#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
622#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
623//XPB_XDMA_RTR_SRC_APRTR2
624#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
625#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
626//XPB_XDMA_RTR_SRC_APRTR3
627#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
628#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
629//XPB_RTR_DEST_MAP0
630#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
631#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
632#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
633#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
634#define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
635#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
636#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
637#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
638#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
639#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
640#define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
641#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
642//XPB_RTR_DEST_MAP1
643#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
644#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
645#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
646#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
647#define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
648#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
649#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
650#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
651#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
652#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
653#define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
654#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
655//XPB_RTR_DEST_MAP2
656#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
657#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
658#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
659#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
660#define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
661#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
662#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
663#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
664#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
665#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
666#define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
667#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
668//XPB_RTR_DEST_MAP3
669#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
670#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
671#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
672#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
673#define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
674#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
675#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L
676#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
677#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
678#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
679#define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
680#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
681//XPB_RTR_DEST_MAP4
682#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
683#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
684#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
685#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
686#define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
687#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
688#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L
689#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL
690#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L
691#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L
692#define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L
693#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L
694//XPB_RTR_DEST_MAP5
695#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
696#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
697#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
698#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
699#define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
700#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
701#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L
702#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL
703#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L
704#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L
705#define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L
706#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L
707//XPB_RTR_DEST_MAP6
708#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
709#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
710#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
711#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
712#define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
713#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
714#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L
715#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL
716#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L
717#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L
718#define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L
719#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L
720//XPB_RTR_DEST_MAP7
721#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
722#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
723#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
724#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
725#define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
726#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
727#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L
728#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL
729#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L
730#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L
731#define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L
732#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L
733//XPB_RTR_DEST_MAP8
734#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
735#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
736#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
737#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
738#define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
739#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
740#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L
741#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL
742#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L
743#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L
744#define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L
745#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L
746//XPB_RTR_DEST_MAP9
747#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
748#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
749#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
750#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
751#define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
752#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
753#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L
754#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL
755#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L
756#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L
757#define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L
758#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L
759//XPB_XDMA_RTR_DEST_MAP0
760#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
761#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
762#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
763#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
764#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
765#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
766#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L
767#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
768#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
769#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
770#define XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
771#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
772//XPB_XDMA_RTR_DEST_MAP1
773#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
774#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
775#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
776#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
777#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
778#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
779#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L
780#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
781#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
782#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
783#define XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
784#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
785//XPB_XDMA_RTR_DEST_MAP2
786#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
787#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
788#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
789#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
790#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
791#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
792#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L
793#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
794#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
795#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
796#define XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
797#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
798//XPB_XDMA_RTR_DEST_MAP3
799#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
800#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
801#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
802#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
803#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
804#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
805#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L
806#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL
807#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L
808#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L
809#define XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L
810#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L
811//XPB_CLG_CFG0
812#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
813#define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
814#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
815#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
816#define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
817#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL
818#define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L
819#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L
820#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L
821#define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L
822//XPB_CLG_CFG1
823#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
824#define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
825#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
826#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
827#define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
828#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL
829#define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L
830#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L
831#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L
832#define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L
833//XPB_CLG_CFG2
834#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
835#define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
836#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
837#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
838#define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
839#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL
840#define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L
841#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L
842#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L
843#define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L
844//XPB_CLG_CFG3
845#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
846#define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
847#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
848#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
849#define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
850#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL
851#define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L
852#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L
853#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L
854#define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L
855//XPB_CLG_CFG4
856#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
857#define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
858#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
859#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
860#define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
861#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL
862#define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L
863#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L
864#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L
865#define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L
866//XPB_CLG_CFG5
867#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
868#define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
869#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
870#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
871#define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
872#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL
873#define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L
874#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L
875#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L
876#define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L
877//XPB_CLG_CFG6
878#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
879#define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
880#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
881#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
882#define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
883#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL
884#define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L
885#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L
886#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L
887#define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L
888//XPB_CLG_CFG7
889#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
890#define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
891#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
892#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
893#define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
894#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL
895#define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L
896#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L
897#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L
898#define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L
899//XPB_CLG_EXTRA0
900#define XPB_CLG_EXTRA0__CMP0_HIGH__SHIFT 0x0
901#define XPB_CLG_EXTRA0__CMP0_LOW__SHIFT 0x8
902#define XPB_CLG_EXTRA0__VLD0__SHIFT 0xd
903#define XPB_CLG_EXTRA0__CLG0_NUM__SHIFT 0xe
904#define XPB_CLG_EXTRA0__CMP0_HIGH_MASK 0x000000FFL
905#define XPB_CLG_EXTRA0__CMP0_LOW_MASK 0x00001F00L
906#define XPB_CLG_EXTRA0__VLD0_MASK 0x00002000L
907#define XPB_CLG_EXTRA0__CLG0_NUM_MASK 0x0001C000L
908//XPB_CLG_EXTRA1
909#define XPB_CLG_EXTRA1__CMP1_HIGH__SHIFT 0x0
910#define XPB_CLG_EXTRA1__CMP1_LOW__SHIFT 0x8
911#define XPB_CLG_EXTRA1__VLD1__SHIFT 0xd
912#define XPB_CLG_EXTRA1__CLG1_NUM__SHIFT 0xe
913#define XPB_CLG_EXTRA1__CMP1_HIGH_MASK 0x000000FFL
914#define XPB_CLG_EXTRA1__CMP1_LOW_MASK 0x00001F00L
915#define XPB_CLG_EXTRA1__VLD1_MASK 0x00002000L
916#define XPB_CLG_EXTRA1__CLG1_NUM_MASK 0x0001C000L
917//XPB_CLG_EXTRA_MSK
918#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0
919#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x8
920#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xd
921#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x15
922#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x000000FFL
923#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x00001F00L
924#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x001FE000L
925#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x03E00000L
926//XPB_LB_ADDR
927#define XPB_LB_ADDR__CMP0__SHIFT 0x0
928#define XPB_LB_ADDR__MASK0__SHIFT 0xa
929#define XPB_LB_ADDR__CMP1__SHIFT 0x14
930#define XPB_LB_ADDR__MASK1__SHIFT 0x1a
931#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL
932#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L
933#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L
934#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L
935//XPB_WCB_STS
936#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
937#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
938#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
939#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL
940#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L
941#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L
942//XPB_HST_CFG
943#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0
944#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L
945//XPB_P2P_BAR_CFG
946#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
947#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
948#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
949#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
950#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
951#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
952#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
953#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
954#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
955#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL
956#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L
957#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L
958#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L
959#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L
960#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L
961#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L
962#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L
963#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L
964//XPB_P2P_BAR0
965#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
966#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
967#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
968#define XPB_P2P_BAR0__VALID__SHIFT 0xc
969#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
970#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
971#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf
972#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
973#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL
974#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L
975#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L
976#define XPB_P2P_BAR0__VALID_MASK 0x00001000L
977#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L
978#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L
979#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L
980#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L
981//XPB_P2P_BAR1
982#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
983#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
984#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
985#define XPB_P2P_BAR1__VALID__SHIFT 0xc
986#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
987#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
988#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf
989#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
990#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL
991#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L
992#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L
993#define XPB_P2P_BAR1__VALID_MASK 0x00001000L
994#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L
995#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L
996#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L
997#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L
998//XPB_P2P_BAR2
999#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
1000#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
1001#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
1002#define XPB_P2P_BAR2__VALID__SHIFT 0xc
1003#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
1004#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
1005#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf
1006#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
1007#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL
1008#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L
1009#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L
1010#define XPB_P2P_BAR2__VALID_MASK 0x00001000L
1011#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L
1012#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L
1013#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L
1014#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L
1015//XPB_P2P_BAR3
1016#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
1017#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
1018#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
1019#define XPB_P2P_BAR3__VALID__SHIFT 0xc
1020#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
1021#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
1022#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf
1023#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
1024#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL
1025#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L
1026#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L
1027#define XPB_P2P_BAR3__VALID_MASK 0x00001000L
1028#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L
1029#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L
1030#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L
1031#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L
1032//XPB_P2P_BAR4
1033#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
1034#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
1035#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
1036#define XPB_P2P_BAR4__VALID__SHIFT 0xc
1037#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
1038#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
1039#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf
1040#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
1041#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL
1042#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L
1043#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L
1044#define XPB_P2P_BAR4__VALID_MASK 0x00001000L
1045#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L
1046#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L
1047#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L
1048#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L
1049//XPB_P2P_BAR5
1050#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
1051#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
1052#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
1053#define XPB_P2P_BAR5__VALID__SHIFT 0xc
1054#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
1055#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
1056#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf
1057#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
1058#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL
1059#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L
1060#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L
1061#define XPB_P2P_BAR5__VALID_MASK 0x00001000L
1062#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L
1063#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L
1064#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L
1065#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L
1066//XPB_P2P_BAR6
1067#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
1068#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
1069#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
1070#define XPB_P2P_BAR6__VALID__SHIFT 0xc
1071#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
1072#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
1073#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf
1074#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
1075#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL
1076#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L
1077#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L
1078#define XPB_P2P_BAR6__VALID_MASK 0x00001000L
1079#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L
1080#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L
1081#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L
1082#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L
1083//XPB_P2P_BAR7
1084#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
1085#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
1086#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
1087#define XPB_P2P_BAR7__VALID__SHIFT 0xc
1088#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
1089#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
1090#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf
1091#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
1092#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL
1093#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L
1094#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L
1095#define XPB_P2P_BAR7__VALID_MASK 0x00001000L
1096#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L
1097#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L
1098#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L
1099#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L
1100//XPB_P2P_BAR_SETUP
1101#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
1102#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
1103#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
1104#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
1105#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
1106#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
1107#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
1108#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL
1109#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L
1110#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L
1111#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L
1112#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L
1113#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L
1114#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L
1115//XPB_P2P_BAR_DELTA_ABOVE
1116#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
1117#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
1118#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL
1119#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L
1120//XPB_P2P_BAR_DELTA_BELOW
1121#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
1122#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
1123#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL
1124#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L
1125//XPB_PEER_SYS_BAR0
1126#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
1127#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1
1128#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L
1129#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
1130//XPB_PEER_SYS_BAR1
1131#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
1132#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1
1133#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L
1134#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
1135//XPB_PEER_SYS_BAR2
1136#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
1137#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1
1138#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L
1139#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
1140//XPB_PEER_SYS_BAR3
1141#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
1142#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1
1143#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L
1144#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
1145//XPB_PEER_SYS_BAR4
1146#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
1147#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1
1148#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L
1149#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL
1150//XPB_PEER_SYS_BAR5
1151#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
1152#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1
1153#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L
1154#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL
1155//XPB_PEER_SYS_BAR6
1156#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
1157#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1
1158#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L
1159#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL
1160//XPB_PEER_SYS_BAR7
1161#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
1162#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1
1163#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L
1164#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL
1165//XPB_PEER_SYS_BAR8
1166#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
1167#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1
1168#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L
1169#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL
1170//XPB_PEER_SYS_BAR9
1171#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
1172#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1
1173#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L
1174#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL
1175//XPB_XDMA_PEER_SYS_BAR0
1176#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
1177#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1
1178#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L
1179#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL
1180//XPB_XDMA_PEER_SYS_BAR1
1181#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
1182#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1
1183#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L
1184#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL
1185//XPB_XDMA_PEER_SYS_BAR2
1186#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
1187#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1
1188#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L
1189#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL
1190//XPB_XDMA_PEER_SYS_BAR3
1191#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
1192#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1
1193#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L
1194#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL
1195//XPB_CLK_GAT
1196#define XPB_CLK_GAT__ONDLY__SHIFT 0x0
1197#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6
1198#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc
1199#define XPB_CLK_GAT__ENABLE__SHIFT 0x12
1200#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
1201#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL
1202#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L
1203#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L
1204#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L
1205#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L
1206//XPB_INTF_CFG
1207#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
1208#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
1209#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
1210#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
1211#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
1212#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
1213#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
1214#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
1215#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
1216#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
1217#define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA__SHIFT 0x1f
1218#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL
1219#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L
1220#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L
1221#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L
1222#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L
1223#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L
1224#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L
1225#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L
1226#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L
1227#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L
1228#define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA_MASK 0x80000000L
1229//XPB_INTF_STS
1230#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
1231#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
1232#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
1233#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
1234#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
1235#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
1236#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
1237#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL
1238#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L
1239#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L
1240#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L
1241#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L
1242#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L
1243#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L
1244//XPB_PIPE_STS
1245#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
1246#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
1247#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
1248#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
1249#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
1250#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
1251#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
1252#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
1253#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
1254#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
1255#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
1256#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
1257#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
1258#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L
1259#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL
1260#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L
1261#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L
1262#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L
1263#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L
1264#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L
1265#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L
1266#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L
1267#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L
1268#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L
1269#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L
1270#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L
1271//XPB_SUB_CTRL
1272#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
1273#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
1274#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
1275#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
1276#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
1277#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
1278#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
1279#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
1280#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
1281#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
1282#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
1283#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
1284#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
1285#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
1286#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
1287#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
1288#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
1289#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
1290#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
1291#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
1292#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L
1293#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L
1294#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L
1295#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L
1296#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L
1297#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L
1298#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L
1299#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L
1300#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L
1301#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L
1302#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L
1303#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L
1304#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L
1305#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L
1306#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L
1307#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L
1308#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L
1309#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L
1310#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L
1311#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L
1312//XPB_MAP_INVERT_FLUSH_NUM_LSB
1313#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
1314#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL
1315//XPB_PERF_KNOBS
1316#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
1317#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
1318#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
1319#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL
1320#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L
1321#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L
1322//XPB_STICKY
1323#define XPB_STICKY__BITS__SHIFT 0x0
1324#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL
1325//XPB_STICKY_W1C
1326#define XPB_STICKY_W1C__BITS__SHIFT 0x0
1327#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL
1328//XPB_MISC_CFG
1329#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
1330#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
1331#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
1332#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
1333#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
1334#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL
1335#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L
1336#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L
1337#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L
1338#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L
1339//XPB_INTF_CFG2
1340#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
1341#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL
1342//XPB_CLG_EXTRA_RD
1343#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0
1344#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6
1345#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb
1346#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc
1347#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf
1348#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15
1349#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a
1350#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b
1351#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL
1352#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L
1353#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L
1354#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L
1355#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L
1356#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L
1357#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L
1358#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L
1359//XPB_CLG_EXTRA_MSK_RD
1360#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0
1361#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6
1362#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb
1363#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11
1364#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL
1365#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L
1366#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L
1367#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L
1368//XPB_CLG_GFX_MATCH
1369#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0
1370#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x8
1371#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0x10
1372#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x18
1373#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x000000FFL
1374#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x0000FF00L
1375#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x00FF0000L
1376#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0xFF000000L
1377//XPB_CLG_GFX_MATCH_VLD
1378#define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0
1379#define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1
1380#define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2
1381#define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3
1382#define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L
1383#define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L
1384#define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L
1385#define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L
1386//XPB_CLG_GFX_MATCH_MSK
1387#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
1388#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8
1389#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10
1390#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18
1391#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL
1392#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L
1393#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L
1394#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L
1395//XPB_CLG_MM_MATCH
1396#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0
1397#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x8
1398#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0x10
1399#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x18
1400#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x000000FFL
1401#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x0000FF00L
1402#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x00FF0000L
1403#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0xFF000000L
1404//XPB_CLG_MM_MATCH_VLD
1405#define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0
1406#define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1
1407#define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2
1408#define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3
1409#define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L
1410#define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L
1411#define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L
1412#define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L
1413//XPB_CLG_MM_MATCH_MSK
1414#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0
1415#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8
1416#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10
1417#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18
1418#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL
1419#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L
1420#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L
1421#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L
1422//XPB_CLG_GFX_UNITID_MAPPING0
1423#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
1424#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
1425#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
1426#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
1427#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
1428#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
1429//XPB_CLG_GFX_UNITID_MAPPING1
1430#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
1431#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
1432#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
1433#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
1434#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
1435#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
1436//XPB_CLG_GFX_UNITID_MAPPING2
1437#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
1438#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
1439#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
1440#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
1441#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
1442#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
1443//XPB_CLG_GFX_UNITID_MAPPING3
1444#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
1445#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
1446#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
1447#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
1448#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
1449#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
1450//XPB_CLG_GFX_UNITID_MAPPING4
1451#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0
1452#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5
1453#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6
1454#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL
1455#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L
1456#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L
1457//XPB_CLG_GFX_UNITID_MAPPING5
1458#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0
1459#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5
1460#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6
1461#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL
1462#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L
1463#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L
1464//XPB_CLG_GFX_UNITID_MAPPING6
1465#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0
1466#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5
1467#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6
1468#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL
1469#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L
1470#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L
1471//XPB_CLG_GFX_UNITID_MAPPING7
1472#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0
1473#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5
1474#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6
1475#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL
1476#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L
1477#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L
1478//XPB_CLG_MM_UNITID_MAPPING0
1479#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0
1480#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
1481#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6
1482#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL
1483#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L
1484#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L
1485//XPB_CLG_MM_UNITID_MAPPING1
1486#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0
1487#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
1488#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6
1489#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL
1490#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L
1491#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L
1492//XPB_CLG_MM_UNITID_MAPPING2
1493#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0
1494#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
1495#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6
1496#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL
1497#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L
1498#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L
1499//XPB_CLG_MM_UNITID_MAPPING3
1500#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0
1501#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
1502#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6
1503#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL
1504#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L
1505#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L
1506
1507
1508// addressBlock: aid_athub_rpbdec
1509//RPB_PASSPW_CONF
1510#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0
1511#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1
1512#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2
1513#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3
1514#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4
1515#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5
1516#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6
1517#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7
1518#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8
1519#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9
1520#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa
1521#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb
1522#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc
1523#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd
1524#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe
1525#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf
1526#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10
1527#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11
1528#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L
1529#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L
1530#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L
1531#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L
1532#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L
1533#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L
1534#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L
1535#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L
1536#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L
1537#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L
1538#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L
1539#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L
1540#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L
1541#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L
1542#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L
1543#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L
1544#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L
1545#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L
1546//RPB_BLOCKLEVEL_CONF
1547#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0
1548#define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL__SHIFT 0x2
1549#define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL__SHIFT 0x4
1550#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x6
1551#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x8
1552#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xa
1553#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xc
1554#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xe
1555#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10
1556#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11
1557#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x12
1558#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13
1559#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L
1560#define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL_MASK 0x0000000CL
1561#define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL_MASK 0x00000030L
1562#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x000000C0L
1563#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000300L
1564#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L
1565#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L
1566#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L
1567#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L
1568#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L
1569#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00040000L
1570#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L
1571//RPB_TAG_CONF
1572#define RPB_TAG_CONF__RPB_ATS_VC0_TR__SHIFT 0x0
1573#define RPB_TAG_CONF__RPB_ATS_VC5_TR__SHIFT 0xa
1574#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x14
1575#define RPB_TAG_CONF__RPB_ATS_VC0_TR_MASK 0x000003FFL
1576#define RPB_TAG_CONF__RPB_ATS_VC5_TR_MASK 0x000FFC00L
1577#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x3FF00000L
1578//RPB_TAG_CONF2
1579#define RPB_TAG_CONF2__RPB_IO_WR__SHIFT 0x0
1580#define RPB_TAG_CONF2__RPB_IO_MAX_LIMIT__SHIFT 0xa
1581#define RPB_TAG_CONF2__RPB_IO_RD_MARGIN__SHIFT 0x15
1582#define RPB_TAG_CONF2__RPB_IO_WR_MASK 0x000003FFL
1583#define RPB_TAG_CONF2__RPB_IO_MAX_LIMIT_MASK 0x001FFC00L
1584#define RPB_TAG_CONF2__RPB_IO_RD_MARGIN_MASK 0xFFE00000L
1585//RPB_ARB_CNTL
1586#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0
1587#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8
1588#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10
1589#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18
1590#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19
1591#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL
1592#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L
1593#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L
1594#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L
1595#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L
1596//RPB_ARB_CNTL2
1597#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0
1598#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8
1599#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10
1600#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL
1601#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L
1602#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L
1603//RPB_BIF_CNTL
1604#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x0
1605#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x1
1606#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x3
1607#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x4
1608#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0xc
1609#define RPB_BIF_CNTL__VC0TR_PRI_EN__SHIFT 0xd
1610#define RPB_BIF_CNTL__VC5TR_PRI_EN__SHIFT 0xe
1611#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0xf
1612#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00000001L
1613#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00000006L
1614#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00000008L
1615#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x00000FF0L
1616#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x00001000L
1617#define RPB_BIF_CNTL__VC0TR_PRI_EN_MASK 0x00002000L
1618#define RPB_BIF_CNTL__VC5TR_PRI_EN_MASK 0x00004000L
1619#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x00008000L
1620//RPB_BIF_CNTL2
1621#define RPB_BIF_CNTL2__VC0_SWITCH_NUM__SHIFT 0x0
1622#define RPB_BIF_CNTL2__VC1_SWITCH_NUM__SHIFT 0x8
1623#define RPB_BIF_CNTL2__VC5_SWITCH_NUM__SHIFT 0x10
1624#define RPB_BIF_CNTL2__VC0_SWITCH_NUM_MASK 0x000000FFL
1625#define RPB_BIF_CNTL2__VC1_SWITCH_NUM_MASK 0x0000FF00L
1626#define RPB_BIF_CNTL2__VC5_SWITCH_NUM_MASK 0x00FF0000L
1627//RPB_PERF_COUNTER_CNTL
1628#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
1629#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
1630#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
1631#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
1632#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
1633#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
1634#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
1635#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
1636#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
1637#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L
1638#define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L
1639#define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L
1640#define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L
1641#define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L
1642#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L
1643#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L
1644#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L
1645#define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L
1646//RPB_DEINTRLV_COMBINE_CNTL
1647#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0
1648#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4
1649#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5
1650#define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN__SHIFT 0x6
1651#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL
1652#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L
1653#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L
1654#define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN_MASK 0x00000040L
1655//RPB_VC_SWITCH_RDWR
1656#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0
1657#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2
1658#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa
1659#define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12
1660#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L
1661#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL
1662#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L
1663#define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L
1664//RPB_PERFCOUNTER_LO
1665#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
1666#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
1667//RPB_PERFCOUNTER_HI
1668#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
1669#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
1670#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
1671#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
1672//RPB_PERFCOUNTER0_CFG
1673#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
1674#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
1675#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
1676#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
1677#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
1678#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
1679#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
1680#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
1681#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
1682#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
1683//RPB_PERFCOUNTER1_CFG
1684#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
1685#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
1686#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
1687#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
1688#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
1689#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
1690#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
1691#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
1692#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
1693#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
1694//RPB_PERFCOUNTER2_CFG
1695#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
1696#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
1697#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
1698#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
1699#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
1700#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
1701#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
1702#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
1703#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
1704#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
1705//RPB_PERFCOUNTER3_CFG
1706#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
1707#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
1708#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
1709#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
1710#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
1711#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
1712#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
1713#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
1714#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
1715#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
1716//RPB_PERFCOUNTER_RSLT_CNTL
1717#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
1718#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
1719#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
1720#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
1721#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
1722#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
1723#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
1724#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
1725#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
1726#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
1727#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
1728#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
1729//RPB_ATS_CNTL
1730#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0
1731#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1
1732#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2
1733#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7
1734#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf
1735#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13
1736#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17
1737#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19
1738#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L
1739#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L
1740#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL
1741#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L
1742#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L
1743#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L
1744#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L
1745#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L
1746//RPB_ATS_CNTL2
1747#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0
1748#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6
1749#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc
1750#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf
1751#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12
1752#define RPB_ATS_CNTL2__MM_TRANS_VC5_ENABLE__SHIFT 0x14
1753#define RPB_ATS_CNTL2__GC_TRANS_VC5_ENABLE__SHIFT 0x15
1754#define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x16
1755#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL
1756#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L
1757#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L
1758#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L
1759#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L
1760#define RPB_ATS_CNTL2__MM_TRANS_VC5_ENABLE_MASK 0x00100000L
1761#define RPB_ATS_CNTL2__GC_TRANS_VC5_ENABLE_MASK 0x00200000L
1762#define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x07C00000L
1763//RPB_SDPPORT_CNTL
1764#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0
1765#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1
1766#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3
1767#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4
1768#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5
1769#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6
1770#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa
1771#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb
1772#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd
1773#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe
1774#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf
1775#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10
1776#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14
1777#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15
1778#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16
1779#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17
1780#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18
1781#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19
1782#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a
1783#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b
1784#define RPB_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0x1c
1785#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L
1786#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L
1787#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L
1788#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L
1789#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L
1790#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L
1791#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L
1792#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L
1793#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L
1794#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L
1795#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L
1796#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L
1797#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L
1798#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L
1799#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L
1800#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L
1801#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L
1802#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L
1803#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L
1804#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L
1805#define RPB_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0xF0000000L
1806
1807#endif
1808

source code of linux/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_8_0_sh_mask.h