1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _athub_2_0_0_OFFSET_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: athub_atsdec |
26 | // base address: 0x3000 |
27 | #define mmATC_ATS_CNTL 0x0000 |
28 | #define mmATC_ATS_CNTL_BASE_IDX 0 |
29 | #define mmATC_ATS_STATUS 0x0003 |
30 | #define mmATC_ATS_STATUS_BASE_IDX 0 |
31 | #define mmATC_ATS_FAULT_CNTL 0x0004 |
32 | #define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 |
33 | #define mmATC_ATS_FAULT_STATUS_INFO 0x0005 |
34 | #define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 |
35 | #define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 |
36 | #define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 |
37 | #define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 |
38 | #define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 |
39 | #define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 |
40 | #define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 |
41 | #define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 |
42 | #define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 |
43 | #define mmATHUB_MISC_CNTL 0x000a |
44 | #define mmATHUB_MISC_CNTL_BASE_IDX 0 |
45 | #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b |
46 | #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 |
47 | #define mmATC_VMID0_PASID_MAPPING 0x000c |
48 | #define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 |
49 | #define mmATC_VMID1_PASID_MAPPING 0x000d |
50 | #define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 |
51 | #define mmATC_VMID2_PASID_MAPPING 0x000e |
52 | #define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 |
53 | #define mmATC_VMID3_PASID_MAPPING 0x000f |
54 | #define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 |
55 | #define mmATC_VMID4_PASID_MAPPING 0x0010 |
56 | #define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 |
57 | #define mmATC_VMID5_PASID_MAPPING 0x0011 |
58 | #define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 |
59 | #define mmATC_VMID6_PASID_MAPPING 0x0012 |
60 | #define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 |
61 | #define mmATC_VMID7_PASID_MAPPING 0x0013 |
62 | #define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 |
63 | #define mmATC_VMID8_PASID_MAPPING 0x0014 |
64 | #define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 |
65 | #define mmATC_VMID9_PASID_MAPPING 0x0015 |
66 | #define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 |
67 | #define mmATC_VMID10_PASID_MAPPING 0x0016 |
68 | #define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 |
69 | #define mmATC_VMID11_PASID_MAPPING 0x0017 |
70 | #define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 |
71 | #define mmATC_VMID12_PASID_MAPPING 0x0018 |
72 | #define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 |
73 | #define mmATC_VMID13_PASID_MAPPING 0x0019 |
74 | #define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 |
75 | #define mmATC_VMID14_PASID_MAPPING 0x001a |
76 | #define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 |
77 | #define mmATC_VMID15_PASID_MAPPING 0x001b |
78 | #define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 |
79 | #define mmATC_ATS_VMID_STATUS 0x001c |
80 | #define mmATC_ATS_VMID_STATUS_BASE_IDX 0 |
81 | #define mmATC_ATS_GFX_ATCL2_STATUS 0x001d |
82 | #define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 |
83 | #define mmATC_PERFCOUNTER0_CFG 0x001e |
84 | #define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 |
85 | #define mmATC_PERFCOUNTER1_CFG 0x001f |
86 | #define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 |
87 | #define mmATC_PERFCOUNTER2_CFG 0x0020 |
88 | #define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 |
89 | #define mmATC_PERFCOUNTER3_CFG 0x0021 |
90 | #define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 |
91 | #define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 |
92 | #define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
93 | #define mmATC_PERFCOUNTER_LO 0x0023 |
94 | #define mmATC_PERFCOUNTER_LO_BASE_IDX 0 |
95 | #define mmATC_PERFCOUNTER_HI 0x0024 |
96 | #define mmATC_PERFCOUNTER_HI_BASE_IDX 0 |
97 | #define mmATHUB_PCIE_ATS_CNTL 0x0025 |
98 | #define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 |
99 | #define mmATHUB_PCIE_PASID_CNTL 0x0026 |
100 | #define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 |
101 | #define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 |
102 | #define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 |
103 | #define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 |
104 | #define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 |
105 | #define mmATHUB_COMMAND 0x0029 |
106 | #define mmATHUB_COMMAND_BASE_IDX 0 |
107 | #define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a |
108 | #define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 |
109 | #define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b |
110 | #define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 |
111 | #define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c |
112 | #define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 |
113 | #define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d |
114 | #define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 |
115 | #define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e |
116 | #define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 |
117 | #define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f |
118 | #define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 |
119 | #define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 |
120 | #define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 |
121 | #define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 |
122 | #define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 |
123 | #define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 |
124 | #define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 |
125 | #define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 |
126 | #define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 |
127 | #define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 |
128 | #define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 |
129 | #define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 |
130 | #define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 |
131 | #define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 |
132 | #define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 |
133 | #define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 |
134 | #define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 |
135 | #define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 |
136 | #define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 |
137 | #define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 |
138 | #define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 |
139 | #define mmATHUB_PCIE_ATS_CNTL_VF_16 0x003a |
140 | #define mmATHUB_PCIE_ATS_CNTL_VF_16_BASE_IDX 0 |
141 | #define mmATHUB_PCIE_ATS_CNTL_VF_17 0x003b |
142 | #define mmATHUB_PCIE_ATS_CNTL_VF_17_BASE_IDX 0 |
143 | #define mmATHUB_PCIE_ATS_CNTL_VF_18 0x003c |
144 | #define mmATHUB_PCIE_ATS_CNTL_VF_18_BASE_IDX 0 |
145 | #define mmATHUB_PCIE_ATS_CNTL_VF_19 0x003d |
146 | #define mmATHUB_PCIE_ATS_CNTL_VF_19_BASE_IDX 0 |
147 | #define mmATHUB_PCIE_ATS_CNTL_VF_20 0x003e |
148 | #define mmATHUB_PCIE_ATS_CNTL_VF_20_BASE_IDX 0 |
149 | #define mmATHUB_PCIE_ATS_CNTL_VF_21 0x003f |
150 | #define mmATHUB_PCIE_ATS_CNTL_VF_21_BASE_IDX 0 |
151 | #define mmATHUB_PCIE_ATS_CNTL_VF_22 0x0040 |
152 | #define mmATHUB_PCIE_ATS_CNTL_VF_22_BASE_IDX 0 |
153 | #define mmATHUB_PCIE_ATS_CNTL_VF_23 0x0041 |
154 | #define mmATHUB_PCIE_ATS_CNTL_VF_23_BASE_IDX 0 |
155 | #define mmATHUB_PCIE_ATS_CNTL_VF_24 0x0042 |
156 | #define mmATHUB_PCIE_ATS_CNTL_VF_24_BASE_IDX 0 |
157 | #define mmATHUB_PCIE_ATS_CNTL_VF_25 0x0043 |
158 | #define mmATHUB_PCIE_ATS_CNTL_VF_25_BASE_IDX 0 |
159 | #define mmATHUB_PCIE_ATS_CNTL_VF_26 0x0044 |
160 | #define mmATHUB_PCIE_ATS_CNTL_VF_26_BASE_IDX 0 |
161 | #define mmATHUB_PCIE_ATS_CNTL_VF_27 0x0045 |
162 | #define mmATHUB_PCIE_ATS_CNTL_VF_27_BASE_IDX 0 |
163 | #define mmATHUB_PCIE_ATS_CNTL_VF_28 0x0046 |
164 | #define mmATHUB_PCIE_ATS_CNTL_VF_28_BASE_IDX 0 |
165 | #define mmATHUB_PCIE_ATS_CNTL_VF_29 0x0047 |
166 | #define mmATHUB_PCIE_ATS_CNTL_VF_29_BASE_IDX 0 |
167 | #define mmATHUB_PCIE_ATS_CNTL_VF_30 0x0048 |
168 | #define mmATHUB_PCIE_ATS_CNTL_VF_30_BASE_IDX 0 |
169 | #define mmATHUB_MEM_POWER_LS 0x0049 |
170 | #define mmATHUB_MEM_POWER_LS_BASE_IDX 0 |
171 | #define mmATS_IH_CREDIT 0x004a |
172 | #define mmATS_IH_CREDIT_BASE_IDX 0 |
173 | #define mmATHUB_IH_CREDIT 0x004b |
174 | #define mmATHUB_IH_CREDIT_BASE_IDX 0 |
175 | #define mmATC_VMID16_PASID_MAPPING 0x004c |
176 | #define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 |
177 | #define mmATC_VMID17_PASID_MAPPING 0x004d |
178 | #define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 |
179 | #define mmATC_VMID18_PASID_MAPPING 0x004e |
180 | #define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 |
181 | #define mmATC_VMID19_PASID_MAPPING 0x004f |
182 | #define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 |
183 | #define mmATC_VMID20_PASID_MAPPING 0x0050 |
184 | #define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 |
185 | #define mmATC_VMID21_PASID_MAPPING 0x0051 |
186 | #define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 |
187 | #define mmATC_VMID22_PASID_MAPPING 0x0052 |
188 | #define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 |
189 | #define mmATC_VMID23_PASID_MAPPING 0x0053 |
190 | #define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 |
191 | #define mmATC_VMID24_PASID_MAPPING 0x0054 |
192 | #define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 |
193 | #define mmATC_VMID25_PASID_MAPPING 0x0055 |
194 | #define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 |
195 | #define mmATC_VMID26_PASID_MAPPING 0x0056 |
196 | #define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 |
197 | #define mmATC_VMID27_PASID_MAPPING 0x0057 |
198 | #define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 |
199 | #define mmATC_VMID28_PASID_MAPPING 0x0058 |
200 | #define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 |
201 | #define mmATC_VMID29_PASID_MAPPING 0x0059 |
202 | #define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 |
203 | #define mmATC_VMID30_PASID_MAPPING 0x005a |
204 | #define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 |
205 | #define mmATC_VMID31_PASID_MAPPING 0x005b |
206 | #define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 |
207 | #define mmATC_ATS_MMHUB_ATCL2_STATUS 0x005c |
208 | #define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 |
209 | #define mmATHUB_SHARED_VIRT_RESET_REQ 0x005d |
210 | #define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 |
211 | #define mmATHUB_SHARED_ACTIVE_FCN_ID 0x005e |
212 | #define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 |
213 | #define mmATC_ATS_SDPPORT_CNTL 0x005f |
214 | #define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 |
215 | #define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0061 |
216 | #define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 |
217 | #define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0062 |
218 | #define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 |
219 | |
220 | |
221 | // addressBlock: athub_xpbdec |
222 | // base address: 0x3190 |
223 | #define mmXPB_RTR_SRC_APRTR0 0x0064 |
224 | #define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 |
225 | #define mmXPB_RTR_SRC_APRTR1 0x0065 |
226 | #define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 |
227 | #define mmXPB_RTR_SRC_APRTR2 0x0066 |
228 | #define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 |
229 | #define mmXPB_RTR_SRC_APRTR3 0x0067 |
230 | #define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 |
231 | #define mmXPB_RTR_SRC_APRTR4 0x0068 |
232 | #define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 |
233 | #define mmXPB_RTR_SRC_APRTR5 0x0069 |
234 | #define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 |
235 | #define mmXPB_RTR_SRC_APRTR6 0x006a |
236 | #define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 |
237 | #define mmXPB_RTR_SRC_APRTR7 0x006b |
238 | #define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 |
239 | #define mmXPB_RTR_SRC_APRTR8 0x006c |
240 | #define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 |
241 | #define mmXPB_RTR_SRC_APRTR9 0x006d |
242 | #define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 |
243 | #define mmXPB_XDMA_RTR_SRC_APRTR0 0x006e |
244 | #define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 |
245 | #define mmXPB_XDMA_RTR_SRC_APRTR1 0x006f |
246 | #define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 |
247 | #define mmXPB_XDMA_RTR_SRC_APRTR2 0x0070 |
248 | #define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 |
249 | #define mmXPB_XDMA_RTR_SRC_APRTR3 0x0071 |
250 | #define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 |
251 | #define mmXPB_RTR_DEST_MAP0 0x0072 |
252 | #define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 |
253 | #define mmXPB_RTR_DEST_MAP1 0x0073 |
254 | #define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 |
255 | #define mmXPB_RTR_DEST_MAP2 0x0074 |
256 | #define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 |
257 | #define mmXPB_RTR_DEST_MAP3 0x0075 |
258 | #define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 |
259 | #define mmXPB_RTR_DEST_MAP4 0x0076 |
260 | #define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 |
261 | #define mmXPB_RTR_DEST_MAP5 0x0077 |
262 | #define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 |
263 | #define mmXPB_RTR_DEST_MAP6 0x0078 |
264 | #define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 |
265 | #define mmXPB_RTR_DEST_MAP7 0x0079 |
266 | #define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 |
267 | #define mmXPB_RTR_DEST_MAP8 0x007a |
268 | #define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 |
269 | #define mmXPB_RTR_DEST_MAP9 0x007b |
270 | #define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 |
271 | #define mmXPB_XDMA_RTR_DEST_MAP0 0x007c |
272 | #define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 |
273 | #define mmXPB_XDMA_RTR_DEST_MAP1 0x007d |
274 | #define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 |
275 | #define mmXPB_XDMA_RTR_DEST_MAP2 0x007e |
276 | #define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 |
277 | #define mmXPB_XDMA_RTR_DEST_MAP3 0x007f |
278 | #define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 |
279 | #define mmXPB_CLG_CFG0 0x0080 |
280 | #define mmXPB_CLG_CFG0_BASE_IDX 0 |
281 | #define mmXPB_CLG_CFG1 0x0081 |
282 | #define mmXPB_CLG_CFG1_BASE_IDX 0 |
283 | #define mmXPB_CLG_CFG2 0x0082 |
284 | #define mmXPB_CLG_CFG2_BASE_IDX 0 |
285 | #define mmXPB_CLG_CFG3 0x0083 |
286 | #define mmXPB_CLG_CFG3_BASE_IDX 0 |
287 | #define mmXPB_CLG_CFG4 0x0084 |
288 | #define mmXPB_CLG_CFG4_BASE_IDX 0 |
289 | #define mmXPB_CLG_CFG5 0x0085 |
290 | #define mmXPB_CLG_CFG5_BASE_IDX 0 |
291 | #define mmXPB_CLG_CFG6 0x0086 |
292 | #define mmXPB_CLG_CFG6_BASE_IDX 0 |
293 | #define mmXPB_CLG_CFG7 0x0087 |
294 | #define mmXPB_CLG_CFG7_BASE_IDX 0 |
295 | #define 0x0088 |
296 | #define 0 |
297 | #define 0x0089 |
298 | #define 0 |
299 | #define mmXPB_LB_ADDR 0x008a |
300 | #define mmXPB_LB_ADDR_BASE_IDX 0 |
301 | #define mmXPB_WCB_STS 0x008b |
302 | #define mmXPB_WCB_STS_BASE_IDX 0 |
303 | #define mmXPB_HST_CFG 0x008c |
304 | #define mmXPB_HST_CFG_BASE_IDX 0 |
305 | #define mmXPB_P2P_BAR_CFG 0x008d |
306 | #define mmXPB_P2P_BAR_CFG_BASE_IDX 0 |
307 | #define mmXPB_P2P_BAR0 0x008e |
308 | #define mmXPB_P2P_BAR0_BASE_IDX 0 |
309 | #define mmXPB_P2P_BAR1 0x008f |
310 | #define mmXPB_P2P_BAR1_BASE_IDX 0 |
311 | #define mmXPB_P2P_BAR2 0x0090 |
312 | #define mmXPB_P2P_BAR2_BASE_IDX 0 |
313 | #define mmXPB_P2P_BAR3 0x0091 |
314 | #define mmXPB_P2P_BAR3_BASE_IDX 0 |
315 | #define mmXPB_P2P_BAR4 0x0092 |
316 | #define mmXPB_P2P_BAR4_BASE_IDX 0 |
317 | #define mmXPB_P2P_BAR5 0x0093 |
318 | #define mmXPB_P2P_BAR5_BASE_IDX 0 |
319 | #define mmXPB_P2P_BAR6 0x0094 |
320 | #define mmXPB_P2P_BAR6_BASE_IDX 0 |
321 | #define mmXPB_P2P_BAR7 0x0095 |
322 | #define mmXPB_P2P_BAR7_BASE_IDX 0 |
323 | #define mmXPB_P2P_BAR_SETUP 0x0096 |
324 | #define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 |
325 | #define mmXPB_P2P_BAR_DELTA_ABOVE 0x0098 |
326 | #define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 |
327 | #define mmXPB_P2P_BAR_DELTA_BELOW 0x0099 |
328 | #define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 |
329 | #define mmXPB_PEER_SYS_BAR0 0x009a |
330 | #define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 |
331 | #define mmXPB_PEER_SYS_BAR1 0x009b |
332 | #define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 |
333 | #define mmXPB_PEER_SYS_BAR2 0x009c |
334 | #define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 |
335 | #define mmXPB_PEER_SYS_BAR3 0x009d |
336 | #define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 |
337 | #define mmXPB_PEER_SYS_BAR4 0x009e |
338 | #define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 |
339 | #define mmXPB_PEER_SYS_BAR5 0x009f |
340 | #define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 |
341 | #define mmXPB_PEER_SYS_BAR6 0x00a0 |
342 | #define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 |
343 | #define mmXPB_PEER_SYS_BAR7 0x00a1 |
344 | #define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 |
345 | #define mmXPB_PEER_SYS_BAR8 0x00a2 |
346 | #define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 |
347 | #define mmXPB_PEER_SYS_BAR9 0x00a3 |
348 | #define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 |
349 | #define mmXPB_XDMA_PEER_SYS_BAR0 0x00a4 |
350 | #define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 |
351 | #define mmXPB_XDMA_PEER_SYS_BAR1 0x00a5 |
352 | #define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 |
353 | #define mmXPB_XDMA_PEER_SYS_BAR2 0x00a6 |
354 | #define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 |
355 | #define mmXPB_XDMA_PEER_SYS_BAR3 0x00a7 |
356 | #define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 |
357 | #define mmXPB_CLK_GAT 0x00a8 |
358 | #define mmXPB_CLK_GAT_BASE_IDX 0 |
359 | #define mmXPB_INTF_CFG 0x00a9 |
360 | #define mmXPB_INTF_CFG_BASE_IDX 0 |
361 | #define mmXPB_INTF_STS 0x00aa |
362 | #define mmXPB_INTF_STS_BASE_IDX 0 |
363 | #define mmXPB_PIPE_STS 0x00ab |
364 | #define mmXPB_PIPE_STS_BASE_IDX 0 |
365 | #define mmXPB_SUB_CTRL 0x00ac |
366 | #define mmXPB_SUB_CTRL_BASE_IDX 0 |
367 | #define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00ad |
368 | #define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 |
369 | #define mmXPB_PERF_KNOBS 0x00ae |
370 | #define mmXPB_PERF_KNOBS_BASE_IDX 0 |
371 | #define mmXPB_STICKY 0x00af |
372 | #define mmXPB_STICKY_BASE_IDX 0 |
373 | #define mmXPB_STICKY_W1C 0x00b0 |
374 | #define mmXPB_STICKY_W1C_BASE_IDX 0 |
375 | #define mmXPB_MISC_CFG 0x00b1 |
376 | #define mmXPB_MISC_CFG_BASE_IDX 0 |
377 | #define mmXPB_INTF_CFG2 0x00b2 |
378 | #define mmXPB_INTF_CFG2_BASE_IDX 0 |
379 | #define 0x00b3 |
380 | #define 0 |
381 | #define 0x00b4 |
382 | #define 0 |
383 | #define mmXPB_CLG_GFX_MATCH 0x00b5 |
384 | #define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 |
385 | #define mmXPB_CLG_GFX_MATCH_MSK 0x00b6 |
386 | #define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 |
387 | #define mmXPB_CLG_MM_MATCH 0x00b7 |
388 | #define mmXPB_CLG_MM_MATCH_BASE_IDX 0 |
389 | #define mmXPB_CLG_MM_MATCH_MSK 0x00b8 |
390 | #define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 |
391 | #define mmXPB_CLG_GUS_MATCH 0x00b9 |
392 | #define mmXPB_CLG_GUS_MATCH_BASE_IDX 0 |
393 | #define mmXPB_CLG_GUS_MATCH_MSK 0x00ba |
394 | #define mmXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0 |
395 | #define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00bb |
396 | #define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 |
397 | #define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00bc |
398 | #define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 |
399 | #define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00bd |
400 | #define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 |
401 | #define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00be |
402 | #define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 |
403 | #define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00bf |
404 | #define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 |
405 | #define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00c0 |
406 | #define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 |
407 | #define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00c1 |
408 | #define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 |
409 | #define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00c2 |
410 | #define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 |
411 | #define mmXPB_CLG_MM_UNITID_MAPPING0 0x00c3 |
412 | #define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 |
413 | #define mmXPB_CLG_MM_UNITID_MAPPING1 0x00c4 |
414 | #define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 |
415 | #define mmXPB_CLG_MM_UNITID_MAPPING2 0x00c5 |
416 | #define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 |
417 | #define mmXPB_CLG_MM_UNITID_MAPPING3 0x00c6 |
418 | #define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 |
419 | #define mmXPB_CLG_GUS_UNITID_MAPPING0 0x00c7 |
420 | #define mmXPB_CLG_GUS_UNITID_MAPPING0_BASE_IDX 0 |
421 | #define mmXPB_CLG_GUS_UNITID_MAPPING1 0x00c8 |
422 | #define mmXPB_CLG_GUS_UNITID_MAPPING1_BASE_IDX 0 |
423 | #define mmXPB_CLG_GUS_UNITID_MAPPING2 0x00c9 |
424 | #define mmXPB_CLG_GUS_UNITID_MAPPING2_BASE_IDX 0 |
425 | #define mmXPB_CLG_GUS_UNITID_MAPPING3 0x00ca |
426 | #define mmXPB_CLG_GUS_UNITID_MAPPING3_BASE_IDX 0 |
427 | #define mmXPB_CLG_GUS_UNITID_MAPPING4 0x00cb |
428 | #define mmXPB_CLG_GUS_UNITID_MAPPING4_BASE_IDX 0 |
429 | #define mmXPB_CLG_GUS_UNITID_MAPPING5 0x00cc |
430 | #define mmXPB_CLG_GUS_UNITID_MAPPING5_BASE_IDX 0 |
431 | #define mmXPB_CLG_GUS_UNITID_MAPPING6 0x00cd |
432 | #define mmXPB_CLG_GUS_UNITID_MAPPING6_BASE_IDX 0 |
433 | #define mmXPB_CLG_GUS_UNITID_MAPPING7 0x00ce |
434 | #define mmXPB_CLG_GUS_UNITID_MAPPING7_BASE_IDX 0 |
435 | |
436 | |
437 | // addressBlock: athub_rpbdec |
438 | // base address: 0x3350 |
439 | #define mmRPB_PASSPW_CONF 0x00d4 |
440 | #define mmRPB_PASSPW_CONF_BASE_IDX 0 |
441 | #define mmRPB_BLOCKLEVEL_CONF 0x00d5 |
442 | #define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 |
443 | #define mmRPB_TAG_CONF 0x00d7 |
444 | #define mmRPB_TAG_CONF_BASE_IDX 0 |
445 | #define mmRPB_EFF_CNTL 0x00d9 |
446 | #define mmRPB_EFF_CNTL_BASE_IDX 0 |
447 | #define mmRPB_ARB_CNTL 0x00da |
448 | #define mmRPB_ARB_CNTL_BASE_IDX 0 |
449 | #define mmRPB_ARB_CNTL2 0x00db |
450 | #define mmRPB_ARB_CNTL2_BASE_IDX 0 |
451 | #define mmRPB_BIF_CNTL 0x00dc |
452 | #define mmRPB_BIF_CNTL_BASE_IDX 0 |
453 | #define mmRPB_WR_SWITCH_CNTL 0x00dd |
454 | #define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 |
455 | #define mmRPB_WR_COMBINE_CNTL 0x00de |
456 | #define mmRPB_WR_COMBINE_CNTL_BASE_IDX 0 |
457 | #define mmRPB_RD_SWITCH_CNTL 0x00df |
458 | #define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 |
459 | #define mmRPB_CID_QUEUE_WR 0x00e0 |
460 | #define mmRPB_CID_QUEUE_WR_BASE_IDX 0 |
461 | #define mmRPB_CID_QUEUE_RD 0x00e1 |
462 | #define mmRPB_CID_QUEUE_RD_BASE_IDX 0 |
463 | #define mmRPB_PERF_COUNTER_CNTL 0x00e2 |
464 | #define mmRPB_PERF_COUNTER_CNTL_BASE_IDX 0 |
465 | #define mmRPB_PERF_COUNTER_STATUS 0x00e3 |
466 | #define mmRPB_PERF_COUNTER_STATUS_BASE_IDX 0 |
467 | #define mmRPB_CID_QUEUE_EX 0x00e4 |
468 | #define mmRPB_CID_QUEUE_EX_BASE_IDX 0 |
469 | #define mmRPB_CID_QUEUE_EX_DATA 0x00e5 |
470 | #define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 |
471 | #define mmRPB_SWITCH_CNTL2 0x00e6 |
472 | #define mmRPB_SWITCH_CNTL2_BASE_IDX 0 |
473 | #define mmRPB_DEINTRLV_COMBINE_CNTL 0x00e7 |
474 | #define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 |
475 | #define mmRPB_VC_SWITCH_RDWR 0x00e8 |
476 | #define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 |
477 | #define mmRPB_PERFCOUNTER_LO 0x00e9 |
478 | #define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 |
479 | #define mmRPB_PERFCOUNTER_HI 0x00ea |
480 | #define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 |
481 | #define mmRPB_PERFCOUNTER0_CFG 0x00eb |
482 | #define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 |
483 | #define mmRPB_PERFCOUNTER1_CFG 0x00ec |
484 | #define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 |
485 | #define mmRPB_PERFCOUNTER2_CFG 0x00ed |
486 | #define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 |
487 | #define mmRPB_PERFCOUNTER3_CFG 0x00ee |
488 | #define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 |
489 | #define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00ef |
490 | #define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
491 | #define mmRPB_BIF_CNTL2 0x00f0 |
492 | #define mmRPB_BIF_CNTL2_BASE_IDX 0 |
493 | #define mmRPB_RD_QUEUE_CNTL 0x00f1 |
494 | #define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 |
495 | #define mmRPB_RD_QUEUE_CNTL2 0x00f2 |
496 | #define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 |
497 | #define mmRPB_WR_QUEUE_CNTL 0x00f3 |
498 | #define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 |
499 | #define mmRPB_WR_QUEUE_CNTL2 0x00f4 |
500 | #define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 |
501 | #define mmRPB_EA_QUEUE_WR 0x00f5 |
502 | #define mmRPB_EA_QUEUE_WR_BASE_IDX 0 |
503 | #define mmRPB_ATS_CNTL 0x00f6 |
504 | #define mmRPB_ATS_CNTL_BASE_IDX 0 |
505 | #define mmRPB_ATS_CNTL2 0x00f7 |
506 | #define mmRPB_ATS_CNTL2_BASE_IDX 0 |
507 | #define mmRPB_DF_SDPPORT_CNTL 0x00f8 |
508 | #define mmRPB_DF_SDPPORT_CNTL_BASE_IDX 0 |
509 | #define mmRPB_SDPPORT_CNTL 0x00f9 |
510 | #define mmRPB_SDPPORT_CNTL_BASE_IDX 0 |
511 | #define mmRPB_NBIF_SDPPORT_CNTL 0x00fa |
512 | #define mmRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0 |
513 | |
514 | #endif |
515 | |