1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _athub_3_0_0_OFFSET_HEADER
24#define _athub_3_0_0_OFFSET_HEADER
25
26
27
28// addressBlock: athub_xpbdec
29// base address: 0x3000
30#define regXPB_RTR_SRC_APRTR0 0x0000
31#define regXPB_RTR_SRC_APRTR0_BASE_IDX 0
32#define regXPB_RTR_SRC_APRTR1 0x0001
33#define regXPB_RTR_SRC_APRTR1_BASE_IDX 0
34#define regXPB_RTR_SRC_APRTR2 0x0002
35#define regXPB_RTR_SRC_APRTR2_BASE_IDX 0
36#define regXPB_RTR_SRC_APRTR3 0x0003
37#define regXPB_RTR_SRC_APRTR3_BASE_IDX 0
38#define regXPB_RTR_SRC_APRTR4 0x0004
39#define regXPB_RTR_SRC_APRTR4_BASE_IDX 0
40#define regXPB_RTR_SRC_APRTR5 0x0005
41#define regXPB_RTR_SRC_APRTR5_BASE_IDX 0
42#define regXPB_RTR_SRC_APRTR6 0x0006
43#define regXPB_RTR_SRC_APRTR6_BASE_IDX 0
44#define regXPB_RTR_SRC_APRTR7 0x0007
45#define regXPB_RTR_SRC_APRTR7_BASE_IDX 0
46#define regXPB_RTR_SRC_APRTR8 0x0008
47#define regXPB_RTR_SRC_APRTR8_BASE_IDX 0
48#define regXPB_RTR_SRC_APRTR9 0x0009
49#define regXPB_RTR_SRC_APRTR9_BASE_IDX 0
50#define regXPB_RTR_SRC_APRTR10 0x000a
51#define regXPB_RTR_SRC_APRTR10_BASE_IDX 0
52#define regXPB_RTR_SRC_APRTR11 0x000b
53#define regXPB_RTR_SRC_APRTR11_BASE_IDX 0
54#define regXPB_RTR_SRC_APRTR12 0x000c
55#define regXPB_RTR_SRC_APRTR12_BASE_IDX 0
56#define regXPB_RTR_SRC_APRTR13 0x000d
57#define regXPB_RTR_SRC_APRTR13_BASE_IDX 0
58#define regXPB_RTR_DEST_MAP0 0x000e
59#define regXPB_RTR_DEST_MAP0_BASE_IDX 0
60#define regXPB_RTR_DEST_MAP1 0x000f
61#define regXPB_RTR_DEST_MAP1_BASE_IDX 0
62#define regXPB_RTR_DEST_MAP2 0x0010
63#define regXPB_RTR_DEST_MAP2_BASE_IDX 0
64#define regXPB_RTR_DEST_MAP3 0x0011
65#define regXPB_RTR_DEST_MAP3_BASE_IDX 0
66#define regXPB_RTR_DEST_MAP4 0x0012
67#define regXPB_RTR_DEST_MAP4_BASE_IDX 0
68#define regXPB_RTR_DEST_MAP5 0x0013
69#define regXPB_RTR_DEST_MAP5_BASE_IDX 0
70#define regXPB_RTR_DEST_MAP6 0x0014
71#define regXPB_RTR_DEST_MAP6_BASE_IDX 0
72#define regXPB_RTR_DEST_MAP7 0x0015
73#define regXPB_RTR_DEST_MAP7_BASE_IDX 0
74#define regXPB_RTR_DEST_MAP8 0x0016
75#define regXPB_RTR_DEST_MAP8_BASE_IDX 0
76#define regXPB_RTR_DEST_MAP9 0x0017
77#define regXPB_RTR_DEST_MAP9_BASE_IDX 0
78#define regXPB_RTR_DEST_MAP10 0x0018
79#define regXPB_RTR_DEST_MAP10_BASE_IDX 0
80#define regXPB_RTR_DEST_MAP11 0x0019
81#define regXPB_RTR_DEST_MAP11_BASE_IDX 0
82#define regXPB_RTR_DEST_MAP12 0x001a
83#define regXPB_RTR_DEST_MAP12_BASE_IDX 0
84#define regXPB_RTR_DEST_MAP13 0x001b
85#define regXPB_RTR_DEST_MAP13_BASE_IDX 0
86#define regXPB_CLG_CFG0 0x001c
87#define regXPB_CLG_CFG0_BASE_IDX 0
88#define regXPB_CLG_CFG1 0x001d
89#define regXPB_CLG_CFG1_BASE_IDX 0
90#define regXPB_CLG_CFG2 0x001e
91#define regXPB_CLG_CFG2_BASE_IDX 0
92#define regXPB_CLG_CFG3 0x001f
93#define regXPB_CLG_CFG3_BASE_IDX 0
94#define regXPB_CLG_CFG4 0x0020
95#define regXPB_CLG_CFG4_BASE_IDX 0
96#define regXPB_CLG_CFG5 0x0021
97#define regXPB_CLG_CFG5_BASE_IDX 0
98#define regXPB_CLG_CFG6 0x0022
99#define regXPB_CLG_CFG6_BASE_IDX 0
100#define regXPB_CLG_CFG7 0x0023
101#define regXPB_CLG_CFG7_BASE_IDX 0
102#define regXPB_CLG_EXTRA 0x0024
103#define regXPB_CLG_EXTRA_BASE_IDX 0
104#define regXPB_CLG_EXTRA_MSK 0x0025
105#define regXPB_CLG_EXTRA_MSK_BASE_IDX 0
106#define regXPB_LB_ADDR 0x0026
107#define regXPB_LB_ADDR_BASE_IDX 0
108#define regXPB_WCB_STS 0x0027
109#define regXPB_WCB_STS_BASE_IDX 0
110#define regXPB_HST_CFG 0x0028
111#define regXPB_HST_CFG_BASE_IDX 0
112#define regXPB_P2P_BAR_CFG 0x0029
113#define regXPB_P2P_BAR_CFG_BASE_IDX 0
114#define regXPB_P2P_BAR0 0x002a
115#define regXPB_P2P_BAR0_BASE_IDX 0
116#define regXPB_P2P_BAR1 0x002b
117#define regXPB_P2P_BAR1_BASE_IDX 0
118#define regXPB_P2P_BAR2 0x002c
119#define regXPB_P2P_BAR2_BASE_IDX 0
120#define regXPB_P2P_BAR3 0x002d
121#define regXPB_P2P_BAR3_BASE_IDX 0
122#define regXPB_P2P_BAR4 0x002e
123#define regXPB_P2P_BAR4_BASE_IDX 0
124#define regXPB_P2P_BAR5 0x002f
125#define regXPB_P2P_BAR5_BASE_IDX 0
126#define regXPB_P2P_BAR6 0x0030
127#define regXPB_P2P_BAR6_BASE_IDX 0
128#define regXPB_P2P_BAR7 0x0031
129#define regXPB_P2P_BAR7_BASE_IDX 0
130#define regXPB_P2P_BAR_SETUP 0x0032
131#define regXPB_P2P_BAR_SETUP_BASE_IDX 0
132#define regXPB_P2P_BAR_DELTA_ABOVE 0x0034
133#define regXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0
134#define regXPB_P2P_BAR_DELTA_BELOW 0x0035
135#define regXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0
136#define regXPB_PEER_SYS_BAR0 0x0036
137#define regXPB_PEER_SYS_BAR0_BASE_IDX 0
138#define regXPB_PEER_SYS_BAR1 0x0037
139#define regXPB_PEER_SYS_BAR1_BASE_IDX 0
140#define regXPB_PEER_SYS_BAR2 0x0038
141#define regXPB_PEER_SYS_BAR2_BASE_IDX 0
142#define regXPB_PEER_SYS_BAR3 0x0039
143#define regXPB_PEER_SYS_BAR3_BASE_IDX 0
144#define regXPB_PEER_SYS_BAR4 0x003a
145#define regXPB_PEER_SYS_BAR4_BASE_IDX 0
146#define regXPB_PEER_SYS_BAR5 0x003b
147#define regXPB_PEER_SYS_BAR5_BASE_IDX 0
148#define regXPB_PEER_SYS_BAR6 0x003c
149#define regXPB_PEER_SYS_BAR6_BASE_IDX 0
150#define regXPB_PEER_SYS_BAR7 0x003d
151#define regXPB_PEER_SYS_BAR7_BASE_IDX 0
152#define regXPB_PEER_SYS_BAR8 0x003e
153#define regXPB_PEER_SYS_BAR8_BASE_IDX 0
154#define regXPB_PEER_SYS_BAR9 0x003f
155#define regXPB_PEER_SYS_BAR9_BASE_IDX 0
156#define regXPB_PEER_SYS_BAR10 0x0040
157#define regXPB_PEER_SYS_BAR10_BASE_IDX 0
158#define regXPB_PEER_SYS_BAR11 0x0041
159#define regXPB_PEER_SYS_BAR11_BASE_IDX 0
160#define regXPB_PEER_SYS_BAR12 0x0042
161#define regXPB_PEER_SYS_BAR12_BASE_IDX 0
162#define regXPB_PEER_SYS_BAR13 0x0043
163#define regXPB_PEER_SYS_BAR13_BASE_IDX 0
164#define regXPB_CLK_GAT 0x0044
165#define regXPB_CLK_GAT_BASE_IDX 0
166#define regXPB_INTF_CFG 0x0045
167#define regXPB_INTF_CFG_BASE_IDX 0
168#define regXPB_INTF_STS 0x0046
169#define regXPB_INTF_STS_BASE_IDX 0
170#define regXPB_PIPE_STS 0x0047
171#define regXPB_PIPE_STS_BASE_IDX 0
172#define regXPB_SUB_CTRL 0x0048
173#define regXPB_SUB_CTRL_BASE_IDX 0
174#define regXPB_MAP_INVERT_FLUSH_NUM_LSB 0x0049
175#define regXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0
176#define regXPB_PERF_KNOBS 0x004a
177#define regXPB_PERF_KNOBS_BASE_IDX 0
178#define regXPB_STICKY 0x004b
179#define regXPB_STICKY_BASE_IDX 0
180#define regXPB_STICKY_W1C 0x004c
181#define regXPB_STICKY_W1C_BASE_IDX 0
182#define regXPB_MISC_CFG 0x004d
183#define regXPB_MISC_CFG_BASE_IDX 0
184#define regXPB_INTF_CFG2 0x004e
185#define regXPB_INTF_CFG2_BASE_IDX 0
186#define regXPB_CLG_EXTRA_RD 0x004f
187#define regXPB_CLG_EXTRA_RD_BASE_IDX 0
188#define regXPB_CLG_EXTRA_MSK_RD 0x0050
189#define regXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0
190#define regXPB_CLG_GFX_MATCH 0x0051
191#define regXPB_CLG_GFX_MATCH_BASE_IDX 0
192#define regXPB_CLG_GFX_MATCH_MSK 0x0052
193#define regXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0
194#define regXPB_CLG_MM_MATCH 0x0053
195#define regXPB_CLG_MM_MATCH_BASE_IDX 0
196#define regXPB_CLG_MM_MATCH_MSK 0x0054
197#define regXPB_CLG_MM_MATCH_MSK_BASE_IDX 0
198#define regXPB_CLG_GUS_MATCH 0x0055
199#define regXPB_CLG_GUS_MATCH_BASE_IDX 0
200#define regXPB_CLG_GUS_MATCH_MSK 0x0056
201#define regXPB_CLG_GUS_MATCH_MSK_BASE_IDX 0
202
203
204// addressBlock: athub_rpbdec
205// base address: 0x31b0
206#define regRPB_PASSPW_CONF 0x006c
207#define regRPB_PASSPW_CONF_BASE_IDX 0
208#define regRPB_BLOCKLEVEL_CONF 0x006d
209#define regRPB_BLOCKLEVEL_CONF_BASE_IDX 0
210#define regRPB_TAG_CONF 0x006e
211#define regRPB_TAG_CONF_BASE_IDX 0
212#define regRPB_ARB_CNTL 0x0071
213#define regRPB_ARB_CNTL_BASE_IDX 0
214#define regRPB_ARB_CNTL2 0x0072
215#define regRPB_ARB_CNTL2_BASE_IDX 0
216#define regRPB_BIF_CNTL 0x0073
217#define regRPB_BIF_CNTL_BASE_IDX 0
218#define regRPB_BIF_CNTL2 0x0074
219#define regRPB_BIF_CNTL2_BASE_IDX 0
220#define regATHUB_MISC_CNTL 0x0075
221#define regATHUB_MISC_CNTL_BASE_IDX 0
222#define regATHUB_MEM_POWER_LS 0x0078
223#define regATHUB_MEM_POWER_LS_BASE_IDX 0
224#define regRPB_SDPPORT_CNTL 0x007a
225#define regRPB_SDPPORT_CNTL_BASE_IDX 0
226#define regRPB_NBIF_SDPPORT_CNTL 0x007b
227#define regRPB_NBIF_SDPPORT_CNTL_BASE_IDX 0
228#define regRPB_DEINTRLV_COMBINE_CNTL 0x007c
229#define regRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0
230#define regRPB_VC_SWITCH_RDWR 0x007d
231#define regRPB_VC_SWITCH_RDWR_BASE_IDX 0
232#define regRPB_PERF_COUNTER_CNTL 0x007e
233#define regRPB_PERF_COUNTER_CNTL_BASE_IDX 0
234#define regRPB_PERF_COUNTER_STATUS 0x007f
235#define regRPB_PERF_COUNTER_STATUS_BASE_IDX 0
236#define regRPB_PERFCOUNTER_LO 0x0080
237#define regRPB_PERFCOUNTER_LO_BASE_IDX 0
238#define regRPB_PERFCOUNTER_HI 0x0081
239#define regRPB_PERFCOUNTER_HI_BASE_IDX 0
240#define regRPB_PERFCOUNTER0_CFG 0x0082
241#define regRPB_PERFCOUNTER0_CFG_BASE_IDX 0
242#define regRPB_PERFCOUNTER1_CFG 0x0083
243#define regRPB_PERFCOUNTER1_CFG_BASE_IDX 0
244#define regRPB_PERFCOUNTER2_CFG 0x0084
245#define regRPB_PERFCOUNTER2_CFG_BASE_IDX 0
246#define regRPB_PERFCOUNTER3_CFG 0x0085
247#define regRPB_PERFCOUNTER3_CFG_BASE_IDX 0
248#define regRPB_PERFCOUNTER_RSLT_CNTL 0x0086
249#define regRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
250#define regRPB_ATS_CNTL3 0x0087
251#define regRPB_ATS_CNTL3_BASE_IDX 0
252#define regRPB_DF_SDPPORT_CNTL 0x0088
253#define regRPB_DF_SDPPORT_CNTL_BASE_IDX 0
254#define regRPB_ATS_CNTL 0x0089
255#define regRPB_ATS_CNTL_BASE_IDX 0
256#define regRPB_ATS_CNTL2 0x008a
257#define regRPB_ATS_CNTL2_BASE_IDX 0
258
259#endif
260

source code of linux/drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h