| 1 | /* |
|---|
| 2 | * |
|---|
| 3 | * Copyright (C) 2016 Advanced Micro Devices, Inc. |
|---|
| 4 | * |
|---|
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
|---|
| 6 | * copy of this software and associated documentation files (the "Software"), |
|---|
| 7 | * to deal in the Software without restriction, including without limitation |
|---|
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
|---|
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
|---|
| 10 | * Software is furnished to do so, subject to the following conditions: |
|---|
| 11 | * |
|---|
| 12 | * The above copyright notice and this permission notice shall be included |
|---|
| 13 | * in all copies or substantial portions of the Software. |
|---|
| 14 | * |
|---|
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
|---|
| 16 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
|---|
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
|---|
| 18 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
|---|
| 19 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
|---|
| 20 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
|---|
| 21 | */ |
|---|
| 22 | |
|---|
| 23 | #ifndef BIF_3_0_SH_MASK_H |
|---|
| 24 | #define BIF_3_0_SH_MASK_H |
|---|
| 25 | |
|---|
| 26 | #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L |
|---|
| 27 | #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 |
|---|
| 28 | #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L |
|---|
| 29 | #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 |
|---|
| 30 | #define BACO_CNTL__BACO_EN_MASK 0x00000001L |
|---|
| 31 | #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 |
|---|
| 32 | #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L |
|---|
| 33 | #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 |
|---|
| 34 | #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L |
|---|
| 35 | #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 |
|---|
| 36 | #define BACO_CNTL__BACO_MODE_MASK 0x00000040L |
|---|
| 37 | #define BACO_CNTL__BACO_MODE__SHIFT 0x00000006 |
|---|
| 38 | #define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
|---|
| 39 | #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003 |
|---|
| 40 | #define BACO_CNTL__BACO_RESET_EN_MASK 0x00000010L |
|---|
| 41 | #define BACO_CNTL__BACO_RESET_EN__SHIFT 0x00000004 |
|---|
| 42 | #define BACO_CNTL__PWRGOOD_BF_MASK 0x00000200L |
|---|
| 43 | #define BACO_CNTL__PWRGOOD_BF__SHIFT 0x00000009 |
|---|
| 44 | #define BACO_CNTL__PWRGOOD_DVO_MASK 0x00001000L |
|---|
| 45 | #define BACO_CNTL__PWRGOOD_DVO__SHIFT 0x0000000c |
|---|
| 46 | #define BACO_CNTL__PWRGOOD_GPIO_MASK 0x00000400L |
|---|
| 47 | #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0x0000000a |
|---|
| 48 | #define BACO_CNTL__PWRGOOD_MEM_MASK 0x00000800L |
|---|
| 49 | #define BACO_CNTL__PWRGOOD_MEM__SHIFT 0x0000000b |
|---|
| 50 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000100L |
|---|
| 51 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000008 |
|---|
| 52 | #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x00000001L |
|---|
| 53 | #define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x00000000 |
|---|
| 54 | #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x00000002L |
|---|
| 55 | #define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x00000001 |
|---|
| 56 | #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x00000001L |
|---|
| 57 | #define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x00000000 |
|---|
| 58 | #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x00000001L |
|---|
| 59 | #define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x00000000 |
|---|
| 60 | #define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x00000001L |
|---|
| 61 | #define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x00000000 |
|---|
| 62 | #define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL |
|---|
| 63 | #define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000 |
|---|
| 64 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L |
|---|
| 65 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008 |
|---|
| 66 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL |
|---|
| 67 | #define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000 |
|---|
| 68 | #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L |
|---|
| 69 | #define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011 |
|---|
| 70 | #define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L |
|---|
| 71 | #define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010 |
|---|
| 72 | #define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL |
|---|
| 73 | #define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000 |
|---|
| 74 | #define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L |
|---|
| 75 | #define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008 |
|---|
| 76 | #define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L |
|---|
| 77 | #define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010 |
|---|
| 78 | #define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L |
|---|
| 79 | #define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018 |
|---|
| 80 | #define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL |
|---|
| 81 | #define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000 |
|---|
| 82 | #define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L |
|---|
| 83 | #define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008 |
|---|
| 84 | #define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L |
|---|
| 85 | #define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010 |
|---|
| 86 | #define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L |
|---|
| 87 | #define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018 |
|---|
| 88 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL |
|---|
| 89 | #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000 |
|---|
| 90 | #define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x000003ffL |
|---|
| 91 | #define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x00000000 |
|---|
| 92 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L |
|---|
| 93 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004 |
|---|
| 94 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L |
|---|
| 95 | #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005 |
|---|
| 96 | #define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L |
|---|
| 97 | #define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000 |
|---|
| 98 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L |
|---|
| 99 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008 |
|---|
| 100 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L |
|---|
| 101 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010 |
|---|
| 102 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L |
|---|
| 103 | #define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018 |
|---|
| 104 | #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L |
|---|
| 105 | #define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001 |
|---|
| 106 | #define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L |
|---|
| 107 | #define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002 |
|---|
| 108 | #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L |
|---|
| 109 | #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003 |
|---|
| 110 | #define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L |
|---|
| 111 | #define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007 |
|---|
| 112 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L |
|---|
| 113 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x0000001e |
|---|
| 114 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x00000040L |
|---|
| 115 | #define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x00000006 |
|---|
| 116 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x0000003fL |
|---|
| 117 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x00000000 |
|---|
| 118 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x00003f00L |
|---|
| 119 | #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x00000008 |
|---|
| 120 | #define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x0001ffffL |
|---|
| 121 | #define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x00000000 |
|---|
| 122 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000ffL |
|---|
| 123 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x00000000 |
|---|
| 124 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000ff00L |
|---|
| 125 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x00000008 |
|---|
| 126 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00ff0000L |
|---|
| 127 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x00000010 |
|---|
| 128 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000L |
|---|
| 129 | #define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x00000018 |
|---|
| 130 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000ffL |
|---|
| 131 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x00000000 |
|---|
| 132 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000ff00L |
|---|
| 133 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x00000008 |
|---|
| 134 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00ff0000L |
|---|
| 135 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x00000010 |
|---|
| 136 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000L |
|---|
| 137 | #define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x00000018 |
|---|
| 138 | #define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
|---|
| 139 | #define BIF_FB_EN__FB_READ_EN__SHIFT 0x00000000 |
|---|
| 140 | #define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
|---|
| 141 | #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x00000001 |
|---|
| 142 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
|---|
| 143 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x00000003 |
|---|
| 144 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
|---|
| 145 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x00000002 |
|---|
| 146 | #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x00000100L |
|---|
| 147 | #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x00000008 |
|---|
| 148 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
|---|
| 149 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x00000000 |
|---|
| 150 | #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x00000080L |
|---|
| 151 | #define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x00000007 |
|---|
| 152 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L |
|---|
| 153 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x00000005 |
|---|
| 154 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L |
|---|
| 155 | #define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x00000006 |
|---|
| 156 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
|---|
| 157 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x00000001 |
|---|
| 158 | #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L |
|---|
| 159 | #define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x00000004 |
|---|
| 160 | #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL |
|---|
| 161 | #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 |
|---|
| 162 | #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffffL |
|---|
| 163 | #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x00000000 |
|---|
| 164 | #define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x00000001L |
|---|
| 165 | #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x00000000 |
|---|
| 166 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x00000002L |
|---|
| 167 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x00000001 |
|---|
| 168 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x00000004L |
|---|
| 169 | #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x00000002 |
|---|
| 170 | #define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x00001f00L |
|---|
| 171 | #define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000008 |
|---|
| 172 | #define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x0003e000L |
|---|
| 173 | #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000d |
|---|
| 174 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x00000007L |
|---|
| 175 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x00000000 |
|---|
| 176 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x00000038L |
|---|
| 177 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x00000003 |
|---|
| 178 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x000003c0L |
|---|
| 179 | #define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x00000006 |
|---|
| 180 | #define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x00400000L |
|---|
| 181 | #define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x00000016 |
|---|
| 182 | #define BIF_RESET_EN__CFG_RESET_EN_MASK 0x00000040L |
|---|
| 183 | #define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x00000006 |
|---|
| 184 | #define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x0003f000L |
|---|
| 185 | #define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0x0000000c |
|---|
| 186 | #define BIF_RESET_EN__COR_RESET_EN_MASK 0x00000008L |
|---|
| 187 | #define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x00000003 |
|---|
| 188 | #define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0x000c0000L |
|---|
| 189 | #define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x00000012 |
|---|
| 190 | #define BIF_RESET_EN__DRV_RESET_EN_MASK 0x00000080L |
|---|
| 191 | #define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x00000007 |
|---|
| 192 | #define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x00800000L |
|---|
| 193 | #define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x00000017 |
|---|
| 194 | #define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0x0c000000L |
|---|
| 195 | #define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x0000001a |
|---|
| 196 | #define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x01000000L |
|---|
| 197 | #define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x00000018 |
|---|
| 198 | #define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000L |
|---|
| 199 | #define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x0000001c |
|---|
| 200 | #define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x02000000L |
|---|
| 201 | #define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x00000019 |
|---|
| 202 | #define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000L |
|---|
| 203 | #define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x0000001e |
|---|
| 204 | #define BIF_RESET_EN__HOT_RESET_EN_MASK 0x00000200L |
|---|
| 205 | #define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x00000009 |
|---|
| 206 | #define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x00000400L |
|---|
| 207 | #define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0x0000000a |
|---|
| 208 | #define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x00000800L |
|---|
| 209 | #define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0x0000000b |
|---|
| 210 | #define BIF_RESET_EN__PHY_RESET_EN_MASK 0x00000004L |
|---|
| 211 | #define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x00000002 |
|---|
| 212 | #define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x00100000L |
|---|
| 213 | #define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x00000014 |
|---|
| 214 | #define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x00200000L |
|---|
| 215 | #define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x00000015 |
|---|
| 216 | #define BIF_RESET_EN__REG_RESET_EN_MASK 0x00000010L |
|---|
| 217 | #define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x00000004 |
|---|
| 218 | #define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x00000100L |
|---|
| 219 | #define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x00000008 |
|---|
| 220 | #define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x00000002L |
|---|
| 221 | #define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x00000001 |
|---|
| 222 | #define BIF_RESET_EN__STY_RESET_EN_MASK 0x00000020L |
|---|
| 223 | #define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x00000005 |
|---|
| 224 | #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffffL |
|---|
| 225 | #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x00000000 |
|---|
| 226 | #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffffL |
|---|
| 227 | #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x00000000 |
|---|
| 228 | #define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x0003fffcL |
|---|
| 229 | #define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x00000002 |
|---|
| 230 | #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000L |
|---|
| 231 | #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 232 | #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000L |
|---|
| 233 | #define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 234 | #define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x0003fffcL |
|---|
| 235 | #define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x00000002 |
|---|
| 236 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x0003fffcL |
|---|
| 237 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x00000002 |
|---|
| 238 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000L |
|---|
| 239 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 240 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000L |
|---|
| 241 | #define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 242 | #define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x0003fffcL |
|---|
| 243 | #define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x00000002 |
|---|
| 244 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x0003fffcL |
|---|
| 245 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x00000002 |
|---|
| 246 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000L |
|---|
| 247 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 248 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000L |
|---|
| 249 | #define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 250 | #define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x0003fffcL |
|---|
| 251 | #define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x00000002 |
|---|
| 252 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x0003fffcL |
|---|
| 253 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x00000002 |
|---|
| 254 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000L |
|---|
| 255 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 256 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000L |
|---|
| 257 | #define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 258 | #define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x0003fffcL |
|---|
| 259 | #define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x00000002 |
|---|
| 260 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x0003fffcL |
|---|
| 261 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x00000002 |
|---|
| 262 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000L |
|---|
| 263 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 264 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000L |
|---|
| 265 | #define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 266 | #define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x0003fffcL |
|---|
| 267 | #define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x00000002 |
|---|
| 268 | #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000L |
|---|
| 269 | #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x0000001d |
|---|
| 270 | #define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x0003fffcL |
|---|
| 271 | #define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x00000002 |
|---|
| 272 | #define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000L |
|---|
| 273 | #define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x0000001e |
|---|
| 274 | #define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000L |
|---|
| 275 | #define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x0000001f |
|---|
| 276 | #define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x0003fffcL |
|---|
| 277 | #define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x00000002 |
|---|
| 278 | #define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x00000002L |
|---|
| 279 | #define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x00000001 |
|---|
| 280 | #define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x00000001L |
|---|
| 281 | #define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x00000000 |
|---|
| 282 | #define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x00000004L |
|---|
| 283 | #define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x00000002 |
|---|
| 284 | #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffffL |
|---|
| 285 | #define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x00000000 |
|---|
| 286 | #define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L |
|---|
| 287 | #define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x0000001f |
|---|
| 288 | #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffffL |
|---|
| 289 | #define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x00000000 |
|---|
| 290 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffffL |
|---|
| 291 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x00000000 |
|---|
| 292 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffffL |
|---|
| 293 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x00000000 |
|---|
| 294 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffffL |
|---|
| 295 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x00000000 |
|---|
| 296 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffffL |
|---|
| 297 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x00000000 |
|---|
| 298 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffffL |
|---|
| 299 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x00000000 |
|---|
| 300 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffffL |
|---|
| 301 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x00000000 |
|---|
| 302 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffffL |
|---|
| 303 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x00000000 |
|---|
| 304 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffffL |
|---|
| 305 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x00000000 |
|---|
| 306 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffffL |
|---|
| 307 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x00000000 |
|---|
| 308 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffffL |
|---|
| 309 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x00000000 |
|---|
| 310 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffffL |
|---|
| 311 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x00000000 |
|---|
| 312 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffffL |
|---|
| 313 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x00000000 |
|---|
| 314 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffffL |
|---|
| 315 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x00000000 |
|---|
| 316 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffffL |
|---|
| 317 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x00000000 |
|---|
| 318 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffffL |
|---|
| 319 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x00000000 |
|---|
| 320 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffffL |
|---|
| 321 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x00000000 |
|---|
| 322 | #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x00000100L |
|---|
| 323 | #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x00000008 |
|---|
| 324 | #define BUS_CNTL__BIOS_ROM_DIS_MASK 0x00000002L |
|---|
| 325 | #define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x00000001 |
|---|
| 326 | #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x00000001L |
|---|
| 327 | #define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x00000000 |
|---|
| 328 | #define BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L |
|---|
| 329 | #define BUS_CNTL__PMI_BM_DIS__SHIFT 0x00000004 |
|---|
| 330 | #define BUS_CNTL__PMI_INT_DIS_MASK 0x00000020L |
|---|
| 331 | #define BUS_CNTL__PMI_INT_DIS__SHIFT 0x00000005 |
|---|
| 332 | #define BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L |
|---|
| 333 | #define BUS_CNTL__PMI_IO_DIS__SHIFT 0x00000002 |
|---|
| 334 | #define BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L |
|---|
| 335 | #define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x00000003 |
|---|
| 336 | #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
|---|
| 337 | #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x00000012 |
|---|
| 338 | #define BUS_CNTL__SET_AZ_TC_MASK 0x00001c00L |
|---|
| 339 | #define BUS_CNTL__SET_AZ_TC__SHIFT 0x0000000a |
|---|
| 340 | #define BUS_CNTL__SET_MC_TC_MASK 0x0000e000L |
|---|
| 341 | #define BUS_CNTL__SET_MC_TC__SHIFT 0x0000000d |
|---|
| 342 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
|---|
| 343 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x00000007 |
|---|
| 344 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
|---|
| 345 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x00000006 |
|---|
| 346 | #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
|---|
| 347 | #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x00000011 |
|---|
| 348 | #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
|---|
| 349 | #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x00000010 |
|---|
| 350 | #define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L |
|---|
| 351 | #define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x00000000 |
|---|
| 352 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
|---|
| 353 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x00000000 |
|---|
| 354 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
|---|
| 355 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0x0000000c |
|---|
| 356 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
|---|
| 357 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x00000002 |
|---|
| 358 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
|---|
| 359 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0x0000000b |
|---|
| 360 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
|---|
| 361 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x00000001 |
|---|
| 362 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
|---|
| 363 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x00000009 |
|---|
| 364 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
|---|
| 365 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x00000005 |
|---|
| 366 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
|---|
| 367 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x00000006 |
|---|
| 368 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
|---|
| 369 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x00000007 |
|---|
| 370 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
|---|
| 371 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x00000008 |
|---|
| 372 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
|---|
| 373 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x00000003 |
|---|
| 374 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
|---|
| 375 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0x0000000a |
|---|
| 376 | #define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffffL |
|---|
| 377 | #define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x00000000 |
|---|
| 378 | #define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L |
|---|
| 379 | #define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x00000000 |
|---|
| 380 | #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L |
|---|
| 381 | #define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x00000002 |
|---|
| 382 | #define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L |
|---|
| 383 | #define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x00000003 |
|---|
| 384 | #define CONFIG_CNTL__VGA_DIS_MASK 0x00000002L |
|---|
| 385 | #define CONFIG_CNTL__VGA_DIS__SHIFT 0x00000001 |
|---|
| 386 | #define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffffL |
|---|
| 387 | #define CONFIG_F0_BASE__F0_BASE__SHIFT 0x00000000 |
|---|
| 388 | #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffffL |
|---|
| 389 | #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x00000000 |
|---|
| 390 | #define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000fffffL |
|---|
| 391 | #define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x00000000 |
|---|
| 392 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 393 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x00000000 |
|---|
| 394 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 395 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x00000000 |
|---|
| 396 | #define HOST_BUSNUM__HOST_ID_MASK 0x0000ffffL |
|---|
| 397 | #define HOST_BUSNUM__HOST_ID__SHIFT 0x00000000 |
|---|
| 398 | #define HW_DEBUG__HW_00_DEBUG_MASK 0x00000001L |
|---|
| 399 | #define HW_DEBUG__HW_00_DEBUG__SHIFT 0x00000000 |
|---|
| 400 | #define HW_DEBUG__HW_01_DEBUG_MASK 0x00000002L |
|---|
| 401 | #define HW_DEBUG__HW_01_DEBUG__SHIFT 0x00000001 |
|---|
| 402 | #define HW_DEBUG__HW_02_DEBUG_MASK 0x00000004L |
|---|
| 403 | #define HW_DEBUG__HW_02_DEBUG__SHIFT 0x00000002 |
|---|
| 404 | #define HW_DEBUG__HW_03_DEBUG_MASK 0x00000008L |
|---|
| 405 | #define HW_DEBUG__HW_03_DEBUG__SHIFT 0x00000003 |
|---|
| 406 | #define HW_DEBUG__HW_04_DEBUG_MASK 0x00000010L |
|---|
| 407 | #define HW_DEBUG__HW_04_DEBUG__SHIFT 0x00000004 |
|---|
| 408 | #define HW_DEBUG__HW_05_DEBUG_MASK 0x00000020L |
|---|
| 409 | #define HW_DEBUG__HW_05_DEBUG__SHIFT 0x00000005 |
|---|
| 410 | #define HW_DEBUG__HW_06_DEBUG_MASK 0x00000040L |
|---|
| 411 | #define HW_DEBUG__HW_06_DEBUG__SHIFT 0x00000006 |
|---|
| 412 | #define HW_DEBUG__HW_07_DEBUG_MASK 0x00000080L |
|---|
| 413 | #define HW_DEBUG__HW_07_DEBUG__SHIFT 0x00000007 |
|---|
| 414 | #define HW_DEBUG__HW_08_DEBUG_MASK 0x00000100L |
|---|
| 415 | #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x00000008 |
|---|
| 416 | #define HW_DEBUG__HW_09_DEBUG_MASK 0x00000200L |
|---|
| 417 | #define HW_DEBUG__HW_09_DEBUG__SHIFT 0x00000009 |
|---|
| 418 | #define HW_DEBUG__HW_10_DEBUG_MASK 0x00000400L |
|---|
| 419 | #define HW_DEBUG__HW_10_DEBUG__SHIFT 0x0000000a |
|---|
| 420 | #define HW_DEBUG__HW_11_DEBUG_MASK 0x00000800L |
|---|
| 421 | #define HW_DEBUG__HW_11_DEBUG__SHIFT 0x0000000b |
|---|
| 422 | #define HW_DEBUG__HW_12_DEBUG_MASK 0x00001000L |
|---|
| 423 | #define HW_DEBUG__HW_12_DEBUG__SHIFT 0x0000000c |
|---|
| 424 | #define HW_DEBUG__HW_13_DEBUG_MASK 0x00002000L |
|---|
| 425 | #define HW_DEBUG__HW_13_DEBUG__SHIFT 0x0000000d |
|---|
| 426 | #define HW_DEBUG__HW_14_DEBUG_MASK 0x00004000L |
|---|
| 427 | #define HW_DEBUG__HW_14_DEBUG__SHIFT 0x0000000e |
|---|
| 428 | #define HW_DEBUG__HW_15_DEBUG_MASK 0x00008000L |
|---|
| 429 | #define HW_DEBUG__HW_15_DEBUG__SHIFT 0x0000000f |
|---|
| 430 | #define HW_DEBUG__HW_16_DEBUG_MASK 0x00010000L |
|---|
| 431 | #define HW_DEBUG__HW_16_DEBUG__SHIFT 0x00000010 |
|---|
| 432 | #define HW_DEBUG__HW_17_DEBUG_MASK 0x00020000L |
|---|
| 433 | #define HW_DEBUG__HW_17_DEBUG__SHIFT 0x00000011 |
|---|
| 434 | #define HW_DEBUG__HW_18_DEBUG_MASK 0x00040000L |
|---|
| 435 | #define HW_DEBUG__HW_18_DEBUG__SHIFT 0x00000012 |
|---|
| 436 | #define HW_DEBUG__HW_19_DEBUG_MASK 0x00080000L |
|---|
| 437 | #define HW_DEBUG__HW_19_DEBUG__SHIFT 0x00000013 |
|---|
| 438 | #define HW_DEBUG__HW_20_DEBUG_MASK 0x00100000L |
|---|
| 439 | #define HW_DEBUG__HW_20_DEBUG__SHIFT 0x00000014 |
|---|
| 440 | #define HW_DEBUG__HW_21_DEBUG_MASK 0x00200000L |
|---|
| 441 | #define HW_DEBUG__HW_21_DEBUG__SHIFT 0x00000015 |
|---|
| 442 | #define HW_DEBUG__HW_22_DEBUG_MASK 0x00400000L |
|---|
| 443 | #define HW_DEBUG__HW_22_DEBUG__SHIFT 0x00000016 |
|---|
| 444 | #define HW_DEBUG__HW_23_DEBUG_MASK 0x00800000L |
|---|
| 445 | #define HW_DEBUG__HW_23_DEBUG__SHIFT 0x00000017 |
|---|
| 446 | #define HW_DEBUG__HW_24_DEBUG_MASK 0x01000000L |
|---|
| 447 | #define HW_DEBUG__HW_24_DEBUG__SHIFT 0x00000018 |
|---|
| 448 | #define HW_DEBUG__HW_25_DEBUG_MASK 0x02000000L |
|---|
| 449 | #define HW_DEBUG__HW_25_DEBUG__SHIFT 0x00000019 |
|---|
| 450 | #define HW_DEBUG__HW_26_DEBUG_MASK 0x04000000L |
|---|
| 451 | #define HW_DEBUG__HW_26_DEBUG__SHIFT 0x0000001a |
|---|
| 452 | #define HW_DEBUG__HW_27_DEBUG_MASK 0x08000000L |
|---|
| 453 | #define HW_DEBUG__HW_27_DEBUG__SHIFT 0x0000001b |
|---|
| 454 | #define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000L |
|---|
| 455 | #define HW_DEBUG__HW_28_DEBUG__SHIFT 0x0000001c |
|---|
| 456 | #define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000L |
|---|
| 457 | #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x0000001d |
|---|
| 458 | #define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000L |
|---|
| 459 | #define HW_DEBUG__HW_30_DEBUG__SHIFT 0x0000001e |
|---|
| 460 | #define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000L |
|---|
| 461 | #define HW_DEBUG__HW_31_DEBUG__SHIFT 0x0000001f |
|---|
| 462 | #define IMPCTL_RESET__IMP_SW_RESET_MASK 0x00000001L |
|---|
| 463 | #define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x00000000 |
|---|
| 464 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffffL |
|---|
| 465 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x00000000 |
|---|
| 466 | #define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x00001e00L |
|---|
| 467 | #define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x00000009 |
|---|
| 468 | #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
|---|
| 469 | #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x00000008 |
|---|
| 470 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
|---|
| 471 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x00000001 |
|---|
| 472 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
|---|
| 473 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x00000000 |
|---|
| 474 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000f0L |
|---|
| 475 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x00000004 |
|---|
| 476 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
|---|
| 477 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x00000003 |
|---|
| 478 | #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x00006000L |
|---|
| 479 | #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0x0000000d |
|---|
| 480 | #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x003f0000L |
|---|
| 481 | #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x00000010 |
|---|
| 482 | #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x0000003fL |
|---|
| 483 | #define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x00000000 |
|---|
| 484 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
|---|
| 485 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x00000000 |
|---|
| 486 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x00000008L |
|---|
| 487 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x00000003 |
|---|
| 488 | #define MM_DATA__MM_DATA_MASK 0xffffffffL |
|---|
| 489 | #define MM_DATA__MM_DATA__SHIFT 0x00000000 |
|---|
| 490 | #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffffL |
|---|
| 491 | #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x00000000 |
|---|
| 492 | #define MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 493 | #define MM_INDEX__MM_APER__SHIFT 0x0000001f |
|---|
| 494 | #define MM_INDEX__MM_OFFSET_MASK 0x7fffffffL |
|---|
| 495 | #define MM_INDEX__MM_OFFSET__SHIFT 0x00000000 |
|---|
| 496 | #define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x000003ffL |
|---|
| 497 | #define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x00000000 |
|---|
| 498 | #define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x00000400L |
|---|
| 499 | #define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0x0000000a |
|---|
| 500 | #define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x00200000L |
|---|
| 501 | #define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x00000015 |
|---|
| 502 | #define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x00000001L |
|---|
| 503 | #define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x00000000 |
|---|
| 504 | #define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x001ffffeL |
|---|
| 505 | #define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x00000001 |
|---|
| 506 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L |
|---|
| 507 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 |
|---|
| 508 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL |
|---|
| 509 | #define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 |
|---|
| 510 | #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L |
|---|
| 511 | #define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 |
|---|
| 512 | #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L |
|---|
| 513 | #define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 |
|---|
| 514 | #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L |
|---|
| 515 | #define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 |
|---|
| 516 | #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL |
|---|
| 517 | #define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 |
|---|
| 518 | #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L |
|---|
| 519 | #define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 |
|---|
| 520 | #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L |
|---|
| 521 | #define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 |
|---|
| 522 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L |
|---|
| 523 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 |
|---|
| 524 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL |
|---|
| 525 | #define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 |
|---|
| 526 | #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL |
|---|
| 527 | #define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 |
|---|
| 528 | #define PB0_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL |
|---|
| 529 | #define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 |
|---|
| 530 | #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L |
|---|
| 531 | #define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 |
|---|
| 532 | #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L |
|---|
| 533 | #define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 |
|---|
| 534 | #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L |
|---|
| 535 | #define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 |
|---|
| 536 | #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L |
|---|
| 537 | #define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 |
|---|
| 538 | #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L |
|---|
| 539 | #define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 |
|---|
| 540 | #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L |
|---|
| 541 | #define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a |
|---|
| 542 | #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L |
|---|
| 543 | #define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e |
|---|
| 544 | #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L |
|---|
| 545 | #define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f |
|---|
| 546 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L |
|---|
| 547 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 |
|---|
| 548 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL |
|---|
| 549 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 |
|---|
| 550 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L |
|---|
| 551 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 |
|---|
| 552 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L |
|---|
| 553 | #define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 |
|---|
| 554 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L |
|---|
| 555 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e |
|---|
| 556 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L |
|---|
| 557 | #define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f |
|---|
| 558 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L |
|---|
| 559 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 |
|---|
| 560 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L |
|---|
| 561 | #define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 |
|---|
| 562 | #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L |
|---|
| 563 | #define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e |
|---|
| 564 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L |
|---|
| 565 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 |
|---|
| 566 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL |
|---|
| 567 | #define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 |
|---|
| 568 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L |
|---|
| 569 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 |
|---|
| 570 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L |
|---|
| 571 | #define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 |
|---|
| 572 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L |
|---|
| 573 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 |
|---|
| 574 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L |
|---|
| 575 | #define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 |
|---|
| 576 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L |
|---|
| 577 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 |
|---|
| 578 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L |
|---|
| 579 | #define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 |
|---|
| 580 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L |
|---|
| 581 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 |
|---|
| 582 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L |
|---|
| 583 | #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 |
|---|
| 584 | #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L |
|---|
| 585 | #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 |
|---|
| 586 | #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L |
|---|
| 587 | #define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e |
|---|
| 588 | #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L |
|---|
| 589 | #define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c |
|---|
| 590 | #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L |
|---|
| 591 | #define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b |
|---|
| 592 | #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L |
|---|
| 593 | #define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 |
|---|
| 594 | #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L |
|---|
| 595 | #define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f |
|---|
| 596 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L |
|---|
| 597 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 |
|---|
| 598 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L |
|---|
| 599 | #define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 |
|---|
| 600 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L |
|---|
| 601 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b |
|---|
| 602 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L |
|---|
| 603 | #define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c |
|---|
| 604 | #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L |
|---|
| 605 | #define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 |
|---|
| 606 | #define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL |
|---|
| 607 | #define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 |
|---|
| 608 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L |
|---|
| 609 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 |
|---|
| 610 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL |
|---|
| 611 | #define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 |
|---|
| 612 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L |
|---|
| 613 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 |
|---|
| 614 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L |
|---|
| 615 | #define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 |
|---|
| 616 | #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L |
|---|
| 617 | #define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a |
|---|
| 618 | #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L |
|---|
| 619 | #define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c |
|---|
| 620 | #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L |
|---|
| 621 | #define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b |
|---|
| 622 | #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL |
|---|
| 623 | #define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 |
|---|
| 624 | #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL |
|---|
| 625 | #define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 626 | #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L |
|---|
| 627 | #define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 |
|---|
| 628 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L |
|---|
| 629 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f |
|---|
| 630 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L |
|---|
| 631 | #define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 |
|---|
| 632 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L |
|---|
| 633 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 |
|---|
| 634 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L |
|---|
| 635 | #define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 |
|---|
| 636 | #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L |
|---|
| 637 | #define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 |
|---|
| 638 | #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L |
|---|
| 639 | #define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 |
|---|
| 640 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L |
|---|
| 641 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 |
|---|
| 642 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L |
|---|
| 643 | #define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 |
|---|
| 644 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 645 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 646 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L |
|---|
| 647 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 |
|---|
| 648 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 649 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 650 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 651 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 652 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L |
|---|
| 653 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 |
|---|
| 654 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L |
|---|
| 655 | #define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 |
|---|
| 656 | #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L |
|---|
| 657 | #define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 |
|---|
| 658 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L |
|---|
| 659 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 |
|---|
| 660 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L |
|---|
| 661 | #define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c |
|---|
| 662 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L |
|---|
| 663 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c |
|---|
| 664 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L |
|---|
| 665 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d |
|---|
| 666 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L |
|---|
| 667 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e |
|---|
| 668 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L |
|---|
| 669 | #define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f |
|---|
| 670 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L |
|---|
| 671 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 |
|---|
| 672 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L |
|---|
| 673 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 |
|---|
| 674 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L |
|---|
| 675 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a |
|---|
| 676 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L |
|---|
| 677 | #define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e |
|---|
| 678 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L |
|---|
| 679 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 |
|---|
| 680 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L |
|---|
| 681 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 |
|---|
| 682 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 683 | #define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 684 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L |
|---|
| 685 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 |
|---|
| 686 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L |
|---|
| 687 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 |
|---|
| 688 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L |
|---|
| 689 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 |
|---|
| 690 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L |
|---|
| 691 | #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c |
|---|
| 692 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L |
|---|
| 693 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c |
|---|
| 694 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L |
|---|
| 695 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d |
|---|
| 696 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L |
|---|
| 697 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e |
|---|
| 698 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L |
|---|
| 699 | #define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f |
|---|
| 700 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L |
|---|
| 701 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 |
|---|
| 702 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L |
|---|
| 703 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 |
|---|
| 704 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L |
|---|
| 705 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a |
|---|
| 706 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L |
|---|
| 707 | #define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e |
|---|
| 708 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L |
|---|
| 709 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 |
|---|
| 710 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 711 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 712 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L |
|---|
| 713 | #define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 |
|---|
| 714 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L |
|---|
| 715 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 |
|---|
| 716 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L |
|---|
| 717 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 |
|---|
| 718 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L |
|---|
| 719 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 |
|---|
| 720 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L |
|---|
| 721 | #define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c |
|---|
| 722 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L |
|---|
| 723 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e |
|---|
| 724 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L |
|---|
| 725 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f |
|---|
| 726 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L |
|---|
| 727 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c |
|---|
| 728 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L |
|---|
| 729 | #define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d |
|---|
| 730 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L |
|---|
| 731 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a |
|---|
| 732 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L |
|---|
| 733 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e |
|---|
| 734 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L |
|---|
| 735 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 |
|---|
| 736 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L |
|---|
| 737 | #define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 |
|---|
| 738 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 739 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 740 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L |
|---|
| 741 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 |
|---|
| 742 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L |
|---|
| 743 | #define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 |
|---|
| 744 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L |
|---|
| 745 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 |
|---|
| 746 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L |
|---|
| 747 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c |
|---|
| 748 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L |
|---|
| 749 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 |
|---|
| 750 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L |
|---|
| 751 | #define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 |
|---|
| 752 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L |
|---|
| 753 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c |
|---|
| 754 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L |
|---|
| 755 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d |
|---|
| 756 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L |
|---|
| 757 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e |
|---|
| 758 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L |
|---|
| 759 | #define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f |
|---|
| 760 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L |
|---|
| 761 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 |
|---|
| 762 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L |
|---|
| 763 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 |
|---|
| 764 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L |
|---|
| 765 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a |
|---|
| 766 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L |
|---|
| 767 | #define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e |
|---|
| 768 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L |
|---|
| 769 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 |
|---|
| 770 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L |
|---|
| 771 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 |
|---|
| 772 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L |
|---|
| 773 | #define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 |
|---|
| 774 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L |
|---|
| 775 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 |
|---|
| 776 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L |
|---|
| 777 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 |
|---|
| 778 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L |
|---|
| 779 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 |
|---|
| 780 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L |
|---|
| 781 | #define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c |
|---|
| 782 | #define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x00000001L |
|---|
| 783 | #define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x00000000 |
|---|
| 784 | #define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x00000002L |
|---|
| 785 | #define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x00000001 |
|---|
| 786 | #define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x00000004L |
|---|
| 787 | #define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x00000002 |
|---|
| 788 | #define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x00000008L |
|---|
| 789 | #define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x00000003 |
|---|
| 790 | #define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x00000010L |
|---|
| 791 | #define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x00000004 |
|---|
| 792 | #define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x00000020L |
|---|
| 793 | #define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x00000005 |
|---|
| 794 | #define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x00000040L |
|---|
| 795 | #define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x00000006 |
|---|
| 796 | #define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x00000080L |
|---|
| 797 | #define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x00000007 |
|---|
| 798 | #define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x00000100L |
|---|
| 799 | #define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x00000008 |
|---|
| 800 | #define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x00000200L |
|---|
| 801 | #define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x00000009 |
|---|
| 802 | #define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x00000400L |
|---|
| 803 | #define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0x0000000a |
|---|
| 804 | #define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x00000800L |
|---|
| 805 | #define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0x0000000b |
|---|
| 806 | #define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x00001000L |
|---|
| 807 | #define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0x0000000c |
|---|
| 808 | #define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x00002000L |
|---|
| 809 | #define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0x0000000d |
|---|
| 810 | #define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x00004000L |
|---|
| 811 | #define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0x0000000e |
|---|
| 812 | #define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x00008000L |
|---|
| 813 | #define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0x0000000f |
|---|
| 814 | #define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x00010000L |
|---|
| 815 | #define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x00000010 |
|---|
| 816 | #define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x00020000L |
|---|
| 817 | #define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x00000011 |
|---|
| 818 | #define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x00040000L |
|---|
| 819 | #define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x00000012 |
|---|
| 820 | #define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x00080000L |
|---|
| 821 | #define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x00000013 |
|---|
| 822 | #define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x00100000L |
|---|
| 823 | #define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x00000014 |
|---|
| 824 | #define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x00200000L |
|---|
| 825 | #define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x00000015 |
|---|
| 826 | #define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x00400000L |
|---|
| 827 | #define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x00000016 |
|---|
| 828 | #define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x00800000L |
|---|
| 829 | #define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x00000017 |
|---|
| 830 | #define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x01000000L |
|---|
| 831 | #define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x00000018 |
|---|
| 832 | #define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x02000000L |
|---|
| 833 | #define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x00000019 |
|---|
| 834 | #define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x04000000L |
|---|
| 835 | #define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x0000001a |
|---|
| 836 | #define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x08000000L |
|---|
| 837 | #define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x0000001b |
|---|
| 838 | #define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000L |
|---|
| 839 | #define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x0000001c |
|---|
| 840 | #define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000L |
|---|
| 841 | #define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x0000001d |
|---|
| 842 | #define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000L |
|---|
| 843 | #define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x0000001e |
|---|
| 844 | #define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000L |
|---|
| 845 | #define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x0000001f |
|---|
| 846 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L |
|---|
| 847 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 |
|---|
| 848 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L |
|---|
| 849 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 |
|---|
| 850 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L |
|---|
| 851 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 |
|---|
| 852 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L |
|---|
| 853 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 |
|---|
| 854 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L |
|---|
| 855 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 |
|---|
| 856 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L |
|---|
| 857 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 |
|---|
| 858 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L |
|---|
| 859 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 |
|---|
| 860 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L |
|---|
| 861 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 |
|---|
| 862 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L |
|---|
| 863 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 |
|---|
| 864 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L |
|---|
| 865 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a |
|---|
| 866 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L |
|---|
| 867 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b |
|---|
| 868 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L |
|---|
| 869 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c |
|---|
| 870 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L |
|---|
| 871 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d |
|---|
| 872 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L |
|---|
| 873 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e |
|---|
| 874 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L |
|---|
| 875 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f |
|---|
| 876 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L |
|---|
| 877 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 |
|---|
| 878 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L |
|---|
| 879 | #define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 |
|---|
| 880 | #define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L |
|---|
| 881 | #define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 |
|---|
| 882 | #define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L |
|---|
| 883 | #define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 |
|---|
| 884 | #define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L |
|---|
| 885 | #define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 |
|---|
| 886 | #define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L |
|---|
| 887 | #define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 |
|---|
| 888 | #define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L |
|---|
| 889 | #define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 |
|---|
| 890 | #define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L |
|---|
| 891 | #define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d |
|---|
| 892 | #define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L |
|---|
| 893 | #define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 |
|---|
| 894 | #define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L |
|---|
| 895 | #define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 |
|---|
| 896 | #define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L |
|---|
| 897 | #define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 |
|---|
| 898 | #define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L |
|---|
| 899 | #define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 |
|---|
| 900 | #define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L |
|---|
| 901 | #define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c |
|---|
| 902 | #define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L |
|---|
| 903 | #define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d |
|---|
| 904 | #define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L |
|---|
| 905 | #define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 |
|---|
| 906 | #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L |
|---|
| 907 | #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 |
|---|
| 908 | #define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L |
|---|
| 909 | #define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 |
|---|
| 910 | #define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L |
|---|
| 911 | #define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a |
|---|
| 912 | #define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L |
|---|
| 913 | #define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 |
|---|
| 914 | #define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L |
|---|
| 915 | #define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 |
|---|
| 916 | #define PB0_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L |
|---|
| 917 | #define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 |
|---|
| 918 | #define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L |
|---|
| 919 | #define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b |
|---|
| 920 | #define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L |
|---|
| 921 | #define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 |
|---|
| 922 | #define PB0_PIF_CNTL__TXGND_TIME_MASK 0x00010000L |
|---|
| 923 | #define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 |
|---|
| 924 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x00000001L |
|---|
| 925 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x00000000 |
|---|
| 926 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x00000002L |
|---|
| 927 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x00000001 |
|---|
| 928 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x00000004L |
|---|
| 929 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x00000002 |
|---|
| 930 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x00000008L |
|---|
| 931 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x00000003 |
|---|
| 932 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x00000010L |
|---|
| 933 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x00000004 |
|---|
| 934 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x00000020L |
|---|
| 935 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x00000005 |
|---|
| 936 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x00000040L |
|---|
| 937 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x00000006 |
|---|
| 938 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x00000080L |
|---|
| 939 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x00000007 |
|---|
| 940 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x00000100L |
|---|
| 941 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x00000008 |
|---|
| 942 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x00000200L |
|---|
| 943 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x00000009 |
|---|
| 944 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x00000400L |
|---|
| 945 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0x0000000a |
|---|
| 946 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x00000800L |
|---|
| 947 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0x0000000b |
|---|
| 948 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x00001000L |
|---|
| 949 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0x0000000c |
|---|
| 950 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x00002000L |
|---|
| 951 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0x0000000d |
|---|
| 952 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x00004000L |
|---|
| 953 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0x0000000e |
|---|
| 954 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x00008000L |
|---|
| 955 | #define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0x0000000f |
|---|
| 956 | #define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L |
|---|
| 957 | #define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 |
|---|
| 958 | #define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L |
|---|
| 959 | #define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 |
|---|
| 960 | #define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L |
|---|
| 961 | #define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 |
|---|
| 962 | #define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L |
|---|
| 963 | #define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 |
|---|
| 964 | #define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L |
|---|
| 965 | #define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 |
|---|
| 966 | #define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L |
|---|
| 967 | #define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 |
|---|
| 968 | #define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L |
|---|
| 969 | #define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 |
|---|
| 970 | #define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L |
|---|
| 971 | #define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 |
|---|
| 972 | #define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L |
|---|
| 973 | #define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 |
|---|
| 974 | #define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L |
|---|
| 975 | #define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 |
|---|
| 976 | #define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L |
|---|
| 977 | #define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a |
|---|
| 978 | #define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L |
|---|
| 979 | #define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b |
|---|
| 980 | #define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L |
|---|
| 981 | #define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 |
|---|
| 982 | #define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L |
|---|
| 983 | #define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 |
|---|
| 984 | #define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L |
|---|
| 985 | #define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 |
|---|
| 986 | #define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x00010000L |
|---|
| 987 | #define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x00000010 |
|---|
| 988 | #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x00000100L |
|---|
| 989 | #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x00000008 |
|---|
| 990 | #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x00000200L |
|---|
| 991 | #define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x00000009 |
|---|
| 992 | #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x00000010L |
|---|
| 993 | #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000004 |
|---|
| 994 | #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0x000000e0L |
|---|
| 995 | #define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000005 |
|---|
| 996 | #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x00004000L |
|---|
| 997 | #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0x0000000e |
|---|
| 998 | #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x00038000L |
|---|
| 999 | #define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000f |
|---|
| 1000 | #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x00000001L |
|---|
| 1001 | #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x00000000 |
|---|
| 1002 | #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0x0000000eL |
|---|
| 1003 | #define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x00000001 |
|---|
| 1004 | #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x00000400L |
|---|
| 1005 | #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0x0000000a |
|---|
| 1006 | #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x00003800L |
|---|
| 1007 | #define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0x0000000b |
|---|
| 1008 | #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x00000100L |
|---|
| 1009 | #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x00000008 |
|---|
| 1010 | #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x00000200L |
|---|
| 1011 | #define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x00000009 |
|---|
| 1012 | #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x00000010L |
|---|
| 1013 | #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000004 |
|---|
| 1014 | #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0x000000e0L |
|---|
| 1015 | #define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000005 |
|---|
| 1016 | #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x00004000L |
|---|
| 1017 | #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0x0000000e |
|---|
| 1018 | #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x00038000L |
|---|
| 1019 | #define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000f |
|---|
| 1020 | #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x00000001L |
|---|
| 1021 | #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x00000000 |
|---|
| 1022 | #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0x0000000eL |
|---|
| 1023 | #define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x00000001 |
|---|
| 1024 | #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x00000400L |
|---|
| 1025 | #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0x0000000a |
|---|
| 1026 | #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x00003800L |
|---|
| 1027 | #define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0x0000000b |
|---|
| 1028 | #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x00000100L |
|---|
| 1029 | #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x00000008 |
|---|
| 1030 | #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x00000200L |
|---|
| 1031 | #define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x00000009 |
|---|
| 1032 | #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x00000010L |
|---|
| 1033 | #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000004 |
|---|
| 1034 | #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0x000000e0L |
|---|
| 1035 | #define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000005 |
|---|
| 1036 | #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x00004000L |
|---|
| 1037 | #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0x0000000e |
|---|
| 1038 | #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x00038000L |
|---|
| 1039 | #define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000f |
|---|
| 1040 | #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x00000001L |
|---|
| 1041 | #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x00000000 |
|---|
| 1042 | #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0x0000000eL |
|---|
| 1043 | #define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x00000001 |
|---|
| 1044 | #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x00000400L |
|---|
| 1045 | #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0x0000000a |
|---|
| 1046 | #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x00003800L |
|---|
| 1047 | #define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0x0000000b |
|---|
| 1048 | #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x00000100L |
|---|
| 1049 | #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x00000008 |
|---|
| 1050 | #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x00000200L |
|---|
| 1051 | #define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x00000009 |
|---|
| 1052 | #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x00000010L |
|---|
| 1053 | #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000004 |
|---|
| 1054 | #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0x000000e0L |
|---|
| 1055 | #define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000005 |
|---|
| 1056 | #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x00004000L |
|---|
| 1057 | #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0x0000000e |
|---|
| 1058 | #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x00038000L |
|---|
| 1059 | #define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000f |
|---|
| 1060 | #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x00000001L |
|---|
| 1061 | #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x00000000 |
|---|
| 1062 | #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0x0000000eL |
|---|
| 1063 | #define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x00000001 |
|---|
| 1064 | #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x00000400L |
|---|
| 1065 | #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0x0000000a |
|---|
| 1066 | #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x00003800L |
|---|
| 1067 | #define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0x0000000b |
|---|
| 1068 | #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x00000100L |
|---|
| 1069 | #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x00000008 |
|---|
| 1070 | #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x00000200L |
|---|
| 1071 | #define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x00000009 |
|---|
| 1072 | #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x00000010L |
|---|
| 1073 | #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000004 |
|---|
| 1074 | #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0x000000e0L |
|---|
| 1075 | #define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000005 |
|---|
| 1076 | #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x00004000L |
|---|
| 1077 | #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0x0000000e |
|---|
| 1078 | #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x00038000L |
|---|
| 1079 | #define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000f |
|---|
| 1080 | #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x00000001L |
|---|
| 1081 | #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x00000000 |
|---|
| 1082 | #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0x0000000eL |
|---|
| 1083 | #define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x00000001 |
|---|
| 1084 | #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x00000400L |
|---|
| 1085 | #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0x0000000a |
|---|
| 1086 | #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x00003800L |
|---|
| 1087 | #define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0x0000000b |
|---|
| 1088 | #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x00000100L |
|---|
| 1089 | #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x00000008 |
|---|
| 1090 | #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x00000200L |
|---|
| 1091 | #define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x00000009 |
|---|
| 1092 | #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x00000010L |
|---|
| 1093 | #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000004 |
|---|
| 1094 | #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0x000000e0L |
|---|
| 1095 | #define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000005 |
|---|
| 1096 | #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x00004000L |
|---|
| 1097 | #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0x0000000e |
|---|
| 1098 | #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x00038000L |
|---|
| 1099 | #define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000f |
|---|
| 1100 | #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x00000001L |
|---|
| 1101 | #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x00000000 |
|---|
| 1102 | #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0x0000000eL |
|---|
| 1103 | #define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x00000001 |
|---|
| 1104 | #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x00000400L |
|---|
| 1105 | #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0x0000000a |
|---|
| 1106 | #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x00003800L |
|---|
| 1107 | #define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0x0000000b |
|---|
| 1108 | #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x00000100L |
|---|
| 1109 | #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x00000008 |
|---|
| 1110 | #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x00000200L |
|---|
| 1111 | #define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x00000009 |
|---|
| 1112 | #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x00000010L |
|---|
| 1113 | #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000004 |
|---|
| 1114 | #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0x000000e0L |
|---|
| 1115 | #define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000005 |
|---|
| 1116 | #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x00004000L |
|---|
| 1117 | #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0x0000000e |
|---|
| 1118 | #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x00038000L |
|---|
| 1119 | #define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000f |
|---|
| 1120 | #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x00000001L |
|---|
| 1121 | #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x00000000 |
|---|
| 1122 | #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0x0000000eL |
|---|
| 1123 | #define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x00000001 |
|---|
| 1124 | #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x00000400L |
|---|
| 1125 | #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0x0000000a |
|---|
| 1126 | #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x00003800L |
|---|
| 1127 | #define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0x0000000b |
|---|
| 1128 | #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x00000100L |
|---|
| 1129 | #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x00000008 |
|---|
| 1130 | #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x00000200L |
|---|
| 1131 | #define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x00000009 |
|---|
| 1132 | #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x00000010L |
|---|
| 1133 | #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000004 |
|---|
| 1134 | #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0x000000e0L |
|---|
| 1135 | #define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000005 |
|---|
| 1136 | #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x00004000L |
|---|
| 1137 | #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0x0000000e |
|---|
| 1138 | #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x00038000L |
|---|
| 1139 | #define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000f |
|---|
| 1140 | #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x00000001L |
|---|
| 1141 | #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x00000000 |
|---|
| 1142 | #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0x0000000eL |
|---|
| 1143 | #define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x00000001 |
|---|
| 1144 | #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x00000400L |
|---|
| 1145 | #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0x0000000a |
|---|
| 1146 | #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x00003800L |
|---|
| 1147 | #define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0x0000000b |
|---|
| 1148 | #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x00000100L |
|---|
| 1149 | #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x00000008 |
|---|
| 1150 | #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x00000200L |
|---|
| 1151 | #define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x00000009 |
|---|
| 1152 | #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x00000010L |
|---|
| 1153 | #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000004 |
|---|
| 1154 | #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0x000000e0L |
|---|
| 1155 | #define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000005 |
|---|
| 1156 | #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x00004000L |
|---|
| 1157 | #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0x0000000e |
|---|
| 1158 | #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x00038000L |
|---|
| 1159 | #define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000f |
|---|
| 1160 | #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x00000001L |
|---|
| 1161 | #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x00000000 |
|---|
| 1162 | #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0x0000000eL |
|---|
| 1163 | #define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x00000001 |
|---|
| 1164 | #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x00000400L |
|---|
| 1165 | #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0x0000000a |
|---|
| 1166 | #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x00003800L |
|---|
| 1167 | #define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0x0000000b |
|---|
| 1168 | #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x00000100L |
|---|
| 1169 | #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x00000008 |
|---|
| 1170 | #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x00000200L |
|---|
| 1171 | #define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x00000009 |
|---|
| 1172 | #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x00000010L |
|---|
| 1173 | #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000004 |
|---|
| 1174 | #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0x000000e0L |
|---|
| 1175 | #define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000005 |
|---|
| 1176 | #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x00004000L |
|---|
| 1177 | #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0x0000000e |
|---|
| 1178 | #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x00038000L |
|---|
| 1179 | #define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000f |
|---|
| 1180 | #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x00000001L |
|---|
| 1181 | #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x00000000 |
|---|
| 1182 | #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0x0000000eL |
|---|
| 1183 | #define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x00000001 |
|---|
| 1184 | #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x00000400L |
|---|
| 1185 | #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0x0000000a |
|---|
| 1186 | #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x00003800L |
|---|
| 1187 | #define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0x0000000b |
|---|
| 1188 | #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x00000100L |
|---|
| 1189 | #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x00000008 |
|---|
| 1190 | #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x00000200L |
|---|
| 1191 | #define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x00000009 |
|---|
| 1192 | #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x00000010L |
|---|
| 1193 | #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000004 |
|---|
| 1194 | #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0x000000e0L |
|---|
| 1195 | #define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000005 |
|---|
| 1196 | #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x00004000L |
|---|
| 1197 | #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0x0000000e |
|---|
| 1198 | #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x00038000L |
|---|
| 1199 | #define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000f |
|---|
| 1200 | #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x00000001L |
|---|
| 1201 | #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x00000000 |
|---|
| 1202 | #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0x0000000eL |
|---|
| 1203 | #define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x00000001 |
|---|
| 1204 | #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x00000400L |
|---|
| 1205 | #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0x0000000a |
|---|
| 1206 | #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x00003800L |
|---|
| 1207 | #define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0x0000000b |
|---|
| 1208 | #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x00000100L |
|---|
| 1209 | #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x00000008 |
|---|
| 1210 | #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x00000200L |
|---|
| 1211 | #define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x00000009 |
|---|
| 1212 | #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x00000010L |
|---|
| 1213 | #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000004 |
|---|
| 1214 | #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0x000000e0L |
|---|
| 1215 | #define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000005 |
|---|
| 1216 | #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x00004000L |
|---|
| 1217 | #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0x0000000e |
|---|
| 1218 | #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x00038000L |
|---|
| 1219 | #define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000f |
|---|
| 1220 | #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x00000001L |
|---|
| 1221 | #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x00000000 |
|---|
| 1222 | #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0x0000000eL |
|---|
| 1223 | #define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x00000001 |
|---|
| 1224 | #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x00000400L |
|---|
| 1225 | #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0x0000000a |
|---|
| 1226 | #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x00003800L |
|---|
| 1227 | #define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0x0000000b |
|---|
| 1228 | #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x00000100L |
|---|
| 1229 | #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x00000008 |
|---|
| 1230 | #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x00000200L |
|---|
| 1231 | #define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x00000009 |
|---|
| 1232 | #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x00000010L |
|---|
| 1233 | #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000004 |
|---|
| 1234 | #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0x000000e0L |
|---|
| 1235 | #define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000005 |
|---|
| 1236 | #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x00004000L |
|---|
| 1237 | #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0x0000000e |
|---|
| 1238 | #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x00038000L |
|---|
| 1239 | #define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000f |
|---|
| 1240 | #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x00000001L |
|---|
| 1241 | #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x00000000 |
|---|
| 1242 | #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0x0000000eL |
|---|
| 1243 | #define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x00000001 |
|---|
| 1244 | #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x00000400L |
|---|
| 1245 | #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0x0000000a |
|---|
| 1246 | #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x00003800L |
|---|
| 1247 | #define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0x0000000b |
|---|
| 1248 | #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x00000100L |
|---|
| 1249 | #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x00000008 |
|---|
| 1250 | #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x00000200L |
|---|
| 1251 | #define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x00000009 |
|---|
| 1252 | #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x00000010L |
|---|
| 1253 | #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000004 |
|---|
| 1254 | #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0x000000e0L |
|---|
| 1255 | #define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000005 |
|---|
| 1256 | #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x00004000L |
|---|
| 1257 | #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0x0000000e |
|---|
| 1258 | #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x00038000L |
|---|
| 1259 | #define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000f |
|---|
| 1260 | #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x00000001L |
|---|
| 1261 | #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x00000000 |
|---|
| 1262 | #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0x0000000eL |
|---|
| 1263 | #define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x00000001 |
|---|
| 1264 | #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x00000400L |
|---|
| 1265 | #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0x0000000a |
|---|
| 1266 | #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x00003800L |
|---|
| 1267 | #define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0x0000000b |
|---|
| 1268 | #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x00000100L |
|---|
| 1269 | #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x00000008 |
|---|
| 1270 | #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x00000200L |
|---|
| 1271 | #define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x00000009 |
|---|
| 1272 | #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x00000010L |
|---|
| 1273 | #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000004 |
|---|
| 1274 | #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0x000000e0L |
|---|
| 1275 | #define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000005 |
|---|
| 1276 | #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x00004000L |
|---|
| 1277 | #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0x0000000e |
|---|
| 1278 | #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x00038000L |
|---|
| 1279 | #define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000f |
|---|
| 1280 | #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x00000001L |
|---|
| 1281 | #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x00000000 |
|---|
| 1282 | #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0x0000000eL |
|---|
| 1283 | #define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x00000001 |
|---|
| 1284 | #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x00000400L |
|---|
| 1285 | #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0x0000000a |
|---|
| 1286 | #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x00003800L |
|---|
| 1287 | #define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0x0000000b |
|---|
| 1288 | #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x00000100L |
|---|
| 1289 | #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x00000008 |
|---|
| 1290 | #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x00000200L |
|---|
| 1291 | #define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x00000009 |
|---|
| 1292 | #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x00000010L |
|---|
| 1293 | #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000004 |
|---|
| 1294 | #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0x000000e0L |
|---|
| 1295 | #define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000005 |
|---|
| 1296 | #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x00004000L |
|---|
| 1297 | #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0x0000000e |
|---|
| 1298 | #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x00038000L |
|---|
| 1299 | #define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000f |
|---|
| 1300 | #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x00000001L |
|---|
| 1301 | #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x00000000 |
|---|
| 1302 | #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0x0000000eL |
|---|
| 1303 | #define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x00000001 |
|---|
| 1304 | #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x00000400L |
|---|
| 1305 | #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0x0000000a |
|---|
| 1306 | #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x00003800L |
|---|
| 1307 | #define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0x0000000b |
|---|
| 1308 | #define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x00000008L |
|---|
| 1309 | #define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x00000003 |
|---|
| 1310 | #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x00001c00L |
|---|
| 1311 | #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0x0000000a |
|---|
| 1312 | #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x00000380L |
|---|
| 1313 | #define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x00000007 |
|---|
| 1314 | #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000L |
|---|
| 1315 | #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x0000001c |
|---|
| 1316 | #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000L |
|---|
| 1317 | #define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x0000001d |
|---|
| 1318 | #define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x07000000L |
|---|
| 1319 | #define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x00000018 |
|---|
| 1320 | #define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x00000070L |
|---|
| 1321 | #define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x00000004 |
|---|
| 1322 | #define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x00010000L |
|---|
| 1323 | #define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x00000010 |
|---|
| 1324 | #define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x00000007L |
|---|
| 1325 | #define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x00000000 |
|---|
| 1326 | #define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x00000008L |
|---|
| 1327 | #define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x00000003 |
|---|
| 1328 | #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x00001c00L |
|---|
| 1329 | #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0x0000000a |
|---|
| 1330 | #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x00000380L |
|---|
| 1331 | #define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x00000007 |
|---|
| 1332 | #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000L |
|---|
| 1333 | #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x0000001c |
|---|
| 1334 | #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000L |
|---|
| 1335 | #define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x0000001d |
|---|
| 1336 | #define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x07000000L |
|---|
| 1337 | #define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x00000018 |
|---|
| 1338 | #define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x00000070L |
|---|
| 1339 | #define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x00000004 |
|---|
| 1340 | #define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x00010000L |
|---|
| 1341 | #define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x00000010 |
|---|
| 1342 | #define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x00000007L |
|---|
| 1343 | #define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x00000000 |
|---|
| 1344 | #define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x00000008L |
|---|
| 1345 | #define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x00000003 |
|---|
| 1346 | #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x00001c00L |
|---|
| 1347 | #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0x0000000a |
|---|
| 1348 | #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x00000380L |
|---|
| 1349 | #define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x00000007 |
|---|
| 1350 | #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000L |
|---|
| 1351 | #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x0000001c |
|---|
| 1352 | #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000L |
|---|
| 1353 | #define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x0000001d |
|---|
| 1354 | #define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x07000000L |
|---|
| 1355 | #define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x00000018 |
|---|
| 1356 | #define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x00000070L |
|---|
| 1357 | #define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x00000004 |
|---|
| 1358 | #define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x00010000L |
|---|
| 1359 | #define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x00000010 |
|---|
| 1360 | #define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x00000007L |
|---|
| 1361 | #define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x00000000 |
|---|
| 1362 | #define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x00000008L |
|---|
| 1363 | #define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x00000003 |
|---|
| 1364 | #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x00001c00L |
|---|
| 1365 | #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0x0000000a |
|---|
| 1366 | #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x00000380L |
|---|
| 1367 | #define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x00000007 |
|---|
| 1368 | #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000L |
|---|
| 1369 | #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x0000001c |
|---|
| 1370 | #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000L |
|---|
| 1371 | #define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x0000001d |
|---|
| 1372 | #define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x07000000L |
|---|
| 1373 | #define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x00000018 |
|---|
| 1374 | #define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x00000070L |
|---|
| 1375 | #define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x00000004 |
|---|
| 1376 | #define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x00010000L |
|---|
| 1377 | #define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x00000010 |
|---|
| 1378 | #define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x00000007L |
|---|
| 1379 | #define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x00000000 |
|---|
| 1380 | #define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x00000001L |
|---|
| 1381 | #define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x00000000 |
|---|
| 1382 | #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L |
|---|
| 1383 | #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x00000005 |
|---|
| 1384 | #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L |
|---|
| 1385 | #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x00000004 |
|---|
| 1386 | #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x00000008L |
|---|
| 1387 | #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x00000003 |
|---|
| 1388 | #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x00000004L |
|---|
| 1389 | #define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x00000002 |
|---|
| 1390 | #define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x00010000L |
|---|
| 1391 | #define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010 |
|---|
| 1392 | #define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x04000000L |
|---|
| 1393 | #define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x0000001a |
|---|
| 1394 | #define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x08000000L |
|---|
| 1395 | #define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x0000001b |
|---|
| 1396 | #define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000L |
|---|
| 1397 | #define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x0000001c |
|---|
| 1398 | #define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000L |
|---|
| 1399 | #define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x0000001d |
|---|
| 1400 | #define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000L |
|---|
| 1401 | #define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x0000001e |
|---|
| 1402 | #define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000L |
|---|
| 1403 | #define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x0000001f |
|---|
| 1404 | #define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x00020000L |
|---|
| 1405 | #define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x00000011 |
|---|
| 1406 | #define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x00040000L |
|---|
| 1407 | #define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x00000012 |
|---|
| 1408 | #define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x00080000L |
|---|
| 1409 | #define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x00000013 |
|---|
| 1410 | #define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x00100000L |
|---|
| 1411 | #define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x00000014 |
|---|
| 1412 | #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x00200000L |
|---|
| 1413 | #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015 |
|---|
| 1414 | #define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x00400000L |
|---|
| 1415 | #define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x00000016 |
|---|
| 1416 | #define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x00800000L |
|---|
| 1417 | #define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x00000017 |
|---|
| 1418 | #define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x01000000L |
|---|
| 1419 | #define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x00000018 |
|---|
| 1420 | #define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x02000000L |
|---|
| 1421 | #define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x00000019 |
|---|
| 1422 | #define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L |
|---|
| 1423 | #define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x00000008 |
|---|
| 1424 | #define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x00000200L |
|---|
| 1425 | #define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x00000009 |
|---|
| 1426 | #define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x00000400L |
|---|
| 1427 | #define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0x0000000a |
|---|
| 1428 | #define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x00000800L |
|---|
| 1429 | #define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0x0000000b |
|---|
| 1430 | #define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x00001000L |
|---|
| 1431 | #define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0x0000000c |
|---|
| 1432 | #define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x00002000L |
|---|
| 1433 | #define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0x0000000d |
|---|
| 1434 | #define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x00004000L |
|---|
| 1435 | #define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0x0000000e |
|---|
| 1436 | #define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x00008000L |
|---|
| 1437 | #define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0x0000000f |
|---|
| 1438 | #define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x00000002L |
|---|
| 1439 | #define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x00000001 |
|---|
| 1440 | #define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x00000040L |
|---|
| 1441 | #define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x00000006 |
|---|
| 1442 | #define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffffL |
|---|
| 1443 | #define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x00000000 |
|---|
| 1444 | #define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x00000001L |
|---|
| 1445 | #define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x00000000 |
|---|
| 1446 | #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x00000020L |
|---|
| 1447 | #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x00000005 |
|---|
| 1448 | #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x00000010L |
|---|
| 1449 | #define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x00000004 |
|---|
| 1450 | #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x00000008L |
|---|
| 1451 | #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x00000003 |
|---|
| 1452 | #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x00000004L |
|---|
| 1453 | #define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x00000002 |
|---|
| 1454 | #define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x00000700L |
|---|
| 1455 | #define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x00000008 |
|---|
| 1456 | #define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x00000002L |
|---|
| 1457 | #define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x00000001 |
|---|
| 1458 | #define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x00000040L |
|---|
| 1459 | #define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x00000006 |
|---|
| 1460 | #define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x00000001L |
|---|
| 1461 | #define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x00000000 |
|---|
| 1462 | #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x00000020L |
|---|
| 1463 | #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x00000005 |
|---|
| 1464 | #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x00000010L |
|---|
| 1465 | #define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x00000004 |
|---|
| 1466 | #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x00000008L |
|---|
| 1467 | #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x00000003 |
|---|
| 1468 | #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x00000004L |
|---|
| 1469 | #define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x00000002 |
|---|
| 1470 | #define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x00000700L |
|---|
| 1471 | #define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x00000008 |
|---|
| 1472 | #define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x00000002L |
|---|
| 1473 | #define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x00000001 |
|---|
| 1474 | #define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x00000040L |
|---|
| 1475 | #define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x00000006 |
|---|
| 1476 | #define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x00000001L |
|---|
| 1477 | #define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x00000000 |
|---|
| 1478 | #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x00000020L |
|---|
| 1479 | #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x00000005 |
|---|
| 1480 | #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x00000010L |
|---|
| 1481 | #define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x00000004 |
|---|
| 1482 | #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x00000008L |
|---|
| 1483 | #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x00000003 |
|---|
| 1484 | #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x00000004L |
|---|
| 1485 | #define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x00000002 |
|---|
| 1486 | #define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x00000700L |
|---|
| 1487 | #define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x00000008 |
|---|
| 1488 | #define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x00000002L |
|---|
| 1489 | #define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x00000001 |
|---|
| 1490 | #define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x00000040L |
|---|
| 1491 | #define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x00000006 |
|---|
| 1492 | #define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x00000001L |
|---|
| 1493 | #define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x00000000 |
|---|
| 1494 | #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x00000020L |
|---|
| 1495 | #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x00000005 |
|---|
| 1496 | #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x00000010L |
|---|
| 1497 | #define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x00000004 |
|---|
| 1498 | #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x00000008L |
|---|
| 1499 | #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x00000003 |
|---|
| 1500 | #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x00000004L |
|---|
| 1501 | #define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x00000002 |
|---|
| 1502 | #define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x00000700L |
|---|
| 1503 | #define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x00000008 |
|---|
| 1504 | #define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x00000002L |
|---|
| 1505 | #define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x00000001 |
|---|
| 1506 | #define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x00000040L |
|---|
| 1507 | #define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x00000006 |
|---|
| 1508 | #define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x00000001L |
|---|
| 1509 | #define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x00000000 |
|---|
| 1510 | #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x00000020L |
|---|
| 1511 | #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x00000005 |
|---|
| 1512 | #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x00000010L |
|---|
| 1513 | #define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x00000004 |
|---|
| 1514 | #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x00000008L |
|---|
| 1515 | #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x00000003 |
|---|
| 1516 | #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x00000004L |
|---|
| 1517 | #define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x00000002 |
|---|
| 1518 | #define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x00000700L |
|---|
| 1519 | #define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x00000008 |
|---|
| 1520 | #define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x00000002L |
|---|
| 1521 | #define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x00000001 |
|---|
| 1522 | #define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x00000040L |
|---|
| 1523 | #define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x00000006 |
|---|
| 1524 | #define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x00000001L |
|---|
| 1525 | #define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x00000000 |
|---|
| 1526 | #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x00000020L |
|---|
| 1527 | #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x00000005 |
|---|
| 1528 | #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x00000010L |
|---|
| 1529 | #define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x00000004 |
|---|
| 1530 | #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x00000008L |
|---|
| 1531 | #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x00000003 |
|---|
| 1532 | #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x00000004L |
|---|
| 1533 | #define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x00000002 |
|---|
| 1534 | #define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x00000700L |
|---|
| 1535 | #define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x00000008 |
|---|
| 1536 | #define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x00000002L |
|---|
| 1537 | #define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x00000001 |
|---|
| 1538 | #define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x00000040L |
|---|
| 1539 | #define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x00000006 |
|---|
| 1540 | #define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x00000001L |
|---|
| 1541 | #define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x00000000 |
|---|
| 1542 | #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x00000020L |
|---|
| 1543 | #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x00000005 |
|---|
| 1544 | #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x00000010L |
|---|
| 1545 | #define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x00000004 |
|---|
| 1546 | #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x00000008L |
|---|
| 1547 | #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x00000003 |
|---|
| 1548 | #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x00000004L |
|---|
| 1549 | #define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x00000002 |
|---|
| 1550 | #define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x00000700L |
|---|
| 1551 | #define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x00000008 |
|---|
| 1552 | #define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x00000002L |
|---|
| 1553 | #define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x00000001 |
|---|
| 1554 | #define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x00000040L |
|---|
| 1555 | #define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x00000006 |
|---|
| 1556 | #define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x00000001L |
|---|
| 1557 | #define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x00000000 |
|---|
| 1558 | #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x00000020L |
|---|
| 1559 | #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x00000005 |
|---|
| 1560 | #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x00000010L |
|---|
| 1561 | #define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x00000004 |
|---|
| 1562 | #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x00000008L |
|---|
| 1563 | #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x00000003 |
|---|
| 1564 | #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x00000004L |
|---|
| 1565 | #define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x00000002 |
|---|
| 1566 | #define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x00000700L |
|---|
| 1567 | #define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x00000008 |
|---|
| 1568 | #define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x00000002L |
|---|
| 1569 | #define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x00000001 |
|---|
| 1570 | #define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x00000040L |
|---|
| 1571 | #define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x00000006 |
|---|
| 1572 | #define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x00000001L |
|---|
| 1573 | #define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x00000000 |
|---|
| 1574 | #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x00000020L |
|---|
| 1575 | #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x00000005 |
|---|
| 1576 | #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x00000010L |
|---|
| 1577 | #define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x00000004 |
|---|
| 1578 | #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x00000008L |
|---|
| 1579 | #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x00000003 |
|---|
| 1580 | #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x00000004L |
|---|
| 1581 | #define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x00000002 |
|---|
| 1582 | #define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x00000700L |
|---|
| 1583 | #define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x00000008 |
|---|
| 1584 | #define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x00000002L |
|---|
| 1585 | #define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x00000001 |
|---|
| 1586 | #define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x00000040L |
|---|
| 1587 | #define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x00000006 |
|---|
| 1588 | #define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x00000001L |
|---|
| 1589 | #define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x00000000 |
|---|
| 1590 | #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x00000020L |
|---|
| 1591 | #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x00000005 |
|---|
| 1592 | #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x00000010L |
|---|
| 1593 | #define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x00000004 |
|---|
| 1594 | #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x00000008L |
|---|
| 1595 | #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x00000003 |
|---|
| 1596 | #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x00000004L |
|---|
| 1597 | #define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x00000002 |
|---|
| 1598 | #define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x00000700L |
|---|
| 1599 | #define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x00000008 |
|---|
| 1600 | #define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x00000002L |
|---|
| 1601 | #define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x00000001 |
|---|
| 1602 | #define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x00000040L |
|---|
| 1603 | #define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x00000006 |
|---|
| 1604 | #define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x00000001L |
|---|
| 1605 | #define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x00000000 |
|---|
| 1606 | #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x00000020L |
|---|
| 1607 | #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x00000005 |
|---|
| 1608 | #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x00000010L |
|---|
| 1609 | #define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x00000004 |
|---|
| 1610 | #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x00000008L |
|---|
| 1611 | #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x00000003 |
|---|
| 1612 | #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x00000004L |
|---|
| 1613 | #define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x00000002 |
|---|
| 1614 | #define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x00000700L |
|---|
| 1615 | #define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x00000008 |
|---|
| 1616 | #define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x00000002L |
|---|
| 1617 | #define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x00000001 |
|---|
| 1618 | #define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x00000040L |
|---|
| 1619 | #define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x00000006 |
|---|
| 1620 | #define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x00000001L |
|---|
| 1621 | #define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x00000000 |
|---|
| 1622 | #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x00000020L |
|---|
| 1623 | #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x00000005 |
|---|
| 1624 | #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x00000010L |
|---|
| 1625 | #define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x00000004 |
|---|
| 1626 | #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x00000008L |
|---|
| 1627 | #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x00000003 |
|---|
| 1628 | #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x00000004L |
|---|
| 1629 | #define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x00000002 |
|---|
| 1630 | #define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x00000700L |
|---|
| 1631 | #define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x00000008 |
|---|
| 1632 | #define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x00000002L |
|---|
| 1633 | #define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x00000001 |
|---|
| 1634 | #define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x00000040L |
|---|
| 1635 | #define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x00000006 |
|---|
| 1636 | #define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x00000001L |
|---|
| 1637 | #define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x00000000 |
|---|
| 1638 | #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x00000020L |
|---|
| 1639 | #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x00000005 |
|---|
| 1640 | #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x00000010L |
|---|
| 1641 | #define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x00000004 |
|---|
| 1642 | #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x00000008L |
|---|
| 1643 | #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x00000003 |
|---|
| 1644 | #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x00000004L |
|---|
| 1645 | #define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x00000002 |
|---|
| 1646 | #define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x00000700L |
|---|
| 1647 | #define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x00000008 |
|---|
| 1648 | #define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x00000002L |
|---|
| 1649 | #define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x00000001 |
|---|
| 1650 | #define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x00000040L |
|---|
| 1651 | #define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x00000006 |
|---|
| 1652 | #define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x00000001L |
|---|
| 1653 | #define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x00000000 |
|---|
| 1654 | #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x00000020L |
|---|
| 1655 | #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x00000005 |
|---|
| 1656 | #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x00000010L |
|---|
| 1657 | #define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x00000004 |
|---|
| 1658 | #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x00000008L |
|---|
| 1659 | #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x00000003 |
|---|
| 1660 | #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x00000004L |
|---|
| 1661 | #define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x00000002 |
|---|
| 1662 | #define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x00000700L |
|---|
| 1663 | #define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x00000008 |
|---|
| 1664 | #define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x00000002L |
|---|
| 1665 | #define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x00000001 |
|---|
| 1666 | #define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x00000040L |
|---|
| 1667 | #define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x00000006 |
|---|
| 1668 | #define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x00000001L |
|---|
| 1669 | #define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x00000000 |
|---|
| 1670 | #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x00000020L |
|---|
| 1671 | #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x00000005 |
|---|
| 1672 | #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x00000010L |
|---|
| 1673 | #define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x00000004 |
|---|
| 1674 | #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x00000008L |
|---|
| 1675 | #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x00000003 |
|---|
| 1676 | #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x00000004L |
|---|
| 1677 | #define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x00000002 |
|---|
| 1678 | #define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x00000700L |
|---|
| 1679 | #define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x00000008 |
|---|
| 1680 | #define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x00000002L |
|---|
| 1681 | #define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x00000001 |
|---|
| 1682 | #define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x00000040L |
|---|
| 1683 | #define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x00000006 |
|---|
| 1684 | #define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x00000001L |
|---|
| 1685 | #define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x00000000 |
|---|
| 1686 | #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x00000020L |
|---|
| 1687 | #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x00000005 |
|---|
| 1688 | #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x00000010L |
|---|
| 1689 | #define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x00000004 |
|---|
| 1690 | #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x00000008L |
|---|
| 1691 | #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x00000003 |
|---|
| 1692 | #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x00000004L |
|---|
| 1693 | #define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x00000002 |
|---|
| 1694 | #define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x00000700L |
|---|
| 1695 | #define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x00000008 |
|---|
| 1696 | #define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x00000002L |
|---|
| 1697 | #define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x00000001 |
|---|
| 1698 | #define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x00000040L |
|---|
| 1699 | #define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x00000006 |
|---|
| 1700 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x00000001L |
|---|
| 1701 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x00000000 |
|---|
| 1702 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x00000400L |
|---|
| 1703 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0x0000000a |
|---|
| 1704 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x00000800L |
|---|
| 1705 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0x0000000b |
|---|
| 1706 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x00001000L |
|---|
| 1707 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0x0000000c |
|---|
| 1708 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x00002000L |
|---|
| 1709 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0x0000000d |
|---|
| 1710 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x00004000L |
|---|
| 1711 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0x0000000e |
|---|
| 1712 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x00008000L |
|---|
| 1713 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0x0000000f |
|---|
| 1714 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x00000002L |
|---|
| 1715 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x00000001 |
|---|
| 1716 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x00000004L |
|---|
| 1717 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x00000002 |
|---|
| 1718 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x00000008L |
|---|
| 1719 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x00000003 |
|---|
| 1720 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x00000010L |
|---|
| 1721 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x00000004 |
|---|
| 1722 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x00000020L |
|---|
| 1723 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x00000005 |
|---|
| 1724 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x00000040L |
|---|
| 1725 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x00000006 |
|---|
| 1726 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x00000080L |
|---|
| 1727 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x00000007 |
|---|
| 1728 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x00000100L |
|---|
| 1729 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x00000008 |
|---|
| 1730 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x00000200L |
|---|
| 1731 | #define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x00000009 |
|---|
| 1732 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x00000003L |
|---|
| 1733 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x00000000 |
|---|
| 1734 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x00000004L |
|---|
| 1735 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x00000002 |
|---|
| 1736 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x00000008L |
|---|
| 1737 | #define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x00000003 |
|---|
| 1738 | #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x00000010L |
|---|
| 1739 | #define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x00000004 |
|---|
| 1740 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x00000008L |
|---|
| 1741 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000003 |
|---|
| 1742 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x00000007L |
|---|
| 1743 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 |
|---|
| 1744 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x00000080L |
|---|
| 1745 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x00000007 |
|---|
| 1746 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000070L |
|---|
| 1747 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000004 |
|---|
| 1748 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x00000200L |
|---|
| 1749 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x00000009 |
|---|
| 1750 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x00000100L |
|---|
| 1751 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x00000008 |
|---|
| 1752 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x00040000L |
|---|
| 1753 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x00000012 |
|---|
| 1754 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x0003fc00L |
|---|
| 1755 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0x0000000a |
|---|
| 1756 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000L |
|---|
| 1757 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x0000001c |
|---|
| 1758 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0x0ff80000L |
|---|
| 1759 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x00000013 |
|---|
| 1760 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000L |
|---|
| 1761 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x0000001f |
|---|
| 1762 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000L |
|---|
| 1763 | #define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x0000001d |
|---|
| 1764 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x00000008L |
|---|
| 1765 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000003 |
|---|
| 1766 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x00000007L |
|---|
| 1767 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000000 |
|---|
| 1768 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x00040000L |
|---|
| 1769 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x00000012 |
|---|
| 1770 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x0003c000L |
|---|
| 1771 | #define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0x0000000e |
|---|
| 1772 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000020L |
|---|
| 1773 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x00000005 |
|---|
| 1774 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000010L |
|---|
| 1775 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000004 |
|---|
| 1776 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00000080L |
|---|
| 1777 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x00000007 |
|---|
| 1778 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000040L |
|---|
| 1779 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x00000006 |
|---|
| 1780 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x00000200L |
|---|
| 1781 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x00000009 |
|---|
| 1782 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x00000100L |
|---|
| 1783 | #define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x00000008 |
|---|
| 1784 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x00000300L |
|---|
| 1785 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x00000008 |
|---|
| 1786 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1787 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1788 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1789 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1790 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x00000070L |
|---|
| 1791 | #define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x00000004 |
|---|
| 1792 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L |
|---|
| 1793 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x00000008 |
|---|
| 1794 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1795 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1796 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1797 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1798 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x00000070L |
|---|
| 1799 | #define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x00000004 |
|---|
| 1800 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x00000300L |
|---|
| 1801 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x00000008 |
|---|
| 1802 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1803 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1804 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1805 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1806 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x00000070L |
|---|
| 1807 | #define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x00000004 |
|---|
| 1808 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x00000300L |
|---|
| 1809 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x00000008 |
|---|
| 1810 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1811 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1812 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1813 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1814 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x00000070L |
|---|
| 1815 | #define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x00000004 |
|---|
| 1816 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x00000003L |
|---|
| 1817 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x00000000 |
|---|
| 1818 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x00000004L |
|---|
| 1819 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x00000002 |
|---|
| 1820 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x000007f0L |
|---|
| 1821 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x00000004 |
|---|
| 1822 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x00000008L |
|---|
| 1823 | #define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x00000003 |
|---|
| 1824 | #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x00000800L |
|---|
| 1825 | #define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0x0000000b |
|---|
| 1826 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x00000100L |
|---|
| 1827 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x00000008 |
|---|
| 1828 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0x000000ffL |
|---|
| 1829 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x00000000 |
|---|
| 1830 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x00001000L |
|---|
| 1831 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0x0000000c |
|---|
| 1832 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0x00000e00L |
|---|
| 1833 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x00000009 |
|---|
| 1834 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x00004000L |
|---|
| 1835 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0x0000000e |
|---|
| 1836 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x00002000L |
|---|
| 1837 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0x0000000d |
|---|
| 1838 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000L |
|---|
| 1839 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x0000001c |
|---|
| 1840 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0x0fff8000L |
|---|
| 1841 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0x0000000f |
|---|
| 1842 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000L |
|---|
| 1843 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x0000001f |
|---|
| 1844 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000L |
|---|
| 1845 | #define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x0000001e |
|---|
| 1846 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x00400000L |
|---|
| 1847 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x00000016 |
|---|
| 1848 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x00380000L |
|---|
| 1849 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x00000013 |
|---|
| 1850 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x00000020L |
|---|
| 1851 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x00000005 |
|---|
| 1852 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x0000001fL |
|---|
| 1853 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x00000000 |
|---|
| 1854 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x00000100L |
|---|
| 1855 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x00000008 |
|---|
| 1856 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0x000000c0L |
|---|
| 1857 | #define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x00000006 |
|---|
| 1858 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x00000400L |
|---|
| 1859 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x0000000a |
|---|
| 1860 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x00000200L |
|---|
| 1861 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x00000009 |
|---|
| 1862 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x00001000L |
|---|
| 1863 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x0000000c |
|---|
| 1864 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x00000800L |
|---|
| 1865 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x0000000b |
|---|
| 1866 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x00004000L |
|---|
| 1867 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0x0000000e |
|---|
| 1868 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x00002000L |
|---|
| 1869 | #define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0x0000000d |
|---|
| 1870 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x00000300L |
|---|
| 1871 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x00000008 |
|---|
| 1872 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1873 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1874 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1875 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1876 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x00000070L |
|---|
| 1877 | #define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x00000004 |
|---|
| 1878 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x00000300L |
|---|
| 1879 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x00000008 |
|---|
| 1880 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1881 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1882 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1883 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1884 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x00000070L |
|---|
| 1885 | #define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x00000004 |
|---|
| 1886 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x00000300L |
|---|
| 1887 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x00000008 |
|---|
| 1888 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1889 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1890 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1891 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1892 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x00000070L |
|---|
| 1893 | #define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x00000004 |
|---|
| 1894 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x00000300L |
|---|
| 1895 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x00000008 |
|---|
| 1896 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x00000002L |
|---|
| 1897 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x00000001 |
|---|
| 1898 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x00000001L |
|---|
| 1899 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x00000000 |
|---|
| 1900 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x00000070L |
|---|
| 1901 | #define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x00000004 |
|---|
| 1902 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000200L |
|---|
| 1903 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000009 |
|---|
| 1904 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000400L |
|---|
| 1905 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000a |
|---|
| 1906 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000800L |
|---|
| 1907 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000b |
|---|
| 1908 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00100000L |
|---|
| 1909 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000014 |
|---|
| 1910 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00200000L |
|---|
| 1911 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000015 |
|---|
| 1912 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00001000L |
|---|
| 1913 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x0000000c |
|---|
| 1914 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00002000L |
|---|
| 1915 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x0000000d |
|---|
| 1916 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00004000L |
|---|
| 1917 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x0000000e |
|---|
| 1918 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00400000L |
|---|
| 1919 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000016 |
|---|
| 1920 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00800000L |
|---|
| 1921 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000017 |
|---|
| 1922 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x00000100L |
|---|
| 1923 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000008 |
|---|
| 1924 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x00000002L |
|---|
| 1925 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x00000001 |
|---|
| 1926 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x00000004L |
|---|
| 1927 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x00000002 |
|---|
| 1928 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x00000008L |
|---|
| 1929 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x00000003 |
|---|
| 1930 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x00010000L |
|---|
| 1931 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x00000010 |
|---|
| 1932 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x00020000L |
|---|
| 1933 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x00000011 |
|---|
| 1934 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x00000010L |
|---|
| 1935 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x00000004 |
|---|
| 1936 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x00000020L |
|---|
| 1937 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x00000005 |
|---|
| 1938 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x00000040L |
|---|
| 1939 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x00000006 |
|---|
| 1940 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x00040000L |
|---|
| 1941 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x00000012 |
|---|
| 1942 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x00080000L |
|---|
| 1943 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x00000013 |
|---|
| 1944 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x00000080L |
|---|
| 1945 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000007 |
|---|
| 1946 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x00000001L |
|---|
| 1947 | #define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x00000000 |
|---|
| 1948 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x000003ffL |
|---|
| 1949 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x00000000 |
|---|
| 1950 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0x000ffc00L |
|---|
| 1951 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0x0000000a |
|---|
| 1952 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000L |
|---|
| 1953 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x00000014 |
|---|
| 1954 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000L |
|---|
| 1955 | #define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x0000001e |
|---|
| 1956 | #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000L |
|---|
| 1957 | #define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x0000001e |
|---|
| 1958 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0x0000000fL |
|---|
| 1959 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x00000000 |
|---|
| 1960 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0x000000f0L |
|---|
| 1961 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x00000004 |
|---|
| 1962 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0x00000f00L |
|---|
| 1963 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x00000008 |
|---|
| 1964 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0x0000f000L |
|---|
| 1965 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0x0000000c |
|---|
| 1966 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0x000f0000L |
|---|
| 1967 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x00000010 |
|---|
| 1968 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0x00f00000L |
|---|
| 1969 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x00000014 |
|---|
| 1970 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x01000000L |
|---|
| 1971 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x00000018 |
|---|
| 1972 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x02000000L |
|---|
| 1973 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x00000019 |
|---|
| 1974 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x04000000L |
|---|
| 1975 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x0000001a |
|---|
| 1976 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x08000000L |
|---|
| 1977 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x0000001b |
|---|
| 1978 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000L |
|---|
| 1979 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x0000001c |
|---|
| 1980 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000L |
|---|
| 1981 | #define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x0000001d |
|---|
| 1982 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0x0000f000L |
|---|
| 1983 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0x0000000c |
|---|
| 1984 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0x000f0000L |
|---|
| 1985 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x00000010 |
|---|
| 1986 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0x00f00000L |
|---|
| 1987 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x00000014 |
|---|
| 1988 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x03000000L |
|---|
| 1989 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x00000018 |
|---|
| 1990 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0x0c000000L |
|---|
| 1991 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x0000001a |
|---|
| 1992 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000L |
|---|
| 1993 | #define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x0000001c |
|---|
| 1994 | #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000L |
|---|
| 1995 | #define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x0000001e |
|---|
| 1996 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x00000001L |
|---|
| 1997 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x00000000 |
|---|
| 1998 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x00000002L |
|---|
| 1999 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x00000001 |
|---|
| 2000 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x00000004L |
|---|
| 2001 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x00000002 |
|---|
| 2002 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0x00f00000L |
|---|
| 2003 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x00000014 |
|---|
| 2004 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0x0f000000L |
|---|
| 2005 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x00000018 |
|---|
| 2006 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000L |
|---|
| 2007 | #define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x0000001c |
|---|
| 2008 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x00000007L |
|---|
| 2009 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x00000000 |
|---|
| 2010 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x00000038L |
|---|
| 2011 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x00000003 |
|---|
| 2012 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x000001c0L |
|---|
| 2013 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x00000006 |
|---|
| 2014 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0x00f00000L |
|---|
| 2015 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x00000014 |
|---|
| 2016 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0x0f000000L |
|---|
| 2017 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x00000018 |
|---|
| 2018 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000L |
|---|
| 2019 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x0000001c |
|---|
| 2020 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0x00000e00L |
|---|
| 2021 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x00000009 |
|---|
| 2022 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x00007000L |
|---|
| 2023 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0x0000000c |
|---|
| 2024 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x00038000L |
|---|
| 2025 | #define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0x0000000f |
|---|
| 2026 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x0000001fL |
|---|
| 2027 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x00000000 |
|---|
| 2028 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x000003e0L |
|---|
| 2029 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x00000005 |
|---|
| 2030 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x00007c00L |
|---|
| 2031 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0x0000000a |
|---|
| 2032 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x00008000L |
|---|
| 2033 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0x0000000f |
|---|
| 2034 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x00010000L |
|---|
| 2035 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x00000010 |
|---|
| 2036 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x00020000L |
|---|
| 2037 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x00000011 |
|---|
| 2038 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x00040000L |
|---|
| 2039 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x00000012 |
|---|
| 2040 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x00080000L |
|---|
| 2041 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x00000013 |
|---|
| 2042 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x00100000L |
|---|
| 2043 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x00000014 |
|---|
| 2044 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x08000000L |
|---|
| 2045 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x0000001b |
|---|
| 2046 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000L |
|---|
| 2047 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x0000001c |
|---|
| 2048 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L |
|---|
| 2049 | #define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x0000001d |
|---|
| 2050 | #define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000L |
|---|
| 2051 | #define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x0000001e |
|---|
| 2052 | #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x08000000L |
|---|
| 2053 | #define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001b |
|---|
| 2054 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0x0000000fL |
|---|
| 2055 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x00000000 |
|---|
| 2056 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0x000000f0L |
|---|
| 2057 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x00000004 |
|---|
| 2058 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0x00000f00L |
|---|
| 2059 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x00000008 |
|---|
| 2060 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0x0000f000L |
|---|
| 2061 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0x0000000c |
|---|
| 2062 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0x000f0000L |
|---|
| 2063 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x00000010 |
|---|
| 2064 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0x00f00000L |
|---|
| 2065 | #define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x00000014 |
|---|
| 2066 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x01000000L |
|---|
| 2067 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x00000018 |
|---|
| 2068 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x04000000L |
|---|
| 2069 | #define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x0000001a |
|---|
| 2070 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x001c0000L |
|---|
| 2071 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x00000012 |
|---|
| 2072 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0x00e00000L |
|---|
| 2073 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x00000015 |
|---|
| 2074 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x07000000L |
|---|
| 2075 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x00000018 |
|---|
| 2076 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x08000000L |
|---|
| 2077 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x0000001b |
|---|
| 2078 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000L |
|---|
| 2079 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x0000001c |
|---|
| 2080 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000L |
|---|
| 2081 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x0000001d |
|---|
| 2082 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0x0000000fL |
|---|
| 2083 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x00000000 |
|---|
| 2084 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0x000000f0L |
|---|
| 2085 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x00000004 |
|---|
| 2086 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0x00000f00L |
|---|
| 2087 | #define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x00000008 |
|---|
| 2088 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x00001000L |
|---|
| 2089 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x0000000c |
|---|
| 2090 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x00002000L |
|---|
| 2091 | #define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0x0000000d |
|---|
| 2092 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x00020000L |
|---|
| 2093 | #define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x00000011 |
|---|
| 2094 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000L |
|---|
| 2095 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x0000001f |
|---|
| 2096 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000L |
|---|
| 2097 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x0000001e |
|---|
| 2098 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x00000002L |
|---|
| 2099 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x00000001 |
|---|
| 2100 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x00000001L |
|---|
| 2101 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2102 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x00000008L |
|---|
| 2103 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x00000003 |
|---|
| 2104 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x00000004L |
|---|
| 2105 | #define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x00000002 |
|---|
| 2106 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000L |
|---|
| 2107 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x0000001d |
|---|
| 2108 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000L |
|---|
| 2109 | #define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x0000001c |
|---|
| 2110 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000100L |
|---|
| 2111 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000008 |
|---|
| 2112 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x000000c0L |
|---|
| 2113 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000006 |
|---|
| 2114 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x00000400L |
|---|
| 2115 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0x0000000a |
|---|
| 2116 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x00000200L |
|---|
| 2117 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x00000009 |
|---|
| 2118 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00001000L |
|---|
| 2119 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000c |
|---|
| 2120 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000800L |
|---|
| 2121 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x0000000b |
|---|
| 2122 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x00004000L |
|---|
| 2123 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0x0000000e |
|---|
| 2124 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x00002000L |
|---|
| 2125 | #define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0x0000000d |
|---|
| 2126 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x00010000L |
|---|
| 2127 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x00000010 |
|---|
| 2128 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x00008000L |
|---|
| 2129 | #define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0x0000000f |
|---|
| 2130 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x00040000L |
|---|
| 2131 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x00000012 |
|---|
| 2132 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x00020000L |
|---|
| 2133 | #define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x00000011 |
|---|
| 2134 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x00100000L |
|---|
| 2135 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x00000014 |
|---|
| 2136 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x00080000L |
|---|
| 2137 | #define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x00000013 |
|---|
| 2138 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x00400000L |
|---|
| 2139 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x00000016 |
|---|
| 2140 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x00200000L |
|---|
| 2141 | #define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x00000015 |
|---|
| 2142 | #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x01000000L |
|---|
| 2143 | #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x00000018 |
|---|
| 2144 | #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x00800000L |
|---|
| 2145 | #define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x00000017 |
|---|
| 2146 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x00000002L |
|---|
| 2147 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x00000001 |
|---|
| 2148 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x00000001L |
|---|
| 2149 | #define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2150 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x00000010L |
|---|
| 2151 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x00000004 |
|---|
| 2152 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x00000080L |
|---|
| 2153 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x00000007 |
|---|
| 2154 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x00000020L |
|---|
| 2155 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x00000005 |
|---|
| 2156 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x00000040L |
|---|
| 2157 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x00000006 |
|---|
| 2158 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x00001000L |
|---|
| 2159 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0x0000000c |
|---|
| 2160 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x00008000L |
|---|
| 2161 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0x0000000f |
|---|
| 2162 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x00002000L |
|---|
| 2163 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0x0000000d |
|---|
| 2164 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x00004000L |
|---|
| 2165 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0x0000000e |
|---|
| 2166 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x00010000L |
|---|
| 2167 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x00000010 |
|---|
| 2168 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x00080000L |
|---|
| 2169 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x00000013 |
|---|
| 2170 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x00020000L |
|---|
| 2171 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x00000011 |
|---|
| 2172 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x00040000L |
|---|
| 2173 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x00000012 |
|---|
| 2174 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x00100000L |
|---|
| 2175 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x00000014 |
|---|
| 2176 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x00800000L |
|---|
| 2177 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x00000017 |
|---|
| 2178 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x00200000L |
|---|
| 2179 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x00000015 |
|---|
| 2180 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x00400000L |
|---|
| 2181 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x00000016 |
|---|
| 2182 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x00000100L |
|---|
| 2183 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x00000008 |
|---|
| 2184 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x00000800L |
|---|
| 2185 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0x0000000b |
|---|
| 2186 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x00000200L |
|---|
| 2187 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x00000009 |
|---|
| 2188 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x00000400L |
|---|
| 2189 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0x0000000a |
|---|
| 2190 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 2191 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 2192 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x00000008L |
|---|
| 2193 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 |
|---|
| 2194 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 2195 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 2196 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 2197 | #define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 2198 | #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0x000000ffL |
|---|
| 2199 | #define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x00000000 |
|---|
| 2200 | #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x00002000L |
|---|
| 2201 | #define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0x0000000d |
|---|
| 2202 | #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0x00000c00L |
|---|
| 2203 | #define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0x0000000a |
|---|
| 2204 | #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x00001000L |
|---|
| 2205 | #define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0x0000000c |
|---|
| 2206 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x00000008L |
|---|
| 2207 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x00000003 |
|---|
| 2208 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x00000080L |
|---|
| 2209 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x00000007 |
|---|
| 2210 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x00000100L |
|---|
| 2211 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x00000008 |
|---|
| 2212 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x00000200L |
|---|
| 2213 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x00000009 |
|---|
| 2214 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x00000070L |
|---|
| 2215 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x00000004 |
|---|
| 2216 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x00000007L |
|---|
| 2217 | #define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x00000000 |
|---|
| 2218 | #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0x000000ffL |
|---|
| 2219 | #define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x00000000 |
|---|
| 2220 | #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x00002000L |
|---|
| 2221 | #define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0x0000000d |
|---|
| 2222 | #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0x00000c00L |
|---|
| 2223 | #define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0x0000000a |
|---|
| 2224 | #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x00001000L |
|---|
| 2225 | #define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0x0000000c |
|---|
| 2226 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x00000008L |
|---|
| 2227 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x00000003 |
|---|
| 2228 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x00000080L |
|---|
| 2229 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x00000007 |
|---|
| 2230 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x00000100L |
|---|
| 2231 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x00000008 |
|---|
| 2232 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x00000200L |
|---|
| 2233 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x00000009 |
|---|
| 2234 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x00000070L |
|---|
| 2235 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x00000004 |
|---|
| 2236 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x00000007L |
|---|
| 2237 | #define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x00000000 |
|---|
| 2238 | #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0x000000ffL |
|---|
| 2239 | #define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x00000000 |
|---|
| 2240 | #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x00002000L |
|---|
| 2241 | #define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0x0000000d |
|---|
| 2242 | #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0x00000c00L |
|---|
| 2243 | #define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0x0000000a |
|---|
| 2244 | #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x00001000L |
|---|
| 2245 | #define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0x0000000c |
|---|
| 2246 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x00000008L |
|---|
| 2247 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x00000003 |
|---|
| 2248 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x00000080L |
|---|
| 2249 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x00000007 |
|---|
| 2250 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x00000100L |
|---|
| 2251 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x00000008 |
|---|
| 2252 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x00000200L |
|---|
| 2253 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x00000009 |
|---|
| 2254 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x00000070L |
|---|
| 2255 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x00000004 |
|---|
| 2256 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x00000007L |
|---|
| 2257 | #define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x00000000 |
|---|
| 2258 | #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0x000000ffL |
|---|
| 2259 | #define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x00000000 |
|---|
| 2260 | #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x00002000L |
|---|
| 2261 | #define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0x0000000d |
|---|
| 2262 | #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0x00000c00L |
|---|
| 2263 | #define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0x0000000a |
|---|
| 2264 | #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x00001000L |
|---|
| 2265 | #define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0x0000000c |
|---|
| 2266 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x00000008L |
|---|
| 2267 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x00000003 |
|---|
| 2268 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x00000080L |
|---|
| 2269 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x00000007 |
|---|
| 2270 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x00000100L |
|---|
| 2271 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x00000008 |
|---|
| 2272 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x00000200L |
|---|
| 2273 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x00000009 |
|---|
| 2274 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x00000070L |
|---|
| 2275 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x00000004 |
|---|
| 2276 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x00000007L |
|---|
| 2277 | #define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x00000000 |
|---|
| 2278 | #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0x000000ffL |
|---|
| 2279 | #define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x00000000 |
|---|
| 2280 | #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x00002000L |
|---|
| 2281 | #define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0x0000000d |
|---|
| 2282 | #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0x00000c00L |
|---|
| 2283 | #define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0x0000000a |
|---|
| 2284 | #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x00001000L |
|---|
| 2285 | #define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0x0000000c |
|---|
| 2286 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x00000008L |
|---|
| 2287 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x00000003 |
|---|
| 2288 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x00000080L |
|---|
| 2289 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x00000007 |
|---|
| 2290 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x00000100L |
|---|
| 2291 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x00000008 |
|---|
| 2292 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x00000200L |
|---|
| 2293 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x00000009 |
|---|
| 2294 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x00000070L |
|---|
| 2295 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x00000004 |
|---|
| 2296 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x00000007L |
|---|
| 2297 | #define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x00000000 |
|---|
| 2298 | #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0x000000ffL |
|---|
| 2299 | #define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x00000000 |
|---|
| 2300 | #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x00002000L |
|---|
| 2301 | #define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0x0000000d |
|---|
| 2302 | #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0x00000c00L |
|---|
| 2303 | #define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0x0000000a |
|---|
| 2304 | #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x00001000L |
|---|
| 2305 | #define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0x0000000c |
|---|
| 2306 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x00000008L |
|---|
| 2307 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x00000003 |
|---|
| 2308 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x00000080L |
|---|
| 2309 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x00000007 |
|---|
| 2310 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x00000100L |
|---|
| 2311 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x00000008 |
|---|
| 2312 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x00000200L |
|---|
| 2313 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x00000009 |
|---|
| 2314 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x00000070L |
|---|
| 2315 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x00000004 |
|---|
| 2316 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x00000007L |
|---|
| 2317 | #define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x00000000 |
|---|
| 2318 | #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0x000000ffL |
|---|
| 2319 | #define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x00000000 |
|---|
| 2320 | #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x00002000L |
|---|
| 2321 | #define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0x0000000d |
|---|
| 2322 | #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0x00000c00L |
|---|
| 2323 | #define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0x0000000a |
|---|
| 2324 | #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x00001000L |
|---|
| 2325 | #define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0x0000000c |
|---|
| 2326 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x00000008L |
|---|
| 2327 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x00000003 |
|---|
| 2328 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x00000080L |
|---|
| 2329 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x00000007 |
|---|
| 2330 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x00000100L |
|---|
| 2331 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x00000008 |
|---|
| 2332 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x00000200L |
|---|
| 2333 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x00000009 |
|---|
| 2334 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x00000070L |
|---|
| 2335 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x00000004 |
|---|
| 2336 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x00000007L |
|---|
| 2337 | #define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x00000000 |
|---|
| 2338 | #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0x000000ffL |
|---|
| 2339 | #define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x00000000 |
|---|
| 2340 | #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x00002000L |
|---|
| 2341 | #define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0x0000000d |
|---|
| 2342 | #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0x00000c00L |
|---|
| 2343 | #define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0x0000000a |
|---|
| 2344 | #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x00001000L |
|---|
| 2345 | #define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0x0000000c |
|---|
| 2346 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x00000008L |
|---|
| 2347 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x00000003 |
|---|
| 2348 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x00000080L |
|---|
| 2349 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x00000007 |
|---|
| 2350 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x00000100L |
|---|
| 2351 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x00000008 |
|---|
| 2352 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x00000200L |
|---|
| 2353 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x00000009 |
|---|
| 2354 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x00000070L |
|---|
| 2355 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x00000004 |
|---|
| 2356 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x00000007L |
|---|
| 2357 | #define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x00000000 |
|---|
| 2358 | #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0x000000ffL |
|---|
| 2359 | #define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x00000000 |
|---|
| 2360 | #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x00002000L |
|---|
| 2361 | #define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0x0000000d |
|---|
| 2362 | #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0x00000c00L |
|---|
| 2363 | #define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0x0000000a |
|---|
| 2364 | #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x00001000L |
|---|
| 2365 | #define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0x0000000c |
|---|
| 2366 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x00000008L |
|---|
| 2367 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x00000003 |
|---|
| 2368 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x00000080L |
|---|
| 2369 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x00000007 |
|---|
| 2370 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x00000100L |
|---|
| 2371 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x00000008 |
|---|
| 2372 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x00000200L |
|---|
| 2373 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x00000009 |
|---|
| 2374 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x00000070L |
|---|
| 2375 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x00000004 |
|---|
| 2376 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x00000007L |
|---|
| 2377 | #define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x00000000 |
|---|
| 2378 | #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0x000000ffL |
|---|
| 2379 | #define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x00000000 |
|---|
| 2380 | #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x00002000L |
|---|
| 2381 | #define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0x0000000d |
|---|
| 2382 | #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0x00000c00L |
|---|
| 2383 | #define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0x0000000a |
|---|
| 2384 | #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x00001000L |
|---|
| 2385 | #define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0x0000000c |
|---|
| 2386 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x00000008L |
|---|
| 2387 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x00000003 |
|---|
| 2388 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x00000080L |
|---|
| 2389 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x00000007 |
|---|
| 2390 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x00000100L |
|---|
| 2391 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x00000008 |
|---|
| 2392 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x00000200L |
|---|
| 2393 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x00000009 |
|---|
| 2394 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x00000070L |
|---|
| 2395 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x00000004 |
|---|
| 2396 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x00000007L |
|---|
| 2397 | #define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x00000000 |
|---|
| 2398 | #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0x000000ffL |
|---|
| 2399 | #define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x00000000 |
|---|
| 2400 | #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x00002000L |
|---|
| 2401 | #define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0x0000000d |
|---|
| 2402 | #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0x00000c00L |
|---|
| 2403 | #define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0x0000000a |
|---|
| 2404 | #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x00001000L |
|---|
| 2405 | #define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0x0000000c |
|---|
| 2406 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x00000008L |
|---|
| 2407 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x00000003 |
|---|
| 2408 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x00000080L |
|---|
| 2409 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x00000007 |
|---|
| 2410 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x00000100L |
|---|
| 2411 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x00000008 |
|---|
| 2412 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x00000200L |
|---|
| 2413 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x00000009 |
|---|
| 2414 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x00000070L |
|---|
| 2415 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x00000004 |
|---|
| 2416 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x00000007L |
|---|
| 2417 | #define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x00000000 |
|---|
| 2418 | #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0x000000ffL |
|---|
| 2419 | #define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x00000000 |
|---|
| 2420 | #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x00002000L |
|---|
| 2421 | #define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0x0000000d |
|---|
| 2422 | #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0x00000c00L |
|---|
| 2423 | #define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0x0000000a |
|---|
| 2424 | #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x00001000L |
|---|
| 2425 | #define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0x0000000c |
|---|
| 2426 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x00000008L |
|---|
| 2427 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x00000003 |
|---|
| 2428 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x00000080L |
|---|
| 2429 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x00000007 |
|---|
| 2430 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x00000100L |
|---|
| 2431 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x00000008 |
|---|
| 2432 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x00000200L |
|---|
| 2433 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x00000009 |
|---|
| 2434 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x00000070L |
|---|
| 2435 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x00000004 |
|---|
| 2436 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x00000007L |
|---|
| 2437 | #define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x00000000 |
|---|
| 2438 | #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0x000000ffL |
|---|
| 2439 | #define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x00000000 |
|---|
| 2440 | #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x00002000L |
|---|
| 2441 | #define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0x0000000d |
|---|
| 2442 | #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0x00000c00L |
|---|
| 2443 | #define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0x0000000a |
|---|
| 2444 | #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x00001000L |
|---|
| 2445 | #define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0x0000000c |
|---|
| 2446 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x00000008L |
|---|
| 2447 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x00000003 |
|---|
| 2448 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x00000080L |
|---|
| 2449 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x00000007 |
|---|
| 2450 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x00000100L |
|---|
| 2451 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x00000008 |
|---|
| 2452 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x00000200L |
|---|
| 2453 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x00000009 |
|---|
| 2454 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x00000070L |
|---|
| 2455 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x00000004 |
|---|
| 2456 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x00000007L |
|---|
| 2457 | #define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x00000000 |
|---|
| 2458 | #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0x000000ffL |
|---|
| 2459 | #define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x00000000 |
|---|
| 2460 | #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x00002000L |
|---|
| 2461 | #define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0x0000000d |
|---|
| 2462 | #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0x00000c00L |
|---|
| 2463 | #define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0x0000000a |
|---|
| 2464 | #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x00001000L |
|---|
| 2465 | #define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0x0000000c |
|---|
| 2466 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x00000008L |
|---|
| 2467 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x00000003 |
|---|
| 2468 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x00000080L |
|---|
| 2469 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x00000007 |
|---|
| 2470 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x00000100L |
|---|
| 2471 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x00000008 |
|---|
| 2472 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x00000200L |
|---|
| 2473 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x00000009 |
|---|
| 2474 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x00000070L |
|---|
| 2475 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x00000004 |
|---|
| 2476 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x00000007L |
|---|
| 2477 | #define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x00000000 |
|---|
| 2478 | #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0x000000ffL |
|---|
| 2479 | #define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x00000000 |
|---|
| 2480 | #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x00002000L |
|---|
| 2481 | #define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0x0000000d |
|---|
| 2482 | #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0x00000c00L |
|---|
| 2483 | #define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0x0000000a |
|---|
| 2484 | #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x00001000L |
|---|
| 2485 | #define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0x0000000c |
|---|
| 2486 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x00000008L |
|---|
| 2487 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x00000003 |
|---|
| 2488 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x00000080L |
|---|
| 2489 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x00000007 |
|---|
| 2490 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x00000100L |
|---|
| 2491 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x00000008 |
|---|
| 2492 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x00000200L |
|---|
| 2493 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x00000009 |
|---|
| 2494 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x00000070L |
|---|
| 2495 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x00000004 |
|---|
| 2496 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x00000007L |
|---|
| 2497 | #define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x00000000 |
|---|
| 2498 | #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0x000000ffL |
|---|
| 2499 | #define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x00000000 |
|---|
| 2500 | #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x00002000L |
|---|
| 2501 | #define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0x0000000d |
|---|
| 2502 | #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0x00000c00L |
|---|
| 2503 | #define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0x0000000a |
|---|
| 2504 | #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x00001000L |
|---|
| 2505 | #define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0x0000000c |
|---|
| 2506 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x00000008L |
|---|
| 2507 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x00000003 |
|---|
| 2508 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x00000080L |
|---|
| 2509 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x00000007 |
|---|
| 2510 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x00000100L |
|---|
| 2511 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x00000008 |
|---|
| 2512 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x00000200L |
|---|
| 2513 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x00000009 |
|---|
| 2514 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x00000070L |
|---|
| 2515 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x00000004 |
|---|
| 2516 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x00000007L |
|---|
| 2517 | #define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x00000000 |
|---|
| 2518 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x00008000L |
|---|
| 2519 | #define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000000f |
|---|
| 2520 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x00000001L |
|---|
| 2521 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x00000000 |
|---|
| 2522 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x00000400L |
|---|
| 2523 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0x0000000a |
|---|
| 2524 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x00000800L |
|---|
| 2525 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0x0000000b |
|---|
| 2526 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x00001000L |
|---|
| 2527 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0x0000000c |
|---|
| 2528 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x00002000L |
|---|
| 2529 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0x0000000d |
|---|
| 2530 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x00004000L |
|---|
| 2531 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0x0000000e |
|---|
| 2532 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x00008000L |
|---|
| 2533 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0x0000000f |
|---|
| 2534 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x00010000L |
|---|
| 2535 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x00000010 |
|---|
| 2536 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x00020000L |
|---|
| 2537 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x00000011 |
|---|
| 2538 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x00040000L |
|---|
| 2539 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x00000012 |
|---|
| 2540 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x00080000L |
|---|
| 2541 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x00000013 |
|---|
| 2542 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x00000002L |
|---|
| 2543 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x00000001 |
|---|
| 2544 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x00100000L |
|---|
| 2545 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x00000014 |
|---|
| 2546 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x00200000L |
|---|
| 2547 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x00000015 |
|---|
| 2548 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x00400000L |
|---|
| 2549 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x00000016 |
|---|
| 2550 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x00800000L |
|---|
| 2551 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x00000017 |
|---|
| 2552 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x01000000L |
|---|
| 2553 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x00000018 |
|---|
| 2554 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x02000000L |
|---|
| 2555 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x00000019 |
|---|
| 2556 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x04000000L |
|---|
| 2557 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x0000001a |
|---|
| 2558 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x08000000L |
|---|
| 2559 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x0000001b |
|---|
| 2560 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000L |
|---|
| 2561 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x0000001c |
|---|
| 2562 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000L |
|---|
| 2563 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x0000001d |
|---|
| 2564 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x00000004L |
|---|
| 2565 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x00000002 |
|---|
| 2566 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000L |
|---|
| 2567 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x0000001e |
|---|
| 2568 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000L |
|---|
| 2569 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x0000001f |
|---|
| 2570 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x00000008L |
|---|
| 2571 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x00000003 |
|---|
| 2572 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x00000010L |
|---|
| 2573 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x00000004 |
|---|
| 2574 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x00000020L |
|---|
| 2575 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x00000005 |
|---|
| 2576 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x00000040L |
|---|
| 2577 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x00000006 |
|---|
| 2578 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x00000080L |
|---|
| 2579 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x00000007 |
|---|
| 2580 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x00000100L |
|---|
| 2581 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x00000008 |
|---|
| 2582 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x00000200L |
|---|
| 2583 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x00000009 |
|---|
| 2584 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x00000001L |
|---|
| 2585 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x00000000 |
|---|
| 2586 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x00000002L |
|---|
| 2587 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x00000001 |
|---|
| 2588 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x00000004L |
|---|
| 2589 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x00000002 |
|---|
| 2590 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x00000008L |
|---|
| 2591 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x00000003 |
|---|
| 2592 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x00000010L |
|---|
| 2593 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x00000004 |
|---|
| 2594 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x00000020L |
|---|
| 2595 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x00000005 |
|---|
| 2596 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x00000040L |
|---|
| 2597 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x00000006 |
|---|
| 2598 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x00000080L |
|---|
| 2599 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x00000007 |
|---|
| 2600 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x00000100L |
|---|
| 2601 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x00000008 |
|---|
| 2602 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x00000200L |
|---|
| 2603 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x00000009 |
|---|
| 2604 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x00000400L |
|---|
| 2605 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0x0000000a |
|---|
| 2606 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x00000800L |
|---|
| 2607 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0x0000000b |
|---|
| 2608 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x00001000L |
|---|
| 2609 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0x0000000c |
|---|
| 2610 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x00002000L |
|---|
| 2611 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0x0000000d |
|---|
| 2612 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x00004000L |
|---|
| 2613 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0x0000000e |
|---|
| 2614 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x00008000L |
|---|
| 2615 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0x0000000f |
|---|
| 2616 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x00010000L |
|---|
| 2617 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x00000010 |
|---|
| 2618 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x00020000L |
|---|
| 2619 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x00000011 |
|---|
| 2620 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x00040000L |
|---|
| 2621 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x00000012 |
|---|
| 2622 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x00080000L |
|---|
| 2623 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x00000013 |
|---|
| 2624 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x00100000L |
|---|
| 2625 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x00000014 |
|---|
| 2626 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x00200000L |
|---|
| 2627 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x00000015 |
|---|
| 2628 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x00400000L |
|---|
| 2629 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x00000016 |
|---|
| 2630 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x00800000L |
|---|
| 2631 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x00000017 |
|---|
| 2632 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x01000000L |
|---|
| 2633 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x00000018 |
|---|
| 2634 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x02000000L |
|---|
| 2635 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x00000019 |
|---|
| 2636 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x04000000L |
|---|
| 2637 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x0000001a |
|---|
| 2638 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x08000000L |
|---|
| 2639 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x0000001b |
|---|
| 2640 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000L |
|---|
| 2641 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x0000001c |
|---|
| 2642 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000L |
|---|
| 2643 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x0000001d |
|---|
| 2644 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000L |
|---|
| 2645 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x0000001e |
|---|
| 2646 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000L |
|---|
| 2647 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x0000001f |
|---|
| 2648 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x00000001L |
|---|
| 2649 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x00000000 |
|---|
| 2650 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x00000002L |
|---|
| 2651 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x00000001 |
|---|
| 2652 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x00000004L |
|---|
| 2653 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x00000002 |
|---|
| 2654 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x00000008L |
|---|
| 2655 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x00000003 |
|---|
| 2656 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x00000010L |
|---|
| 2657 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x00000004 |
|---|
| 2658 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x00000020L |
|---|
| 2659 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x00000005 |
|---|
| 2660 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x00000040L |
|---|
| 2661 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x00000006 |
|---|
| 2662 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x00000080L |
|---|
| 2663 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x00000007 |
|---|
| 2664 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x00000100L |
|---|
| 2665 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x00000008 |
|---|
| 2666 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x00000200L |
|---|
| 2667 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x00000009 |
|---|
| 2668 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x00000400L |
|---|
| 2669 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0x0000000a |
|---|
| 2670 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x00000800L |
|---|
| 2671 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0x0000000b |
|---|
| 2672 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x00001000L |
|---|
| 2673 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0x0000000c |
|---|
| 2674 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x00002000L |
|---|
| 2675 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0x0000000d |
|---|
| 2676 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x00004000L |
|---|
| 2677 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0x0000000e |
|---|
| 2678 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x00008000L |
|---|
| 2679 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0x0000000f |
|---|
| 2680 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x00010000L |
|---|
| 2681 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x00000010 |
|---|
| 2682 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x00020000L |
|---|
| 2683 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x00000011 |
|---|
| 2684 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x00040000L |
|---|
| 2685 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x00000012 |
|---|
| 2686 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x00080000L |
|---|
| 2687 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x00000013 |
|---|
| 2688 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x00100000L |
|---|
| 2689 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x00000014 |
|---|
| 2690 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x00200000L |
|---|
| 2691 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x00000015 |
|---|
| 2692 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x00400000L |
|---|
| 2693 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x00000016 |
|---|
| 2694 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x00800000L |
|---|
| 2695 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x00000017 |
|---|
| 2696 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x01000000L |
|---|
| 2697 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x00000018 |
|---|
| 2698 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x02000000L |
|---|
| 2699 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x00000019 |
|---|
| 2700 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x04000000L |
|---|
| 2701 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x0000001a |
|---|
| 2702 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x08000000L |
|---|
| 2703 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x0000001b |
|---|
| 2704 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000L |
|---|
| 2705 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x0000001c |
|---|
| 2706 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000L |
|---|
| 2707 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x0000001d |
|---|
| 2708 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000L |
|---|
| 2709 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x0000001e |
|---|
| 2710 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000L |
|---|
| 2711 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x0000001f |
|---|
| 2712 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x00000010L |
|---|
| 2713 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x00000004 |
|---|
| 2714 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x00000020L |
|---|
| 2715 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x00000005 |
|---|
| 2716 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x00000040L |
|---|
| 2717 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x00000006 |
|---|
| 2718 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x00000080L |
|---|
| 2719 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x00000007 |
|---|
| 2720 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x00000100L |
|---|
| 2721 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x00000008 |
|---|
| 2722 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x00000200L |
|---|
| 2723 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x00000009 |
|---|
| 2724 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x00000400L |
|---|
| 2725 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0x0000000a |
|---|
| 2726 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x00000800L |
|---|
| 2727 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0x0000000b |
|---|
| 2728 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x00001000L |
|---|
| 2729 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0x0000000c |
|---|
| 2730 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x00002000L |
|---|
| 2731 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0x0000000d |
|---|
| 2732 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x00000001L |
|---|
| 2733 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x00000000 |
|---|
| 2734 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x00000002L |
|---|
| 2735 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x00000001 |
|---|
| 2736 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x00000004L |
|---|
| 2737 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x00000002 |
|---|
| 2738 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x00000008L |
|---|
| 2739 | #define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x00000003 |
|---|
| 2740 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x00000700L |
|---|
| 2741 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x00000008 |
|---|
| 2742 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x00003800L |
|---|
| 2743 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0x0000000b |
|---|
| 2744 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x0001c000L |
|---|
| 2745 | #define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0x0000000e |
|---|
| 2746 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x00400000L |
|---|
| 2747 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x00000016 |
|---|
| 2748 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x00200000L |
|---|
| 2749 | #define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x00000015 |
|---|
| 2750 | #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x00080000L |
|---|
| 2751 | #define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x00000013 |
|---|
| 2752 | #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x00800000L |
|---|
| 2753 | #define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x00000017 |
|---|
| 2754 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x00000007L |
|---|
| 2755 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x00000000 |
|---|
| 2756 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x00000038L |
|---|
| 2757 | #define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x00000003 |
|---|
| 2758 | #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x01000000L |
|---|
| 2759 | #define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x00000018 |
|---|
| 2760 | #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x00100000L |
|---|
| 2761 | #define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x00000014 |
|---|
| 2762 | #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x00060000L |
|---|
| 2763 | #define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x00000011 |
|---|
| 2764 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000L |
|---|
| 2765 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x0000001e |
|---|
| 2766 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x00000001L |
|---|
| 2767 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x00000000 |
|---|
| 2768 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x00000400L |
|---|
| 2769 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0x0000000a |
|---|
| 2770 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x00000800L |
|---|
| 2771 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0x0000000b |
|---|
| 2772 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x00001000L |
|---|
| 2773 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0x0000000c |
|---|
| 2774 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x00002000L |
|---|
| 2775 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0x0000000d |
|---|
| 2776 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x00004000L |
|---|
| 2777 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0x0000000e |
|---|
| 2778 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x00008000L |
|---|
| 2779 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0x0000000f |
|---|
| 2780 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x00000002L |
|---|
| 2781 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x00000001 |
|---|
| 2782 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x00000004L |
|---|
| 2783 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x00000002 |
|---|
| 2784 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x00000008L |
|---|
| 2785 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x00000003 |
|---|
| 2786 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x00000010L |
|---|
| 2787 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x00000004 |
|---|
| 2788 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x00000020L |
|---|
| 2789 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x00000005 |
|---|
| 2790 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x00000040L |
|---|
| 2791 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x00000006 |
|---|
| 2792 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x00000080L |
|---|
| 2793 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x00000007 |
|---|
| 2794 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x00000100L |
|---|
| 2795 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x00000008 |
|---|
| 2796 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x00000200L |
|---|
| 2797 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x00000009 |
|---|
| 2798 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x00010000L |
|---|
| 2799 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x00000010 |
|---|
| 2800 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x00200000L |
|---|
| 2801 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x00000015 |
|---|
| 2802 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x00400000L |
|---|
| 2803 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x00000016 |
|---|
| 2804 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x00800000L |
|---|
| 2805 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x00000017 |
|---|
| 2806 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x00020000L |
|---|
| 2807 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x00000011 |
|---|
| 2808 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x00040000L |
|---|
| 2809 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x00000012 |
|---|
| 2810 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x00080000L |
|---|
| 2811 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x00000013 |
|---|
| 2812 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x00100000L |
|---|
| 2813 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x00000014 |
|---|
| 2814 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x01000000L |
|---|
| 2815 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x00000018 |
|---|
| 2816 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x08000000L |
|---|
| 2817 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x0000001b |
|---|
| 2818 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x02000000L |
|---|
| 2819 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x00000019 |
|---|
| 2820 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x04000000L |
|---|
| 2821 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x0000001a |
|---|
| 2822 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000L |
|---|
| 2823 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x0000001c |
|---|
| 2824 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000L |
|---|
| 2825 | #define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x0000001d |
|---|
| 2826 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x00000008L |
|---|
| 2827 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x00000003 |
|---|
| 2828 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x00000007L |
|---|
| 2829 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2830 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0x000000f0L |
|---|
| 2831 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x00000004 |
|---|
| 2832 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x00000100L |
|---|
| 2833 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x00000008 |
|---|
| 2834 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00001e00L |
|---|
| 2835 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000009 |
|---|
| 2836 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x00002000L |
|---|
| 2837 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0x0000000d |
|---|
| 2838 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x0007c000L |
|---|
| 2839 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0x0000000e |
|---|
| 2840 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x00080000L |
|---|
| 2841 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x00000013 |
|---|
| 2842 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x01f00000L |
|---|
| 2843 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000014 |
|---|
| 2844 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x02000000L |
|---|
| 2845 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x00000019 |
|---|
| 2846 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000L |
|---|
| 2847 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x0000001a |
|---|
| 2848 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000L |
|---|
| 2849 | #define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x0000001e |
|---|
| 2850 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0x0000000fL |
|---|
| 2851 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2852 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x00000010L |
|---|
| 2853 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x00000004 |
|---|
| 2854 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x00000020L |
|---|
| 2855 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x00000005 |
|---|
| 2856 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x00000040L |
|---|
| 2857 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x00000006 |
|---|
| 2858 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x00000080L |
|---|
| 2859 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x00000007 |
|---|
| 2860 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x00000100L |
|---|
| 2861 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x00000008 |
|---|
| 2862 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x00000400L |
|---|
| 2863 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0x0000000a |
|---|
| 2864 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x00000200L |
|---|
| 2865 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x00000009 |
|---|
| 2866 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L |
|---|
| 2867 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0x0000000c |
|---|
| 2868 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x00000800L |
|---|
| 2869 | #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0x0000000b |
|---|
| 2870 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x00004000L |
|---|
| 2871 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0x0000000e |
|---|
| 2872 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x00002000L |
|---|
| 2873 | #define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0x0000000d |
|---|
| 2874 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x02000000L |
|---|
| 2875 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x00000019 |
|---|
| 2876 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x01ff8000L |
|---|
| 2877 | #define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0x0000000f |
|---|
| 2878 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x08000000L |
|---|
| 2879 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x0000001b |
|---|
| 2880 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x04000000L |
|---|
| 2881 | #define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x0000001a |
|---|
| 2882 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000L |
|---|
| 2883 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x0000001d |
|---|
| 2884 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000L |
|---|
| 2885 | #define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x0000001c |
|---|
| 2886 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000L |
|---|
| 2887 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x0000001f |
|---|
| 2888 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000L |
|---|
| 2889 | #define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x0000001e |
|---|
| 2890 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0x0000f000L |
|---|
| 2891 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0x0000000c |
|---|
| 2892 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000f0000L |
|---|
| 2893 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000010 |
|---|
| 2894 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x01f00000L |
|---|
| 2895 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x00000014 |
|---|
| 2896 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000L |
|---|
| 2897 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000019 |
|---|
| 2898 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x00000800L |
|---|
| 2899 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0x0000000b |
|---|
| 2900 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x00000400L |
|---|
| 2901 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0x0000000a |
|---|
| 2902 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x00000008L |
|---|
| 2903 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x00000003 |
|---|
| 2904 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x00000004L |
|---|
| 2905 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x00000002 |
|---|
| 2906 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x00000020L |
|---|
| 2907 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x00000005 |
|---|
| 2908 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x00000010L |
|---|
| 2909 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x00000004 |
|---|
| 2910 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x00000080L |
|---|
| 2911 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x00000007 |
|---|
| 2912 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x00000040L |
|---|
| 2913 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x00000006 |
|---|
| 2914 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x00000200L |
|---|
| 2915 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x00000009 |
|---|
| 2916 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x00000100L |
|---|
| 2917 | #define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x00000008 |
|---|
| 2918 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x00000002L |
|---|
| 2919 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x00000001 |
|---|
| 2920 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x00000001L |
|---|
| 2921 | #define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2922 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x00003c00L |
|---|
| 2923 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0x0000000a |
|---|
| 2924 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0003c000L |
|---|
| 2925 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0000000e |
|---|
| 2926 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x007c0000L |
|---|
| 2927 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x00000012 |
|---|
| 2928 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0f800000L |
|---|
| 2929 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000017 |
|---|
| 2930 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0x0000000fL |
|---|
| 2931 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2932 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000L |
|---|
| 2933 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x0000001c |
|---|
| 2934 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0x000000f0L |
|---|
| 2935 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000004 |
|---|
| 2936 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x00000100L |
|---|
| 2937 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x00000008 |
|---|
| 2938 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x00000200L |
|---|
| 2939 | #define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x00000009 |
|---|
| 2940 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0x0000000fL |
|---|
| 2941 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 2942 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x00000010L |
|---|
| 2943 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x00000004 |
|---|
| 2944 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x00000020L |
|---|
| 2945 | #define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x00000005 |
|---|
| 2946 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x00000100L |
|---|
| 2947 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x00000008 |
|---|
| 2948 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x00000800L |
|---|
| 2949 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0x0000000b |
|---|
| 2950 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x00000200L |
|---|
| 2951 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x00000009 |
|---|
| 2952 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x00000400L |
|---|
| 2953 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0x0000000a |
|---|
| 2954 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x00001000L |
|---|
| 2955 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0x0000000c |
|---|
| 2956 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x00008000L |
|---|
| 2957 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0x0000000f |
|---|
| 2958 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x00002000L |
|---|
| 2959 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0x0000000d |
|---|
| 2960 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x00004000L |
|---|
| 2961 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0x0000000e |
|---|
| 2962 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x00000010L |
|---|
| 2963 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x00000004 |
|---|
| 2964 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x00000080L |
|---|
| 2965 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x00000007 |
|---|
| 2966 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x00000020L |
|---|
| 2967 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x00000005 |
|---|
| 2968 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x00000040L |
|---|
| 2969 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x00000006 |
|---|
| 2970 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 2971 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 2972 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x00000008L |
|---|
| 2973 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x00000003 |
|---|
| 2974 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 2975 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 2976 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 2977 | #define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 2978 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x00000001L |
|---|
| 2979 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x00000000 |
|---|
| 2980 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x00000002L |
|---|
| 2981 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x00000001 |
|---|
| 2982 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x00000004L |
|---|
| 2983 | #define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x00000002 |
|---|
| 2984 | #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x00000008L |
|---|
| 2985 | #define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x00000003 |
|---|
| 2986 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x00000002L |
|---|
| 2987 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x00000001 |
|---|
| 2988 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x00000001L |
|---|
| 2989 | #define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x00000000 |
|---|
| 2990 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x00000008L |
|---|
| 2991 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x00000003 |
|---|
| 2992 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x00000004L |
|---|
| 2993 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x00000002 |
|---|
| 2994 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x00000020L |
|---|
| 2995 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x00000005 |
|---|
| 2996 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x00000010L |
|---|
| 2997 | #define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x00000004 |
|---|
| 2998 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x00000080L |
|---|
| 2999 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x00000007 |
|---|
| 3000 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x00000040L |
|---|
| 3001 | #define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x00000006 |
|---|
| 3002 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0x0000fc00L |
|---|
| 3003 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0x0000000a |
|---|
| 3004 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x00000300L |
|---|
| 3005 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x00000008 |
|---|
| 3006 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x00000080L |
|---|
| 3007 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x00000007 |
|---|
| 3008 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x00000008L |
|---|
| 3009 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x00000003 |
|---|
| 3010 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x00000070L |
|---|
| 3011 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x00000004 |
|---|
| 3012 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x00000007L |
|---|
| 3013 | #define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x00000000 |
|---|
| 3014 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x00000001L |
|---|
| 3015 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x00000000 |
|---|
| 3016 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x00000002L |
|---|
| 3017 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x00000001 |
|---|
| 3018 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x00000004L |
|---|
| 3019 | #define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x00000002 |
|---|
| 3020 | #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x00000008L |
|---|
| 3021 | #define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x00000003 |
|---|
| 3022 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x00000002L |
|---|
| 3023 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x00000001 |
|---|
| 3024 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x00000001L |
|---|
| 3025 | #define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x00000000 |
|---|
| 3026 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x00000008L |
|---|
| 3027 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x00000003 |
|---|
| 3028 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x00000004L |
|---|
| 3029 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x00000002 |
|---|
| 3030 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x00000020L |
|---|
| 3031 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x00000005 |
|---|
| 3032 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x00000010L |
|---|
| 3033 | #define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x00000004 |
|---|
| 3034 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x00000080L |
|---|
| 3035 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x00000007 |
|---|
| 3036 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x00000040L |
|---|
| 3037 | #define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x00000006 |
|---|
| 3038 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0x0000fc00L |
|---|
| 3039 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0x0000000a |
|---|
| 3040 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x00000300L |
|---|
| 3041 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x00000008 |
|---|
| 3042 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x00000080L |
|---|
| 3043 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x00000007 |
|---|
| 3044 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x00000008L |
|---|
| 3045 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x00000003 |
|---|
| 3046 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x00000070L |
|---|
| 3047 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x00000004 |
|---|
| 3048 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x00000007L |
|---|
| 3049 | #define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x00000000 |
|---|
| 3050 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x00000001L |
|---|
| 3051 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x00000000 |
|---|
| 3052 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x00000002L |
|---|
| 3053 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x00000001 |
|---|
| 3054 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x00000004L |
|---|
| 3055 | #define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x00000002 |
|---|
| 3056 | #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x00000008L |
|---|
| 3057 | #define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x00000003 |
|---|
| 3058 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x00000002L |
|---|
| 3059 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x00000001 |
|---|
| 3060 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x00000001L |
|---|
| 3061 | #define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x00000000 |
|---|
| 3062 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x00000008L |
|---|
| 3063 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x00000003 |
|---|
| 3064 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x00000004L |
|---|
| 3065 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x00000002 |
|---|
| 3066 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x00000020L |
|---|
| 3067 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x00000005 |
|---|
| 3068 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x00000010L |
|---|
| 3069 | #define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x00000004 |
|---|
| 3070 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x00000080L |
|---|
| 3071 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x00000007 |
|---|
| 3072 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x00000040L |
|---|
| 3073 | #define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x00000006 |
|---|
| 3074 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0x0000fc00L |
|---|
| 3075 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0x0000000a |
|---|
| 3076 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x00000300L |
|---|
| 3077 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x00000008 |
|---|
| 3078 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x00000080L |
|---|
| 3079 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x00000007 |
|---|
| 3080 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x00000008L |
|---|
| 3081 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x00000003 |
|---|
| 3082 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x00000070L |
|---|
| 3083 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x00000004 |
|---|
| 3084 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x00000007L |
|---|
| 3085 | #define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x00000000 |
|---|
| 3086 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x00000001L |
|---|
| 3087 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x00000000 |
|---|
| 3088 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x00000002L |
|---|
| 3089 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x00000001 |
|---|
| 3090 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x00000004L |
|---|
| 3091 | #define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x00000002 |
|---|
| 3092 | #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x00000008L |
|---|
| 3093 | #define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x00000003 |
|---|
| 3094 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x00000002L |
|---|
| 3095 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x00000001 |
|---|
| 3096 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x00000001L |
|---|
| 3097 | #define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x00000000 |
|---|
| 3098 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x00000008L |
|---|
| 3099 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x00000003 |
|---|
| 3100 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x00000004L |
|---|
| 3101 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x00000002 |
|---|
| 3102 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x00000020L |
|---|
| 3103 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x00000005 |
|---|
| 3104 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x00000010L |
|---|
| 3105 | #define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x00000004 |
|---|
| 3106 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x00000080L |
|---|
| 3107 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x00000007 |
|---|
| 3108 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x00000040L |
|---|
| 3109 | #define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x00000006 |
|---|
| 3110 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0x0000fc00L |
|---|
| 3111 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0x0000000a |
|---|
| 3112 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x00000300L |
|---|
| 3113 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x00000008 |
|---|
| 3114 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x00000080L |
|---|
| 3115 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x00000007 |
|---|
| 3116 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x00000008L |
|---|
| 3117 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x00000003 |
|---|
| 3118 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x00000070L |
|---|
| 3119 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x00000004 |
|---|
| 3120 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x00000007L |
|---|
| 3121 | #define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x00000000 |
|---|
| 3122 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x00000001L |
|---|
| 3123 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x00000000 |
|---|
| 3124 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x00000002L |
|---|
| 3125 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x00000001 |
|---|
| 3126 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x00000004L |
|---|
| 3127 | #define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x00000002 |
|---|
| 3128 | #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x00000008L |
|---|
| 3129 | #define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x00000003 |
|---|
| 3130 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x00000002L |
|---|
| 3131 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x00000001 |
|---|
| 3132 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x00000001L |
|---|
| 3133 | #define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x00000000 |
|---|
| 3134 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x00000008L |
|---|
| 3135 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x00000003 |
|---|
| 3136 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x00000004L |
|---|
| 3137 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x00000002 |
|---|
| 3138 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x00000020L |
|---|
| 3139 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x00000005 |
|---|
| 3140 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x00000010L |
|---|
| 3141 | #define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x00000004 |
|---|
| 3142 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x00000080L |
|---|
| 3143 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x00000007 |
|---|
| 3144 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x00000040L |
|---|
| 3145 | #define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x00000006 |
|---|
| 3146 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0x0000fc00L |
|---|
| 3147 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0x0000000a |
|---|
| 3148 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x00000300L |
|---|
| 3149 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x00000008 |
|---|
| 3150 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x00000080L |
|---|
| 3151 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x00000007 |
|---|
| 3152 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x00000008L |
|---|
| 3153 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x00000003 |
|---|
| 3154 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x00000070L |
|---|
| 3155 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x00000004 |
|---|
| 3156 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x00000007L |
|---|
| 3157 | #define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x00000000 |
|---|
| 3158 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x00000001L |
|---|
| 3159 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x00000000 |
|---|
| 3160 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x00000002L |
|---|
| 3161 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x00000001 |
|---|
| 3162 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x00000004L |
|---|
| 3163 | #define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x00000002 |
|---|
| 3164 | #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x00000008L |
|---|
| 3165 | #define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x00000003 |
|---|
| 3166 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x00000002L |
|---|
| 3167 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x00000001 |
|---|
| 3168 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x00000001L |
|---|
| 3169 | #define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x00000000 |
|---|
| 3170 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x00000008L |
|---|
| 3171 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x00000003 |
|---|
| 3172 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x00000004L |
|---|
| 3173 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x00000002 |
|---|
| 3174 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x00000020L |
|---|
| 3175 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x00000005 |
|---|
| 3176 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x00000010L |
|---|
| 3177 | #define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x00000004 |
|---|
| 3178 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x00000080L |
|---|
| 3179 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x00000007 |
|---|
| 3180 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x00000040L |
|---|
| 3181 | #define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x00000006 |
|---|
| 3182 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0x0000fc00L |
|---|
| 3183 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0x0000000a |
|---|
| 3184 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x00000300L |
|---|
| 3185 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x00000008 |
|---|
| 3186 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x00000080L |
|---|
| 3187 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x00000007 |
|---|
| 3188 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x00000008L |
|---|
| 3189 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x00000003 |
|---|
| 3190 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x00000070L |
|---|
| 3191 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x00000004 |
|---|
| 3192 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x00000007L |
|---|
| 3193 | #define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x00000000 |
|---|
| 3194 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x00000001L |
|---|
| 3195 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x00000000 |
|---|
| 3196 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x00000002L |
|---|
| 3197 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x00000001 |
|---|
| 3198 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x00000004L |
|---|
| 3199 | #define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x00000002 |
|---|
| 3200 | #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x00000008L |
|---|
| 3201 | #define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x00000003 |
|---|
| 3202 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x00000002L |
|---|
| 3203 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x00000001 |
|---|
| 3204 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x00000001L |
|---|
| 3205 | #define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x00000000 |
|---|
| 3206 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x00000008L |
|---|
| 3207 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x00000003 |
|---|
| 3208 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x00000004L |
|---|
| 3209 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x00000002 |
|---|
| 3210 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x00000020L |
|---|
| 3211 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x00000005 |
|---|
| 3212 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x00000010L |
|---|
| 3213 | #define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x00000004 |
|---|
| 3214 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x00000080L |
|---|
| 3215 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x00000007 |
|---|
| 3216 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x00000040L |
|---|
| 3217 | #define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x00000006 |
|---|
| 3218 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0x0000fc00L |
|---|
| 3219 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0x0000000a |
|---|
| 3220 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x00000300L |
|---|
| 3221 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x00000008 |
|---|
| 3222 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x00000080L |
|---|
| 3223 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x00000007 |
|---|
| 3224 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x00000008L |
|---|
| 3225 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x00000003 |
|---|
| 3226 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x00000070L |
|---|
| 3227 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x00000004 |
|---|
| 3228 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x00000007L |
|---|
| 3229 | #define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x00000000 |
|---|
| 3230 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x00000001L |
|---|
| 3231 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x00000000 |
|---|
| 3232 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x00000002L |
|---|
| 3233 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x00000001 |
|---|
| 3234 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x00000004L |
|---|
| 3235 | #define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x00000002 |
|---|
| 3236 | #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x00000008L |
|---|
| 3237 | #define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x00000003 |
|---|
| 3238 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x00000002L |
|---|
| 3239 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x00000001 |
|---|
| 3240 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x00000001L |
|---|
| 3241 | #define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x00000000 |
|---|
| 3242 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x00000008L |
|---|
| 3243 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x00000003 |
|---|
| 3244 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x00000004L |
|---|
| 3245 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x00000002 |
|---|
| 3246 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x00000020L |
|---|
| 3247 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x00000005 |
|---|
| 3248 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x00000010L |
|---|
| 3249 | #define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x00000004 |
|---|
| 3250 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x00000080L |
|---|
| 3251 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x00000007 |
|---|
| 3252 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x00000040L |
|---|
| 3253 | #define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x00000006 |
|---|
| 3254 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0x0000fc00L |
|---|
| 3255 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0x0000000a |
|---|
| 3256 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x00000300L |
|---|
| 3257 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x00000008 |
|---|
| 3258 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x00000080L |
|---|
| 3259 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x00000007 |
|---|
| 3260 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x00000008L |
|---|
| 3261 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x00000003 |
|---|
| 3262 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x00000070L |
|---|
| 3263 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x00000004 |
|---|
| 3264 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x00000007L |
|---|
| 3265 | #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000 |
|---|
| 3266 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x00000001L |
|---|
| 3267 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x00000000 |
|---|
| 3268 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x00000002L |
|---|
| 3269 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x00000001 |
|---|
| 3270 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x00000004L |
|---|
| 3271 | #define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x00000002 |
|---|
| 3272 | #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x00000008L |
|---|
| 3273 | #define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x00000003 |
|---|
| 3274 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x00000002L |
|---|
| 3275 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x00000001 |
|---|
| 3276 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x00000001L |
|---|
| 3277 | #define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x00000000 |
|---|
| 3278 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x00000008L |
|---|
| 3279 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x00000003 |
|---|
| 3280 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x00000004L |
|---|
| 3281 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x00000002 |
|---|
| 3282 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x00000020L |
|---|
| 3283 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x00000005 |
|---|
| 3284 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x00000010L |
|---|
| 3285 | #define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x00000004 |
|---|
| 3286 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x00000080L |
|---|
| 3287 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x00000007 |
|---|
| 3288 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x00000040L |
|---|
| 3289 | #define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x00000006 |
|---|
| 3290 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0x0000fc00L |
|---|
| 3291 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0x0000000a |
|---|
| 3292 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x00000300L |
|---|
| 3293 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x00000008 |
|---|
| 3294 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x00000080L |
|---|
| 3295 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x00000007 |
|---|
| 3296 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x00000008L |
|---|
| 3297 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x00000003 |
|---|
| 3298 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x00000070L |
|---|
| 3299 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x00000004 |
|---|
| 3300 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x00000007L |
|---|
| 3301 | #define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x00000000 |
|---|
| 3302 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x00000001L |
|---|
| 3303 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x00000000 |
|---|
| 3304 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x00000002L |
|---|
| 3305 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x00000001 |
|---|
| 3306 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x00000004L |
|---|
| 3307 | #define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x00000002 |
|---|
| 3308 | #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x00000008L |
|---|
| 3309 | #define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x00000003 |
|---|
| 3310 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x00000002L |
|---|
| 3311 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x00000001 |
|---|
| 3312 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x00000001L |
|---|
| 3313 | #define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x00000000 |
|---|
| 3314 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x00000008L |
|---|
| 3315 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x00000003 |
|---|
| 3316 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x00000004L |
|---|
| 3317 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x00000002 |
|---|
| 3318 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x00000020L |
|---|
| 3319 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x00000005 |
|---|
| 3320 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x00000010L |
|---|
| 3321 | #define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x00000004 |
|---|
| 3322 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x00000080L |
|---|
| 3323 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x00000007 |
|---|
| 3324 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x00000040L |
|---|
| 3325 | #define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x00000006 |
|---|
| 3326 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0x0000fc00L |
|---|
| 3327 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0x0000000a |
|---|
| 3328 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x00000300L |
|---|
| 3329 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x00000008 |
|---|
| 3330 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x00000080L |
|---|
| 3331 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x00000007 |
|---|
| 3332 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x00000008L |
|---|
| 3333 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x00000003 |
|---|
| 3334 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x00000070L |
|---|
| 3335 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x00000004 |
|---|
| 3336 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x00000007L |
|---|
| 3337 | #define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x00000000 |
|---|
| 3338 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x00000001L |
|---|
| 3339 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x00000000 |
|---|
| 3340 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x00000002L |
|---|
| 3341 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x00000001 |
|---|
| 3342 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x00000004L |
|---|
| 3343 | #define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x00000002 |
|---|
| 3344 | #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x00000008L |
|---|
| 3345 | #define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x00000003 |
|---|
| 3346 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x00000002L |
|---|
| 3347 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x00000001 |
|---|
| 3348 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x00000001L |
|---|
| 3349 | #define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x00000000 |
|---|
| 3350 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x00000008L |
|---|
| 3351 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x00000003 |
|---|
| 3352 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x00000004L |
|---|
| 3353 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x00000002 |
|---|
| 3354 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x00000020L |
|---|
| 3355 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x00000005 |
|---|
| 3356 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x00000010L |
|---|
| 3357 | #define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x00000004 |
|---|
| 3358 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x00000080L |
|---|
| 3359 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x00000007 |
|---|
| 3360 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x00000040L |
|---|
| 3361 | #define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x00000006 |
|---|
| 3362 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0x0000fc00L |
|---|
| 3363 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0x0000000a |
|---|
| 3364 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x00000300L |
|---|
| 3365 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x00000008 |
|---|
| 3366 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x00000080L |
|---|
| 3367 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x00000007 |
|---|
| 3368 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x00000008L |
|---|
| 3369 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x00000003 |
|---|
| 3370 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x00000070L |
|---|
| 3371 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x00000004 |
|---|
| 3372 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x00000007L |
|---|
| 3373 | #define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x00000000 |
|---|
| 3374 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x00000001L |
|---|
| 3375 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x00000000 |
|---|
| 3376 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x00000002L |
|---|
| 3377 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x00000001 |
|---|
| 3378 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x00000004L |
|---|
| 3379 | #define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x00000002 |
|---|
| 3380 | #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x00000008L |
|---|
| 3381 | #define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x00000003 |
|---|
| 3382 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x00000002L |
|---|
| 3383 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x00000001 |
|---|
| 3384 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x00000001L |
|---|
| 3385 | #define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x00000000 |
|---|
| 3386 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x00000008L |
|---|
| 3387 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x00000003 |
|---|
| 3388 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x00000004L |
|---|
| 3389 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x00000002 |
|---|
| 3390 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x00000020L |
|---|
| 3391 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x00000005 |
|---|
| 3392 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x00000010L |
|---|
| 3393 | #define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x00000004 |
|---|
| 3394 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x00000080L |
|---|
| 3395 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x00000007 |
|---|
| 3396 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x00000040L |
|---|
| 3397 | #define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x00000006 |
|---|
| 3398 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0x0000fc00L |
|---|
| 3399 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0x0000000a |
|---|
| 3400 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x00000300L |
|---|
| 3401 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x00000008 |
|---|
| 3402 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x00000080L |
|---|
| 3403 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x00000007 |
|---|
| 3404 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x00000008L |
|---|
| 3405 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x00000003 |
|---|
| 3406 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x00000070L |
|---|
| 3407 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004 |
|---|
| 3408 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x00000007L |
|---|
| 3409 | #define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x00000000 |
|---|
| 3410 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x00000001L |
|---|
| 3411 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x00000000 |
|---|
| 3412 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x00000002L |
|---|
| 3413 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x00000001 |
|---|
| 3414 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x00000004L |
|---|
| 3415 | #define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x00000002 |
|---|
| 3416 | #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x00000008L |
|---|
| 3417 | #define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x00000003 |
|---|
| 3418 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x00000002L |
|---|
| 3419 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x00000001 |
|---|
| 3420 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x00000001L |
|---|
| 3421 | #define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x00000000 |
|---|
| 3422 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x00000008L |
|---|
| 3423 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x00000003 |
|---|
| 3424 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x00000004L |
|---|
| 3425 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x00000002 |
|---|
| 3426 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x00000020L |
|---|
| 3427 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x00000005 |
|---|
| 3428 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x00000010L |
|---|
| 3429 | #define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x00000004 |
|---|
| 3430 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x00000080L |
|---|
| 3431 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x00000007 |
|---|
| 3432 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x00000040L |
|---|
| 3433 | #define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x00000006 |
|---|
| 3434 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0x0000fc00L |
|---|
| 3435 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0x0000000a |
|---|
| 3436 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x00000300L |
|---|
| 3437 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x00000008 |
|---|
| 3438 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x00000080L |
|---|
| 3439 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x00000007 |
|---|
| 3440 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x00000008L |
|---|
| 3441 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x00000003 |
|---|
| 3442 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x00000070L |
|---|
| 3443 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x00000004 |
|---|
| 3444 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x00000007L |
|---|
| 3445 | #define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x00000000 |
|---|
| 3446 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x00000001L |
|---|
| 3447 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x00000000 |
|---|
| 3448 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x00000002L |
|---|
| 3449 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x00000001 |
|---|
| 3450 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x00000004L |
|---|
| 3451 | #define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x00000002 |
|---|
| 3452 | #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x00000008L |
|---|
| 3453 | #define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x00000003 |
|---|
| 3454 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x00000002L |
|---|
| 3455 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x00000001 |
|---|
| 3456 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x00000001L |
|---|
| 3457 | #define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x00000000 |
|---|
| 3458 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x00000008L |
|---|
| 3459 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x00000003 |
|---|
| 3460 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x00000004L |
|---|
| 3461 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x00000002 |
|---|
| 3462 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x00000020L |
|---|
| 3463 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x00000005 |
|---|
| 3464 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x00000010L |
|---|
| 3465 | #define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x00000004 |
|---|
| 3466 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x00000080L |
|---|
| 3467 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x00000007 |
|---|
| 3468 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x00000040L |
|---|
| 3469 | #define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x00000006 |
|---|
| 3470 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0x0000fc00L |
|---|
| 3471 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0x0000000a |
|---|
| 3472 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x00000300L |
|---|
| 3473 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x00000008 |
|---|
| 3474 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x00000080L |
|---|
| 3475 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x00000007 |
|---|
| 3476 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x00000008L |
|---|
| 3477 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x00000003 |
|---|
| 3478 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x00000070L |
|---|
| 3479 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x00000004 |
|---|
| 3480 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x00000007L |
|---|
| 3481 | #define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x00000000 |
|---|
| 3482 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x00000001L |
|---|
| 3483 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x00000000 |
|---|
| 3484 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x00000002L |
|---|
| 3485 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x00000001 |
|---|
| 3486 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x00000004L |
|---|
| 3487 | #define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x00000002 |
|---|
| 3488 | #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x00000008L |
|---|
| 3489 | #define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x00000003 |
|---|
| 3490 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x00000002L |
|---|
| 3491 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x00000001 |
|---|
| 3492 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x00000001L |
|---|
| 3493 | #define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x00000000 |
|---|
| 3494 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x00000008L |
|---|
| 3495 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x00000003 |
|---|
| 3496 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x00000004L |
|---|
| 3497 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x00000002 |
|---|
| 3498 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x00000020L |
|---|
| 3499 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x00000005 |
|---|
| 3500 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x00000010L |
|---|
| 3501 | #define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x00000004 |
|---|
| 3502 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x00000080L |
|---|
| 3503 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x00000007 |
|---|
| 3504 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x00000040L |
|---|
| 3505 | #define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x00000006 |
|---|
| 3506 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0x0000fc00L |
|---|
| 3507 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0x0000000a |
|---|
| 3508 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x00000300L |
|---|
| 3509 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x00000008 |
|---|
| 3510 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x00000080L |
|---|
| 3511 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x00000007 |
|---|
| 3512 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x00000008L |
|---|
| 3513 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x00000003 |
|---|
| 3514 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x00000070L |
|---|
| 3515 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x00000004 |
|---|
| 3516 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x00000007L |
|---|
| 3517 | #define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x00000000 |
|---|
| 3518 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x00000001L |
|---|
| 3519 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x00000000 |
|---|
| 3520 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x00000002L |
|---|
| 3521 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x00000001 |
|---|
| 3522 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x00000004L |
|---|
| 3523 | #define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x00000002 |
|---|
| 3524 | #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x00000008L |
|---|
| 3525 | #define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x00000003 |
|---|
| 3526 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x00000002L |
|---|
| 3527 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x00000001 |
|---|
| 3528 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x00000001L |
|---|
| 3529 | #define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x00000000 |
|---|
| 3530 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x00000008L |
|---|
| 3531 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x00000003 |
|---|
| 3532 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x00000004L |
|---|
| 3533 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x00000002 |
|---|
| 3534 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x00000020L |
|---|
| 3535 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x00000005 |
|---|
| 3536 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x00000010L |
|---|
| 3537 | #define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x00000004 |
|---|
| 3538 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x00000080L |
|---|
| 3539 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x00000007 |
|---|
| 3540 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x00000040L |
|---|
| 3541 | #define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x00000006 |
|---|
| 3542 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0x0000fc00L |
|---|
| 3543 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0x0000000a |
|---|
| 3544 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x00000300L |
|---|
| 3545 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x00000008 |
|---|
| 3546 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x00000080L |
|---|
| 3547 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x00000007 |
|---|
| 3548 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x00000008L |
|---|
| 3549 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x00000003 |
|---|
| 3550 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x00000070L |
|---|
| 3551 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x00000004 |
|---|
| 3552 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x00000007L |
|---|
| 3553 | #define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x00000000 |
|---|
| 3554 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x00000001L |
|---|
| 3555 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x00000000 |
|---|
| 3556 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x0000003eL |
|---|
| 3557 | #define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x00000001 |
|---|
| 3558 | #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0x00000f00L |
|---|
| 3559 | #define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x00000008 |
|---|
| 3560 | #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x00800000L |
|---|
| 3561 | #define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x00000017 |
|---|
| 3562 | #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x00400000L |
|---|
| 3563 | #define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x00000016 |
|---|
| 3564 | #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x0000001fL |
|---|
| 3565 | #define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x00000000 |
|---|
| 3566 | #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000L |
|---|
| 3567 | #define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x00000018 |
|---|
| 3568 | #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x00010000L |
|---|
| 3569 | #define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x00000010 |
|---|
| 3570 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x00000100L |
|---|
| 3571 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x00000008 |
|---|
| 3572 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0x000000ffL |
|---|
| 3573 | #define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x00000000 |
|---|
| 3574 | #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0x0000ffffL |
|---|
| 3575 | #define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x00000000 |
|---|
| 3576 | #define PB1_GLB_CTRL_REG0__BACKUP_MASK 0x0000ffffL |
|---|
| 3577 | #define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x00000000 |
|---|
| 3578 | #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x00030000L |
|---|
| 3579 | #define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x00000010 |
|---|
| 3580 | #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x00700000L |
|---|
| 3581 | #define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x00000014 |
|---|
| 3582 | #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x00800000L |
|---|
| 3583 | #define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x00000017 |
|---|
| 3584 | #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x01000000L |
|---|
| 3585 | #define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x00000018 |
|---|
| 3586 | #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x02000000L |
|---|
| 3587 | #define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x00000019 |
|---|
| 3588 | #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x04000000L |
|---|
| 3589 | #define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x0000001a |
|---|
| 3590 | #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000L |
|---|
| 3591 | #define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x0000001e |
|---|
| 3592 | #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000L |
|---|
| 3593 | #define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x0000001f |
|---|
| 3594 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x00000001L |
|---|
| 3595 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x00000000 |
|---|
| 3596 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x0000007eL |
|---|
| 3597 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x00000001 |
|---|
| 3598 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x00000080L |
|---|
| 3599 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x00000007 |
|---|
| 3600 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x00003f00L |
|---|
| 3601 | #define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x00000008 |
|---|
| 3602 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x00004000L |
|---|
| 3603 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0x0000000e |
|---|
| 3604 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x003f8000L |
|---|
| 3605 | #define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0x0000000f |
|---|
| 3606 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x00400000L |
|---|
| 3607 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x00000016 |
|---|
| 3608 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000L |
|---|
| 3609 | #define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x00000017 |
|---|
| 3610 | #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000L |
|---|
| 3611 | #define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x0000001e |
|---|
| 3612 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x00000001L |
|---|
| 3613 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x00000000 |
|---|
| 3614 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0x000000feL |
|---|
| 3615 | #define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x00000001 |
|---|
| 3616 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x00000100L |
|---|
| 3617 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x00000008 |
|---|
| 3618 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0x0000fe00L |
|---|
| 3619 | #define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x00000009 |
|---|
| 3620 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x00010000L |
|---|
| 3621 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x00000010 |
|---|
| 3622 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0x00fe0000L |
|---|
| 3623 | #define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x00000011 |
|---|
| 3624 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x01000000L |
|---|
| 3625 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x00000018 |
|---|
| 3626 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000L |
|---|
| 3627 | #define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x00000019 |
|---|
| 3628 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x00000060L |
|---|
| 3629 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x00000005 |
|---|
| 3630 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L |
|---|
| 3631 | #define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x00000007 |
|---|
| 3632 | #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L |
|---|
| 3633 | #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x00000009 |
|---|
| 3634 | #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x0001c000L |
|---|
| 3635 | #define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0x0000000e |
|---|
| 3636 | #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x00001000L |
|---|
| 3637 | #define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0x0000000c |
|---|
| 3638 | #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x00000800L |
|---|
| 3639 | #define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0x0000000b |
|---|
| 3640 | #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x001c0000L |
|---|
| 3641 | #define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x00000012 |
|---|
| 3642 | #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000L |
|---|
| 3643 | #define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x0000001f |
|---|
| 3644 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x00400000L |
|---|
| 3645 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x00000016 |
|---|
| 3646 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x07800000L |
|---|
| 3647 | #define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x00000017 |
|---|
| 3648 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x08000000L |
|---|
| 3649 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x0000001b |
|---|
| 3650 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000L |
|---|
| 3651 | #define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x0000001c |
|---|
| 3652 | #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x00200000L |
|---|
| 3653 | #define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x00000015 |
|---|
| 3654 | #define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x0000001fL |
|---|
| 3655 | #define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x00000000 |
|---|
| 3656 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x03c00000L |
|---|
| 3657 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x00000016 |
|---|
| 3658 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0x0000ffffL |
|---|
| 3659 | #define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x00000000 |
|---|
| 3660 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x00040000L |
|---|
| 3661 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x00000012 |
|---|
| 3662 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x00030000L |
|---|
| 3663 | #define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x00000010 |
|---|
| 3664 | #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x04000000L |
|---|
| 3665 | #define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x0000001a |
|---|
| 3666 | #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000L |
|---|
| 3667 | #define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x0000001c |
|---|
| 3668 | #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x08000000L |
|---|
| 3669 | #define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x0000001b |
|---|
| 3670 | #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0x000000ffL |
|---|
| 3671 | #define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x00000000 |
|---|
| 3672 | #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0x0000ffffL |
|---|
| 3673 | #define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x00000000 |
|---|
| 3674 | #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000L |
|---|
| 3675 | #define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x00000010 |
|---|
| 3676 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x00008000L |
|---|
| 3677 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0x0000000f |
|---|
| 3678 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000L |
|---|
| 3679 | #define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x00000010 |
|---|
| 3680 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x00000004L |
|---|
| 3681 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x00000002 |
|---|
| 3682 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x00000008L |
|---|
| 3683 | #define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x00000003 |
|---|
| 3684 | #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x00000001L |
|---|
| 3685 | #define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x00000000 |
|---|
| 3686 | #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x00000002L |
|---|
| 3687 | #define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x00000001 |
|---|
| 3688 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x00000001L |
|---|
| 3689 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x00000000 |
|---|
| 3690 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x00000002L |
|---|
| 3691 | #define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x00000001 |
|---|
| 3692 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 3693 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 3694 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x00000008L |
|---|
| 3695 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x00000003 |
|---|
| 3696 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 3697 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 3698 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 3699 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 3700 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x00000010L |
|---|
| 3701 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x00000004 |
|---|
| 3702 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x00100000L |
|---|
| 3703 | #define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x00000014 |
|---|
| 3704 | #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0x000f0000L |
|---|
| 3705 | #define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x00000010 |
|---|
| 3706 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0x00000f00L |
|---|
| 3707 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x00000008 |
|---|
| 3708 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0x0000f000L |
|---|
| 3709 | #define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0x0000000c |
|---|
| 3710 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x00001000L |
|---|
| 3711 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0x0000000c |
|---|
| 3712 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x00002000L |
|---|
| 3713 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0x0000000d |
|---|
| 3714 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x00004000L |
|---|
| 3715 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0x0000000e |
|---|
| 3716 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x00008000L |
|---|
| 3717 | #define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0x0000000f |
|---|
| 3718 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0x000c0000L |
|---|
| 3719 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x00000012 |
|---|
| 3720 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0x00c00000L |
|---|
| 3721 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x00000016 |
|---|
| 3722 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0x0c000000L |
|---|
| 3723 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x0000001a |
|---|
| 3724 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000L |
|---|
| 3725 | #define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x0000001e |
|---|
| 3726 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x00000004L |
|---|
| 3727 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x00000002 |
|---|
| 3728 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x00000002L |
|---|
| 3729 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x00000001 |
|---|
| 3730 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x00000001L |
|---|
| 3731 | #define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x00000000 |
|---|
| 3732 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L |
|---|
| 3733 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010 |
|---|
| 3734 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L |
|---|
| 3735 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x00000014 |
|---|
| 3736 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x03000000L |
|---|
| 3737 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x00000018 |
|---|
| 3738 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000L |
|---|
| 3739 | #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x0000001c |
|---|
| 3740 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x00001000L |
|---|
| 3741 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0x0000000c |
|---|
| 3742 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x00002000L |
|---|
| 3743 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0x0000000d |
|---|
| 3744 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x00004000L |
|---|
| 3745 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0x0000000e |
|---|
| 3746 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x00008000L |
|---|
| 3747 | #define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0x0000000f |
|---|
| 3748 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0x000c0000L |
|---|
| 3749 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x00000012 |
|---|
| 3750 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0x00c00000L |
|---|
| 3751 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x00000016 |
|---|
| 3752 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0x0c000000L |
|---|
| 3753 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x0000001a |
|---|
| 3754 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000L |
|---|
| 3755 | #define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x0000001e |
|---|
| 3756 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x00000004L |
|---|
| 3757 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x00000002 |
|---|
| 3758 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x00000002L |
|---|
| 3759 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x00000001 |
|---|
| 3760 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x00000001L |
|---|
| 3761 | #define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x00000000 |
|---|
| 3762 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x00030000L |
|---|
| 3763 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x00000010 |
|---|
| 3764 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L |
|---|
| 3765 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x00000014 |
|---|
| 3766 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x03000000L |
|---|
| 3767 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x00000018 |
|---|
| 3768 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000L |
|---|
| 3769 | #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x0000001c |
|---|
| 3770 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x00004000L |
|---|
| 3771 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0x0000000e |
|---|
| 3772 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x00008000L |
|---|
| 3773 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0x0000000f |
|---|
| 3774 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x00001000L |
|---|
| 3775 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0x0000000c |
|---|
| 3776 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x00002000L |
|---|
| 3777 | #define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0x0000000d |
|---|
| 3778 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0x0c000000L |
|---|
| 3779 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x0000001a |
|---|
| 3780 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000L |
|---|
| 3781 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x0000001e |
|---|
| 3782 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0x000c0000L |
|---|
| 3783 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x00000012 |
|---|
| 3784 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0x00c00000L |
|---|
| 3785 | #define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x00000016 |
|---|
| 3786 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x00000004L |
|---|
| 3787 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x00000002 |
|---|
| 3788 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x00000002L |
|---|
| 3789 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x00000001 |
|---|
| 3790 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x00000001L |
|---|
| 3791 | #define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x00000000 |
|---|
| 3792 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x03000000L |
|---|
| 3793 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018 |
|---|
| 3794 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000L |
|---|
| 3795 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x0000001c |
|---|
| 3796 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x00030000L |
|---|
| 3797 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x00000010 |
|---|
| 3798 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x00300000L |
|---|
| 3799 | #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x00000014 |
|---|
| 3800 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x00001000L |
|---|
| 3801 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0x0000000c |
|---|
| 3802 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x00002000L |
|---|
| 3803 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0x0000000d |
|---|
| 3804 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x00004000L |
|---|
| 3805 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0x0000000e |
|---|
| 3806 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x00008000L |
|---|
| 3807 | #define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0x0000000f |
|---|
| 3808 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0x000c0000L |
|---|
| 3809 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x00000012 |
|---|
| 3810 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0x00c00000L |
|---|
| 3811 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x00000016 |
|---|
| 3812 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0x0c000000L |
|---|
| 3813 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x0000001a |
|---|
| 3814 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000L |
|---|
| 3815 | #define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x0000001e |
|---|
| 3816 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x00000004L |
|---|
| 3817 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x00000002 |
|---|
| 3818 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x00000002L |
|---|
| 3819 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x00000001 |
|---|
| 3820 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x00000001L |
|---|
| 3821 | #define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x00000000 |
|---|
| 3822 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x00030000L |
|---|
| 3823 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x00000010 |
|---|
| 3824 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x00300000L |
|---|
| 3825 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x00000014 |
|---|
| 3826 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x03000000L |
|---|
| 3827 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x00000018 |
|---|
| 3828 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000L |
|---|
| 3829 | #define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x0000001c |
|---|
| 3830 | #define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x00000001L |
|---|
| 3831 | #define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x00000000 |
|---|
| 3832 | #define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x00000002L |
|---|
| 3833 | #define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x00000001 |
|---|
| 3834 | #define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x00000004L |
|---|
| 3835 | #define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x00000002 |
|---|
| 3836 | #define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x00000008L |
|---|
| 3837 | #define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x00000003 |
|---|
| 3838 | #define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x00000010L |
|---|
| 3839 | #define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x00000004 |
|---|
| 3840 | #define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x00000020L |
|---|
| 3841 | #define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x00000005 |
|---|
| 3842 | #define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x00000040L |
|---|
| 3843 | #define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x00000006 |
|---|
| 3844 | #define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x00000080L |
|---|
| 3845 | #define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x00000007 |
|---|
| 3846 | #define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x00000100L |
|---|
| 3847 | #define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x00000008 |
|---|
| 3848 | #define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x00000200L |
|---|
| 3849 | #define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x00000009 |
|---|
| 3850 | #define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x00000400L |
|---|
| 3851 | #define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0x0000000a |
|---|
| 3852 | #define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x00000800L |
|---|
| 3853 | #define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0x0000000b |
|---|
| 3854 | #define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x00001000L |
|---|
| 3855 | #define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0x0000000c |
|---|
| 3856 | #define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x00002000L |
|---|
| 3857 | #define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0x0000000d |
|---|
| 3858 | #define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x00004000L |
|---|
| 3859 | #define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0x0000000e |
|---|
| 3860 | #define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x00008000L |
|---|
| 3861 | #define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0x0000000f |
|---|
| 3862 | #define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x00010000L |
|---|
| 3863 | #define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x00000010 |
|---|
| 3864 | #define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x00020000L |
|---|
| 3865 | #define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x00000011 |
|---|
| 3866 | #define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x00040000L |
|---|
| 3867 | #define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x00000012 |
|---|
| 3868 | #define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x00080000L |
|---|
| 3869 | #define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x00000013 |
|---|
| 3870 | #define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x00100000L |
|---|
| 3871 | #define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x00000014 |
|---|
| 3872 | #define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x00200000L |
|---|
| 3873 | #define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x00000015 |
|---|
| 3874 | #define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x00400000L |
|---|
| 3875 | #define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x00000016 |
|---|
| 3876 | #define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x00800000L |
|---|
| 3877 | #define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x00000017 |
|---|
| 3878 | #define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x01000000L |
|---|
| 3879 | #define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x00000018 |
|---|
| 3880 | #define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x02000000L |
|---|
| 3881 | #define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x00000019 |
|---|
| 3882 | #define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x04000000L |
|---|
| 3883 | #define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x0000001a |
|---|
| 3884 | #define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x08000000L |
|---|
| 3885 | #define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x0000001b |
|---|
| 3886 | #define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000L |
|---|
| 3887 | #define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x0000001c |
|---|
| 3888 | #define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000L |
|---|
| 3889 | #define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x0000001d |
|---|
| 3890 | #define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000L |
|---|
| 3891 | #define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x0000001e |
|---|
| 3892 | #define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000L |
|---|
| 3893 | #define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x0000001f |
|---|
| 3894 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x00000080L |
|---|
| 3895 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x00000007 |
|---|
| 3896 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x00000100L |
|---|
| 3897 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x00000008 |
|---|
| 3898 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x00040000L |
|---|
| 3899 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x00000012 |
|---|
| 3900 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x00080000L |
|---|
| 3901 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x00000013 |
|---|
| 3902 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x00100000L |
|---|
| 3903 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x00000014 |
|---|
| 3904 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x00200000L |
|---|
| 3905 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x00000015 |
|---|
| 3906 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x00400000L |
|---|
| 3907 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x00000016 |
|---|
| 3908 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x00800000L |
|---|
| 3909 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x00000017 |
|---|
| 3910 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x00000200L |
|---|
| 3911 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x00000009 |
|---|
| 3912 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x00000400L |
|---|
| 3913 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x0000000a |
|---|
| 3914 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x00000800L |
|---|
| 3915 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x0000000b |
|---|
| 3916 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x00001000L |
|---|
| 3917 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x0000000c |
|---|
| 3918 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x00002000L |
|---|
| 3919 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x0000000d |
|---|
| 3920 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x00004000L |
|---|
| 3921 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x0000000e |
|---|
| 3922 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x00008000L |
|---|
| 3923 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x0000000f |
|---|
| 3924 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x00010000L |
|---|
| 3925 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x00000010 |
|---|
| 3926 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x00020000L |
|---|
| 3927 | #define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x00000011 |
|---|
| 3928 | #define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x00000006L |
|---|
| 3929 | #define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x00000001 |
|---|
| 3930 | #define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x07000000L |
|---|
| 3931 | #define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x00000018 |
|---|
| 3932 | #define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x00000002L |
|---|
| 3933 | #define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x00000001 |
|---|
| 3934 | #define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x00000020L |
|---|
| 3935 | #define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x00000005 |
|---|
| 3936 | #define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x00000200L |
|---|
| 3937 | #define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x00000009 |
|---|
| 3938 | #define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x00002000L |
|---|
| 3939 | #define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0x0000000d |
|---|
| 3940 | #define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x00000100L |
|---|
| 3941 | #define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x00000008 |
|---|
| 3942 | #define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x00700000L |
|---|
| 3943 | #define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x00000014 |
|---|
| 3944 | #define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x00000010L |
|---|
| 3945 | #define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x00000004 |
|---|
| 3946 | #define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x00800000L |
|---|
| 3947 | #define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x00000017 |
|---|
| 3948 | #define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000L |
|---|
| 3949 | #define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x0000001c |
|---|
| 3950 | #define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000L |
|---|
| 3951 | #define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x0000001d |
|---|
| 3952 | #define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0x000e0000L |
|---|
| 3953 | #define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x00000011 |
|---|
| 3954 | #define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L |
|---|
| 3955 | #define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x00000003 |
|---|
| 3956 | #define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x00000004L |
|---|
| 3957 | #define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x00000002 |
|---|
| 3958 | #define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L |
|---|
| 3959 | #define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0x0000000a |
|---|
| 3960 | #define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x00000040L |
|---|
| 3961 | #define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x00000006 |
|---|
| 3962 | #define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x00000080L |
|---|
| 3963 | #define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x00000007 |
|---|
| 3964 | #define PB1_PIF_CNTL__RXEN_GATER_MASK 0x0f000000L |
|---|
| 3965 | #define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x00000018 |
|---|
| 3966 | #define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x00000800L |
|---|
| 3967 | #define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0x0000000b |
|---|
| 3968 | #define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x00000001L |
|---|
| 3969 | #define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x00000000 |
|---|
| 3970 | #define PB1_PIF_CNTL__TXGND_TIME_MASK 0x00010000L |
|---|
| 3971 | #define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x00000010 |
|---|
| 3972 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x00000001L |
|---|
| 3973 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x00000000 |
|---|
| 3974 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x00000002L |
|---|
| 3975 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x00000001 |
|---|
| 3976 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x00000004L |
|---|
| 3977 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x00000002 |
|---|
| 3978 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x00000008L |
|---|
| 3979 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x00000003 |
|---|
| 3980 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x00000010L |
|---|
| 3981 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x00000004 |
|---|
| 3982 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x00000020L |
|---|
| 3983 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x00000005 |
|---|
| 3984 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x00000040L |
|---|
| 3985 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x00000006 |
|---|
| 3986 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x00000080L |
|---|
| 3987 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x00000007 |
|---|
| 3988 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x00000100L |
|---|
| 3989 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x00000008 |
|---|
| 3990 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x00000200L |
|---|
| 3991 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x00000009 |
|---|
| 3992 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x00000400L |
|---|
| 3993 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0x0000000a |
|---|
| 3994 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x00000800L |
|---|
| 3995 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0x0000000b |
|---|
| 3996 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x00001000L |
|---|
| 3997 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0x0000000c |
|---|
| 3998 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x00002000L |
|---|
| 3999 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0x0000000d |
|---|
| 4000 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x00004000L |
|---|
| 4001 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0x0000000e |
|---|
| 4002 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x00008000L |
|---|
| 4003 | #define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0x0000000f |
|---|
| 4004 | #define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x02000000L |
|---|
| 4005 | #define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x00000019 |
|---|
| 4006 | #define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x00100000L |
|---|
| 4007 | #define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x00000014 |
|---|
| 4008 | #define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x00000001L |
|---|
| 4009 | #define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x00000000 |
|---|
| 4010 | #define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x00000020L |
|---|
| 4011 | #define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x00000005 |
|---|
| 4012 | #define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x00000040L |
|---|
| 4013 | #define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x00000006 |
|---|
| 4014 | #define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x00000080L |
|---|
| 4015 | #define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x00000007 |
|---|
| 4016 | #define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x00000002L |
|---|
| 4017 | #define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x00000001 |
|---|
| 4018 | #define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x00000004L |
|---|
| 4019 | #define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x00000002 |
|---|
| 4020 | #define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x00000008L |
|---|
| 4021 | #define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x00000003 |
|---|
| 4022 | #define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x00000010L |
|---|
| 4023 | #define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x00000004 |
|---|
| 4024 | #define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x00000400L |
|---|
| 4025 | #define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0x0000000a |
|---|
| 4026 | #define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x00000800L |
|---|
| 4027 | #define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0x0000000b |
|---|
| 4028 | #define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x00000100L |
|---|
| 4029 | #define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x00000008 |
|---|
| 4030 | #define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x00000200L |
|---|
| 4031 | #define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x00000009 |
|---|
| 4032 | #define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x00020000L |
|---|
| 4033 | #define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x00000011 |
|---|
| 4034 | #define |
|---|