1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _clk_10_0_2_SH_MASK_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: clk_clk1_0_SmuClkDec |
26 | //CLK1_CLK_PLL_REQ |
27 | #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 |
28 | #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc |
29 | #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 |
30 | #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL |
31 | #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L |
32 | #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L |
33 | //CLK1_CLK0_BYPASS_CNTL |
34 | #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 |
35 | #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10 |
36 | #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L |
37 | #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L |
38 | //CLK1_CLK1_BYPASS_CNTL |
39 | #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 |
40 | #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10 |
41 | #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L |
42 | #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L |
43 | //CLK1_CLK2_BYPASS_CNTL |
44 | #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 |
45 | #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 |
46 | #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L |
47 | #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L |
48 | //CLK1_CLK3_DS_CNTL |
49 | #define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 |
50 | #define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L |
51 | //CLK1_CLK3_ALLOW_DS |
52 | #define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0 |
53 | #define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L |
54 | //CLK1_CLK3_BYPASS_CNTL |
55 | #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 |
56 | #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10 |
57 | #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L |
58 | #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L |
59 | //CLK1_CLK0_CURRENT_CNT |
60 | #define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 |
61 | #define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL |
62 | //CLK1_CLK1_CURRENT_CNT |
63 | #define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 |
64 | #define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL |
65 | //CLK1_CLK2_CURRENT_CNT |
66 | #define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 |
67 | #define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL |
68 | //CLK1_CLK3_CURRENT_CNT |
69 | #define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 |
70 | #define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL |
71 | |
72 | |
73 | #endif |
74 | |