1 | /* |
2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _dcn_1_0_SH_MASK_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: dce_dc_hda_azcontroller_azdec |
26 | //AZCONTROLLER0_GLOBAL_CAPABILITIES |
27 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 |
28 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
29 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 |
30 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 |
31 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc |
32 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L |
33 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L |
34 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L |
35 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L |
36 | #define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L |
37 | //AZCONTROLLER0_MINOR_VERSION |
38 | #define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 |
39 | #define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK 0xFFL |
40 | //AZCONTROLLER0_MAJOR_VERSION |
41 | #define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 |
42 | #define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK 0xFFL |
43 | //AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY |
44 | #define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
45 | #define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL |
46 | //AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY |
47 | #define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
48 | #define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL |
49 | //AZCONTROLLER0_GLOBAL_CONTROL |
50 | #define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 |
51 | #define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 |
52 | #define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 |
53 | #define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x00000001L |
54 | #define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x00000002L |
55 | #define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000100L |
56 | //AZCONTROLLER0_WAKE_ENABLE |
57 | #define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 |
58 | #define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x0001L |
59 | //AZCONTROLLER0_STATE_CHANGE_STATUS |
60 | #define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 |
61 | #define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x0001L |
62 | //AZCONTROLLER0_GLOBAL_STATUS |
63 | #define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 |
64 | #define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK 0x00000002L |
65 | //AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY |
66 | #define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 |
67 | #define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFFL |
68 | //AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY |
69 | #define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 |
70 | #define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFFL |
71 | //AZCONTROLLER0_INTERRUPT_CONTROL |
72 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 |
73 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 |
74 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 |
75 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 |
76 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 |
77 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 |
78 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 |
79 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 |
80 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 |
81 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 |
82 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa |
83 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb |
84 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc |
85 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd |
86 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe |
87 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf |
88 | #define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e |
89 | #define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f |
90 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x00000001L |
91 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x00000002L |
92 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x00000004L |
93 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x00000008L |
94 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x00000010L |
95 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x00000020L |
96 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x00000040L |
97 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x00000080L |
98 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x00000100L |
99 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x00000200L |
100 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x00000400L |
101 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x00000800L |
102 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x00001000L |
103 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x00002000L |
104 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x00004000L |
105 | #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x00008000L |
106 | #define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000L |
107 | #define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000L |
108 | //AZCONTROLLER0_INTERRUPT_STATUS |
109 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 |
110 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 |
111 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 |
112 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 |
113 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 |
114 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 |
115 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 |
116 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 |
117 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 |
118 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 |
119 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa |
120 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb |
121 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc |
122 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd |
123 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe |
124 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf |
125 | #define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e |
126 | #define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f |
127 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x00000001L |
128 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x00000002L |
129 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x00000004L |
130 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x00000008L |
131 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x00000010L |
132 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x00000020L |
133 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x00000040L |
134 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x00000080L |
135 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x00000100L |
136 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x00000200L |
137 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x00000400L |
138 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x00000800L |
139 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x00001000L |
140 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x00002000L |
141 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x00004000L |
142 | #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x00008000L |
143 | #define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000L |
144 | #define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000L |
145 | //AZCONTROLLER0_WALL_CLOCK_COUNTER |
146 | #define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 |
147 | #define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xFFFFFFFFL |
148 | //AZCONTROLLER0_STREAM_SYNCHRONIZATION |
149 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 |
150 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 |
151 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 |
152 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 |
153 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 |
154 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 |
155 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 |
156 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 |
157 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 |
158 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 |
159 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa |
160 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb |
161 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc |
162 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd |
163 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe |
164 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf |
165 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x00000001L |
166 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x00000002L |
167 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x00000004L |
168 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x00000008L |
169 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x00000010L |
170 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x00000020L |
171 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x00000040L |
172 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x00000080L |
173 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x00000100L |
174 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x00000200L |
175 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x00000400L |
176 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x00000800L |
177 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x00001000L |
178 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x00002000L |
179 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x00004000L |
180 | #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x00008000L |
181 | //AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS |
182 | #define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
183 | #define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
184 | #define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
185 | #define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
186 | //AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS |
187 | #define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
188 | #define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
189 | //AZCONTROLLER0_CORB_WRITE_POINTER |
190 | #define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 |
191 | #define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL |
192 | //AZCONTROLLER0_CORB_READ_POINTER |
193 | #define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 |
194 | #define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf |
195 | #define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL |
196 | #define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L |
197 | //AZCONTROLLER0_CORB_CONTROL |
198 | #define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 |
199 | #define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 |
200 | #define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L |
201 | #define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L |
202 | //AZCONTROLLER0_CORB_STATUS |
203 | #define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 |
204 | #define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L |
205 | //AZCONTROLLER0_CORB_SIZE |
206 | #define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT 0x0 |
207 | #define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 |
208 | #define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK 0x0003L |
209 | #define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L |
210 | //AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS |
211 | #define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
212 | #define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
213 | #define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
214 | #define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
215 | //AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS |
216 | #define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
217 | #define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
218 | //AZCONTROLLER0_RIRB_WRITE_POINTER |
219 | #define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 |
220 | #define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf |
221 | #define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL |
222 | #define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L |
223 | //AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT |
224 | #define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 |
225 | #define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL |
226 | //AZCONTROLLER0_RIRB_CONTROL |
227 | #define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 |
228 | #define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 |
229 | #define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 |
230 | #define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L |
231 | #define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L |
232 | #define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L |
233 | //AZCONTROLLER0_RIRB_STATUS |
234 | #define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 |
235 | #define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 |
236 | #define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L |
237 | #define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L |
238 | //AZCONTROLLER0_RIRB_SIZE |
239 | #define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 |
240 | #define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 |
241 | #define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L |
242 | #define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L |
243 | //AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE |
244 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 |
245 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c |
246 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL |
247 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L |
248 | //AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
249 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
250 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
251 | //AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
252 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
253 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL |
254 | //AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE |
255 | #define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 |
256 | #define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL |
257 | //AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS |
258 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 |
259 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 |
260 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L |
261 | #define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L |
262 | //AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS |
263 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 |
264 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 |
265 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 |
266 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L |
267 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL |
268 | #define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
269 | //AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS |
270 | #define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 |
271 | #define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
272 | //AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS |
273 | #define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 |
274 | #define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL |
275 | |
276 | |
277 | // addressBlock: dce_dc_hda_azendpoint_azdec |
278 | //AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
279 | #define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
280 | #define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
281 | //AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
282 | #define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
283 | #define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
284 | |
285 | |
286 | // addressBlock: dce_dc_hda_azinputendpoint_azdec |
287 | //AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA |
288 | #define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
289 | #define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
290 | //AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX |
291 | #define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
292 | #define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
293 | |
294 | |
295 | // addressBlock: dce_dc_hda_azroot_azdec |
296 | //AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
297 | #define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
298 | #define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
299 | //AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
300 | #define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
301 | #define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
302 | |
303 | |
304 | // addressBlock: dce_dc_hda_azstream0_azdec |
305 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
306 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
307 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
308 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
309 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
310 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
311 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
312 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
313 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
314 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
315 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
316 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
317 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
318 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
319 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
320 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
321 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
322 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
323 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
324 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
325 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
326 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
327 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
328 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
329 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
330 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
331 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
332 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
333 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
334 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
335 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
336 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
337 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
338 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
339 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
340 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
341 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
342 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
343 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
344 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
345 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
346 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
347 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
348 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
349 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
350 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
351 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
352 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
353 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
354 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
355 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
356 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
357 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
358 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
359 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
360 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
361 | //AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
362 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
363 | #define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
364 | |
365 | |
366 | // addressBlock: dce_dc_hda_azstream1_azdec |
367 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
368 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
369 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
370 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
371 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
372 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
373 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
374 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
375 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
376 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
377 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
378 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
379 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
380 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
381 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
382 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
383 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
384 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
385 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
386 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
387 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
388 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
389 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
390 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
391 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
392 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
393 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
394 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
395 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
396 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
397 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
398 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
399 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
400 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
401 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
402 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
403 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
404 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
405 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
406 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
407 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
408 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
409 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
410 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
411 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
412 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
413 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
414 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
415 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
416 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
417 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
418 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
419 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
420 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
421 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
422 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
423 | //AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
424 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
425 | #define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
426 | |
427 | |
428 | // addressBlock: dce_dc_hda_azstream2_azdec |
429 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
430 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
431 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
432 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
433 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
434 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
435 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
436 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
437 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
438 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
439 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
440 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
441 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
442 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
443 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
444 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
445 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
446 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
447 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
448 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
449 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
450 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
451 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
452 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
453 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
454 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
455 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
456 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
457 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
458 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
459 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
460 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
461 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
462 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
463 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
464 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
465 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
466 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
467 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
468 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
469 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
470 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
471 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
472 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
473 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
474 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
475 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
476 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
477 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
478 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
479 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
480 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
481 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
482 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
483 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
484 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
485 | //AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
486 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
487 | #define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
488 | |
489 | |
490 | // addressBlock: dce_dc_hda_azstream3_azdec |
491 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
492 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
493 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
494 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
495 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
496 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
497 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
498 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
499 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
500 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
501 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
502 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
503 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
504 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
505 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
506 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
507 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
508 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
509 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
510 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
511 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
512 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
513 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
514 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
515 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
516 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
517 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
518 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
519 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
520 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
521 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
522 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
523 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
524 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
525 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
526 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
527 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
528 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
529 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
530 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
531 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
532 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
533 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
534 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
535 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
536 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
537 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
538 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
539 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
540 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
541 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
542 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
543 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
544 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
545 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
546 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
547 | //AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
548 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
549 | #define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
550 | |
551 | |
552 | // addressBlock: dce_dc_hda_azstream4_azdec |
553 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
554 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
555 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
556 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
557 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
558 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
559 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
560 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
561 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
562 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
563 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
564 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
565 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
566 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
567 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
568 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
569 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
570 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
571 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
572 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
573 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
574 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
575 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
576 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
577 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
578 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
579 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
580 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
581 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
582 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
583 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
584 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
585 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
586 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
587 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
588 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
589 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
590 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
591 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
592 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
593 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
594 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
595 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
596 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
597 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
598 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
599 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
600 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
601 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
602 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
603 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
604 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
605 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
606 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
607 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
608 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
609 | //AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
610 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
611 | #define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
612 | |
613 | |
614 | // addressBlock: dce_dc_hda_azstream5_azdec |
615 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
616 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
617 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
618 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
619 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
620 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
621 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
622 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
623 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
624 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
625 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
626 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
627 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
628 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
629 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
630 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
631 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
632 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
633 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
634 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
635 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
636 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
637 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
638 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
639 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
640 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
641 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
642 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
643 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
644 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
645 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
646 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
647 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
648 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
649 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
650 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
651 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
652 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
653 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
654 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
655 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
656 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
657 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
658 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
659 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
660 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
661 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
662 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
663 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
664 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
665 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
666 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
667 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
668 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
669 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
670 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
671 | //AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
672 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
673 | #define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
674 | |
675 | |
676 | // addressBlock: dce_dc_hda_azstream6_azdec |
677 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
678 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
679 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
680 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
681 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
682 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
683 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
684 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
685 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
686 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
687 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
688 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
689 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
690 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
691 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
692 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
693 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
694 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
695 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
696 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
697 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
698 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
699 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
700 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
701 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
702 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
703 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
704 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
705 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
706 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
707 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
708 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
709 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
710 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
711 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
712 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
713 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
714 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
715 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
716 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
717 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
718 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
719 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
720 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
721 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
722 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
723 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
724 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
725 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
726 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
727 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
728 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
729 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
730 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
731 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
732 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
733 | //AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
734 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
735 | #define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
736 | |
737 | |
738 | // addressBlock: dce_dc_hda_azstream7_azdec |
739 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
740 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
741 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
742 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
743 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
744 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
745 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
746 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
747 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
748 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
749 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
750 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
751 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
752 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
753 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
754 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
755 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
756 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
757 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
758 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
759 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
760 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
761 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
762 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
763 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
764 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
765 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
766 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
767 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
768 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
769 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
770 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
771 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
772 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
773 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
774 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
775 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
776 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
777 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
778 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
779 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
780 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
781 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
782 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
783 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
784 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
785 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
786 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
787 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
788 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
789 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
790 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
791 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
792 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
793 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
794 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
795 | //AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
796 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
797 | #define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
798 | |
799 | |
800 | // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] |
801 | //VGA_MEM_WRITE_PAGE_ADDR |
802 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 |
803 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 |
804 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL |
805 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L |
806 | //VGA_MEM_READ_PAGE_ADDR |
807 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 |
808 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 |
809 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL |
810 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L |
811 | |
812 | |
813 | // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] |
814 | //CRTC8_IDX |
815 | #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 |
816 | #define CRTC8_IDX__VCRTC_IDX_MASK 0x3FL |
817 | //CRTC8_DATA |
818 | #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 |
819 | #define CRTC8_DATA__VCRTC_DATA_MASK 0xFFL |
820 | //GENFC_WT |
821 | #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 |
822 | #define GENFC_WT__VSYNC_SEL_W_MASK 0x08L |
823 | //GENS1 |
824 | #define GENS1__NO_DISPLAY__SHIFT 0x0 |
825 | #define GENS1__VGA_VSTATUS__SHIFT 0x3 |
826 | #define GENS1__PIXEL_READ_BACK__SHIFT 0x4 |
827 | #define GENS1__NO_DISPLAY_MASK 0x01L |
828 | #define GENS1__VGA_VSTATUS_MASK 0x08L |
829 | #define GENS1__PIXEL_READ_BACK_MASK 0x30L |
830 | //ATTRDW |
831 | #define ATTRDW__ATTR_DATA__SHIFT 0x0 |
832 | #define ATTRDW__ATTR_DATA_MASK 0xFFL |
833 | //ATTRX |
834 | #define ATTRX__ATTR_IDX__SHIFT 0x0 |
835 | #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 |
836 | #define ATTRX__ATTR_IDX_MASK 0x1FL |
837 | #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20L |
838 | //ATTRDR |
839 | #define ATTRDR__ATTR_DATA__SHIFT 0x0 |
840 | #define ATTRDR__ATTR_DATA_MASK 0xFFL |
841 | //GENMO_WT |
842 | #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
843 | #define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 |
844 | #define GENMO_WT__VGA_CKSEL__SHIFT 0x2 |
845 | #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
846 | #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 |
847 | #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 |
848 | #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x01L |
849 | #define GENMO_WT__VGA_RAM_EN_MASK 0x02L |
850 | #define GENMO_WT__VGA_CKSEL_MASK 0x0CL |
851 | #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20L |
852 | #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40L |
853 | #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80L |
854 | //GENS0 |
855 | #define GENS0__SENSE_SWITCH__SHIFT 0x4 |
856 | #define GENS0__CRT_INTR__SHIFT 0x7 |
857 | #define GENS0__SENSE_SWITCH_MASK 0x10L |
858 | #define GENS0__CRT_INTR_MASK 0x80L |
859 | //GENENB |
860 | #define GENENB__BLK_IO_BASE__SHIFT 0x0 |
861 | #define GENENB__BLK_IO_BASE_MASK 0xFFL |
862 | //SEQ8_IDX |
863 | #define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 |
864 | #define SEQ8_IDX__SEQ_IDX_MASK 0x07L |
865 | //SEQ8_DATA |
866 | #define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 |
867 | #define SEQ8_DATA__SEQ_DATA_MASK 0xFFL |
868 | //DAC_MASK |
869 | #define DAC_MASK__DAC_MASK__SHIFT 0x0 |
870 | #define DAC_MASK__DAC_MASK_MASK 0xFFL |
871 | //DAC_R_INDEX |
872 | #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 |
873 | #define DAC_R_INDEX__DAC_R_INDEX_MASK 0xFFL |
874 | //DAC_W_INDEX |
875 | #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 |
876 | #define DAC_W_INDEX__DAC_W_INDEX_MASK 0xFFL |
877 | //DAC_DATA |
878 | #define DAC_DATA__DAC_DATA__SHIFT 0x0 |
879 | #define DAC_DATA__DAC_DATA_MASK 0x3FL |
880 | //GENFC_RD |
881 | #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 |
882 | #define GENFC_RD__VSYNC_SEL_R_MASK 0x08L |
883 | //GENMO_RD |
884 | #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
885 | #define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 |
886 | #define GENMO_RD__VGA_CKSEL__SHIFT 0x2 |
887 | #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
888 | #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 |
889 | #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 |
890 | #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x01L |
891 | #define GENMO_RD__VGA_RAM_EN_MASK 0x02L |
892 | #define GENMO_RD__VGA_CKSEL_MASK 0x0CL |
893 | #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20L |
894 | #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40L |
895 | #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80L |
896 | //GRPH8_IDX |
897 | #define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 |
898 | #define GRPH8_IDX__GRPH_IDX_MASK 0x0FL |
899 | //GRPH8_DATA |
900 | #define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 |
901 | #define GRPH8_DATA__GRPH_DATA_MASK 0xFFL |
902 | //CRTC8_IDX_1 |
903 | #define CRTC8_IDX_1__VCRTC_IDX__SHIFT 0x0 |
904 | #define CRTC8_IDX_1__VCRTC_IDX_MASK 0x3FL |
905 | //CRTC8_DATA_1 |
906 | #define CRTC8_DATA_1__VCRTC_DATA__SHIFT 0x0 |
907 | #define CRTC8_DATA_1__VCRTC_DATA_MASK 0xFFL |
908 | //GENFC_WT_1 |
909 | #define GENFC_WT_1__VSYNC_SEL_W__SHIFT 0x3 |
910 | #define GENFC_WT_1__VSYNC_SEL_W_MASK 0x08L |
911 | //GENS1_1 |
912 | #define GENS1_1__NO_DISPLAY__SHIFT 0x0 |
913 | #define GENS1_1__VGA_VSTATUS__SHIFT 0x3 |
914 | #define GENS1_1__PIXEL_READ_BACK__SHIFT 0x4 |
915 | #define GENS1_1__NO_DISPLAY_MASK 0x01L |
916 | #define GENS1_1__VGA_VSTATUS_MASK 0x08L |
917 | #define GENS1_1__PIXEL_READ_BACK_MASK 0x30L |
918 | |
919 | |
920 | // addressBlock: dce_dc_hda_azcontroller_azdec |
921 | //CORB_WRITE_POINTER |
922 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 |
923 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL |
924 | //CORB_READ_POINTER |
925 | #define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 |
926 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf |
927 | #define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL |
928 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L |
929 | //CORB_CONTROL |
930 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 |
931 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 |
932 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L |
933 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L |
934 | //CORB_STATUS |
935 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 |
936 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L |
937 | //CORB_SIZE |
938 | #define CORB_SIZE__CORB_SIZE__SHIFT 0x0 |
939 | #define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 |
940 | #define CORB_SIZE__CORB_SIZE_MASK 0x0003L |
941 | #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L |
942 | //RIRB_LOWER_BASE_ADDRESS |
943 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
944 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
945 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
946 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
947 | //RIRB_UPPER_BASE_ADDRESS |
948 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
949 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
950 | //RIRB_WRITE_POINTER |
951 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 |
952 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf |
953 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL |
954 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L |
955 | //RESPONSE_INTERRUPT_COUNT |
956 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 |
957 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL |
958 | //RIRB_CONTROL |
959 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 |
960 | #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 |
961 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 |
962 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L |
963 | #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L |
964 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L |
965 | //RIRB_STATUS |
966 | #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 |
967 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 |
968 | #define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L |
969 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L |
970 | //RIRB_SIZE |
971 | #define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 |
972 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 |
973 | #define RIRB_SIZE__RIRB_SIZE_MASK 0x0003L |
974 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L |
975 | //IMMEDIATE_COMMAND_OUTPUT_INTERFACE |
976 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 |
977 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c |
978 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL |
979 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L |
980 | //IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
981 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
982 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
983 | //IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
984 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
985 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL |
986 | //IMMEDIATE_RESPONSE_INPUT_INTERFACE |
987 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 |
988 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL |
989 | //IMMEDIATE_COMMAND_STATUS |
990 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 |
991 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 |
992 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L |
993 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L |
994 | //DMA_POSITION_LOWER_BASE_ADDRESS |
995 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 |
996 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 |
997 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 |
998 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L |
999 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL |
1000 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1001 | //DMA_POSITION_UPPER_BASE_ADDRESS |
1002 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1003 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1004 | //WALL_CLOCK_COUNTER_ALIAS |
1005 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 |
1006 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL |
1007 | |
1008 | |
1009 | // addressBlock: dce_dc_hda_azendpoint_azdec |
1010 | //AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
1011 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1012 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
1013 | //AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
1014 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1015 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
1016 | |
1017 | |
1018 | // addressBlock: dce_dc_hda_azinputendpoint_azdec |
1019 | //AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA |
1020 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1021 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
1022 | //AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX |
1023 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1024 | #define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
1025 | |
1026 | |
1027 | // addressBlock: dce_dc_hda_azroot_azdec |
1028 | //AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA |
1029 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1030 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL |
1031 | //AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX |
1032 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
1033 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL |
1034 | |
1035 | |
1036 | // addressBlock: dce_dc_hda_azstream0_azdec |
1037 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1038 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1039 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1040 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1041 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1042 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1043 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1044 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1045 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1046 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1047 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1048 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1049 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1050 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1051 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1052 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1053 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1054 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1055 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1056 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1057 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1058 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1059 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1060 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1061 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1062 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1063 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1064 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1065 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1066 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1067 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1068 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1069 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1070 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1071 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1072 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1073 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1074 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1075 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1076 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1077 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1078 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1079 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1080 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1081 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1082 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1083 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1084 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1085 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1086 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1087 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1088 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1089 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1090 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1091 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1092 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1093 | //AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1094 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1095 | #define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1096 | |
1097 | |
1098 | // addressBlock: dce_dc_hda_azstream1_azdec |
1099 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1100 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1101 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1102 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1103 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1104 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1105 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1106 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1107 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1108 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1109 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1110 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1111 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1112 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1113 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1114 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1115 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1116 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1117 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1118 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1119 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1120 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1121 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1122 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1123 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1124 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1125 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1126 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1127 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1128 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1129 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1130 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1131 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1132 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1133 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1134 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1135 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1136 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1137 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1138 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1139 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1140 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1141 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1142 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1143 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1144 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1145 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1146 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1147 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1148 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1149 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1150 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1151 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1152 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1153 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1154 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1155 | //AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1156 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1157 | #define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1158 | |
1159 | |
1160 | // addressBlock: dce_dc_hda_azstream2_azdec |
1161 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1162 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1163 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1164 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1165 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1166 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1167 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1168 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1169 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1170 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1171 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1172 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1173 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1174 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1175 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1176 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1177 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1178 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1179 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1180 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1181 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1182 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1183 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1184 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1185 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1186 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1187 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1188 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1189 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1190 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1191 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1192 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1193 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1194 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1195 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1196 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1197 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1198 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1199 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1200 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1201 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1202 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1203 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1204 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1205 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1206 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1207 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1208 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1209 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1210 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1211 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1212 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1213 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1214 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1215 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1216 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1217 | //AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1218 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1219 | #define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1220 | |
1221 | |
1222 | // addressBlock: dce_dc_hda_azstream3_azdec |
1223 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1224 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1225 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1226 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1227 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1228 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1229 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1230 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1231 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1232 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1233 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1234 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1235 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1236 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1237 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1238 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1239 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1240 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1241 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1242 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1243 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1244 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1245 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1246 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1247 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1248 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1249 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1250 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1251 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1252 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1253 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1254 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1255 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1256 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1257 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1258 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1259 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1260 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1261 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1262 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1263 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1264 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1265 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1266 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1267 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1268 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1269 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1270 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1271 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1272 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1273 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1274 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1275 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1276 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1277 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1278 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1279 | //AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1280 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1281 | #define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1282 | |
1283 | |
1284 | // addressBlock: dce_dc_hda_azstream4_azdec |
1285 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1286 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1287 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1288 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1289 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1290 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1291 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1292 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1293 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1294 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1295 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1296 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1297 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1298 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1299 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1300 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1301 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1302 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1303 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1304 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1305 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1306 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1307 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1308 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1309 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1310 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1311 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1312 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1313 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1314 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1315 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1316 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1317 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1318 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1319 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1320 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1321 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1322 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1323 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1324 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1325 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1326 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1327 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1328 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1329 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1330 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1331 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1332 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1333 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1334 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1335 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1336 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1337 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1338 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1339 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1340 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1341 | //AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1342 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1343 | #define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1344 | |
1345 | |
1346 | // addressBlock: dce_dc_hda_azstream5_azdec |
1347 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1348 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1349 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1350 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1351 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1352 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1353 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1354 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1355 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1356 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1357 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1358 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1359 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1360 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1361 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1362 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1363 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1364 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1365 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1366 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1367 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1368 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1369 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1370 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1371 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1372 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1373 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1374 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1375 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1376 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1377 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1378 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1379 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1380 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1381 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1382 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1383 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1384 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1385 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1386 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1387 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1388 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1389 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1390 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1391 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1392 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1393 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1394 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1395 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1396 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1397 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1398 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1399 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1400 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1401 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1402 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1403 | //AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1404 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1405 | #define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1406 | |
1407 | |
1408 | // addressBlock: dce_dc_hda_azstream6_azdec |
1409 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1410 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1411 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1412 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1413 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1414 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1415 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1416 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1417 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1418 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1419 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1420 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1421 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1422 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1423 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1424 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1425 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1426 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1427 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1428 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1429 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1430 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1431 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1432 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1433 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1434 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1435 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1436 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1437 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1438 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1439 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1440 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1441 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1442 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1443 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1444 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1445 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1446 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1447 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1448 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1449 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1450 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1451 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1452 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1453 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1454 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1455 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1456 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1457 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1458 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1459 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1460 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1461 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1462 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1463 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1464 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1465 | //AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1466 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1467 | #define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1468 | |
1469 | |
1470 | // addressBlock: dce_dc_hda_azstream7_azdec |
1471 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS |
1472 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
1473 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
1474 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
1475 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
1476 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
1477 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
1478 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
1479 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
1480 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
1481 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
1482 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
1483 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
1484 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L |
1485 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L |
1486 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L |
1487 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L |
1488 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L |
1489 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L |
1490 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L |
1491 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L |
1492 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L |
1493 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L |
1494 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L |
1495 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L |
1496 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER |
1497 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
1498 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL |
1499 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH |
1500 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
1501 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL |
1502 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX |
1503 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
1504 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL |
1505 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE |
1506 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
1507 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL |
1508 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT |
1509 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
1510 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
1511 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
1512 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
1513 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
1514 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL |
1515 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L |
1516 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L |
1517 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L |
1518 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L |
1519 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS |
1520 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
1521 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
1522 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL |
1523 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L |
1524 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS |
1525 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
1526 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1527 | //AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS |
1528 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
1529 | #define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL |
1530 | |
1531 | |
1532 | // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] |
1533 | |
1534 | |
1535 | // addressBlock: dce_dc_mmhubbub_vga_dispdec |
1536 | //VGA_RENDER_CONTROL |
1537 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 |
1538 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 |
1539 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 |
1540 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 |
1541 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 |
1542 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 |
1543 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 |
1544 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL |
1545 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L |
1546 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L |
1547 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L |
1548 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L |
1549 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L |
1550 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L |
1551 | //VGA_SEQUENCER_RESET_CONTROL |
1552 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 |
1553 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 |
1554 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 |
1555 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 |
1556 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 |
1557 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 |
1558 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 |
1559 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 |
1560 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa |
1561 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb |
1562 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc |
1563 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd |
1564 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 |
1565 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 |
1566 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 |
1567 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L |
1568 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L |
1569 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L |
1570 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L |
1571 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L |
1572 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L |
1573 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L |
1574 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L |
1575 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L |
1576 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L |
1577 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L |
1578 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L |
1579 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L |
1580 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L |
1581 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L |
1582 | //VGA_MODE_CONTROL |
1583 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 |
1584 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 |
1585 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 |
1586 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 |
1587 | #define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 |
1588 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L |
1589 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L |
1590 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L |
1591 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L |
1592 | #define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L |
1593 | //VGA_SURFACE_PITCH_SELECT |
1594 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 |
1595 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 |
1596 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L |
1597 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L |
1598 | //VGA_MEMORY_BASE_ADDRESS |
1599 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 |
1600 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL |
1601 | //VGA_DISPBUF1_SURFACE_ADDR |
1602 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 |
1603 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL |
1604 | //VGA_DISPBUF2_SURFACE_ADDR |
1605 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 |
1606 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL |
1607 | //VGA_MEMORY_BASE_ADDRESS_HIGH |
1608 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 |
1609 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000FFL |
1610 | //VGA_HDP_CONTROL |
1611 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 |
1612 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 |
1613 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 |
1614 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 |
1615 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 |
1616 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L |
1617 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L |
1618 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L |
1619 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L |
1620 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L |
1621 | //VGA_CACHE_CONTROL |
1622 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 |
1623 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 |
1624 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 |
1625 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 |
1626 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 |
1627 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L |
1628 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L |
1629 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L |
1630 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L |
1631 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L |
1632 | //D1VGA_CONTROL |
1633 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 |
1634 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 |
1635 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1636 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1637 | #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 |
1638 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L |
1639 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L |
1640 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1641 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1642 | #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L |
1643 | //D2VGA_CONTROL |
1644 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 |
1645 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 |
1646 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1647 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1648 | #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 |
1649 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L |
1650 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L |
1651 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1652 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1653 | #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L |
1654 | //VGA_STATUS |
1655 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 |
1656 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 |
1657 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 |
1658 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 |
1659 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L |
1660 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L |
1661 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L |
1662 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L |
1663 | //VGA_INTERRUPT_CONTROL |
1664 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 |
1665 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 |
1666 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 |
1667 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 |
1668 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L |
1669 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L |
1670 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L |
1671 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L |
1672 | //VGA_STATUS_CLEAR |
1673 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 |
1674 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 |
1675 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 |
1676 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 |
1677 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L |
1678 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L |
1679 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L |
1680 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L |
1681 | //VGA_INTERRUPT_STATUS |
1682 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 |
1683 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 |
1684 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 |
1685 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 |
1686 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L |
1687 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L |
1688 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L |
1689 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L |
1690 | //VGA_MAIN_CONTROL |
1691 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 |
1692 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 |
1693 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 |
1694 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 |
1695 | #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc |
1696 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 |
1697 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 |
1698 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a |
1699 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d |
1700 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f |
1701 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L |
1702 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L |
1703 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L |
1704 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L |
1705 | #define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L |
1706 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L |
1707 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L |
1708 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L |
1709 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L |
1710 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L |
1711 | //VGA_TEST_CONTROL |
1712 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 |
1713 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 |
1714 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 |
1715 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 |
1716 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L |
1717 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L |
1718 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L |
1719 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L |
1720 | //VGA_QOS_CTRL |
1721 | #define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 |
1722 | #define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 |
1723 | #define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL |
1724 | #define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L |
1725 | //D3VGA_CONTROL |
1726 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 |
1727 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 |
1728 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1729 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1730 | #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 |
1731 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L |
1732 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L |
1733 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1734 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1735 | #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L |
1736 | //D4VGA_CONTROL |
1737 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 |
1738 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 |
1739 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1740 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1741 | #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 |
1742 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L |
1743 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L |
1744 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1745 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1746 | #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L |
1747 | //D5VGA_CONTROL |
1748 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 |
1749 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 |
1750 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1751 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1752 | #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 |
1753 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L |
1754 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L |
1755 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1756 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1757 | #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L |
1758 | //D6VGA_CONTROL |
1759 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 |
1760 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 |
1761 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
1762 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
1763 | #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 |
1764 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L |
1765 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L |
1766 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L |
1767 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L |
1768 | #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L |
1769 | //VGA_SOURCE_SELECT |
1770 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 |
1771 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 |
1772 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L |
1773 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L |
1774 | |
1775 | |
1776 | // addressBlock: dce_dc_dccg_dccg_dispdec |
1777 | //PHYPLLA_PIXCLK_RESYNC_CNTL |
1778 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1779 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1780 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 |
1781 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1782 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1783 | #define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L |
1784 | //PHYPLLB_PIXCLK_RESYNC_CNTL |
1785 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1786 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1787 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 |
1788 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1789 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1790 | #define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L |
1791 | //PHYPLLC_PIXCLK_RESYNC_CNTL |
1792 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1793 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1794 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 |
1795 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1796 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1797 | #define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L |
1798 | //PHYPLLD_PIXCLK_RESYNC_CNTL |
1799 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1800 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1801 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 |
1802 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1803 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1804 | #define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L |
1805 | //DP_DTO_DBUF_EN |
1806 | #define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 |
1807 | #define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 |
1808 | #define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 |
1809 | #define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 |
1810 | #define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 |
1811 | #define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 |
1812 | #define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 |
1813 | #define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 |
1814 | #define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L |
1815 | #define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L |
1816 | #define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L |
1817 | #define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L |
1818 | #define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L |
1819 | #define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L |
1820 | #define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L |
1821 | #define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L |
1822 | //DPREFCLK_CGTT_BLK_CTRL_REG |
1823 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 |
1824 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
1825 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL |
1826 | #define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
1827 | //REFCLK_CNTL |
1828 | #define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 |
1829 | #define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 |
1830 | #define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L |
1831 | #define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L |
1832 | //MIPI_CLK_CNTL |
1833 | #define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE__SHIFT 0x0 |
1834 | #define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE__SHIFT 0x1 |
1835 | #define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE__SHIFT 0x2 |
1836 | #define MIPI_CLK_CNTL__DSICLK_CLOCK_ENABLE_MASK 0x00000001L |
1837 | #define MIPI_CLK_CNTL__BYTECLK_CLOCK_ENABLE_MASK 0x00000002L |
1838 | #define MIPI_CLK_CNTL__ESCCLK_CLOCK_ENABLE_MASK 0x00000004L |
1839 | //REFCLK_CGTT_BLK_CTRL_REG |
1840 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 |
1841 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
1842 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL |
1843 | #define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
1844 | //PHYPLLE_PIXCLK_RESYNC_CNTL |
1845 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1846 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1847 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 |
1848 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1849 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1850 | #define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L |
1851 | //DCCG_PERFMON_CNTL2 |
1852 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 |
1853 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 |
1854 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 |
1855 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 |
1856 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 |
1857 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 |
1858 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 |
1859 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 |
1860 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 |
1861 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L |
1862 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L |
1863 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L |
1864 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L |
1865 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L |
1866 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L |
1867 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L |
1868 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L |
1869 | #define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L |
1870 | //DSICLK_CGTT_BLK_CTRL_REG |
1871 | #define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY__SHIFT 0x0 |
1872 | #define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY__SHIFT 0x4 |
1873 | #define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_ON_DELAY_MASK 0x0000000FL |
1874 | #define DSICLK_CGTT_BLK_CTRL_REG__DSICLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
1875 | //DCCG_CBUS_WRCMD_DELAY |
1876 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 |
1877 | #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0x0000000FL |
1878 | //DCCG_DS_DTO_INCR |
1879 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 |
1880 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL |
1881 | //DCCG_DS_DTO_MODULO |
1882 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 |
1883 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL |
1884 | //DCCG_DS_CNTL |
1885 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 |
1886 | #define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 |
1887 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 |
1888 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 |
1889 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 |
1890 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 |
1891 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 |
1892 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L |
1893 | #define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L |
1894 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L |
1895 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L |
1896 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L |
1897 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L |
1898 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L |
1899 | //DCCG_DS_HW_CAL_INTERVAL |
1900 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 |
1901 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL |
1902 | //SYMCLKG_CLOCK_ENABLE |
1903 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 |
1904 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 |
1905 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 |
1906 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x00000001L |
1907 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x00000010L |
1908 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x00000700L |
1909 | //DPREFCLK_CNTL |
1910 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 |
1911 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 |
1912 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L |
1913 | #define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x00000100L |
1914 | //AOMCLK0_CNTL |
1915 | #define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN__SHIFT 0x0 |
1916 | #define AOMCLK0_CNTL__AOMCLK0_CLOCK_EN_MASK 0x00000001L |
1917 | //AOMCLK1_CNTL |
1918 | #define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN__SHIFT 0x0 |
1919 | #define AOMCLK1_CNTL__AOMCLK1_CLOCK_EN_MASK 0x00000001L |
1920 | //AOMCLK2_CNTL |
1921 | #define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN__SHIFT 0x0 |
1922 | #define AOMCLK2_CNTL__AOMCLK2_CLOCK_EN_MASK 0x00000001L |
1923 | //DCCG_AUDIO_DTO2_PHASE |
1924 | #define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE__SHIFT 0x0 |
1925 | #define DCCG_AUDIO_DTO2_PHASE__DCCG_AUDIO_DTO2_PHASE_MASK 0xFFFFFFFFL |
1926 | //DCCG_AUDIO_DTO2_MODULO |
1927 | #define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO__SHIFT 0x0 |
1928 | #define DCCG_AUDIO_DTO2_MODULO__DCCG_AUDIO_DTO2_MODULO_MASK 0xFFFFFFFFL |
1929 | //DCE_VERSION |
1930 | #define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 |
1931 | #define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 |
1932 | #define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL |
1933 | #define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L |
1934 | //PHYPLLG_PIXCLK_RESYNC_CNTL |
1935 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
1936 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
1937 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8 |
1938 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
1939 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
1940 | #define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L |
1941 | //DCCG_GTC_CNTL |
1942 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 |
1943 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L |
1944 | //DCCG_GTC_DTO_INCR |
1945 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 |
1946 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL |
1947 | //DCCG_GTC_DTO_MODULO |
1948 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 |
1949 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL |
1950 | //DCCG_GTC_CURRENT |
1951 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 |
1952 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL |
1953 | //MIPI_DTO_CNTL |
1954 | #define MIPI_DTO_CNTL__MIPI_DTO_ENABLE__SHIFT 0x0 |
1955 | #define MIPI_DTO_CNTL__MIPI_DTO_ENABLE_MASK 0x00000001L |
1956 | //MIPI_DTO_PHASE |
1957 | #define MIPI_DTO_PHASE__MIPI_DTO_PHASE__SHIFT 0x0 |
1958 | #define MIPI_DTO_PHASE__MIPI_DTO_PHASE_MASK 0xFFFFFFFFL |
1959 | //MIPI_DTO_MODULO |
1960 | #define MIPI_DTO_MODULO__MIPI_DTO_MODULO__SHIFT 0x0 |
1961 | #define MIPI_DTO_MODULO__MIPI_DTO_MODULO_MASK 0xFFFFFFFFL |
1962 | //DAC_CLK_ENABLE |
1963 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 |
1964 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L |
1965 | //DVO_CLK_ENABLE |
1966 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 |
1967 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L |
1968 | //AVSYNC_COUNTER_WRITE |
1969 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 |
1970 | #define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xFFFFFFFFL |
1971 | //AVSYNC_COUNTER_CONTROL |
1972 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 |
1973 | #define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x00000001L |
1974 | //AVSYNC_COUNTER_READ |
1975 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 |
1976 | #define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xFFFFFFFFL |
1977 | //MILLISECOND_TIME_BASE_DIV |
1978 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 |
1979 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
1980 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL |
1981 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L |
1982 | //DISPCLK_FREQ_CHANGE_CNTL |
1983 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 |
1984 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 |
1985 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 |
1986 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 |
1987 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c |
1988 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d |
1989 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e |
1990 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f |
1991 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL |
1992 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L |
1993 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L |
1994 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L |
1995 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L |
1996 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L |
1997 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L |
1998 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L |
1999 | //DC_MEM_GLOBAL_PWR_REQ_CNTL |
2000 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 |
2001 | #define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L |
2002 | //DCCG_PERFMON_CNTL |
2003 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 |
2004 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 |
2005 | #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 |
2006 | #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 |
2007 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 |
2008 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 |
2009 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 |
2010 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 |
2011 | #define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 |
2012 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb |
2013 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L |
2014 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L |
2015 | #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L |
2016 | #define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L |
2017 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L |
2018 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L |
2019 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L |
2020 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L |
2021 | #define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L |
2022 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L |
2023 | //DCCG_GATE_DISABLE_CNTL |
2024 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 |
2025 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 |
2026 | #define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 |
2027 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 |
2028 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 |
2029 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 |
2030 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 |
2031 | #define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 |
2032 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 |
2033 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 |
2034 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 |
2035 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 |
2036 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 |
2037 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 |
2038 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a |
2039 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b |
2040 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c |
2041 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d |
2042 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e |
2043 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L |
2044 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L |
2045 | #define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L |
2046 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L |
2047 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L |
2048 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L |
2049 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L |
2050 | #define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L |
2051 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L |
2052 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L |
2053 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L |
2054 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L |
2055 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L |
2056 | #define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x00800000L |
2057 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L |
2058 | #define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L |
2059 | #define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L |
2060 | #define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L |
2061 | #define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L |
2062 | //DISPCLK_CGTT_BLK_CTRL_REG |
2063 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 |
2064 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 |
2065 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL |
2066 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
2067 | //SOCCLK_CGTT_BLK_CTRL_REG |
2068 | #define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 |
2069 | #define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 |
2070 | #define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL |
2071 | #define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
2072 | //DCCG_CAC_STATUS |
2073 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 |
2074 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL |
2075 | //PIXCLK1_RESYNC_CNTL |
2076 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 |
2077 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 |
2078 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L |
2079 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L |
2080 | //PIXCLK2_RESYNC_CNTL |
2081 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 |
2082 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 |
2083 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L |
2084 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L |
2085 | //PIXCLK0_RESYNC_CNTL |
2086 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 |
2087 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 |
2088 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L |
2089 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L |
2090 | //MICROSECOND_TIME_BASE_DIV |
2091 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 |
2092 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 |
2093 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 |
2094 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 |
2095 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
2096 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL |
2097 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L |
2098 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L |
2099 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L |
2100 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L |
2101 | //DCCG_GATE_DISABLE_CNTL2 |
2102 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 |
2103 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 |
2104 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 |
2105 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 |
2106 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 |
2107 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 |
2108 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 |
2109 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 |
2110 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 |
2111 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 |
2112 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 |
2113 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 |
2114 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 |
2115 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 |
2116 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L |
2117 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L |
2118 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L |
2119 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L |
2120 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L |
2121 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L |
2122 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L |
2123 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L |
2124 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L |
2125 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L |
2126 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L |
2127 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L |
2128 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L |
2129 | #define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L |
2130 | //SYMCLK_CGTT_BLK_CTRL_REG |
2131 | #define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 |
2132 | #define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 |
2133 | #define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL |
2134 | #define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
2135 | //PHYPLLF_PIXCLK_RESYNC_CNTL |
2136 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 |
2137 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 |
2138 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8 |
2139 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L |
2140 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L |
2141 | #define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L |
2142 | //DCCG_DISP_CNTL_REG |
2143 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 |
2144 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L |
2145 | //OTG0_PIXEL_RATE_CNTL |
2146 | #define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2147 | #define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 |
2148 | #define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 |
2149 | #define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 |
2150 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 |
2151 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2152 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2153 | #define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2154 | #define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L |
2155 | #define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L |
2156 | #define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L |
2157 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L |
2158 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2159 | #define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2160 | //DP_DTO0_PHASE |
2161 | #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 |
2162 | #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL |
2163 | //DP_DTO0_MODULO |
2164 | #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 |
2165 | #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL |
2166 | //OTG0_PHYPLL_PIXEL_RATE_CNTL |
2167 | #define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2168 | #define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2169 | #define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2170 | #define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2171 | //OTG1_PIXEL_RATE_CNTL |
2172 | #define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2173 | #define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 |
2174 | #define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 |
2175 | #define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 |
2176 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 |
2177 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2178 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2179 | #define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2180 | #define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L |
2181 | #define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L |
2182 | #define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L |
2183 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L |
2184 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2185 | #define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2186 | //DP_DTO1_PHASE |
2187 | #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 |
2188 | #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL |
2189 | //DP_DTO1_MODULO |
2190 | #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 |
2191 | #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL |
2192 | //OTG1_PHYPLL_PIXEL_RATE_CNTL |
2193 | #define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2194 | #define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2195 | #define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2196 | #define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2197 | //OTG2_PIXEL_RATE_CNTL |
2198 | #define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2199 | #define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 |
2200 | #define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 |
2201 | #define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 |
2202 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 |
2203 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2204 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2205 | #define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2206 | #define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L |
2207 | #define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L |
2208 | #define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L |
2209 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L |
2210 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2211 | #define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2212 | //DP_DTO2_PHASE |
2213 | #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 |
2214 | #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL |
2215 | //DP_DTO2_MODULO |
2216 | #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 |
2217 | #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL |
2218 | //OTG2_PHYPLL_PIXEL_RATE_CNTL |
2219 | #define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2220 | #define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2221 | #define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2222 | #define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2223 | //OTG3_PIXEL_RATE_CNTL |
2224 | #define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2225 | #define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 |
2226 | #define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 |
2227 | #define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 |
2228 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 |
2229 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2230 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2231 | #define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2232 | #define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L |
2233 | #define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L |
2234 | #define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L |
2235 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L |
2236 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2237 | #define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2238 | //DP_DTO3_PHASE |
2239 | #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 |
2240 | #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL |
2241 | //DP_DTO3_MODULO |
2242 | #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 |
2243 | #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL |
2244 | //OTG3_PHYPLL_PIXEL_RATE_CNTL |
2245 | #define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2246 | #define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2247 | #define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2248 | #define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2249 | //OTG4_PIXEL_RATE_CNTL |
2250 | #define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2251 | #define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 |
2252 | #define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 |
2253 | #define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL__SHIFT 0x8 |
2254 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL__SHIFT 0x9 |
2255 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2256 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2257 | #define OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2258 | #define OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L |
2259 | #define OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x00000020L |
2260 | #define OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL_MASK 0x00000100L |
2261 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL_MASK 0x00000200L |
2262 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2263 | #define OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2264 | //DP_DTO4_PHASE |
2265 | #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 |
2266 | #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xFFFFFFFFL |
2267 | //DP_DTO4_MODULO |
2268 | #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 |
2269 | #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xFFFFFFFFL |
2270 | //OTG4_PHYPLL_PIXEL_RATE_CNTL |
2271 | #define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2272 | #define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2273 | #define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2274 | #define OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2275 | //OTG5_PIXEL_RATE_CNTL |
2276 | #define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2277 | #define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 |
2278 | #define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 |
2279 | #define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL__SHIFT 0x8 |
2280 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL__SHIFT 0x9 |
2281 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR__SHIFT 0xe |
2282 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
2283 | #define OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE_MASK 0x00000003L |
2284 | #define OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L |
2285 | #define OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x00000020L |
2286 | #define OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL_MASK 0x00000100L |
2287 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL_MASK 0x00000200L |
2288 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR_MASK 0x0000C000L |
2289 | #define OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT_MASK 0x0FFF0000L |
2290 | //DP_DTO5_PHASE |
2291 | #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 |
2292 | #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xFFFFFFFFL |
2293 | //DP_DTO5_MODULO |
2294 | #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 |
2295 | #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xFFFFFFFFL |
2296 | //OTG5_PHYPLL_PIXEL_RATE_CNTL |
2297 | #define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 |
2298 | #define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 |
2299 | #define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L |
2300 | #define OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L |
2301 | //DPPCLK_CGTT_BLK_CTRL_REG |
2302 | #define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 |
2303 | #define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 |
2304 | #define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL |
2305 | #define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
2306 | //SYMCLKA_CLOCK_ENABLE |
2307 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 |
2308 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 |
2309 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 |
2310 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L |
2311 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L |
2312 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L |
2313 | //SYMCLKB_CLOCK_ENABLE |
2314 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 |
2315 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 |
2316 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 |
2317 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L |
2318 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L |
2319 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L |
2320 | //SYMCLKC_CLOCK_ENABLE |
2321 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 |
2322 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 |
2323 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 |
2324 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L |
2325 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L |
2326 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L |
2327 | //SYMCLKD_CLOCK_ENABLE |
2328 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 |
2329 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 |
2330 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 |
2331 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L |
2332 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L |
2333 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L |
2334 | //SYMCLKE_CLOCK_ENABLE |
2335 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 |
2336 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 |
2337 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 |
2338 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L |
2339 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L |
2340 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L |
2341 | //SYMCLKF_CLOCK_ENABLE |
2342 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 |
2343 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 |
2344 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 |
2345 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L |
2346 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L |
2347 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L |
2348 | //DCCG_SOFT_RESET |
2349 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 |
2350 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 |
2351 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 |
2352 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 |
2353 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 |
2354 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 |
2355 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc |
2356 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd |
2357 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe |
2358 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf |
2359 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 |
2360 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 |
2361 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 |
2362 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 |
2363 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 |
2364 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 |
2365 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L |
2366 | #define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L |
2367 | #define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L |
2368 | #define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L |
2369 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L |
2370 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L |
2371 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L |
2372 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L |
2373 | #define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L |
2374 | #define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L |
2375 | #define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L |
2376 | #define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L |
2377 | #define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L |
2378 | #define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L |
2379 | #define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L |
2380 | #define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L |
2381 | //DVOACLKD_CNTL |
2382 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 |
2383 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 |
2384 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 |
2385 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 |
2386 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 |
2387 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L |
2388 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001F00L |
2389 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L |
2390 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L |
2391 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L |
2392 | //DVOACLKC_MVP_CNTL |
2393 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 |
2394 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 |
2395 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 |
2396 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 |
2397 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 |
2398 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 |
2399 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L |
2400 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001F00L |
2401 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L |
2402 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L |
2403 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L |
2404 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L |
2405 | //DVOACLKC_CNTL |
2406 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 |
2407 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 |
2408 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 |
2409 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 |
2410 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 |
2411 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L |
2412 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001F00L |
2413 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L |
2414 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L |
2415 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L |
2416 | //DCCG_AUDIO_DTO_SOURCE |
2417 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 |
2418 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 |
2419 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc |
2420 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 |
2421 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 |
2422 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 |
2423 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c |
2424 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L |
2425 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L |
2426 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L |
2427 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L |
2428 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L |
2429 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L |
2430 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L |
2431 | //DCCG_AUDIO_DTO0_PHASE |
2432 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 |
2433 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL |
2434 | //DCCG_AUDIO_DTO0_MODULE |
2435 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 |
2436 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL |
2437 | //DCCG_AUDIO_DTO1_PHASE |
2438 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 |
2439 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL |
2440 | //DCCG_AUDIO_DTO1_MODULE |
2441 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 |
2442 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL |
2443 | //DCCG_VSYNC_OTG0_LATCH_VALUE |
2444 | #define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 |
2445 | #define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL |
2446 | //DCCG_VSYNC_OTG1_LATCH_VALUE |
2447 | #define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 |
2448 | #define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL |
2449 | //DCCG_VSYNC_OTG2_LATCH_VALUE |
2450 | #define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 |
2451 | #define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL |
2452 | //DCCG_VSYNC_OTG3_LATCH_VALUE |
2453 | #define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 |
2454 | #define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL |
2455 | //DCCG_VSYNC_OTG4_LATCH_VALUE |
2456 | #define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 |
2457 | #define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL |
2458 | //DCCG_VSYNC_OTG5_LATCH_VALUE |
2459 | #define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 |
2460 | #define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL |
2461 | //DCCG_VSYNC_CNT_CTRL |
2462 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 |
2463 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1 |
2464 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 |
2465 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 |
2466 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 |
2467 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 |
2468 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 |
2469 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 |
2470 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 |
2471 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 |
2472 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 |
2473 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 |
2474 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 |
2475 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 |
2476 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a |
2477 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b |
2478 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c |
2479 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d |
2480 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L |
2481 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L |
2482 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L |
2483 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L |
2484 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L |
2485 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L |
2486 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L |
2487 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L |
2488 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L |
2489 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L |
2490 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L |
2491 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L |
2492 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L |
2493 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L |
2494 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L |
2495 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L |
2496 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L |
2497 | #define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L |
2498 | //DCCG_VSYNC_CNT_INT_CTRL |
2499 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 |
2500 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 |
2501 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 |
2502 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 |
2503 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 |
2504 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 |
2505 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 |
2506 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 |
2507 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 |
2508 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 |
2509 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 |
2510 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 |
2511 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 |
2512 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 |
2513 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa |
2514 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb |
2515 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc |
2516 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd |
2517 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L |
2518 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L |
2519 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L |
2520 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L |
2521 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L |
2522 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L |
2523 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L |
2524 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L |
2525 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L |
2526 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L |
2527 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L |
2528 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L |
2529 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L |
2530 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L |
2531 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L |
2532 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L |
2533 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L |
2534 | #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L |
2535 | //DCCG_TEST_CLK_SEL |
2536 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 |
2537 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc |
2538 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 |
2539 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c |
2540 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL |
2541 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L |
2542 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L |
2543 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L |
2544 | |
2545 | |
2546 | // addressBlock: dce_dc_dccg_dccg_dfs_dispdec |
2547 | //DENTIST_DISPCLK_CNTL |
2548 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 |
2549 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 |
2550 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf |
2551 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 |
2552 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 |
2553 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 |
2554 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 |
2555 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 |
2556 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 |
2557 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 |
2558 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL |
2559 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L |
2560 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L |
2561 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L |
2562 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L |
2563 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L |
2564 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L |
2565 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L |
2566 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L |
2567 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7F000000L |
2568 | |
2569 | |
2570 | // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec |
2571 | //DC_PERFMON0_PERFCOUNTER_CNTL |
2572 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
2573 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
2574 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
2575 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
2576 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
2577 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
2578 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
2579 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
2580 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
2581 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
2582 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
2583 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
2584 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
2585 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
2586 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
2587 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
2588 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
2589 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
2590 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
2591 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
2592 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
2593 | #define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
2594 | //DC_PERFMON0_PERFCOUNTER_CNTL2 |
2595 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
2596 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
2597 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
2598 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
2599 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
2600 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
2601 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
2602 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
2603 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
2604 | #define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
2605 | //DC_PERFMON0_PERFCOUNTER_STATE |
2606 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
2607 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
2608 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
2609 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
2610 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
2611 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
2612 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
2613 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
2614 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
2615 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
2616 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
2617 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
2618 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
2619 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
2620 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
2621 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
2622 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
2623 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
2624 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
2625 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
2626 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
2627 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
2628 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
2629 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
2630 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
2631 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
2632 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
2633 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
2634 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
2635 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
2636 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
2637 | #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
2638 | //DC_PERFMON0_PERFMON_CNTL |
2639 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
2640 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
2641 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
2642 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
2643 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
2644 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
2645 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
2646 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
2647 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
2648 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
2649 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
2650 | #define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
2651 | //DC_PERFMON0_PERFMON_CNTL2 |
2652 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
2653 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
2654 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
2655 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
2656 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
2657 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
2658 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
2659 | #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
2660 | //DC_PERFMON0_PERFMON_CVALUE_INT_MISC |
2661 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
2662 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
2663 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
2664 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
2665 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
2666 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
2667 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
2668 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
2669 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
2670 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
2671 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
2672 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
2673 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
2674 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
2675 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
2676 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
2677 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
2678 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
2679 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
2680 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
2681 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
2682 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
2683 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
2684 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
2685 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
2686 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
2687 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
2688 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
2689 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
2690 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
2691 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
2692 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
2693 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
2694 | #define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
2695 | //DC_PERFMON0_PERFMON_CVALUE_LOW |
2696 | #define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
2697 | #define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
2698 | //DC_PERFMON0_PERFMON_HI |
2699 | #define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
2700 | #define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
2701 | #define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
2702 | #define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
2703 | //DC_PERFMON0_PERFMON_LOW |
2704 | #define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
2705 | #define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
2706 | |
2707 | |
2708 | // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec |
2709 | //DC_PERFMON1_PERFCOUNTER_CNTL |
2710 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
2711 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
2712 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
2713 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
2714 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
2715 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
2716 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
2717 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
2718 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
2719 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
2720 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
2721 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
2722 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
2723 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
2724 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
2725 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
2726 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
2727 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
2728 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
2729 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
2730 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
2731 | #define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
2732 | //DC_PERFMON1_PERFCOUNTER_CNTL2 |
2733 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
2734 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
2735 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
2736 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
2737 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
2738 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
2739 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
2740 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
2741 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
2742 | #define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
2743 | //DC_PERFMON1_PERFCOUNTER_STATE |
2744 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
2745 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
2746 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
2747 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
2748 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
2749 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
2750 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
2751 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
2752 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
2753 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
2754 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
2755 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
2756 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
2757 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
2758 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
2759 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
2760 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
2761 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
2762 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
2763 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
2764 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
2765 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
2766 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
2767 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
2768 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
2769 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
2770 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
2771 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
2772 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
2773 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
2774 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
2775 | #define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
2776 | //DC_PERFMON1_PERFMON_CNTL |
2777 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
2778 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
2779 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
2780 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
2781 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
2782 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
2783 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
2784 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
2785 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
2786 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
2787 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
2788 | #define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
2789 | //DC_PERFMON1_PERFMON_CNTL2 |
2790 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
2791 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
2792 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
2793 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
2794 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
2795 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
2796 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
2797 | #define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
2798 | //DC_PERFMON1_PERFMON_CVALUE_INT_MISC |
2799 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
2800 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
2801 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
2802 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
2803 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
2804 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
2805 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
2806 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
2807 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
2808 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
2809 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
2810 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
2811 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
2812 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
2813 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
2814 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
2815 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
2816 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
2817 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
2818 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
2819 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
2820 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
2821 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
2822 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
2823 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
2824 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
2825 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
2826 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
2827 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
2828 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
2829 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
2830 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
2831 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
2832 | #define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
2833 | //DC_PERFMON1_PERFMON_CVALUE_LOW |
2834 | #define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
2835 | #define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
2836 | //DC_PERFMON1_PERFMON_HI |
2837 | #define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
2838 | #define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
2839 | #define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
2840 | #define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
2841 | //DC_PERFMON1_PERFMON_LOW |
2842 | #define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
2843 | #define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
2844 | |
2845 | |
2846 | // addressBlock: dce_dc_dccg_dccg_pll_dispdec |
2847 | //PLL_MACRO_CNTL_RESERVED0 |
2848 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2849 | #define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2850 | //PLL_MACRO_CNTL_RESERVED1 |
2851 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2852 | #define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2853 | //PLL_MACRO_CNTL_RESERVED2 |
2854 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2855 | #define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2856 | //PLL_MACRO_CNTL_RESERVED3 |
2857 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2858 | #define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2859 | //PLL_MACRO_CNTL_RESERVED4 |
2860 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2861 | #define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2862 | //PLL_MACRO_CNTL_RESERVED5 |
2863 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2864 | #define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2865 | //PLL_MACRO_CNTL_RESERVED6 |
2866 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2867 | #define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2868 | //PLL_MACRO_CNTL_RESERVED7 |
2869 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2870 | #define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2871 | //PLL_MACRO_CNTL_RESERVED8 |
2872 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2873 | #define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2874 | //PLL_MACRO_CNTL_RESERVED9 |
2875 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2876 | #define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2877 | //PLL_MACRO_CNTL_RESERVED10 |
2878 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2879 | #define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2880 | //PLL_MACRO_CNTL_RESERVED11 |
2881 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2882 | #define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2883 | //PLL_MACRO_CNTL_RESERVED12 |
2884 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2885 | #define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2886 | //PLL_MACRO_CNTL_RESERVED13 |
2887 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2888 | #define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2889 | //PLL_MACRO_CNTL_RESERVED14 |
2890 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2891 | #define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2892 | //PLL_MACRO_CNTL_RESERVED15 |
2893 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2894 | #define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2895 | //PLL_MACRO_CNTL_RESERVED16 |
2896 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2897 | #define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2898 | //PLL_MACRO_CNTL_RESERVED17 |
2899 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2900 | #define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2901 | //PLL_MACRO_CNTL_RESERVED18 |
2902 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2903 | #define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2904 | //PLL_MACRO_CNTL_RESERVED19 |
2905 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2906 | #define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2907 | //PLL_MACRO_CNTL_RESERVED20 |
2908 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2909 | #define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2910 | //PLL_MACRO_CNTL_RESERVED21 |
2911 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2912 | #define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2913 | //PLL_MACRO_CNTL_RESERVED22 |
2914 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2915 | #define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2916 | //PLL_MACRO_CNTL_RESERVED23 |
2917 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2918 | #define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2919 | //PLL_MACRO_CNTL_RESERVED24 |
2920 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2921 | #define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2922 | //PLL_MACRO_CNTL_RESERVED25 |
2923 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2924 | #define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2925 | //PLL_MACRO_CNTL_RESERVED26 |
2926 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2927 | #define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2928 | //PLL_MACRO_CNTL_RESERVED27 |
2929 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2930 | #define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2931 | //PLL_MACRO_CNTL_RESERVED28 |
2932 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2933 | #define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2934 | //PLL_MACRO_CNTL_RESERVED29 |
2935 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2936 | #define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2937 | //PLL_MACRO_CNTL_RESERVED30 |
2938 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2939 | #define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2940 | //PLL_MACRO_CNTL_RESERVED31 |
2941 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2942 | #define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2943 | //PLL_MACRO_CNTL_RESERVED32 |
2944 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2945 | #define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2946 | //PLL_MACRO_CNTL_RESERVED33 |
2947 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2948 | #define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2949 | //PLL_MACRO_CNTL_RESERVED34 |
2950 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2951 | #define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2952 | //PLL_MACRO_CNTL_RESERVED35 |
2953 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2954 | #define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2955 | //PLL_MACRO_CNTL_RESERVED36 |
2956 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2957 | #define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2958 | //PLL_MACRO_CNTL_RESERVED37 |
2959 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2960 | #define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2961 | //PLL_MACRO_CNTL_RESERVED38 |
2962 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2963 | #define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2964 | //PLL_MACRO_CNTL_RESERVED39 |
2965 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2966 | #define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2967 | //PLL_MACRO_CNTL_RESERVED40 |
2968 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2969 | #define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2970 | //PLL_MACRO_CNTL_RESERVED41 |
2971 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
2972 | #define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
2973 | |
2974 | |
2975 | // addressBlock: dce_dc_dmu_rbbmif_dispdec |
2976 | //RBBMIF_TIMEOUT |
2977 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 |
2978 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 |
2979 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL |
2980 | #define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L |
2981 | //RBBMIF_STATUS |
2982 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 |
2983 | #define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x3FFFFFFFL |
2984 | //RBBMIF_INT_STATUS |
2985 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c |
2986 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d |
2987 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e |
2988 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f |
2989 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L |
2990 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L |
2991 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L |
2992 | #define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L |
2993 | //RBBMIF_TIMEOUT_DIS |
2994 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 |
2995 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 |
2996 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 |
2997 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 |
2998 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 |
2999 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 |
3000 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 |
3001 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 |
3002 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 |
3003 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 |
3004 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa |
3005 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb |
3006 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc |
3007 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd |
3008 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe |
3009 | #define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf |
3010 | #define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 |
3011 | #define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 |
3012 | #define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 |
3013 | #define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 |
3014 | #define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 |
3015 | #define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 |
3016 | #define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 |
3017 | #define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 |
3018 | #define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 |
3019 | #define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 |
3020 | #define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a |
3021 | #define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b |
3022 | #define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c |
3023 | #define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d |
3024 | #define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L |
3025 | #define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L |
3026 | #define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L |
3027 | #define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L |
3028 | #define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L |
3029 | #define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L |
3030 | #define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L |
3031 | #define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L |
3032 | #define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L |
3033 | #define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L |
3034 | #define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L |
3035 | #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L |
3036 | #define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L |
3037 | #define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L |
3038 | #define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L |
3039 | #define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L |
3040 | #define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L |
3041 | #define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L |
3042 | #define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L |
3043 | #define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L |
3044 | #define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L |
3045 | #define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L |
3046 | #define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L |
3047 | #define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L |
3048 | #define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L |
3049 | #define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L |
3050 | #define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L |
3051 | #define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L |
3052 | #define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L |
3053 | #define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L |
3054 | //RBBMIF_STATUS_FLAG |
3055 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 |
3056 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 |
3057 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 |
3058 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 |
3059 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 |
3060 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 |
3061 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 |
3062 | #define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L |
3063 | #define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L |
3064 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L |
3065 | #define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L |
3066 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L |
3067 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L |
3068 | #define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L |
3069 | |
3070 | |
3071 | // addressBlock: dce_dc_dmu_dc_pg_dispdec |
3072 | //DOMAIN0_PG_CONFIG |
3073 | #define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT 0x0 |
3074 | #define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT 0x8 |
3075 | #define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK 0x00000001L |
3076 | #define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK 0x00000100L |
3077 | //DOMAIN0_PG_STATUS |
3078 | #define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT 0x1c |
3079 | #define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT 0x1e |
3080 | #define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK 0x10000000L |
3081 | #define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3082 | //DOMAIN1_PG_CONFIG |
3083 | #define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT 0x0 |
3084 | #define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT 0x8 |
3085 | #define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK 0x00000001L |
3086 | #define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK 0x00000100L |
3087 | //DOMAIN1_PG_STATUS |
3088 | #define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT 0x1c |
3089 | #define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT 0x1e |
3090 | #define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK 0x10000000L |
3091 | #define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3092 | //DOMAIN2_PG_CONFIG |
3093 | #define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT 0x0 |
3094 | #define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT 0x8 |
3095 | #define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK 0x00000001L |
3096 | #define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK 0x00000100L |
3097 | //DOMAIN2_PG_STATUS |
3098 | #define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT 0x1c |
3099 | #define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT 0x1e |
3100 | #define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK 0x10000000L |
3101 | #define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3102 | //DOMAIN3_PG_CONFIG |
3103 | #define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT 0x0 |
3104 | #define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT 0x8 |
3105 | #define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK 0x00000001L |
3106 | #define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK 0x00000100L |
3107 | //DOMAIN3_PG_STATUS |
3108 | #define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT 0x1c |
3109 | #define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT 0x1e |
3110 | #define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK 0x10000000L |
3111 | #define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3112 | //DOMAIN4_PG_CONFIG |
3113 | #define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT 0x0 |
3114 | #define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT 0x8 |
3115 | #define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK 0x00000001L |
3116 | #define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK 0x00000100L |
3117 | //DOMAIN4_PG_STATUS |
3118 | #define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT 0x1c |
3119 | #define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT 0x1e |
3120 | #define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK 0x10000000L |
3121 | #define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3122 | //DOMAIN5_PG_CONFIG |
3123 | #define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT 0x0 |
3124 | #define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT 0x8 |
3125 | #define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK 0x00000001L |
3126 | #define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK 0x00000100L |
3127 | //DOMAIN5_PG_STATUS |
3128 | #define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT 0x1c |
3129 | #define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT 0x1e |
3130 | #define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK 0x10000000L |
3131 | #define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3132 | //DOMAIN6_PG_CONFIG |
3133 | #define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT 0x0 |
3134 | #define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT 0x8 |
3135 | #define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK 0x00000001L |
3136 | #define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK 0x00000100L |
3137 | //DOMAIN6_PG_STATUS |
3138 | #define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT 0x1c |
3139 | #define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT 0x1e |
3140 | #define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK 0x10000000L |
3141 | #define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3142 | //DOMAIN7_PG_CONFIG |
3143 | #define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT 0x0 |
3144 | #define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT 0x8 |
3145 | #define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK 0x00000001L |
3146 | #define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK 0x00000100L |
3147 | //DOMAIN7_PG_STATUS |
3148 | #define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT 0x1c |
3149 | #define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT 0x1e |
3150 | #define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK 0x10000000L |
3151 | #define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3152 | //DOMAIN8_PG_CONFIG |
3153 | #define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON__SHIFT 0x0 |
3154 | #define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE__SHIFT 0x8 |
3155 | #define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_FORCEON_MASK 0x00000001L |
3156 | #define DOMAIN8_PG_CONFIG__DOMAIN8_POWER_GATE_MASK 0x00000100L |
3157 | //DOMAIN8_PG_STATUS |
3158 | #define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE__SHIFT 0x1c |
3159 | #define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS__SHIFT 0x1e |
3160 | #define DOMAIN8_PG_STATUS__DOMAIN8_DESIRED_PWR_STATE_MASK 0x10000000L |
3161 | #define DOMAIN8_PG_STATUS__DOMAIN8_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3162 | //DOMAIN9_PG_CONFIG |
3163 | #define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON__SHIFT 0x0 |
3164 | #define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE__SHIFT 0x8 |
3165 | #define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_FORCEON_MASK 0x00000001L |
3166 | #define DOMAIN9_PG_CONFIG__DOMAIN9_POWER_GATE_MASK 0x00000100L |
3167 | //DOMAIN9_PG_STATUS |
3168 | #define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE__SHIFT 0x1c |
3169 | #define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS__SHIFT 0x1e |
3170 | #define DOMAIN9_PG_STATUS__DOMAIN9_DESIRED_PWR_STATE_MASK 0x10000000L |
3171 | #define DOMAIN9_PG_STATUS__DOMAIN9_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3172 | //DOMAIN10_PG_CONFIG |
3173 | #define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON__SHIFT 0x0 |
3174 | #define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE__SHIFT 0x8 |
3175 | #define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_FORCEON_MASK 0x00000001L |
3176 | #define DOMAIN10_PG_CONFIG__DOMAIN10_POWER_GATE_MASK 0x00000100L |
3177 | //DOMAIN10_PG_STATUS |
3178 | #define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE__SHIFT 0x1c |
3179 | #define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS__SHIFT 0x1e |
3180 | #define DOMAIN10_PG_STATUS__DOMAIN10_DESIRED_PWR_STATE_MASK 0x10000000L |
3181 | #define DOMAIN10_PG_STATUS__DOMAIN10_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3182 | //DOMAIN11_PG_CONFIG |
3183 | #define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON__SHIFT 0x0 |
3184 | #define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE__SHIFT 0x8 |
3185 | #define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_FORCEON_MASK 0x00000001L |
3186 | #define DOMAIN11_PG_CONFIG__DOMAIN11_POWER_GATE_MASK 0x00000100L |
3187 | //DOMAIN11_PG_STATUS |
3188 | #define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE__SHIFT 0x1c |
3189 | #define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS__SHIFT 0x1e |
3190 | #define DOMAIN11_PG_STATUS__DOMAIN11_DESIRED_PWR_STATE_MASK 0x10000000L |
3191 | #define DOMAIN11_PG_STATUS__DOMAIN11_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3192 | //DOMAIN12_PG_CONFIG |
3193 | #define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON__SHIFT 0x0 |
3194 | #define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE__SHIFT 0x8 |
3195 | #define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_FORCEON_MASK 0x00000001L |
3196 | #define DOMAIN12_PG_CONFIG__DOMAIN12_POWER_GATE_MASK 0x00000100L |
3197 | //DOMAIN12_PG_STATUS |
3198 | #define DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE__SHIFT 0x1c |
3199 | #define DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS__SHIFT 0x1e |
3200 | #define DOMAIN12_PG_STATUS__DOMAIN12_DESIRED_PWR_STATE_MASK 0x10000000L |
3201 | #define DOMAIN12_PG_STATUS__DOMAIN12_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3202 | //DOMAIN13_PG_CONFIG |
3203 | #define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON__SHIFT 0x0 |
3204 | #define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE__SHIFT 0x8 |
3205 | #define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_FORCEON_MASK 0x00000001L |
3206 | #define DOMAIN13_PG_CONFIG__DOMAIN13_POWER_GATE_MASK 0x00000100L |
3207 | //DOMAIN13_PG_STATUS |
3208 | #define DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE__SHIFT 0x1c |
3209 | #define DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS__SHIFT 0x1e |
3210 | #define DOMAIN13_PG_STATUS__DOMAIN13_DESIRED_PWR_STATE_MASK 0x10000000L |
3211 | #define DOMAIN13_PG_STATUS__DOMAIN13_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3212 | //DOMAIN14_PG_CONFIG |
3213 | #define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON__SHIFT 0x0 |
3214 | #define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE__SHIFT 0x8 |
3215 | #define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_FORCEON_MASK 0x00000001L |
3216 | #define DOMAIN14_PG_CONFIG__DOMAIN14_POWER_GATE_MASK 0x00000100L |
3217 | //DOMAIN14_PG_STATUS |
3218 | #define DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE__SHIFT 0x1c |
3219 | #define DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS__SHIFT 0x1e |
3220 | #define DOMAIN14_PG_STATUS__DOMAIN14_DESIRED_PWR_STATE_MASK 0x10000000L |
3221 | #define DOMAIN14_PG_STATUS__DOMAIN14_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3222 | //DOMAIN15_PG_CONFIG |
3223 | #define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON__SHIFT 0x0 |
3224 | #define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE__SHIFT 0x8 |
3225 | #define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_FORCEON_MASK 0x00000001L |
3226 | #define DOMAIN15_PG_CONFIG__DOMAIN15_POWER_GATE_MASK 0x00000100L |
3227 | //DOMAIN15_PG_STATUS |
3228 | #define DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE__SHIFT 0x1c |
3229 | #define DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS__SHIFT 0x1e |
3230 | #define DOMAIN15_PG_STATUS__DOMAIN15_DESIRED_PWR_STATE_MASK 0x10000000L |
3231 | #define DOMAIN15_PG_STATUS__DOMAIN15_PGFSM_PWR_STATUS_MASK 0xC0000000L |
3232 | //DCPG_INTERRUPT_STATUS |
3233 | #define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 |
3234 | #define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 |
3235 | #define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 |
3236 | #define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 |
3237 | #define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 |
3238 | #define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 |
3239 | #define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 |
3240 | #define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 |
3241 | #define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x8 |
3242 | #define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 |
3243 | #define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0xa |
3244 | #define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb |
3245 | #define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0xc |
3246 | #define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xd |
3247 | #define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0xe |
3248 | #define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xf |
3249 | #define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x10 |
3250 | #define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 |
3251 | #define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x12 |
3252 | #define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 |
3253 | #define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x14 |
3254 | #define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 |
3255 | #define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x16 |
3256 | #define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 |
3257 | #define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x18 |
3258 | #define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x19 |
3259 | #define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x1a |
3260 | #define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x1b |
3261 | #define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x1c |
3262 | #define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x1d |
3263 | #define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x1e |
3264 | #define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x1f |
3265 | #define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L |
3266 | #define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L |
3267 | #define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L |
3268 | #define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L |
3269 | #define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L |
3270 | #define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L |
3271 | #define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L |
3272 | #define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L |
3273 | #define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00000100L |
3274 | #define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L |
3275 | #define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00000400L |
3276 | #define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L |
3277 | #define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00001000L |
3278 | #define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L |
3279 | #define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00004000L |
3280 | #define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L |
3281 | #define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00010000L |
3282 | #define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L |
3283 | #define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00040000L |
3284 | #define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L |
3285 | #define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00100000L |
3286 | #define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L |
3287 | #define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00400000L |
3288 | #define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L |
3289 | #define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x01000000L |
3290 | #define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x02000000L |
3291 | #define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x04000000L |
3292 | #define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x08000000L |
3293 | #define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x10000000L |
3294 | #define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x20000000L |
3295 | #define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x40000000L |
3296 | #define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x80000000L |
3297 | //DCPG_INTERRUPT_CONTROL_1 |
3298 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 |
3299 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 |
3300 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 |
3301 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 |
3302 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 |
3303 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 |
3304 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 |
3305 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 |
3306 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 |
3307 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 |
3308 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa |
3309 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb |
3310 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc |
3311 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd |
3312 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe |
3313 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf |
3314 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT 0x10 |
3315 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x11 |
3316 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT 0x12 |
3317 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
3318 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT 0x14 |
3319 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x15 |
3320 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT 0x16 |
3321 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 |
3322 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT 0x18 |
3323 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x19 |
3324 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT 0x1a |
3325 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0x1b |
3326 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT 0x1c |
3327 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1d |
3328 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT 0x1e |
3329 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0x1f |
3330 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L |
3331 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L |
3332 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L |
3333 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L |
3334 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L |
3335 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L |
3336 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L |
3337 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L |
3338 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L |
3339 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L |
3340 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L |
3341 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L |
3342 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L |
3343 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L |
3344 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L |
3345 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L |
3346 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK 0x00010000L |
3347 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00020000L |
3348 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK 0x00040000L |
3349 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L |
3350 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK 0x00100000L |
3351 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00200000L |
3352 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK 0x00400000L |
3353 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L |
3354 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK 0x01000000L |
3355 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x02000000L |
3356 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK 0x04000000L |
3357 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x08000000L |
3358 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK 0x10000000L |
3359 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x20000000L |
3360 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK 0x40000000L |
3361 | #define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x80000000L |
3362 | //DCPG_INTERRUPT_CONTROL_2 |
3363 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT 0x0 |
3364 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x1 |
3365 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT 0x2 |
3366 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0x3 |
3367 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT 0x4 |
3368 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x5 |
3369 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT 0x6 |
3370 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0x7 |
3371 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT 0x8 |
3372 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x9 |
3373 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT 0xa |
3374 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xb |
3375 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT 0xc |
3376 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0xd |
3377 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT 0xe |
3378 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf |
3379 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT 0x10 |
3380 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x11 |
3381 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT 0x12 |
3382 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
3383 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT 0x14 |
3384 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x15 |
3385 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT 0x16 |
3386 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x17 |
3387 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT 0x18 |
3388 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x19 |
3389 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT 0x1a |
3390 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x1b |
3391 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT 0x1c |
3392 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x1d |
3393 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT 0x1e |
3394 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x1f |
3395 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK 0x00000001L |
3396 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000002L |
3397 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK 0x00000004L |
3398 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00000008L |
3399 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK 0x00000010L |
3400 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000020L |
3401 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK 0x00000040L |
3402 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00000080L |
3403 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK 0x00000100L |
3404 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000200L |
3405 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK 0x00000400L |
3406 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00000800L |
3407 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK 0x00001000L |
3408 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00002000L |
3409 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK 0x00004000L |
3410 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L |
3411 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK 0x00010000L |
3412 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00020000L |
3413 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK 0x00040000L |
3414 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00080000L |
3415 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK 0x00100000L |
3416 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00200000L |
3417 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK 0x00400000L |
3418 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00800000L |
3419 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK 0x01000000L |
3420 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x02000000L |
3421 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK 0x04000000L |
3422 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x08000000L |
3423 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK 0x10000000L |
3424 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x20000000L |
3425 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK 0x40000000L |
3426 | #define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x80000000L |
3427 | //DC_IP_REQUEST_CNTL |
3428 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 |
3429 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L |
3430 | //DC_PGCNTL_STATUS_REG |
3431 | |
3432 | |
3433 | // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec |
3434 | //DC_PERFMON2_PERFCOUNTER_CNTL |
3435 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
3436 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
3437 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
3438 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
3439 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
3440 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
3441 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
3442 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
3443 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
3444 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
3445 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
3446 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
3447 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
3448 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
3449 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
3450 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
3451 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
3452 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
3453 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
3454 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
3455 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
3456 | #define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
3457 | //DC_PERFMON2_PERFCOUNTER_CNTL2 |
3458 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
3459 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
3460 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
3461 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
3462 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
3463 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
3464 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
3465 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
3466 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
3467 | #define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
3468 | //DC_PERFMON2_PERFCOUNTER_STATE |
3469 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
3470 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
3471 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
3472 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
3473 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
3474 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
3475 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
3476 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
3477 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
3478 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
3479 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
3480 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
3481 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
3482 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
3483 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
3484 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
3485 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
3486 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
3487 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
3488 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
3489 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
3490 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
3491 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
3492 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
3493 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
3494 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
3495 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
3496 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
3497 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
3498 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
3499 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
3500 | #define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
3501 | //DC_PERFMON2_PERFMON_CNTL |
3502 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
3503 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
3504 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
3505 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
3506 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
3507 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
3508 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
3509 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
3510 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
3511 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
3512 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
3513 | #define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
3514 | //DC_PERFMON2_PERFMON_CNTL2 |
3515 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
3516 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
3517 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
3518 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
3519 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
3520 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
3521 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
3522 | #define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
3523 | //DC_PERFMON2_PERFMON_CVALUE_INT_MISC |
3524 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
3525 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
3526 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
3527 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
3528 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
3529 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
3530 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
3531 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
3532 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
3533 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
3534 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
3535 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
3536 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
3537 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
3538 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
3539 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
3540 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
3541 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
3542 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
3543 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
3544 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
3545 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
3546 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
3547 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
3548 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
3549 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
3550 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
3551 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
3552 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
3553 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
3554 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
3555 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
3556 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
3557 | #define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
3558 | //DC_PERFMON2_PERFMON_CVALUE_LOW |
3559 | #define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
3560 | #define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
3561 | //DC_PERFMON2_PERFMON_HI |
3562 | #define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
3563 | #define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
3564 | #define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
3565 | #define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
3566 | //DC_PERFMON2_PERFMON_LOW |
3567 | #define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
3568 | #define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
3569 | |
3570 | |
3571 | // addressBlock: dce_dc_dmu_dmu_misc_dispdec |
3572 | //CC_DC_PIPE_DIS |
3573 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 |
3574 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL |
3575 | //DMU_CLK_CNTL |
3576 | #define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 |
3577 | #define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x2 |
3578 | #define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x3 |
3579 | #define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x00000003L |
3580 | #define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000004L |
3581 | #define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000008L |
3582 | //DMU_MEM_PWR_CNTL |
3583 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 |
3584 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 |
3585 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 |
3586 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 |
3587 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 |
3588 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 |
3589 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa |
3590 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L |
3591 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L |
3592 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L |
3593 | #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L |
3594 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L |
3595 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L |
3596 | #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L |
3597 | //DMCU_SMU_INTERRUPT_CNTL |
3598 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 |
3599 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 |
3600 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L |
3601 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L |
3602 | //SMU_INTERRUPT_CONTROL |
3603 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 |
3604 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 |
3605 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 |
3606 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L |
3607 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L |
3608 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L |
3609 | |
3610 | |
3611 | // addressBlock: dce_dc_dmu_dmcu_dispdec |
3612 | //DMCU_CTRL |
3613 | #define DMCU_CTRL__RESET_UC__SHIFT 0x0 |
3614 | #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 |
3615 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 |
3616 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 |
3617 | #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 |
3618 | #define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 |
3619 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 |
3620 | #define DMCU_CTRL__RESET_UC_MASK 0x00000001L |
3621 | #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L |
3622 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L |
3623 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L |
3624 | #define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L |
3625 | #define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L |
3626 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L |
3627 | //DMCU_STATUS |
3628 | #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 |
3629 | #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 |
3630 | #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 |
3631 | #define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L |
3632 | #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L |
3633 | #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L |
3634 | //DMCU_PC_START_ADDR |
3635 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 |
3636 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 |
3637 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL |
3638 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L |
3639 | //DMCU_FW_START_ADDR |
3640 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 |
3641 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 |
3642 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL |
3643 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L |
3644 | //DMCU_FW_END_ADDR |
3645 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 |
3646 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 |
3647 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL |
3648 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L |
3649 | //DMCU_FW_ISR_START_ADDR |
3650 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 |
3651 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 |
3652 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL |
3653 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L |
3654 | //DMCU_FW_CS_HI |
3655 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 |
3656 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL |
3657 | //DMCU_FW_CS_LO |
3658 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 |
3659 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL |
3660 | //DMCU_RAM_ACCESS_CTRL |
3661 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 |
3662 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 |
3663 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 |
3664 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 |
3665 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 |
3666 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 |
3667 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L |
3668 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L |
3669 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L |
3670 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L |
3671 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L |
3672 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L |
3673 | //DMCU_ERAM_WR_CTRL |
3674 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 |
3675 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 |
3676 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 |
3677 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL |
3678 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L |
3679 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L |
3680 | //DMCU_ERAM_WR_DATA |
3681 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 |
3682 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL |
3683 | //DMCU_ERAM_RD_CTRL |
3684 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 |
3685 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 |
3686 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 |
3687 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL |
3688 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L |
3689 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L |
3690 | //DMCU_ERAM_RD_DATA |
3691 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 |
3692 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL |
3693 | //DMCU_IRAM_WR_CTRL |
3694 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 |
3695 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL |
3696 | //DMCU_IRAM_WR_DATA |
3697 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 |
3698 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL |
3699 | //DMCU_IRAM_RD_CTRL |
3700 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 |
3701 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL |
3702 | //DMCU_IRAM_RD_DATA |
3703 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 |
3704 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL |
3705 | //DMCU_EVENT_TRIGGER |
3706 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 |
3707 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 |
3708 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 |
3709 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L |
3710 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L |
3711 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L |
3712 | //DMCU_UC_INTERNAL_INT_STATUS |
3713 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 |
3714 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 |
3715 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 |
3716 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 |
3717 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 |
3718 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 |
3719 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 |
3720 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 |
3721 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 |
3722 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 |
3723 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa |
3724 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb |
3725 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc |
3726 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd |
3727 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe |
3728 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf |
3729 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L |
3730 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L |
3731 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L |
3732 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L |
3733 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L |
3734 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L |
3735 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L |
3736 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L |
3737 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L |
3738 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L |
3739 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L |
3740 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L |
3741 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L |
3742 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L |
3743 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L |
3744 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L |
3745 | //DMCU_SS_INTERRUPT_CNTL_STATUS |
3746 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd |
3747 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe |
3748 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe |
3749 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf |
3750 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 |
3751 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 |
3752 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 |
3753 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 |
3754 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 |
3755 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 |
3756 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 |
3757 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 |
3758 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 |
3759 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 |
3760 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 |
3761 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 |
3762 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 |
3763 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 |
3764 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L |
3765 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L |
3766 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L |
3767 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L |
3768 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L |
3769 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L |
3770 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L |
3771 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L |
3772 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L |
3773 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L |
3774 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L |
3775 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L |
3776 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L |
3777 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L |
3778 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L |
3779 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L |
3780 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L |
3781 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L |
3782 | //DMCU_INTERRUPT_STATUS |
3783 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 |
3784 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 |
3785 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 |
3786 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 |
3787 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 |
3788 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 |
3789 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 |
3790 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 |
3791 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 |
3792 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 |
3793 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa |
3794 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa |
3795 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb |
3796 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb |
3797 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc |
3798 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc |
3799 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd |
3800 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd |
3801 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe |
3802 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe |
3803 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf |
3804 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf |
3805 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10 |
3806 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10 |
3807 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11 |
3808 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11 |
3809 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 |
3810 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 |
3811 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 |
3812 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
3813 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 |
3814 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 |
3815 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 |
3816 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 |
3817 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 |
3818 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 |
3819 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 |
3820 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 |
3821 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 |
3822 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 |
3823 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 |
3824 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 |
3825 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a |
3826 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a |
3827 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b |
3828 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b |
3829 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c |
3830 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c |
3831 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d |
3832 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d |
3833 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L |
3834 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L |
3835 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L |
3836 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L |
3837 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L |
3838 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L |
3839 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L |
3840 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L |
3841 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L |
3842 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L |
3843 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L |
3844 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L |
3845 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L |
3846 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L |
3847 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L |
3848 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L |
3849 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L |
3850 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L |
3851 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L |
3852 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L |
3853 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L |
3854 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L |
3855 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L |
3856 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L |
3857 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L |
3858 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L |
3859 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L |
3860 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L |
3861 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L |
3862 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L |
3863 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L |
3864 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L |
3865 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L |
3866 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L |
3867 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L |
3868 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L |
3869 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L |
3870 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L |
3871 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L |
3872 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L |
3873 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L |
3874 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L |
3875 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L |
3876 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L |
3877 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L |
3878 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L |
3879 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L |
3880 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L |
3881 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L |
3882 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L |
3883 | //DMCU_INTERRUPT_STATUS_1 |
3884 | #define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 |
3885 | #define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 |
3886 | #define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 |
3887 | #define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 |
3888 | #define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 |
3889 | #define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 |
3890 | #define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 |
3891 | #define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 |
3892 | #define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa |
3893 | #define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa |
3894 | #define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb |
3895 | #define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb |
3896 | #define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd |
3897 | #define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd |
3898 | #define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L |
3899 | #define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L |
3900 | #define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L |
3901 | #define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L |
3902 | #define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L |
3903 | #define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L |
3904 | #define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L |
3905 | #define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L |
3906 | #define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L |
3907 | #define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L |
3908 | #define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L |
3909 | #define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L |
3910 | #define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L |
3911 | #define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L |
3912 | //DMCU_INTERRUPT_TO_HOST_EN_MASK |
3913 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 |
3914 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 |
3915 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 |
3916 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 |
3917 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 |
3918 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 |
3919 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 |
3920 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa |
3921 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb |
3922 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L |
3923 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L |
3924 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L |
3925 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L |
3926 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L |
3927 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L |
3928 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L |
3929 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L |
3930 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L |
3931 | //DMCU_INTERRUPT_TO_UC_EN_MASK |
3932 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 |
3933 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 |
3934 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 |
3935 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 |
3936 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 |
3937 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 |
3938 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 |
3939 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 |
3940 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa |
3941 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb |
3942 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc |
3943 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd |
3944 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe |
3945 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf |
3946 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 |
3947 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 |
3948 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 |
3949 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 |
3950 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 |
3951 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 |
3952 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 |
3953 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 |
3954 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 |
3955 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 |
3956 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a |
3957 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b |
3958 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c |
3959 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d |
3960 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e |
3961 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L |
3962 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L |
3963 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L |
3964 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L |
3965 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L |
3966 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L |
3967 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L |
3968 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L |
3969 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L |
3970 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L |
3971 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L |
3972 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L |
3973 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L |
3974 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L |
3975 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L |
3976 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L |
3977 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L |
3978 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L |
3979 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L |
3980 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L |
3981 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L |
3982 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L |
3983 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L |
3984 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L |
3985 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L |
3986 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L |
3987 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L |
3988 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L |
3989 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L |
3990 | //DMCU_INTERRUPT_TO_UC_EN_MASK_1 |
3991 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 |
3992 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 |
3993 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 |
3994 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 |
3995 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa |
3996 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb |
3997 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd |
3998 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L |
3999 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L |
4000 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L |
4001 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L |
4002 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L |
4003 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L |
4004 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L |
4005 | //DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL |
4006 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4007 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4008 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4009 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4010 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4011 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
4012 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
4013 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
4014 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
4015 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
4016 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
4017 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
4018 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
4019 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
4020 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
4021 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
4022 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
4023 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
4024 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
4025 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
4026 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
4027 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
4028 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
4029 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
4030 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
4031 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
4032 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
4033 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d |
4034 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e |
4035 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4036 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4037 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4038 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4039 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4040 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L |
4041 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L |
4042 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L |
4043 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L |
4044 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L |
4045 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L |
4046 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L |
4047 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L |
4048 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L |
4049 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L |
4050 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L |
4051 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L |
4052 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L |
4053 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L |
4054 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L |
4055 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L |
4056 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L |
4057 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L |
4058 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L |
4059 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L |
4060 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L |
4061 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L |
4062 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L |
4063 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L |
4064 | //DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 |
4065 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4066 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
4067 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
4068 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
4069 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
4070 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
4071 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
4072 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4073 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L |
4074 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L |
4075 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L |
4076 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L |
4077 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L |
4078 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L |
4079 | //DC_DMCU_SCRATCH |
4080 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 |
4081 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL |
4082 | //DMCU_INT_CNT |
4083 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 |
4084 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 |
4085 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 |
4086 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL |
4087 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L |
4088 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L |
4089 | //DMCU_FW_CHECKSUM_SMPL_BYTE_POS |
4090 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 |
4091 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 |
4092 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L |
4093 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL |
4094 | //DMCU_UC_CLK_GATING_CNTL |
4095 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 |
4096 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 |
4097 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 |
4098 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L |
4099 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L |
4100 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L |
4101 | //MASTER_COMM_DATA_REG1 |
4102 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
4103 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
4104 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
4105 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
4106 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL |
4107 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L |
4108 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L |
4109 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L |
4110 | //MASTER_COMM_DATA_REG2 |
4111 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
4112 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
4113 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
4114 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
4115 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL |
4116 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L |
4117 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L |
4118 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L |
4119 | //MASTER_COMM_DATA_REG3 |
4120 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
4121 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
4122 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
4123 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
4124 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL |
4125 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L |
4126 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L |
4127 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L |
4128 | //MASTER_COMM_CMD_REG |
4129 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
4130 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
4131 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
4132 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
4133 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL |
4134 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L |
4135 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L |
4136 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L |
4137 | //MASTER_COMM_CNTL_REG |
4138 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 |
4139 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L |
4140 | //SLAVE_COMM_DATA_REG1 |
4141 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
4142 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
4143 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
4144 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
4145 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL |
4146 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L |
4147 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L |
4148 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L |
4149 | //SLAVE_COMM_DATA_REG2 |
4150 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
4151 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
4152 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
4153 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
4154 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL |
4155 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L |
4156 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L |
4157 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L |
4158 | //SLAVE_COMM_DATA_REG3 |
4159 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
4160 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
4161 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
4162 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
4163 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL |
4164 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L |
4165 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L |
4166 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L |
4167 | //SLAVE_COMM_CMD_REG |
4168 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
4169 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
4170 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
4171 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
4172 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL |
4173 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L |
4174 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L |
4175 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L |
4176 | //SLAVE_COMM_CNTL_REG |
4177 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 |
4178 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 |
4179 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L |
4180 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L |
4181 | //DMCU_PERFMON_INTERRUPT_STATUS1 |
4182 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 |
4183 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 |
4184 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 |
4185 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 |
4186 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 |
4187 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 |
4188 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L |
4189 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L |
4190 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L |
4191 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L |
4192 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L |
4193 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L |
4194 | //DMCU_PERFMON_INTERRUPT_STATUS2 |
4195 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 |
4196 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 |
4197 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 |
4198 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 |
4199 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 |
4200 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 |
4201 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 |
4202 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 |
4203 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 |
4204 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 |
4205 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 |
4206 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 |
4207 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 |
4208 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 |
4209 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 |
4210 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 |
4211 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 |
4212 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 |
4213 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L |
4214 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L |
4215 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L |
4216 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L |
4217 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L |
4218 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L |
4219 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L |
4220 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L |
4221 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L |
4222 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L |
4223 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L |
4224 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L |
4225 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L |
4226 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L |
4227 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L |
4228 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L |
4229 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L |
4230 | #define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L |
4231 | //DMCU_PERFMON_INTERRUPT_STATUS3 |
4232 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 |
4233 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 |
4234 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 |
4235 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 |
4236 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 |
4237 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 |
4238 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 |
4239 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 |
4240 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 |
4241 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 |
4242 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 |
4243 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 |
4244 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 |
4245 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 |
4246 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 |
4247 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 |
4248 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L |
4249 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L |
4250 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L |
4251 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L |
4252 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L |
4253 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L |
4254 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L |
4255 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L |
4256 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L |
4257 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L |
4258 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L |
4259 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L |
4260 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L |
4261 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L |
4262 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L |
4263 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L |
4264 | //DMCU_PERFMON_INTERRUPT_STATUS4 |
4265 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 |
4266 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 |
4267 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 |
4268 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 |
4269 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 |
4270 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 |
4271 | #define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 |
4272 | #define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 |
4273 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L |
4274 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L |
4275 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L |
4276 | #define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L |
4277 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L |
4278 | #define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L |
4279 | #define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L |
4280 | #define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L |
4281 | //DMCU_PERFMON_INTERRUPT_STATUS5 |
4282 | #define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 |
4283 | #define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 |
4284 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 |
4285 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 |
4286 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 |
4287 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 |
4288 | #define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 |
4289 | #define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 |
4290 | #define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L |
4291 | #define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L |
4292 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L |
4293 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L |
4294 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L |
4295 | #define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L |
4296 | #define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L |
4297 | #define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L |
4298 | //DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 |
4299 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 |
4300 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 |
4301 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 |
4302 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L |
4303 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L |
4304 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L |
4305 | //DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 |
4306 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 |
4307 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 |
4308 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 |
4309 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 |
4310 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 |
4311 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 |
4312 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 |
4313 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 |
4314 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 |
4315 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L |
4316 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L |
4317 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L |
4318 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L |
4319 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L |
4320 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L |
4321 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L |
4322 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L |
4323 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L |
4324 | //DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 |
4325 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 |
4326 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 |
4327 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 |
4328 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 |
4329 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 |
4330 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 |
4331 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 |
4332 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 |
4333 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L |
4334 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L |
4335 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L |
4336 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L |
4337 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L |
4338 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L |
4339 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L |
4340 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L |
4341 | //DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 |
4342 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 |
4343 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 |
4344 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 |
4345 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 |
4346 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L |
4347 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L |
4348 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L |
4349 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L |
4350 | //DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 |
4351 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 |
4352 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 |
4353 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 |
4354 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 |
4355 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L |
4356 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L |
4357 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L |
4358 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L |
4359 | //DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 |
4360 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4361 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4362 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4363 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4364 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4365 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4366 | //DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 |
4367 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4368 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4369 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4370 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4371 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
4372 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
4373 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4374 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
4375 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
4376 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4377 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4378 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4379 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4380 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L |
4381 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L |
4382 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4383 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L |
4384 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L |
4385 | //DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 |
4386 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4387 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4388 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4389 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4390 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
4391 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
4392 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4393 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
4394 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4395 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4396 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4397 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4398 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L |
4399 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L |
4400 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4401 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L |
4402 | //DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 |
4403 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4404 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4405 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4406 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4407 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4408 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4409 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4410 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4411 | //DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 |
4412 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4413 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4414 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4415 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4416 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4417 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4418 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4419 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4420 | //DMCU_DPRX_INTERRUPT_STATUS1 |
4421 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 |
4422 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 |
4423 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 |
4424 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 |
4425 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 |
4426 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 |
4427 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 |
4428 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 |
4429 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 |
4430 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 |
4431 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 |
4432 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 |
4433 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 |
4434 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 |
4435 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 |
4436 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 |
4437 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 |
4438 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 |
4439 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 |
4440 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 |
4441 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa |
4442 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa |
4443 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb |
4444 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb |
4445 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc |
4446 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc |
4447 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd |
4448 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd |
4449 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe |
4450 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe |
4451 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf |
4452 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf |
4453 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 |
4454 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 |
4455 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 |
4456 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 |
4457 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 |
4458 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 |
4459 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 |
4460 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 |
4461 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 |
4462 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 |
4463 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 |
4464 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 |
4465 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 |
4466 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 |
4467 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 |
4468 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 |
4469 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 |
4470 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 |
4471 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 |
4472 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 |
4473 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a |
4474 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a |
4475 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b |
4476 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b |
4477 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c |
4478 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c |
4479 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L |
4480 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L |
4481 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L |
4482 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L |
4483 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L |
4484 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L |
4485 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L |
4486 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L |
4487 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L |
4488 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L |
4489 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L |
4490 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L |
4491 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L |
4492 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L |
4493 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L |
4494 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L |
4495 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L |
4496 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L |
4497 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L |
4498 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L |
4499 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L |
4500 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L |
4501 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L |
4502 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L |
4503 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L |
4504 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L |
4505 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L |
4506 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L |
4507 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L |
4508 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L |
4509 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L |
4510 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L |
4511 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L |
4512 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L |
4513 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L |
4514 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L |
4515 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L |
4516 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L |
4517 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L |
4518 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L |
4519 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L |
4520 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L |
4521 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L |
4522 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L |
4523 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L |
4524 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L |
4525 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L |
4526 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L |
4527 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L |
4528 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L |
4529 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L |
4530 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L |
4531 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L |
4532 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L |
4533 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L |
4534 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L |
4535 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L |
4536 | #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L |
4537 | //DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 |
4538 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 |
4539 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 |
4540 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 |
4541 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 |
4542 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 |
4543 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 |
4544 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 |
4545 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 |
4546 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 |
4547 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 |
4548 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa |
4549 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb |
4550 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc |
4551 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd |
4552 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe |
4553 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf |
4554 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 |
4555 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 |
4556 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 |
4557 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 |
4558 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 |
4559 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 |
4560 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 |
4561 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 |
4562 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 |
4563 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 |
4564 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a |
4565 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b |
4566 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c |
4567 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L |
4568 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L |
4569 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L |
4570 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L |
4571 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L |
4572 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L |
4573 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L |
4574 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L |
4575 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L |
4576 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L |
4577 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L |
4578 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L |
4579 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L |
4580 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L |
4581 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L |
4582 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L |
4583 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L |
4584 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L |
4585 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L |
4586 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L |
4587 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L |
4588 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L |
4589 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L |
4590 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L |
4591 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L |
4592 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L |
4593 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L |
4594 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L |
4595 | #define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L |
4596 | //DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 |
4597 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4598 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4599 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 |
4600 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 |
4601 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
4602 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
4603 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4604 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 |
4605 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 |
4606 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
4607 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
4608 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
4609 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
4610 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
4611 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
4612 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
4613 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
4614 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
4615 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
4616 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
4617 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
4618 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
4619 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
4620 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
4621 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
4622 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
4623 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
4624 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
4625 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
4626 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4627 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4628 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L |
4629 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L |
4630 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L |
4631 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L |
4632 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4633 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L |
4634 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L |
4635 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L |
4636 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L |
4637 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L |
4638 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L |
4639 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L |
4640 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L |
4641 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L |
4642 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L |
4643 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L |
4644 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L |
4645 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L |
4646 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L |
4647 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L |
4648 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L |
4649 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L |
4650 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L |
4651 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L |
4652 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L |
4653 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L |
4654 | #define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L |
4655 | //DMCU_INTERRUPT_STATUS_CONTINUE |
4656 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0 |
4657 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0 |
4658 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1 |
4659 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1 |
4660 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2 |
4661 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2 |
4662 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3 |
4663 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3 |
4664 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4 |
4665 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4 |
4666 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5 |
4667 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5 |
4668 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6 |
4669 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6 |
4670 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7 |
4671 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7 |
4672 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8 |
4673 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8 |
4674 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9 |
4675 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9 |
4676 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa |
4677 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa |
4678 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb |
4679 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb |
4680 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc |
4681 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc |
4682 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd |
4683 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd |
4684 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe |
4685 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe |
4686 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf |
4687 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf |
4688 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10 |
4689 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10 |
4690 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 |
4691 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11 |
4692 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 |
4693 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12 |
4694 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 |
4695 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
4696 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 |
4697 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 |
4698 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 |
4699 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 |
4700 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 |
4701 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 |
4702 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 |
4703 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 |
4704 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 |
4705 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 |
4706 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 |
4707 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 |
4708 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a |
4709 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a |
4710 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b |
4711 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b |
4712 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c |
4713 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c |
4714 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L |
4715 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L |
4716 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L |
4717 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L |
4718 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L |
4719 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L |
4720 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L |
4721 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L |
4722 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L |
4723 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L |
4724 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L |
4725 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L |
4726 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L |
4727 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L |
4728 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L |
4729 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L |
4730 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L |
4731 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L |
4732 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L |
4733 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L |
4734 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L |
4735 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L |
4736 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L |
4737 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L |
4738 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L |
4739 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L |
4740 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L |
4741 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L |
4742 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L |
4743 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L |
4744 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L |
4745 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L |
4746 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L |
4747 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L |
4748 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L |
4749 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L |
4750 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L |
4751 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L |
4752 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L |
4753 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L |
4754 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L |
4755 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L |
4756 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L |
4757 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L |
4758 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L |
4759 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L |
4760 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L |
4761 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L |
4762 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L |
4763 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L |
4764 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L |
4765 | #define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L |
4766 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L |
4767 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L |
4768 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L |
4769 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L |
4770 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L |
4771 | #define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L |
4772 | //DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE |
4773 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 |
4774 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 |
4775 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 |
4776 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 |
4777 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 |
4778 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 |
4779 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6 |
4780 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7 |
4781 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8 |
4782 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9 |
4783 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa |
4784 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb |
4785 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc |
4786 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd |
4787 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe |
4788 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf |
4789 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10 |
4790 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11 |
4791 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 |
4792 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 |
4793 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 |
4794 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 |
4795 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 |
4796 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 |
4797 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 |
4798 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 |
4799 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a |
4800 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b |
4801 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c |
4802 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L |
4803 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L |
4804 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L |
4805 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L |
4806 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L |
4807 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L |
4808 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L |
4809 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L |
4810 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L |
4811 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L |
4812 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L |
4813 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L |
4814 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L |
4815 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L |
4816 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L |
4817 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L |
4818 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L |
4819 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L |
4820 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L |
4821 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L |
4822 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L |
4823 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L |
4824 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L |
4825 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L |
4826 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L |
4827 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L |
4828 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L |
4829 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L |
4830 | #define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L |
4831 | //DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE |
4832 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
4833 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
4834 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
4835 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
4836 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
4837 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
4838 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
4839 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
4840 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
4841 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
4842 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
4843 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
4844 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
4845 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
4846 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
4847 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
4848 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
4849 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
4850 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
4851 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
4852 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 |
4853 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 |
4854 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 |
4855 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 |
4856 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 |
4857 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 |
4858 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
4859 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
4860 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
4861 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L |
4862 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L |
4863 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L |
4864 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L |
4865 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L |
4866 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L |
4867 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L |
4868 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L |
4869 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L |
4870 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L |
4871 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L |
4872 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L |
4873 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L |
4874 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L |
4875 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L |
4876 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L |
4877 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L |
4878 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L |
4879 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L |
4880 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L |
4881 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L |
4882 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L |
4883 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L |
4884 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L |
4885 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L |
4886 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L |
4887 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L |
4888 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L |
4889 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L |
4890 | //DMCU_INT_CNT_CONTINUE |
4891 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 |
4892 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 |
4893 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 |
4894 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL |
4895 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L |
4896 | #define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L |
4897 | |
4898 | |
4899 | // addressBlock: dce_dc_dmu_ihc_dispdec |
4900 | //DC_GPU_TIMER_START_POSITION_V_UPDATE |
4901 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 |
4902 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 |
4903 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 |
4904 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc |
4905 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 |
4906 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 |
4907 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L |
4908 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L |
4909 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L |
4910 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L |
4911 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L |
4912 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L |
4913 | //DC_GPU_TIMER_START_POSITION_VSTARTUP |
4914 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 |
4915 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 |
4916 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 |
4917 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc |
4918 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 |
4919 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 |
4920 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L |
4921 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L |
4922 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L |
4923 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L |
4924 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L |
4925 | #define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L |
4926 | //DC_GPU_TIMER_READ |
4927 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 |
4928 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL |
4929 | //DC_GPU_TIMER_READ_CNTL |
4930 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 |
4931 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 |
4932 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb |
4933 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe |
4934 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 |
4935 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 |
4936 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 |
4937 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL |
4938 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L |
4939 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L |
4940 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L |
4941 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L |
4942 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L |
4943 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L |
4944 | //DISP_INTERRUPT_STATUS |
4945 | #define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
4946 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
4947 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
4948 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
4949 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
4950 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
4951 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
4952 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
4953 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
4954 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
4955 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 |
4956 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 |
4957 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 |
4958 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 |
4959 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT 0x16 |
4960 | #define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 |
4961 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 |
4962 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a |
4963 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c |
4964 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d |
4965 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e |
4966 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f |
4967 | #define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L |
4968 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
4969 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
4970 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
4971 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
4972 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
4973 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
4974 | #define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
4975 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
4976 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
4977 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L |
4978 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L |
4979 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L |
4980 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L |
4981 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK 0x00400000L |
4982 | #define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L |
4983 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L |
4984 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L |
4985 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L |
4986 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L |
4987 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L |
4988 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L |
4989 | //DISP_INTERRUPT_STATUS_CONTINUE |
4990 | #define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
4991 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
4992 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
4993 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
4994 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
4995 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
4996 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
4997 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
4998 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
4999 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
5000 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 |
5001 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 |
5002 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 |
5003 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 |
5004 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
5005 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
5006 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
5007 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c |
5008 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d |
5009 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e |
5010 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f |
5011 | #define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L |
5012 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
5013 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
5014 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
5015 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
5016 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
5017 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
5018 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
5019 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
5020 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
5021 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L |
5022 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L |
5023 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L |
5024 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L |
5025 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L |
5026 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L |
5027 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L |
5028 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L |
5029 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L |
5030 | #define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L |
5031 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L |
5032 | //DISP_INTERRUPT_STATUS_CONTINUE2 |
5033 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
5034 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
5035 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
5036 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
5037 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
5038 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
5039 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
5040 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
5041 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
5042 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
5043 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 |
5044 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 |
5045 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 |
5046 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 |
5047 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
5048 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
5049 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
5050 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c |
5051 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d |
5052 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e |
5053 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f |
5054 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L |
5055 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
5056 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
5057 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
5058 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
5059 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
5060 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
5061 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
5062 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
5063 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
5064 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L |
5065 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L |
5066 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L |
5067 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L |
5068 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L |
5069 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L |
5070 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L |
5071 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L |
5072 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L |
5073 | #define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L |
5074 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L |
5075 | //DISP_INTERRUPT_STATUS_CONTINUE3 |
5076 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
5077 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
5078 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
5079 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
5080 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
5081 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
5082 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
5083 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
5084 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
5085 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
5086 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 |
5087 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 |
5088 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 |
5089 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 |
5090 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT 0x17 |
5091 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 |
5092 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
5093 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
5094 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
5095 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c |
5096 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d |
5097 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e |
5098 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f |
5099 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L |
5100 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
5101 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
5102 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
5103 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
5104 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
5105 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
5106 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
5107 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
5108 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
5109 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L |
5110 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L |
5111 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L |
5112 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L |
5113 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK 0x00800000L |
5114 | #define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L |
5115 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L |
5116 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L |
5117 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L |
5118 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L |
5119 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L |
5120 | #define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L |
5121 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L |
5122 | //DISP_INTERRUPT_STATUS_CONTINUE4 |
5123 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 |
5124 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
5125 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
5126 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
5127 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
5128 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
5129 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
5130 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
5131 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
5132 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
5133 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
5134 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 |
5135 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 |
5136 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 |
5137 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 |
5138 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
5139 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
5140 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
5141 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
5142 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
5143 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
5144 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c |
5145 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d |
5146 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e |
5147 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f |
5148 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L |
5149 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L |
5150 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
5151 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
5152 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
5153 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
5154 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
5155 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
5156 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
5157 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
5158 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
5159 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L |
5160 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L |
5161 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L |
5162 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L |
5163 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L |
5164 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L |
5165 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L |
5166 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L |
5167 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L |
5168 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L |
5169 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L |
5170 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L |
5171 | #define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L |
5172 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L |
5173 | //DISP_INTERRUPT_STATUS_CONTINUE5 |
5174 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
5175 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
5176 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
5177 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 |
5178 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 |
5179 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
5180 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
5181 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
5182 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
5183 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 |
5184 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 |
5185 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 |
5186 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 |
5187 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
5188 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
5189 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
5190 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 |
5191 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a |
5192 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b |
5193 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c |
5194 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d |
5195 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e |
5196 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f |
5197 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L |
5198 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L |
5199 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L |
5200 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L |
5201 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L |
5202 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L |
5203 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L |
5204 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L |
5205 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L |
5206 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L |
5207 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L |
5208 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L |
5209 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L |
5210 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L |
5211 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L |
5212 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L |
5213 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L |
5214 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L |
5215 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L |
5216 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L |
5217 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L |
5218 | #define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L |
5219 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L |
5220 | //DISP_INTERRUPT_STATUS_CONTINUE6 |
5221 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 |
5222 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa |
5223 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 |
5224 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 |
5225 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 |
5226 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 |
5227 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 |
5228 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 |
5229 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 |
5230 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 |
5231 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 |
5232 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a |
5233 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b |
5234 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c |
5235 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0x1d |
5236 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0x1e |
5237 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f |
5238 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L |
5239 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L |
5240 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L |
5241 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L |
5242 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L |
5243 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L |
5244 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L |
5245 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L |
5246 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L |
5247 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L |
5248 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L |
5249 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L |
5250 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L |
5251 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L |
5252 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x20000000L |
5253 | #define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x40000000L |
5254 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L |
5255 | //DISP_INTERRUPT_STATUS_CONTINUE7 |
5256 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5257 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5258 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5259 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5260 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5261 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5262 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b |
5263 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c |
5264 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f |
5265 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5266 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5267 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5268 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5269 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5270 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5271 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L |
5272 | #define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L |
5273 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L |
5274 | //DISP_INTERRUPT_STATUS_CONTINUE8 |
5275 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5276 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5277 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5278 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5279 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5280 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5281 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f |
5282 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5283 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5284 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5285 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5286 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5287 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5288 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L |
5289 | //DISP_INTERRUPT_STATUS_CONTINUE9 |
5290 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5291 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5292 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5293 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5294 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5295 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5296 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT 0x1c |
5297 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1d |
5298 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f |
5299 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5300 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5301 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5302 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5303 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5304 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5305 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK 0x10000000L |
5306 | #define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x20000000L |
5307 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L |
5308 | //DISP_INTERRUPT_STATUS_CONTINUE10 |
5309 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 |
5310 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 |
5311 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 |
5312 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 |
5313 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 |
5314 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 |
5315 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc |
5316 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd |
5317 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT 0x16 |
5318 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT 0x17 |
5319 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT 0x18 |
5320 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT 0x19 |
5321 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1a |
5322 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1b |
5323 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f |
5324 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L |
5325 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L |
5326 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L |
5327 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L |
5328 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L |
5329 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L |
5330 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L |
5331 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L |
5332 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK 0x00400000L |
5333 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK 0x00800000L |
5334 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK 0x01000000L |
5335 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK 0x02000000L |
5336 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK 0x04000000L |
5337 | #define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK 0x08000000L |
5338 | #define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L |
5339 | //DISP_INTERRUPT_STATUS_CONTINUE11 |
5340 | #define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 |
5341 | #define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 |
5342 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf |
5343 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 |
5344 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 |
5345 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 |
5346 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 |
5347 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 |
5348 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 |
5349 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 |
5350 | #define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 |
5351 | #define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f |
5352 | #define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L |
5353 | #define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L |
5354 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L |
5355 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L |
5356 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L |
5357 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L |
5358 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L |
5359 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L |
5360 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L |
5361 | #define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L |
5362 | #define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L |
5363 | #define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L |
5364 | //DISP_INTERRUPT_STATUS_CONTINUE12 |
5365 | #define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5366 | #define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5367 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5368 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5369 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5370 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5371 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f |
5372 | #define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5373 | #define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5374 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5375 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5376 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5377 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5378 | #define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L |
5379 | //DISP_INTERRUPT_STATUS_CONTINUE13 |
5380 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5381 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5382 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 |
5383 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa |
5384 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb |
5385 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc |
5386 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd |
5387 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe |
5388 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf |
5389 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 |
5390 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5391 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5392 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b |
5393 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c |
5394 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d |
5395 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e |
5396 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f |
5397 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5398 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5399 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L |
5400 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L |
5401 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L |
5402 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L |
5403 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L |
5404 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L |
5405 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L |
5406 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L |
5407 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5408 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5409 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L |
5410 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L |
5411 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L |
5412 | #define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L |
5413 | #define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L |
5414 | //DISP_INTERRUPT_STATUS_CONTINUE14 |
5415 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5416 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5417 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5418 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5419 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5420 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5421 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b |
5422 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c |
5423 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d |
5424 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e |
5425 | #define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f |
5426 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5427 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5428 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5429 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5430 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5431 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5432 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L |
5433 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L |
5434 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L |
5435 | #define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L |
5436 | #define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L |
5437 | //DISP_INTERRUPT_STATUS_CONTINUE15 |
5438 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5439 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5440 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
5441 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
5442 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5443 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5444 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b |
5445 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c |
5446 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d |
5447 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1e |
5448 | #define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f |
5449 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5450 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5451 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L |
5452 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L |
5453 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5454 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5455 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L |
5456 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L |
5457 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L |
5458 | #define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x40000000L |
5459 | #define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L |
5460 | //DISP_INTERRUPT_STATUS_CONTINUE16 |
5461 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5462 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5463 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 |
5464 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa |
5465 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb |
5466 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc |
5467 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd |
5468 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe |
5469 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf |
5470 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 |
5471 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 |
5472 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 |
5473 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 |
5474 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 |
5475 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 |
5476 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 |
5477 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 |
5478 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x18 |
5479 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x19 |
5480 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1a |
5481 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1b |
5482 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT__SHIFT 0x1c |
5483 | #define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f |
5484 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5485 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5486 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L |
5487 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L |
5488 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L |
5489 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L |
5490 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L |
5491 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L |
5492 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L |
5493 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L |
5494 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L |
5495 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L |
5496 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L |
5497 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L |
5498 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L |
5499 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L |
5500 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L |
5501 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x01000000L |
5502 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x02000000L |
5503 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x04000000L |
5504 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x08000000L |
5505 | #define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT_MASK 0x10000000L |
5506 | #define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L |
5507 | //DISP_INTERRUPT_STATUS_CONTINUE17 |
5508 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5509 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5510 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 |
5511 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 |
5512 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 |
5513 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 |
5514 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 |
5515 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 |
5516 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 |
5517 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 |
5518 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa |
5519 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb |
5520 | #define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
5521 | #define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
5522 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 |
5523 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 |
5524 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 |
5525 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 |
5526 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 |
5527 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 |
5528 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a |
5529 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b |
5530 | #define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f |
5531 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5532 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5533 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L |
5534 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L |
5535 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L |
5536 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L |
5537 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L |
5538 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L |
5539 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L |
5540 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L |
5541 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L |
5542 | #define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L |
5543 | #define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L |
5544 | #define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L |
5545 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L |
5546 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L |
5547 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L |
5548 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L |
5549 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L |
5550 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L |
5551 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L |
5552 | #define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L |
5553 | #define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L |
5554 | //DISP_INTERRUPT_STATUS_CONTINUE18 |
5555 | #define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
5556 | #define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
5557 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 |
5558 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa |
5559 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb |
5560 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc |
5561 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd |
5562 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe |
5563 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf |
5564 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 |
5565 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 |
5566 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 |
5567 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 |
5568 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 |
5569 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 |
5570 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 |
5571 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 |
5572 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 |
5573 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f |
5574 | #define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L |
5575 | #define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L |
5576 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L |
5577 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L |
5578 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L |
5579 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L |
5580 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L |
5581 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L |
5582 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L |
5583 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L |
5584 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L |
5585 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L |
5586 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L |
5587 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L |
5588 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L |
5589 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L |
5590 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L |
5591 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L |
5592 | #define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L |
5593 | //DISP_INTERRUPT_STATUS_CONTINUE19 |
5594 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 |
5595 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 |
5596 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 |
5597 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 |
5598 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 |
5599 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 |
5600 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 |
5601 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 |
5602 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 |
5603 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 |
5604 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa |
5605 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb |
5606 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc |
5607 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd |
5608 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe |
5609 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf |
5610 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 |
5611 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 |
5612 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 |
5613 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 |
5614 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 |
5615 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 |
5616 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 |
5617 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 |
5618 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c |
5619 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d |
5620 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f |
5621 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L |
5622 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L |
5623 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L |
5624 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L |
5625 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L |
5626 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L |
5627 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L |
5628 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L |
5629 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L |
5630 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L |
5631 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L |
5632 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L |
5633 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L |
5634 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L |
5635 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L |
5636 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L |
5637 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L |
5638 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L |
5639 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L |
5640 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L |
5641 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L |
5642 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L |
5643 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L |
5644 | #define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L |
5645 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L |
5646 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L |
5647 | #define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L |
5648 | //DISP_INTERRUPT_STATUS_CONTINUE20 |
5649 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 |
5650 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 |
5651 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 |
5652 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 |
5653 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 |
5654 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 |
5655 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 |
5656 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 |
5657 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 |
5658 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 |
5659 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa |
5660 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb |
5661 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc |
5662 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd |
5663 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe |
5664 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf |
5665 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 |
5666 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 |
5667 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 |
5668 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 |
5669 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 |
5670 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 |
5671 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 |
5672 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 |
5673 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 |
5674 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 |
5675 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a |
5676 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b |
5677 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c |
5678 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d |
5679 | #define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f |
5680 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L |
5681 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L |
5682 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L |
5683 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L |
5684 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L |
5685 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L |
5686 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L |
5687 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L |
5688 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L |
5689 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L |
5690 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L |
5691 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L |
5692 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L |
5693 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L |
5694 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L |
5695 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L |
5696 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L |
5697 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L |
5698 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L |
5699 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L |
5700 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L |
5701 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L |
5702 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L |
5703 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L |
5704 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L |
5705 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L |
5706 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L |
5707 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L |
5708 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L |
5709 | #define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L |
5710 | #define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L |
5711 | //DISP_INTERRUPT_STATUS_CONTINUE21 |
5712 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 |
5713 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 |
5714 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 |
5715 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 |
5716 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 |
5717 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 |
5718 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 |
5719 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 |
5720 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 |
5721 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 |
5722 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa |
5723 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb |
5724 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc |
5725 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd |
5726 | #define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe |
5727 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c |
5728 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d |
5729 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f |
5730 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L |
5731 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L |
5732 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L |
5733 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L |
5734 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L |
5735 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L |
5736 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L |
5737 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L |
5738 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L |
5739 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L |
5740 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L |
5741 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L |
5742 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L |
5743 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L |
5744 | #define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L |
5745 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L |
5746 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L |
5747 | #define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L |
5748 | //DISP_INTERRUPT_STATUS_CONTINUE22 |
5749 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0 |
5750 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1 |
5751 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2 |
5752 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3 |
5753 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4 |
5754 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5 |
5755 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6 |
5756 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7 |
5757 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8 |
5758 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9 |
5759 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa |
5760 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb |
5761 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc |
5762 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd |
5763 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe |
5764 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf |
5765 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 |
5766 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 |
5767 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 |
5768 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 |
5769 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 |
5770 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 |
5771 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 |
5772 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 |
5773 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 |
5774 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L |
5775 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L |
5776 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L |
5777 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L |
5778 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L |
5779 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L |
5780 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L |
5781 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L |
5782 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L |
5783 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L |
5784 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L |
5785 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L |
5786 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L |
5787 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L |
5788 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L |
5789 | #define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L |
5790 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L |
5791 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L |
5792 | #define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L |
5793 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L |
5794 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L |
5795 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L |
5796 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L |
5797 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L |
5798 | #define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L |
5799 | //DC_GPU_TIMER_START_POSITION_VREADY |
5800 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 |
5801 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 |
5802 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 |
5803 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc |
5804 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 |
5805 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 |
5806 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L |
5807 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L |
5808 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L |
5809 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L |
5810 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L |
5811 | #define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L |
5812 | //DC_GPU_TIMER_START_POSITION_FLIP |
5813 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 |
5814 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 |
5815 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 |
5816 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc |
5817 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 |
5818 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 |
5819 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 |
5820 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c |
5821 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L |
5822 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L |
5823 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L |
5824 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L |
5825 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L |
5826 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L |
5827 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L |
5828 | #define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L |
5829 | //DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK |
5830 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 |
5831 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 |
5832 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 |
5833 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc |
5834 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 |
5835 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 |
5836 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L |
5837 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L |
5838 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L |
5839 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L |
5840 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L |
5841 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L |
5842 | //DC_GPU_TIMER_START_POSITION_FLIP_AWAY |
5843 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 |
5844 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 |
5845 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 |
5846 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc |
5847 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 |
5848 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 |
5849 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 |
5850 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c |
5851 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L |
5852 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L |
5853 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L |
5854 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L |
5855 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L |
5856 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L |
5857 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L |
5858 | #define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L |
5859 | |
5860 | |
5861 | // addressBlock: dce_dc_wb0_dispdec_cnv_dispdec |
5862 | //CNV0_WB_ENABLE |
5863 | #define CNV0_WB_ENABLE__WB_ENABLE__SHIFT 0x0 |
5864 | #define CNV0_WB_ENABLE__WB_ENABLE_MASK 0x00000001L |
5865 | //CNV0_WB_EC_CONFIG |
5866 | #define CNV0_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 |
5867 | #define CNV0_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 |
5868 | #define CNV0_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 |
5869 | #define CNV0_WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 |
5870 | #define CNV0_WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 |
5871 | #define CNV0_WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 |
5872 | #define CNV0_WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 |
5873 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc |
5874 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe |
5875 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf |
5876 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11 |
5877 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13 |
5878 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 |
5879 | #define CNV0_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 |
5880 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18 |
5881 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a |
5882 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c |
5883 | #define CNV0_WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e |
5884 | #define CNV0_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L |
5885 | #define CNV0_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L |
5886 | #define CNV0_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L |
5887 | #define CNV0_WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L |
5888 | #define CNV0_WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L |
5889 | #define CNV0_WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L |
5890 | #define CNV0_WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L |
5891 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L |
5892 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L |
5893 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L |
5894 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L |
5895 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L |
5896 | #define CNV0_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L |
5897 | #define CNV0_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L |
5898 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L |
5899 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L |
5900 | #define CNV0_WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L |
5901 | #define CNV0_WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L |
5902 | //CNV0_CNV_MODE |
5903 | #define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 |
5904 | #define CNV0_CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc |
5905 | #define CNV0_CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd |
5906 | #define CNV0_CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf |
5907 | #define CNV0_CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 |
5908 | #define CNV0_CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 |
5909 | #define CNV0_CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 |
5910 | #define CNV0_CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 |
5911 | #define CNV0_CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 |
5912 | #define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f |
5913 | #define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L |
5914 | #define CNV0_CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L |
5915 | #define CNV0_CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L |
5916 | #define CNV0_CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L |
5917 | #define CNV0_CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L |
5918 | #define CNV0_CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L |
5919 | #define CNV0_CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L |
5920 | #define CNV0_CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L |
5921 | #define CNV0_CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L |
5922 | #define CNV0_CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L |
5923 | //CNV0_CNV_WINDOW_START |
5924 | #define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 |
5925 | #define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 |
5926 | #define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL |
5927 | #define CNV0_CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L |
5928 | //CNV0_CNV_WINDOW_SIZE |
5929 | #define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 |
5930 | #define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 |
5931 | #define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL |
5932 | #define CNV0_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L |
5933 | //CNV0_CNV_UPDATE |
5934 | #define CNV0_CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 |
5935 | #define CNV0_CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 |
5936 | #define CNV0_CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 |
5937 | #define CNV0_CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L |
5938 | #define CNV0_CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L |
5939 | #define CNV0_CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L |
5940 | //CNV0_CNV_SOURCE_SIZE |
5941 | #define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 |
5942 | #define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 |
5943 | #define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL |
5944 | #define CNV0_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L |
5945 | //CNV0_CNV_CSC_CONTROL |
5946 | #define CNV0_CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 |
5947 | #define CNV0_CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L |
5948 | //CNV0_CNV_CSC_C11_C12 |
5949 | #define CNV0_CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 |
5950 | #define CNV0_CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 |
5951 | #define CNV0_CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL |
5952 | #define CNV0_CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L |
5953 | //CNV0_CNV_CSC_C13_C14 |
5954 | #define CNV0_CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 |
5955 | #define CNV0_CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 |
5956 | #define CNV0_CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL |
5957 | #define CNV0_CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L |
5958 | //CNV0_CNV_CSC_C21_C22 |
5959 | #define CNV0_CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 |
5960 | #define CNV0_CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 |
5961 | #define CNV0_CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL |
5962 | #define CNV0_CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L |
5963 | //CNV0_CNV_CSC_C23_C24 |
5964 | #define CNV0_CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 |
5965 | #define CNV0_CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 |
5966 | #define CNV0_CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL |
5967 | #define CNV0_CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L |
5968 | //CNV0_CNV_CSC_C31_C32 |
5969 | #define CNV0_CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 |
5970 | #define CNV0_CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 |
5971 | #define CNV0_CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL |
5972 | #define CNV0_CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L |
5973 | //CNV0_CNV_CSC_C33_C34 |
5974 | #define CNV0_CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 |
5975 | #define CNV0_CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 |
5976 | #define CNV0_CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL |
5977 | #define CNV0_CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L |
5978 | //CNV0_CNV_CSC_ROUND_OFFSET_R |
5979 | #define CNV0_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 |
5980 | #define CNV0_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL |
5981 | //CNV0_CNV_CSC_ROUND_OFFSET_G |
5982 | #define CNV0_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 |
5983 | #define CNV0_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL |
5984 | //CNV0_CNV_CSC_ROUND_OFFSET_B |
5985 | #define CNV0_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 |
5986 | #define CNV0_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL |
5987 | //CNV0_CNV_CSC_CLAMP_R |
5988 | #define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 |
5989 | #define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 |
5990 | #define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL |
5991 | #define CNV0_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L |
5992 | //CNV0_CNV_CSC_CLAMP_G |
5993 | #define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 |
5994 | #define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 |
5995 | #define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL |
5996 | #define CNV0_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L |
5997 | //CNV0_CNV_CSC_CLAMP_B |
5998 | #define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 |
5999 | #define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 |
6000 | #define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL |
6001 | #define CNV0_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L |
6002 | //CNV0_CNV_TEST_CNTL |
6003 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 |
6004 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 |
6005 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 |
6006 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L |
6007 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L |
6008 | #define CNV0_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L |
6009 | //CNV0_CNV_TEST_CRC_RED |
6010 | #define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 |
6011 | #define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 |
6012 | #define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L |
6013 | #define CNV0_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L |
6014 | //CNV0_CNV_TEST_CRC_GREEN |
6015 | #define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 |
6016 | #define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
6017 | #define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L |
6018 | #define CNV0_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L |
6019 | //CNV0_CNV_TEST_CRC_BLUE |
6020 | #define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 |
6021 | #define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
6022 | #define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L |
6023 | #define CNV0_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L |
6024 | //CNV0_CNV_INPUT_SELECT |
6025 | #define CNV0_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 |
6026 | #define CNV0_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 |
6027 | #define CNV0_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L |
6028 | #define CNV0_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL |
6029 | //CNV0_WB_SOFT_RESET |
6030 | #define CNV0_WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 |
6031 | #define CNV0_WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L |
6032 | //CNV0_WB_WARM_UP_MODE_CTL1 |
6033 | #define CNV0_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 |
6034 | #define CNV0_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 |
6035 | #define CNV0_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f |
6036 | #define CNV0_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL |
6037 | #define CNV0_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L |
6038 | #define CNV0_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L |
6039 | //CNV0_WB_WARM_UP_MODE_CTL2 |
6040 | #define CNV0_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 |
6041 | #define CNV0_WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8 |
6042 | #define CNV0_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL |
6043 | #define CNV0_WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L |
6044 | |
6045 | |
6046 | // addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec |
6047 | //WBSCL0_WBSCL_COEF_RAM_SELECT |
6048 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
6049 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 |
6050 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
6051 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L |
6052 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L |
6053 | #define WBSCL0_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L |
6054 | //WBSCL0_WBSCL_COEF_RAM_TAP_DATA |
6055 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
6056 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
6057 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
6058 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
6059 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
6060 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
6061 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
6062 | #define WBSCL0_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
6063 | //WBSCL0_WBSCL_MODE |
6064 | #define WBSCL0_WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 |
6065 | #define WBSCL0_WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L |
6066 | //WBSCL0_WBSCL_TAP_CONTROL |
6067 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 |
6068 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 |
6069 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 |
6070 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc |
6071 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL |
6072 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L |
6073 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L |
6074 | #define WBSCL0_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L |
6075 | //WBSCL0_WBSCL_DEST_SIZE |
6076 | #define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 |
6077 | #define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 |
6078 | #define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL |
6079 | #define WBSCL0_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L |
6080 | //WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO |
6081 | #define WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 |
6082 | #define WBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL |
6083 | //WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB |
6084 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 |
6085 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 |
6086 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL |
6087 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L |
6088 | //WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR |
6089 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 |
6090 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 |
6091 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL |
6092 | #define WBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L |
6093 | //WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO |
6094 | #define WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 |
6095 | #define WBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL |
6096 | //WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB |
6097 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 |
6098 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 |
6099 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL |
6100 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L |
6101 | //WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR |
6102 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 |
6103 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 |
6104 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL |
6105 | #define WBSCL0_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L |
6106 | //WBSCL0_WBSCL_ROUND_OFFSET |
6107 | #define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 |
6108 | #define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
6109 | #define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL |
6110 | #define WBSCL0_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L |
6111 | //WBSCL0_WBSCL_CLAMP |
6112 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 |
6113 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 |
6114 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10 |
6115 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18 |
6116 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL |
6117 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L |
6118 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L |
6119 | #define WBSCL0_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L |
6120 | //WBSCL0_WBSCL_OVERFLOW_STATUS |
6121 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 |
6122 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 |
6123 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc |
6124 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 |
6125 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 |
6126 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L |
6127 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L |
6128 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L |
6129 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L |
6130 | #define WBSCL0_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L |
6131 | //WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS |
6132 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 |
6133 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 |
6134 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc |
6135 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 |
6136 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 |
6137 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L |
6138 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L |
6139 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L |
6140 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L |
6141 | #define WBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L |
6142 | //WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY |
6143 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 |
6144 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8 |
6145 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 |
6146 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18 |
6147 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L |
6148 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L |
6149 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L |
6150 | #define WBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L |
6151 | //WBSCL0_WBSCL_TEST_CNTL |
6152 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 |
6153 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 |
6154 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10 |
6155 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L |
6156 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L |
6157 | #define WBSCL0_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L |
6158 | //WBSCL0_WBSCL_TEST_CRC_RED |
6159 | #define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8 |
6160 | #define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 |
6161 | #define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L |
6162 | #define WBSCL0_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L |
6163 | //WBSCL0_WBSCL_TEST_CRC_GREEN |
6164 | #define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 |
6165 | #define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
6166 | #define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL |
6167 | #define WBSCL0_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L |
6168 | //WBSCL0_WBSCL_TEST_CRC_BLUE |
6169 | #define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8 |
6170 | #define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
6171 | #define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L |
6172 | #define WBSCL0_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L |
6173 | //WBSCL0_WBSCL_BACKPRESSURE_CNT_EN |
6174 | #define WBSCL0_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 |
6175 | #define WBSCL0_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L |
6176 | //WBSCL0_WB_MCIF_BACKPRESSURE_CNT |
6177 | #define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 |
6178 | #define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 |
6179 | #define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL |
6180 | #define WBSCL0_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L |
6181 | //WBSCL0_WBSCL_RAM_SHUTDOWN |
6182 | #define WBSCL0_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0 |
6183 | #define WBSCL0_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L |
6184 | |
6185 | |
6186 | // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec |
6187 | //DC_PERFMON3_PERFCOUNTER_CNTL |
6188 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
6189 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
6190 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
6191 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
6192 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
6193 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
6194 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
6195 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
6196 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
6197 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
6198 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
6199 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
6200 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
6201 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
6202 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
6203 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
6204 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
6205 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
6206 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
6207 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
6208 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
6209 | #define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
6210 | //DC_PERFMON3_PERFCOUNTER_CNTL2 |
6211 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
6212 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
6213 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
6214 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
6215 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
6216 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
6217 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
6218 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
6219 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
6220 | #define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
6221 | //DC_PERFMON3_PERFCOUNTER_STATE |
6222 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
6223 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
6224 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
6225 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
6226 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
6227 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
6228 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
6229 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
6230 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
6231 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
6232 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
6233 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
6234 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
6235 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
6236 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
6237 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
6238 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
6239 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
6240 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
6241 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
6242 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
6243 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
6244 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
6245 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
6246 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
6247 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
6248 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
6249 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
6250 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
6251 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
6252 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
6253 | #define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
6254 | //DC_PERFMON3_PERFMON_CNTL |
6255 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
6256 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
6257 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
6258 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
6259 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
6260 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
6261 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
6262 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
6263 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
6264 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
6265 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
6266 | #define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
6267 | //DC_PERFMON3_PERFMON_CNTL2 |
6268 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
6269 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
6270 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
6271 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
6272 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
6273 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
6274 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
6275 | #define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
6276 | //DC_PERFMON3_PERFMON_CVALUE_INT_MISC |
6277 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
6278 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
6279 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
6280 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
6281 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
6282 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
6283 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
6284 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
6285 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
6286 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
6287 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
6288 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
6289 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
6290 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
6291 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
6292 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
6293 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
6294 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
6295 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
6296 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
6297 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
6298 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
6299 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
6300 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
6301 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
6302 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
6303 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
6304 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
6305 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
6306 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
6307 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
6308 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
6309 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
6310 | #define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
6311 | //DC_PERFMON3_PERFMON_CVALUE_LOW |
6312 | #define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
6313 | #define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
6314 | //DC_PERFMON3_PERFMON_HI |
6315 | #define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
6316 | #define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
6317 | #define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
6318 | #define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
6319 | //DC_PERFMON3_PERFMON_LOW |
6320 | #define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
6321 | #define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
6322 | |
6323 | |
6324 | // addressBlock: dce_dc_wb1_dispdec_cnv_dispdec |
6325 | //CNV1_WB_ENABLE |
6326 | #define CNV1_WB_ENABLE__WB_ENABLE__SHIFT 0x0 |
6327 | #define CNV1_WB_ENABLE__WB_ENABLE_MASK 0x00000001L |
6328 | //CNV1_WB_EC_CONFIG |
6329 | #define CNV1_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 |
6330 | #define CNV1_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 |
6331 | #define CNV1_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 |
6332 | #define CNV1_WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 |
6333 | #define CNV1_WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 |
6334 | #define CNV1_WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 |
6335 | #define CNV1_WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 |
6336 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc |
6337 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe |
6338 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf |
6339 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM__SHIFT 0x11 |
6340 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG__SHIFT 0x13 |
6341 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 |
6342 | #define CNV1_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 |
6343 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM__SHIFT 0x18 |
6344 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG__SHIFT 0x1a |
6345 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c |
6346 | #define CNV1_WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e |
6347 | #define CNV1_WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L |
6348 | #define CNV1_WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L |
6349 | #define CNV1_WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L |
6350 | #define CNV1_WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L |
6351 | #define CNV1_WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L |
6352 | #define CNV1_WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L |
6353 | #define CNV1_WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L |
6354 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L |
6355 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L |
6356 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L |
6357 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_SM_MASK 0x00060000L |
6358 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_BG_MASK 0x00180000L |
6359 | #define CNV1_WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L |
6360 | #define CNV1_WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L |
6361 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_SM_MASK 0x03000000L |
6362 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_BG_MASK 0x0C000000L |
6363 | #define CNV1_WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000L |
6364 | #define CNV1_WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xC0000000L |
6365 | //CNV1_CNV_MODE |
6366 | #define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 |
6367 | #define CNV1_CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc |
6368 | #define CNV1_CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd |
6369 | #define CNV1_CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf |
6370 | #define CNV1_CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 |
6371 | #define CNV1_CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 |
6372 | #define CNV1_CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 |
6373 | #define CNV1_CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 |
6374 | #define CNV1_CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 |
6375 | #define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f |
6376 | #define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L |
6377 | #define CNV1_CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L |
6378 | #define CNV1_CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L |
6379 | #define CNV1_CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L |
6380 | #define CNV1_CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L |
6381 | #define CNV1_CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L |
6382 | #define CNV1_CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L |
6383 | #define CNV1_CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L |
6384 | #define CNV1_CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L |
6385 | #define CNV1_CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L |
6386 | //CNV1_CNV_WINDOW_START |
6387 | #define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 |
6388 | #define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 |
6389 | #define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL |
6390 | #define CNV1_CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L |
6391 | //CNV1_CNV_WINDOW_SIZE |
6392 | #define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 |
6393 | #define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 |
6394 | #define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL |
6395 | #define CNV1_CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L |
6396 | //CNV1_CNV_UPDATE |
6397 | #define CNV1_CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 |
6398 | #define CNV1_CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 |
6399 | #define CNV1_CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 |
6400 | #define CNV1_CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L |
6401 | #define CNV1_CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L |
6402 | #define CNV1_CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L |
6403 | //CNV1_CNV_SOURCE_SIZE |
6404 | #define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 |
6405 | #define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 |
6406 | #define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL |
6407 | #define CNV1_CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L |
6408 | //CNV1_CNV_CSC_CONTROL |
6409 | #define CNV1_CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 |
6410 | #define CNV1_CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x00000001L |
6411 | //CNV1_CNV_CSC_C11_C12 |
6412 | #define CNV1_CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 |
6413 | #define CNV1_CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 |
6414 | #define CNV1_CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x00001FFFL |
6415 | #define CNV1_CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1FFF0000L |
6416 | //CNV1_CNV_CSC_C13_C14 |
6417 | #define CNV1_CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 |
6418 | #define CNV1_CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 |
6419 | #define CNV1_CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x00001FFFL |
6420 | #define CNV1_CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7FFF0000L |
6421 | //CNV1_CNV_CSC_C21_C22 |
6422 | #define CNV1_CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 |
6423 | #define CNV1_CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 |
6424 | #define CNV1_CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x00001FFFL |
6425 | #define CNV1_CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1FFF0000L |
6426 | //CNV1_CNV_CSC_C23_C24 |
6427 | #define CNV1_CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 |
6428 | #define CNV1_CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 |
6429 | #define CNV1_CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x00001FFFL |
6430 | #define CNV1_CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7FFF0000L |
6431 | //CNV1_CNV_CSC_C31_C32 |
6432 | #define CNV1_CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 |
6433 | #define CNV1_CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 |
6434 | #define CNV1_CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x00001FFFL |
6435 | #define CNV1_CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1FFF0000L |
6436 | //CNV1_CNV_CSC_C33_C34 |
6437 | #define CNV1_CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 |
6438 | #define CNV1_CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 |
6439 | #define CNV1_CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x00001FFFL |
6440 | #define CNV1_CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7FFF0000L |
6441 | //CNV1_CNV_CSC_ROUND_OFFSET_R |
6442 | #define CNV1_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 |
6443 | #define CNV1_CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0x0000FFFFL |
6444 | //CNV1_CNV_CSC_ROUND_OFFSET_G |
6445 | #define CNV1_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 |
6446 | #define CNV1_CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0x0000FFFFL |
6447 | //CNV1_CNV_CSC_ROUND_OFFSET_B |
6448 | #define CNV1_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 |
6449 | #define CNV1_CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0x0000FFFFL |
6450 | //CNV1_CNV_CSC_CLAMP_R |
6451 | #define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 |
6452 | #define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 |
6453 | #define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0x0000FFFFL |
6454 | #define CNV1_CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xFFFF0000L |
6455 | //CNV1_CNV_CSC_CLAMP_G |
6456 | #define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 |
6457 | #define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 |
6458 | #define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0x0000FFFFL |
6459 | #define CNV1_CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xFFFF0000L |
6460 | //CNV1_CNV_CSC_CLAMP_B |
6461 | #define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 |
6462 | #define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 |
6463 | #define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0x0000FFFFL |
6464 | #define CNV1_CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xFFFF0000L |
6465 | //CNV1_CNV_TEST_CNTL |
6466 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 |
6467 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 |
6468 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 |
6469 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L |
6470 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L |
6471 | #define CNV1_CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x00010000L |
6472 | //CNV1_CNV_TEST_CRC_RED |
6473 | #define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 |
6474 | #define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 |
6475 | #define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L |
6476 | #define CNV1_CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L |
6477 | //CNV1_CNV_TEST_CRC_GREEN |
6478 | #define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 |
6479 | #define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
6480 | #define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L |
6481 | #define CNV1_CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L |
6482 | //CNV1_CNV_TEST_CRC_BLUE |
6483 | #define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 |
6484 | #define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
6485 | #define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L |
6486 | #define CNV1_CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L |
6487 | //CNV1_CNV_INPUT_SELECT |
6488 | #define CNV1_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 |
6489 | #define CNV1_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 |
6490 | #define CNV1_CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x00000003L |
6491 | #define CNV1_CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x0000001CL |
6492 | //CNV1_WB_SOFT_RESET |
6493 | #define CNV1_WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 |
6494 | #define CNV1_WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L |
6495 | //CNV1_WB_WARM_UP_MODE_CTL1 |
6496 | #define CNV1_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 |
6497 | #define CNV1_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 |
6498 | #define CNV1_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f |
6499 | #define CNV1_WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL |
6500 | #define CNV1_WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L |
6501 | #define CNV1_WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L |
6502 | //CNV1_WB_WARM_UP_MODE_CTL2 |
6503 | #define CNV1_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 |
6504 | #define CNV1_WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x8 |
6505 | #define CNV1_WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000000FFL |
6506 | #define CNV1_WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00000100L |
6507 | |
6508 | |
6509 | // addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec |
6510 | //WBSCL1_WBSCL_COEF_RAM_SELECT |
6511 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
6512 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 |
6513 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
6514 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L |
6515 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L |
6516 | #define WBSCL1_WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L |
6517 | //WBSCL1_WBSCL_COEF_RAM_TAP_DATA |
6518 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
6519 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
6520 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
6521 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
6522 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
6523 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
6524 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
6525 | #define WBSCL1_WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
6526 | //WBSCL1_WBSCL_MODE |
6527 | #define WBSCL1_WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 |
6528 | #define WBSCL1_WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L |
6529 | //WBSCL1_WBSCL_TAP_CONTROL |
6530 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 |
6531 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 |
6532 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 |
6533 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc |
6534 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL |
6535 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L |
6536 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L |
6537 | #define WBSCL1_WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L |
6538 | //WBSCL1_WBSCL_DEST_SIZE |
6539 | #define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 |
6540 | #define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 |
6541 | #define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL |
6542 | #define WBSCL1_WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L |
6543 | //WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO |
6544 | #define WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 |
6545 | #define WBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL |
6546 | //WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB |
6547 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 |
6548 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 |
6549 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL |
6550 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L |
6551 | //WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR |
6552 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 |
6553 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 |
6554 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL |
6555 | #define WBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L |
6556 | //WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO |
6557 | #define WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 |
6558 | #define WBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL |
6559 | //WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB |
6560 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 |
6561 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 |
6562 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL |
6563 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L |
6564 | //WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR |
6565 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 |
6566 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 |
6567 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL |
6568 | #define WBSCL1_WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L |
6569 | //WBSCL1_WBSCL_ROUND_OFFSET |
6570 | #define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 |
6571 | #define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
6572 | #define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x0000FFFFL |
6573 | #define WBSCL1_WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0xFFFF0000L |
6574 | //WBSCL1_WBSCL_CLAMP |
6575 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 |
6576 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 |
6577 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x10 |
6578 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x18 |
6579 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000000FFL |
6580 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x0000FF00L |
6581 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_UPPER_CBCR_MASK 0x00FF0000L |
6582 | #define WBSCL1_WBSCL_CLAMP__WBSCL_CLAMP_LOWER_CBCR_MASK 0xFF000000L |
6583 | //WBSCL1_WBSCL_OVERFLOW_STATUS |
6584 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 |
6585 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 |
6586 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc |
6587 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 |
6588 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 |
6589 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L |
6590 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L |
6591 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L |
6592 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L |
6593 | #define WBSCL1_WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L |
6594 | //WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS |
6595 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 |
6596 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 |
6597 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc |
6598 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 |
6599 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 |
6600 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L |
6601 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L |
6602 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L |
6603 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L |
6604 | #define WBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L |
6605 | //WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY |
6606 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 |
6607 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x8 |
6608 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 |
6609 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x18 |
6610 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L |
6611 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_B_CB_MASK 0x0000FF00L |
6612 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x00FF0000L |
6613 | #define WBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_R_CR_MASK 0xFF000000L |
6614 | //WBSCL1_WBSCL_TEST_CNTL |
6615 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 |
6616 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 |
6617 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY__SHIFT 0x10 |
6618 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L |
6619 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L |
6620 | #define WBSCL1_WBSCL_TEST_CNTL__WBSCL_TEST_CRC_DE_ONLY_MASK 0x00010000L |
6621 | //WBSCL1_WBSCL_TEST_CRC_RED |
6622 | #define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x8 |
6623 | #define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 |
6624 | #define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x0000FF00L |
6625 | #define WBSCL1_WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L |
6626 | //WBSCL1_WBSCL_TEST_CRC_GREEN |
6627 | #define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 |
6628 | #define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
6629 | #define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL |
6630 | #define WBSCL1_WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L |
6631 | //WBSCL1_WBSCL_TEST_CRC_BLUE |
6632 | #define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x8 |
6633 | #define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
6634 | #define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x0000FF00L |
6635 | #define WBSCL1_WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L |
6636 | //WBSCL1_WBSCL_BACKPRESSURE_CNT_EN |
6637 | #define WBSCL1_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 |
6638 | #define WBSCL1_WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L |
6639 | //WBSCL1_WB_MCIF_BACKPRESSURE_CNT |
6640 | #define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 |
6641 | #define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 |
6642 | #define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL |
6643 | #define WBSCL1_WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L |
6644 | //WBSCL1_WBSCL_RAM_SHUTDOWN |
6645 | #define WBSCL1_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL__SHIFT 0x0 |
6646 | #define WBSCL1_WBSCL_RAM_SHUTDOWN__WBSCL_RAM_SHUTDOWN_SEL_MASK 0x00000003L |
6647 | |
6648 | |
6649 | // addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec |
6650 | //DC_PERFMON4_PERFCOUNTER_CNTL |
6651 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
6652 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
6653 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
6654 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
6655 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
6656 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
6657 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
6658 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
6659 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
6660 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
6661 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
6662 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
6663 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
6664 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
6665 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
6666 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
6667 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
6668 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
6669 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
6670 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
6671 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
6672 | #define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
6673 | //DC_PERFMON4_PERFCOUNTER_CNTL2 |
6674 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
6675 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
6676 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
6677 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
6678 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
6679 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
6680 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
6681 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
6682 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
6683 | #define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
6684 | //DC_PERFMON4_PERFCOUNTER_STATE |
6685 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
6686 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
6687 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
6688 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
6689 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
6690 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
6691 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
6692 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
6693 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
6694 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
6695 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
6696 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
6697 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
6698 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
6699 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
6700 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
6701 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
6702 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
6703 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
6704 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
6705 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
6706 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
6707 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
6708 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
6709 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
6710 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
6711 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
6712 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
6713 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
6714 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
6715 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
6716 | #define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
6717 | //DC_PERFMON4_PERFMON_CNTL |
6718 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
6719 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
6720 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
6721 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
6722 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
6723 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
6724 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
6725 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
6726 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
6727 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
6728 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
6729 | #define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
6730 | //DC_PERFMON4_PERFMON_CNTL2 |
6731 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
6732 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
6733 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
6734 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
6735 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
6736 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
6737 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
6738 | #define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
6739 | //DC_PERFMON4_PERFMON_CVALUE_INT_MISC |
6740 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
6741 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
6742 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
6743 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
6744 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
6745 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
6746 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
6747 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
6748 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
6749 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
6750 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
6751 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
6752 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
6753 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
6754 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
6755 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
6756 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
6757 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
6758 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
6759 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
6760 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
6761 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
6762 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
6763 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
6764 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
6765 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
6766 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
6767 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
6768 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
6769 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
6770 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
6771 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
6772 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
6773 | #define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
6774 | //DC_PERFMON4_PERFMON_CVALUE_LOW |
6775 | #define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
6776 | #define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
6777 | //DC_PERFMON4_PERFMON_HI |
6778 | #define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
6779 | #define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
6780 | #define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
6781 | #define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
6782 | //DC_PERFMON4_PERFMON_LOW |
6783 | #define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
6784 | #define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
6785 | |
6786 | |
6787 | // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec |
6788 | //MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL |
6789 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 |
6790 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 |
6791 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 |
6792 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 |
6793 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 |
6794 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 |
6795 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 |
6796 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 |
6797 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 |
6798 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L |
6799 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L |
6800 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L |
6801 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L |
6802 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L |
6803 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L |
6804 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L |
6805 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L |
6806 | #define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L |
6807 | //MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R |
6808 | #define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 |
6809 | #define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL |
6810 | //MCIF_WB0_MCIF_WB_BUFMGR_STATUS |
6811 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 |
6812 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 |
6813 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 |
6814 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 |
6815 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 |
6816 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 |
6817 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc |
6818 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c |
6819 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L |
6820 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L |
6821 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L |
6822 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L |
6823 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L |
6824 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L |
6825 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L |
6826 | #define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L |
6827 | //MCIF_WB0_MCIF_WB_BUF_PITCH |
6828 | #define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 |
6829 | #define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 |
6830 | #define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L |
6831 | #define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L |
6832 | //MCIF_WB0_MCIF_WB_BUF_1_STATUS |
6833 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 |
6834 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 |
6835 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 |
6836 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 |
6837 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 |
6838 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 |
6839 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 |
6840 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc |
6841 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf |
6842 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 |
6843 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d |
6844 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e |
6845 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f |
6846 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L |
6847 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L |
6848 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L |
6849 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L |
6850 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L |
6851 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L |
6852 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L |
6853 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L |
6854 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L |
6855 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L |
6856 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L |
6857 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L |
6858 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L |
6859 | //MCIF_WB0_MCIF_WB_BUF_1_STATUS2 |
6860 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 |
6861 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd |
6862 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe |
6863 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 |
6864 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 |
6865 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL |
6866 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L |
6867 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L |
6868 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L |
6869 | #define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L |
6870 | //MCIF_WB0_MCIF_WB_BUF_2_STATUS |
6871 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 |
6872 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 |
6873 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 |
6874 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 |
6875 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 |
6876 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 |
6877 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 |
6878 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc |
6879 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf |
6880 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 |
6881 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d |
6882 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e |
6883 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f |
6884 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L |
6885 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L |
6886 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L |
6887 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L |
6888 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L |
6889 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L |
6890 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L |
6891 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L |
6892 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L |
6893 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L |
6894 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L |
6895 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L |
6896 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L |
6897 | //MCIF_WB0_MCIF_WB_BUF_2_STATUS2 |
6898 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 |
6899 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd |
6900 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe |
6901 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 |
6902 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 |
6903 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL |
6904 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L |
6905 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L |
6906 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L |
6907 | #define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L |
6908 | //MCIF_WB0_MCIF_WB_BUF_3_STATUS |
6909 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 |
6910 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 |
6911 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 |
6912 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 |
6913 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 |
6914 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 |
6915 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 |
6916 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc |
6917 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf |
6918 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 |
6919 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d |
6920 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e |
6921 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f |
6922 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L |
6923 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L |
6924 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L |
6925 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L |
6926 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L |
6927 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L |
6928 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L |
6929 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L |
6930 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L |
6931 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L |
6932 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L |
6933 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L |
6934 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L |
6935 | //MCIF_WB0_MCIF_WB_BUF_3_STATUS2 |
6936 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 |
6937 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd |
6938 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe |
6939 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 |
6940 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 |
6941 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL |
6942 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L |
6943 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L |
6944 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L |
6945 | #define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L |
6946 | //MCIF_WB0_MCIF_WB_BUF_4_STATUS |
6947 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 |
6948 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 |
6949 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 |
6950 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 |
6951 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 |
6952 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 |
6953 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 |
6954 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc |
6955 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf |
6956 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 |
6957 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d |
6958 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e |
6959 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f |
6960 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L |
6961 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L |
6962 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L |
6963 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L |
6964 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L |
6965 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L |
6966 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L |
6967 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L |
6968 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L |
6969 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L |
6970 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L |
6971 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L |
6972 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L |
6973 | //MCIF_WB0_MCIF_WB_BUF_4_STATUS2 |
6974 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 |
6975 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd |
6976 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe |
6977 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 |
6978 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 |
6979 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL |
6980 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L |
6981 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L |
6982 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L |
6983 | #define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L |
6984 | //MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL |
6985 | #define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 |
6986 | #define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 |
6987 | #define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L |
6988 | #define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L |
6989 | //MCIF_WB0_MCIF_WB_SCLK_CHANGE |
6990 | #define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 |
6991 | #define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 |
6992 | #define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L |
6993 | #define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL |
6994 | //MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y |
6995 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 |
6996 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL |
6997 | //MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET |
6998 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 |
6999 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7000 | //MCIF_WB0_MCIF_WB_BUF_1_ADDR_C |
7001 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 |
7002 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL |
7003 | //MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET |
7004 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 |
7005 | #define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7006 | //MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y |
7007 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 |
7008 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL |
7009 | //MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET |
7010 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 |
7011 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7012 | //MCIF_WB0_MCIF_WB_BUF_2_ADDR_C |
7013 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 |
7014 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL |
7015 | //MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET |
7016 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 |
7017 | #define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7018 | //MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y |
7019 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 |
7020 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL |
7021 | //MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET |
7022 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 |
7023 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7024 | //MCIF_WB0_MCIF_WB_BUF_3_ADDR_C |
7025 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 |
7026 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL |
7027 | //MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET |
7028 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 |
7029 | #define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7030 | //MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y |
7031 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 |
7032 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL |
7033 | //MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET |
7034 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 |
7035 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7036 | //MCIF_WB0_MCIF_WB_BUF_4_ADDR_C |
7037 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 |
7038 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL |
7039 | //MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET |
7040 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 |
7041 | #define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7042 | //MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL |
7043 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 |
7044 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 |
7045 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 |
7046 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 |
7047 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 |
7048 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 |
7049 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L |
7050 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L |
7051 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L |
7052 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L |
7053 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L |
7054 | #define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L |
7055 | //MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK |
7056 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 |
7057 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL |
7058 | //MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL |
7059 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 |
7060 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 |
7061 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 |
7062 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 |
7063 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L |
7064 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L |
7065 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L |
7066 | #define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L |
7067 | //MCIF_WB0_MCIF_WB_WATERMARK |
7068 | #define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 |
7069 | #define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL |
7070 | //MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL |
7071 | #define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 |
7072 | #define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L |
7073 | //MCIF_WB0_MCIF_WB_WARM_UP_CNTL |
7074 | #define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 |
7075 | #define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L |
7076 | //MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL |
7077 | #define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 |
7078 | #define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 |
7079 | #define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L |
7080 | #define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L |
7081 | //MCIF_WB0_MULTI_LEVEL_QOS_CTRL |
7082 | #define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 |
7083 | #define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL |
7084 | //MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE |
7085 | #define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 |
7086 | #define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL |
7087 | //MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE |
7088 | #define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 |
7089 | #define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL |
7090 | |
7091 | |
7092 | // addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec |
7093 | //MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL |
7094 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 |
7095 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 |
7096 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 |
7097 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 |
7098 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 |
7099 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 |
7100 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 |
7101 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 |
7102 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 |
7103 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L |
7104 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L |
7105 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L |
7106 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L |
7107 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L |
7108 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L |
7109 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L |
7110 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L |
7111 | #define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L |
7112 | //MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R |
7113 | #define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 |
7114 | #define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL |
7115 | //MCIF_WB1_MCIF_WB_BUFMGR_STATUS |
7116 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 |
7117 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 |
7118 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 |
7119 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 |
7120 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 |
7121 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 |
7122 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc |
7123 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c |
7124 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L |
7125 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L |
7126 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L |
7127 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L |
7128 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L |
7129 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L |
7130 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L |
7131 | #define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L |
7132 | //MCIF_WB1_MCIF_WB_BUF_PITCH |
7133 | #define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 |
7134 | #define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 |
7135 | #define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L |
7136 | #define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L |
7137 | //MCIF_WB1_MCIF_WB_BUF_1_STATUS |
7138 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 |
7139 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 |
7140 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 |
7141 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 |
7142 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 |
7143 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 |
7144 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 |
7145 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc |
7146 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf |
7147 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 |
7148 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d |
7149 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e |
7150 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f |
7151 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L |
7152 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L |
7153 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L |
7154 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L |
7155 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L |
7156 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L |
7157 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L |
7158 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L |
7159 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L |
7160 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L |
7161 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L |
7162 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L |
7163 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L |
7164 | //MCIF_WB1_MCIF_WB_BUF_1_STATUS2 |
7165 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 |
7166 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd |
7167 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe |
7168 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 |
7169 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 |
7170 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL |
7171 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L |
7172 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L |
7173 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L |
7174 | #define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L |
7175 | //MCIF_WB1_MCIF_WB_BUF_2_STATUS |
7176 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 |
7177 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 |
7178 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 |
7179 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 |
7180 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 |
7181 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 |
7182 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 |
7183 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc |
7184 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf |
7185 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 |
7186 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d |
7187 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e |
7188 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f |
7189 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L |
7190 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L |
7191 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L |
7192 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L |
7193 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L |
7194 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L |
7195 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L |
7196 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L |
7197 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L |
7198 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L |
7199 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L |
7200 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L |
7201 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L |
7202 | //MCIF_WB1_MCIF_WB_BUF_2_STATUS2 |
7203 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 |
7204 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd |
7205 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe |
7206 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 |
7207 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 |
7208 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL |
7209 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L |
7210 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L |
7211 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L |
7212 | #define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L |
7213 | //MCIF_WB1_MCIF_WB_BUF_3_STATUS |
7214 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 |
7215 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 |
7216 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 |
7217 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 |
7218 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 |
7219 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 |
7220 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 |
7221 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc |
7222 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf |
7223 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 |
7224 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d |
7225 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e |
7226 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f |
7227 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L |
7228 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L |
7229 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L |
7230 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L |
7231 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L |
7232 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L |
7233 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L |
7234 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L |
7235 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L |
7236 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L |
7237 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L |
7238 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L |
7239 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L |
7240 | //MCIF_WB1_MCIF_WB_BUF_3_STATUS2 |
7241 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 |
7242 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd |
7243 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe |
7244 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 |
7245 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 |
7246 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL |
7247 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L |
7248 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L |
7249 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L |
7250 | #define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L |
7251 | //MCIF_WB1_MCIF_WB_BUF_4_STATUS |
7252 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 |
7253 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 |
7254 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 |
7255 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 |
7256 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 |
7257 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 |
7258 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 |
7259 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc |
7260 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf |
7261 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 |
7262 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d |
7263 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e |
7264 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f |
7265 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L |
7266 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L |
7267 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L |
7268 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L |
7269 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L |
7270 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L |
7271 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L |
7272 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L |
7273 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L |
7274 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L |
7275 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L |
7276 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L |
7277 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L |
7278 | //MCIF_WB1_MCIF_WB_BUF_4_STATUS2 |
7279 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 |
7280 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd |
7281 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe |
7282 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 |
7283 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 |
7284 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL |
7285 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L |
7286 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L |
7287 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L |
7288 | #define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L |
7289 | //MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL |
7290 | #define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 |
7291 | #define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 |
7292 | #define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L |
7293 | #define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L |
7294 | //MCIF_WB1_MCIF_WB_SCLK_CHANGE |
7295 | #define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 |
7296 | #define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 |
7297 | #define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L |
7298 | #define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL |
7299 | //MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y |
7300 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 |
7301 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL |
7302 | //MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET |
7303 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 |
7304 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7305 | //MCIF_WB1_MCIF_WB_BUF_1_ADDR_C |
7306 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 |
7307 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL |
7308 | //MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET |
7309 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 |
7310 | #define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7311 | //MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y |
7312 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 |
7313 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL |
7314 | //MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET |
7315 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 |
7316 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7317 | //MCIF_WB1_MCIF_WB_BUF_2_ADDR_C |
7318 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 |
7319 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL |
7320 | //MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET |
7321 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 |
7322 | #define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7323 | //MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y |
7324 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 |
7325 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL |
7326 | //MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET |
7327 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 |
7328 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7329 | //MCIF_WB1_MCIF_WB_BUF_3_ADDR_C |
7330 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 |
7331 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL |
7332 | //MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET |
7333 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 |
7334 | #define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7335 | //MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y |
7336 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 |
7337 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL |
7338 | //MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET |
7339 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 |
7340 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL |
7341 | //MCIF_WB1_MCIF_WB_BUF_4_ADDR_C |
7342 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 |
7343 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL |
7344 | //MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET |
7345 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 |
7346 | #define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL |
7347 | //MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL |
7348 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 |
7349 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 |
7350 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 |
7351 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 |
7352 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 |
7353 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 |
7354 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L |
7355 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L |
7356 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L |
7357 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L |
7358 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L |
7359 | #define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L |
7360 | //MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK |
7361 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 |
7362 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0001FFFFL |
7363 | //MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL |
7364 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 |
7365 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 |
7366 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 |
7367 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 |
7368 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L |
7369 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L |
7370 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L |
7371 | #define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L |
7372 | //MCIF_WB1_MCIF_WB_WATERMARK |
7373 | #define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 |
7374 | #define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL |
7375 | //MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL |
7376 | #define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 |
7377 | #define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L |
7378 | //MCIF_WB1_MCIF_WB_WARM_UP_CNTL |
7379 | #define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 |
7380 | #define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L |
7381 | //MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL |
7382 | #define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 |
7383 | #define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 |
7384 | #define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L |
7385 | #define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L |
7386 | //MCIF_WB1_MULTI_LEVEL_QOS_CTRL |
7387 | #define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 |
7388 | #define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL |
7389 | //MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE |
7390 | #define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 |
7391 | #define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL |
7392 | //MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE |
7393 | #define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 |
7394 | #define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL |
7395 | |
7396 | |
7397 | // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec |
7398 | //WBIF0_MISC_CTRL |
7399 | #define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 |
7400 | #define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 |
7401 | #define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL |
7402 | #define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L |
7403 | //WBIF0_SMU_WM_CONTROL |
7404 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT 0x14 |
7405 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT 0x16 |
7406 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 |
7407 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 |
7408 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK 0x00300000L |
7409 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK 0x00400000L |
7410 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L |
7411 | #define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L |
7412 | //WBIF0_PHASE0_OUTSTANDING_COUNTER |
7413 | #define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 |
7414 | #define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7415 | //WBIF0_PHASE1_OUTSTANDING_COUNTER |
7416 | #define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 |
7417 | #define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7418 | //WBIF1_MISC_CTRL |
7419 | #define WBIF1_MISC_CTRL__MCIFWB1_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 |
7420 | #define WBIF1_MISC_CTRL__MCIF_WB1_SOCCLK_DS_ENABLE__SHIFT 0x10 |
7421 | #define WBIF1_MISC_CTRL__MCIFWB1_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL |
7422 | #define WBIF1_MISC_CTRL__MCIF_WB1_SOCCLK_DS_ENABLE_MASK 0x00010000L |
7423 | //WBIF1_SMU_WM_CONTROL |
7424 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_SEL__SHIFT 0x14 |
7425 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_REQ__SHIFT 0x16 |
7426 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_DIS__SHIFT 0x18 |
7427 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 |
7428 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_SEL_MASK 0x00300000L |
7429 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_REQ_MASK 0x00400000L |
7430 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_DIS_MASK 0x01000000L |
7431 | #define WBIF1_SMU_WM_CONTROL__MCIF_WB1_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L |
7432 | //WBIF1_PHASE0_OUTSTANDING_COUNTER |
7433 | #define WBIF1_PHASE0_OUTSTANDING_COUNTER__MCIF_WB1_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 |
7434 | #define WBIF1_PHASE0_OUTSTANDING_COUNTER__MCIF_WB1_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7435 | //WBIF1_PHASE1_OUTSTANDING_COUNTER |
7436 | #define WBIF1_PHASE1_OUTSTANDING_COUNTER__MCIF_WB1_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 |
7437 | #define WBIF1_PHASE1_OUTSTANDING_COUNTER__MCIF_WB1_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7438 | //VGA_SRC_SPLIT_CNTL |
7439 | #define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 |
7440 | #define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L |
7441 | //MMHUBBUB_MEM_PWR_STATUS |
7442 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 |
7443 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 |
7444 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 |
7445 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 |
7446 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM0_PWR_STATE__SHIFT 0x8 |
7447 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM1_PWR_STATE__SHIFT 0xa |
7448 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM0_PWR_STATE__SHIFT 0xc |
7449 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM1_PWR_STATE__SHIFT 0xe |
7450 | #define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f |
7451 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L |
7452 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL |
7453 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L |
7454 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L |
7455 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM0_PWR_STATE_MASK 0x00000300L |
7456 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_LUMA_MEM1_PWR_STATE_MASK 0x00000C00L |
7457 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM0_PWR_STATE_MASK 0x00003000L |
7458 | #define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB1_CHROMA_MEM1_PWR_STATE_MASK 0x0000C000L |
7459 | #define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L |
7460 | //MMHUBBUB_MEM_PWR_CNTL |
7461 | #define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 |
7462 | #define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 |
7463 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 |
7464 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 |
7465 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 |
7466 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 |
7467 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 |
7468 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_FORCE__SHIFT 0x9 |
7469 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_DIS__SHIFT 0xb |
7470 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_MODE_SEL__SHIFT 0xc |
7471 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_LUMA_MEM_EN_NUM__SHIFT 0xe |
7472 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_CHROMA_MEM_EN_NUM__SHIFT 0xf |
7473 | #define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L |
7474 | #define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L |
7475 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL |
7476 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L |
7477 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L |
7478 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L |
7479 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L |
7480 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_FORCE_MASK 0x00000600L |
7481 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_DIS_MASK 0x00000800L |
7482 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_MEM_PWR_MODE_SEL_MASK 0x00003000L |
7483 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_LUMA_MEM_EN_NUM_MASK 0x00004000L |
7484 | #define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB1_CHROMA_MEM_EN_NUM_MASK 0x00008000L |
7485 | //MMHUBBUB_CLOCK_CNTL |
7486 | #define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 |
7487 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 |
7488 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 |
7489 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 |
7490 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 |
7491 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 |
7492 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa |
7493 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF1_GATE_DIS__SHIFT 0xb |
7494 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF1_GATE_DIS__SHIFT 0xc |
7495 | #define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL |
7496 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L |
7497 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L |
7498 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L |
7499 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L |
7500 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L |
7501 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L |
7502 | #define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF1_GATE_DIS_MASK 0x00000800L |
7503 | #define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF1_GATE_DIS_MASK 0x00001000L |
7504 | //MMHUBBUB_SOFT_RESET |
7505 | #define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 |
7506 | #define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 |
7507 | #define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 |
7508 | #define MMHUBBUB_SOFT_RESET__WBIF1_SOFT_RESET__SHIFT 0x3 |
7509 | #define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L |
7510 | #define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L |
7511 | #define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L |
7512 | #define MMHUBBUB_SOFT_RESET__WBIF1_SOFT_RESET_MASK 0x00000008L |
7513 | |
7514 | |
7515 | // addressBlock: dce_dc_mmhubbub_vgaif_dispdec |
7516 | //MCIF_CONTROL |
7517 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e |
7518 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f |
7519 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L |
7520 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L |
7521 | //MCIF_WRITE_COMBINE_CONTROL |
7522 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 |
7523 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL |
7524 | //MCIF_PHASE0_OUTSTANDING_COUNTER |
7525 | #define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 |
7526 | #define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7527 | //MCIF_PHASE1_OUTSTANDING_COUNTER |
7528 | #define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 |
7529 | #define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7530 | //MCIF_PHASE2_OUTSTANDING_COUNTER |
7531 | #define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 |
7532 | #define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL |
7533 | |
7534 | |
7535 | // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec |
7536 | //DC_PERFMON5_PERFCOUNTER_CNTL |
7537 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
7538 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
7539 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
7540 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
7541 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
7542 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
7543 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
7544 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
7545 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
7546 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
7547 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
7548 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
7549 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
7550 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
7551 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
7552 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
7553 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
7554 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
7555 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
7556 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
7557 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
7558 | #define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
7559 | //DC_PERFMON5_PERFCOUNTER_CNTL2 |
7560 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
7561 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
7562 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
7563 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
7564 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
7565 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
7566 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
7567 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
7568 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
7569 | #define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
7570 | //DC_PERFMON5_PERFCOUNTER_STATE |
7571 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
7572 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
7573 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
7574 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
7575 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
7576 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
7577 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
7578 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
7579 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
7580 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
7581 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
7582 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
7583 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
7584 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
7585 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
7586 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
7587 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
7588 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
7589 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
7590 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
7591 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
7592 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
7593 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
7594 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
7595 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
7596 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
7597 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
7598 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
7599 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
7600 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
7601 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
7602 | #define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
7603 | //DC_PERFMON5_PERFMON_CNTL |
7604 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
7605 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
7606 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
7607 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
7608 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
7609 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
7610 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
7611 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
7612 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
7613 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
7614 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
7615 | #define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
7616 | //DC_PERFMON5_PERFMON_CNTL2 |
7617 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
7618 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
7619 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
7620 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
7621 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
7622 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
7623 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
7624 | #define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
7625 | //DC_PERFMON5_PERFMON_CVALUE_INT_MISC |
7626 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
7627 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
7628 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
7629 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
7630 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
7631 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
7632 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
7633 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
7634 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
7635 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
7636 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
7637 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
7638 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
7639 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
7640 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
7641 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
7642 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
7643 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
7644 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
7645 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
7646 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
7647 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
7648 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
7649 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
7650 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
7651 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
7652 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
7653 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
7654 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
7655 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
7656 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
7657 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
7658 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
7659 | #define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
7660 | //DC_PERFMON5_PERFMON_CVALUE_LOW |
7661 | #define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
7662 | #define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
7663 | //DC_PERFMON5_PERFMON_HI |
7664 | #define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
7665 | #define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
7666 | #define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
7667 | #define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
7668 | //DC_PERFMON5_PERFMON_LOW |
7669 | #define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
7670 | #define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
7671 | |
7672 | |
7673 | // addressBlock: dce_dc_hda_azf0stream0_dispdec |
7674 | //AZF0STREAM0_AZALIA_STREAM_INDEX |
7675 | #define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7676 | #define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7677 | #define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7678 | #define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7679 | //AZF0STREAM0_AZALIA_STREAM_DATA |
7680 | #define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7681 | #define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7682 | |
7683 | |
7684 | // addressBlock: dce_dc_hda_azf0stream1_dispdec |
7685 | //AZF0STREAM1_AZALIA_STREAM_INDEX |
7686 | #define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7687 | #define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7688 | #define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7689 | #define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7690 | //AZF0STREAM1_AZALIA_STREAM_DATA |
7691 | #define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7692 | #define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7693 | |
7694 | |
7695 | // addressBlock: dce_dc_hda_azf0stream2_dispdec |
7696 | //AZF0STREAM2_AZALIA_STREAM_INDEX |
7697 | #define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7698 | #define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7699 | #define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7700 | #define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7701 | //AZF0STREAM2_AZALIA_STREAM_DATA |
7702 | #define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7703 | #define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7704 | |
7705 | |
7706 | // addressBlock: dce_dc_hda_azf0stream3_dispdec |
7707 | //AZF0STREAM3_AZALIA_STREAM_INDEX |
7708 | #define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7709 | #define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7710 | #define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7711 | #define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7712 | //AZF0STREAM3_AZALIA_STREAM_DATA |
7713 | #define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7714 | #define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7715 | |
7716 | |
7717 | // addressBlock: dce_dc_hda_azf0stream4_dispdec |
7718 | //AZF0STREAM4_AZALIA_STREAM_INDEX |
7719 | #define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7720 | #define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7721 | #define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7722 | #define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7723 | //AZF0STREAM4_AZALIA_STREAM_DATA |
7724 | #define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7725 | #define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7726 | |
7727 | |
7728 | // addressBlock: dce_dc_hda_azf0stream5_dispdec |
7729 | //AZF0STREAM5_AZALIA_STREAM_INDEX |
7730 | #define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7731 | #define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7732 | #define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7733 | #define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7734 | //AZF0STREAM5_AZALIA_STREAM_DATA |
7735 | #define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7736 | #define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7737 | |
7738 | |
7739 | // addressBlock: dce_dc_hda_azf0stream6_dispdec |
7740 | //AZF0STREAM6_AZALIA_STREAM_INDEX |
7741 | #define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7742 | #define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7743 | #define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7744 | #define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7745 | //AZF0STREAM6_AZALIA_STREAM_DATA |
7746 | #define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7747 | #define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7748 | |
7749 | |
7750 | // addressBlock: dce_dc_hda_azf0stream7_dispdec |
7751 | //AZF0STREAM7_AZALIA_STREAM_INDEX |
7752 | #define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
7753 | #define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
7754 | #define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
7755 | #define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
7756 | //AZF0STREAM7_AZALIA_STREAM_DATA |
7757 | #define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
7758 | #define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
7759 | |
7760 | |
7761 | // addressBlock: dce_dc_hda_az_misc_dispdec |
7762 | //AZ_CLOCK_CNTL |
7763 | #define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 |
7764 | #define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 |
7765 | #define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 |
7766 | #define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 |
7767 | #define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L |
7768 | #define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L |
7769 | #define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L |
7770 | #define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L |
7771 | |
7772 | |
7773 | // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec |
7774 | //DC_PERFMON6_PERFCOUNTER_CNTL |
7775 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
7776 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
7777 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
7778 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
7779 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
7780 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
7781 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
7782 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
7783 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
7784 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
7785 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
7786 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
7787 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
7788 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
7789 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
7790 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
7791 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
7792 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
7793 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
7794 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
7795 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
7796 | #define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
7797 | //DC_PERFMON6_PERFCOUNTER_CNTL2 |
7798 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
7799 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
7800 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
7801 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
7802 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
7803 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
7804 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
7805 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
7806 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
7807 | #define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
7808 | //DC_PERFMON6_PERFCOUNTER_STATE |
7809 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
7810 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
7811 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
7812 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
7813 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
7814 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
7815 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
7816 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
7817 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
7818 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
7819 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
7820 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
7821 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
7822 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
7823 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
7824 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
7825 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
7826 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
7827 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
7828 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
7829 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
7830 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
7831 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
7832 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
7833 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
7834 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
7835 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
7836 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
7837 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
7838 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
7839 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
7840 | #define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
7841 | //DC_PERFMON6_PERFMON_CNTL |
7842 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
7843 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
7844 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
7845 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
7846 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
7847 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
7848 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
7849 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
7850 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
7851 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
7852 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
7853 | #define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
7854 | //DC_PERFMON6_PERFMON_CNTL2 |
7855 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
7856 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
7857 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
7858 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
7859 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
7860 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
7861 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
7862 | #define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
7863 | //DC_PERFMON6_PERFMON_CVALUE_INT_MISC |
7864 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
7865 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
7866 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
7867 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
7868 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
7869 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
7870 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
7871 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
7872 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
7873 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
7874 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
7875 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
7876 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
7877 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
7878 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
7879 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
7880 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
7881 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
7882 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
7883 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
7884 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
7885 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
7886 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
7887 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
7888 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
7889 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
7890 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
7891 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
7892 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
7893 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
7894 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
7895 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
7896 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
7897 | #define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
7898 | //DC_PERFMON6_PERFMON_CVALUE_LOW |
7899 | #define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
7900 | #define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
7901 | //DC_PERFMON6_PERFMON_HI |
7902 | #define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
7903 | #define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
7904 | #define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
7905 | #define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
7906 | //DC_PERFMON6_PERFMON_LOW |
7907 | #define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
7908 | #define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
7909 | |
7910 | |
7911 | // addressBlock: dce_dc_hda_azf0endpoint0_dispdec |
7912 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7913 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7914 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7915 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA |
7916 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7917 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7918 | |
7919 | |
7920 | // addressBlock: dce_dc_hda_azf0endpoint1_dispdec |
7921 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7922 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7923 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7924 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA |
7925 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7926 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7927 | |
7928 | |
7929 | // addressBlock: dce_dc_hda_azf0endpoint2_dispdec |
7930 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7931 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7932 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7933 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA |
7934 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7935 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7936 | |
7937 | |
7938 | // addressBlock: dce_dc_hda_azf0endpoint3_dispdec |
7939 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7940 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7941 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7942 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA |
7943 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7944 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7945 | |
7946 | |
7947 | // addressBlock: dce_dc_hda_azf0endpoint4_dispdec |
7948 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7949 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7950 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7951 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA |
7952 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7953 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7954 | |
7955 | |
7956 | // addressBlock: dce_dc_hda_azf0endpoint5_dispdec |
7957 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7958 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7959 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7960 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA |
7961 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7962 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7963 | |
7964 | |
7965 | // addressBlock: dce_dc_hda_azf0endpoint6_dispdec |
7966 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7967 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7968 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7969 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA |
7970 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7971 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7972 | |
7973 | |
7974 | // addressBlock: dce_dc_hda_azf0endpoint7_dispdec |
7975 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX |
7976 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
7977 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
7978 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA |
7979 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
7980 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
7981 | |
7982 | |
7983 | // addressBlock: dce_dc_hda_azf0controller_dispdec |
7984 | //AZALIA_CONTROLLER_CLOCK_GATING |
7985 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 |
7986 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 |
7987 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L |
7988 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L |
7989 | //AZALIA_AUDIO_DTO |
7990 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 |
7991 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 |
7992 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL |
7993 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L |
7994 | //AZALIA_AUDIO_DTO_CONTROL |
7995 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 |
7996 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L |
7997 | //AZALIA_SOCCLK_CONTROL |
7998 | #define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 |
7999 | #define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L |
8000 | //AZALIA_UNDERFLOW_FILLER_SAMPLE |
8001 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 |
8002 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL |
8003 | //AZALIA_DATA_DMA_CONTROL |
8004 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 |
8005 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 |
8006 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 |
8007 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 |
8008 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 |
8009 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 |
8010 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L |
8011 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL |
8012 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L |
8013 | #define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L |
8014 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L |
8015 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L |
8016 | //AZALIA_BDL_DMA_CONTROL |
8017 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 |
8018 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 |
8019 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 |
8020 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 |
8021 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L |
8022 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL |
8023 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L |
8024 | #define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L |
8025 | //AZALIA_RIRB_AND_DP_CONTROL |
8026 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 |
8027 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 |
8028 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 |
8029 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L |
8030 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L |
8031 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L |
8032 | //AZALIA_CORB_DMA_CONTROL |
8033 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 |
8034 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 |
8035 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L |
8036 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L |
8037 | //AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER |
8038 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 |
8039 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL |
8040 | //AZALIA_CYCLIC_BUFFER_SYNC |
8041 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 |
8042 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L |
8043 | //AZALIA_GLOBAL_CAPABILITIES |
8044 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
8045 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L |
8046 | //AZALIA_OUTPUT_PAYLOAD_CAPABILITY |
8047 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
8048 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 |
8049 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL |
8050 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L |
8051 | //AZALIA_OUTPUT_STREAM_ARBITER_CONTROL |
8052 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 |
8053 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 |
8054 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 |
8055 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL |
8056 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L |
8057 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L |
8058 | //AZALIA_INPUT_PAYLOAD_CAPABILITY |
8059 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
8060 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 |
8061 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL |
8062 | #define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L |
8063 | //AZALIA_INPUT_CRC0_CONTROL0 |
8064 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 |
8065 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 |
8066 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 |
8067 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L |
8068 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L |
8069 | #define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L |
8070 | //AZALIA_INPUT_CRC0_CONTROL1 |
8071 | #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 |
8072 | #define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL |
8073 | //AZALIA_INPUT_CRC0_CONTROL2 |
8074 | #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 |
8075 | #define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL |
8076 | //AZALIA_INPUT_CRC0_CONTROL3 |
8077 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 |
8078 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
8079 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
8080 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L |
8081 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L |
8082 | #define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L |
8083 | //AZALIA_INPUT_CRC0_RESULT |
8084 | #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 |
8085 | #define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL |
8086 | //AZALIA_INPUT_CRC1_CONTROL0 |
8087 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 |
8088 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 |
8089 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 |
8090 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L |
8091 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L |
8092 | #define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L |
8093 | //AZALIA_INPUT_CRC1_CONTROL1 |
8094 | #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 |
8095 | #define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL |
8096 | //AZALIA_INPUT_CRC1_CONTROL2 |
8097 | #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 |
8098 | #define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL |
8099 | //AZALIA_INPUT_CRC1_CONTROL3 |
8100 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 |
8101 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
8102 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
8103 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L |
8104 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L |
8105 | #define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L |
8106 | //AZALIA_INPUT_CRC1_RESULT |
8107 | #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 |
8108 | #define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL |
8109 | //AZALIA_CRC0_CONTROL0 |
8110 | #define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 |
8111 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
8112 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
8113 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
8114 | #define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L |
8115 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L |
8116 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L |
8117 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L |
8118 | //AZALIA_CRC0_CONTROL1 |
8119 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
8120 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL |
8121 | //AZALIA_CRC0_CONTROL2 |
8122 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
8123 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL |
8124 | //AZALIA_CRC0_CONTROL3 |
8125 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
8126 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
8127 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
8128 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L |
8129 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L |
8130 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L |
8131 | //AZALIA_CRC0_RESULT |
8132 | #define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 |
8133 | #define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL |
8134 | //AZALIA_CRC1_CONTROL0 |
8135 | #define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 |
8136 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
8137 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
8138 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
8139 | #define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L |
8140 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L |
8141 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L |
8142 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L |
8143 | //AZALIA_CRC1_CONTROL1 |
8144 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
8145 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL |
8146 | //AZALIA_CRC1_CONTROL2 |
8147 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
8148 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL |
8149 | //AZALIA_CRC1_CONTROL3 |
8150 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
8151 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
8152 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
8153 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L |
8154 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L |
8155 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L |
8156 | //AZALIA_CRC1_RESULT |
8157 | #define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 |
8158 | #define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL |
8159 | //AZALIA_MEM_PWR_CTRL |
8160 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 |
8161 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 |
8162 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 |
8163 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 |
8164 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 |
8165 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 |
8166 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 |
8167 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb |
8168 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc |
8169 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe |
8170 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf |
8171 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 |
8172 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 |
8173 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 |
8174 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c |
8175 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L |
8176 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L |
8177 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L |
8178 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L |
8179 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L |
8180 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L |
8181 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L |
8182 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L |
8183 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L |
8184 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L |
8185 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L |
8186 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L |
8187 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L |
8188 | #define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L |
8189 | #define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L |
8190 | //AZALIA_MEM_PWR_STATUS |
8191 | #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 |
8192 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 |
8193 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 |
8194 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 |
8195 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 |
8196 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa |
8197 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc |
8198 | #define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L |
8199 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL |
8200 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L |
8201 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L |
8202 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L |
8203 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L |
8204 | #define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L |
8205 | |
8206 | |
8207 | // addressBlock: dce_dc_hda_azf0root_dispdec |
8208 | //AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID |
8209 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
8210 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL |
8211 | //AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID |
8212 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
8213 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL |
8214 | //AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL |
8215 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 |
8216 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 |
8217 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L |
8218 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L |
8219 | //AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL |
8220 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 |
8221 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL |
8222 | //AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE |
8223 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
8224 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL |
8225 | //AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES |
8226 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
8227 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
8228 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
8229 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
8230 | //AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS |
8231 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
8232 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL |
8233 | //AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES |
8234 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
8235 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
8236 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
8237 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL |
8238 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L |
8239 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L |
8240 | //AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE |
8241 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
8242 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
8243 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
8244 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
8245 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL |
8246 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L |
8247 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L |
8248 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L |
8249 | //AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET |
8250 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
8251 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L |
8252 | //AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID |
8253 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
8254 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
8255 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
8256 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
8257 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL |
8258 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L |
8259 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L |
8260 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L |
8261 | //AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION |
8262 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
8263 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL |
8264 | //CC_RCU_DC_AUDIO_PORT_CONNECTIVITY |
8265 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 |
8266 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
8267 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L |
8268 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L |
8269 | //CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY |
8270 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 |
8271 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
8272 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L |
8273 | #define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L |
8274 | //AZALIA_F0_GTC_GROUP_OFFSET0 |
8275 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 |
8276 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL |
8277 | //AZALIA_F0_GTC_GROUP_OFFSET1 |
8278 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 |
8279 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL |
8280 | //AZALIA_F0_GTC_GROUP_OFFSET2 |
8281 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 |
8282 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL |
8283 | //AZALIA_F0_GTC_GROUP_OFFSET3 |
8284 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 |
8285 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL |
8286 | //AZALIA_F0_GTC_GROUP_OFFSET4 |
8287 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 |
8288 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL |
8289 | //AZALIA_F0_GTC_GROUP_OFFSET5 |
8290 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 |
8291 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL |
8292 | //AZALIA_F0_GTC_GROUP_OFFSET6 |
8293 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 |
8294 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL |
8295 | //REG_DC_AUDIO_PORT_CONNECTIVITY |
8296 | #define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 |
8297 | #define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
8298 | #define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L |
8299 | #define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L |
8300 | //REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY |
8301 | #define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 |
8302 | #define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
8303 | #define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L |
8304 | #define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L |
8305 | |
8306 | |
8307 | // addressBlock: dce_dc_hda_azf0stream8_dispdec |
8308 | //AZF0STREAM8_AZALIA_STREAM_INDEX |
8309 | #define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8310 | #define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8311 | #define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8312 | #define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8313 | //AZF0STREAM8_AZALIA_STREAM_DATA |
8314 | #define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8315 | #define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8316 | |
8317 | |
8318 | // addressBlock: dce_dc_hda_azf0stream9_dispdec |
8319 | //AZF0STREAM9_AZALIA_STREAM_INDEX |
8320 | #define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8321 | #define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8322 | #define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8323 | #define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8324 | //AZF0STREAM9_AZALIA_STREAM_DATA |
8325 | #define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8326 | #define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8327 | |
8328 | |
8329 | // addressBlock: dce_dc_hda_azf0stream10_dispdec |
8330 | //AZF0STREAM10_AZALIA_STREAM_INDEX |
8331 | #define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8332 | #define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8333 | #define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8334 | #define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8335 | //AZF0STREAM10_AZALIA_STREAM_DATA |
8336 | #define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8337 | #define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8338 | |
8339 | |
8340 | // addressBlock: dce_dc_hda_azf0stream11_dispdec |
8341 | //AZF0STREAM11_AZALIA_STREAM_INDEX |
8342 | #define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8343 | #define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8344 | #define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8345 | #define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8346 | //AZF0STREAM11_AZALIA_STREAM_DATA |
8347 | #define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8348 | #define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8349 | |
8350 | |
8351 | // addressBlock: dce_dc_hda_azf0stream12_dispdec |
8352 | //AZF0STREAM12_AZALIA_STREAM_INDEX |
8353 | #define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8354 | #define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8355 | #define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8356 | #define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8357 | //AZF0STREAM12_AZALIA_STREAM_DATA |
8358 | #define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8359 | #define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8360 | |
8361 | |
8362 | // addressBlock: dce_dc_hda_azf0stream13_dispdec |
8363 | //AZF0STREAM13_AZALIA_STREAM_INDEX |
8364 | #define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8365 | #define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8366 | #define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8367 | #define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8368 | //AZF0STREAM13_AZALIA_STREAM_DATA |
8369 | #define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8370 | #define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8371 | |
8372 | |
8373 | // addressBlock: dce_dc_hda_azf0stream14_dispdec |
8374 | //AZF0STREAM14_AZALIA_STREAM_INDEX |
8375 | #define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8376 | #define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8377 | #define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8378 | #define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8379 | //AZF0STREAM14_AZALIA_STREAM_DATA |
8380 | #define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8381 | #define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8382 | |
8383 | |
8384 | // addressBlock: dce_dc_hda_azf0stream15_dispdec |
8385 | //AZF0STREAM15_AZALIA_STREAM_INDEX |
8386 | #define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
8387 | #define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
8388 | #define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL |
8389 | #define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L |
8390 | //AZF0STREAM15_AZALIA_STREAM_DATA |
8391 | #define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
8392 | #define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL |
8393 | |
8394 | |
8395 | // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec |
8396 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8397 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8398 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8399 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8400 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8401 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8402 | |
8403 | |
8404 | // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec |
8405 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8406 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8407 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8408 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8409 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8410 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8411 | |
8412 | |
8413 | // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec |
8414 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8415 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8416 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8417 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8418 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8419 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8420 | |
8421 | |
8422 | // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec |
8423 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8424 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8425 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8426 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8427 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8428 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8429 | |
8430 | |
8431 | // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec |
8432 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8433 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8434 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8435 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8436 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8437 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8438 | |
8439 | |
8440 | // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec |
8441 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8442 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8443 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8444 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8445 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8446 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8447 | |
8448 | |
8449 | // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec |
8450 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8451 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8452 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8453 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8454 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8455 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8456 | |
8457 | |
8458 | // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec |
8459 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX |
8460 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 |
8461 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL |
8462 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA |
8463 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 |
8464 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL |
8465 | |
8466 | |
8467 | // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec |
8468 | //DCHUBBUB_SDPIF_CFG0 |
8469 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 |
8470 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 |
8471 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 |
8472 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0x6 |
8473 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR__SHIFT 0x7 |
8474 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0x8 |
8475 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0x9 |
8476 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xa |
8477 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xb |
8478 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK__SHIFT 0xc |
8479 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x14 |
8480 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L |
8481 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L |
8482 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L |
8483 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000040L |
8484 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR_MASK 0x00000080L |
8485 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00000100L |
8486 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00000200L |
8487 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00000400L |
8488 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00000800L |
8489 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK_MASK 0x000FF000L |
8490 | #define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x03F00000L |
8491 | //DCHUBBUB_SDPIF_CFG1 |
8492 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO__SHIFT 0x0 |
8493 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC__SHIFT 0x1 |
8494 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO__SHIFT 0x4 |
8495 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC__SHIFT 0x5 |
8496 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO_MASK 0x00000001L |
8497 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC_MASK 0x0000000EL |
8498 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO_MASK 0x00000010L |
8499 | #define DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC_MASK 0x000000E0L |
8500 | //DCHUBBUB_FORCE_IO_STATUS_0 |
8501 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 |
8502 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 |
8503 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 |
8504 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 |
8505 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 |
8506 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa |
8507 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L |
8508 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L |
8509 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L |
8510 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L |
8511 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L |
8512 | #define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L |
8513 | //DCHUBBUB_FORCE_IO_STATUS_1 |
8514 | #define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 |
8515 | #define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL |
8516 | //DCHUBBUB_SDPIF_FB_BASE |
8517 | #define DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE__SHIFT 0x0 |
8518 | #define DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE_MASK 0x00FFFFFFL |
8519 | //DCHUBBUB_SDPIF_FB_TOP |
8520 | #define DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP__SHIFT 0x0 |
8521 | #define DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP_MASK 0x00FFFFFFL |
8522 | //DCHUBBUB_SDPIF_FB_OFFSET |
8523 | #define DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET__SHIFT 0x0 |
8524 | #define DCHUBBUB_SDPIF_FB_OFFSET__SDPIF_FB_OFFSET_MASK 0x00FFFFFFL |
8525 | //DCHUBBUB_SDPIF_AGP_BOT |
8526 | #define DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT__SHIFT 0x0 |
8527 | #define DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT_MASK 0x03FFFFFFL |
8528 | //DCHUBBUB_SDPIF_AGP_TOP |
8529 | #define DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP__SHIFT 0x0 |
8530 | #define DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP_MASK 0x03FFFFFFL |
8531 | //DCHUBBUB_SDPIF_AGP_BASE |
8532 | #define DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE__SHIFT 0x0 |
8533 | #define DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE_MASK 0x03FFFFFFL |
8534 | //DCHUBBUB_SDPIF_APER_BASE |
8535 | #define DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE__SHIFT 0x0 |
8536 | #define DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS__SHIFT 0x1c |
8537 | #define DCHUBBUB_SDPIF_APER_BASE__SDPIF_APER_BASE_MASK 0x0FFFFFFFL |
8538 | #define DCHUBBUB_SDPIF_APER_BASE__SDPIF_LOCK_DRAM_REGS_MASK 0x10000000L |
8539 | //DCHUBBUB_SDPIF_APER_TOP |
8540 | #define DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP__SHIFT 0x0 |
8541 | #define DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP_MASK 0x0FFFFFFFL |
8542 | //DCHUBBUB_SDPIF_APER_DEF_0 |
8543 | #define DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0__SHIFT 0x0 |
8544 | #define DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0_MASK 0xFFFFFFFFL |
8545 | //DCHUBBUB_SDPIF_APER_DEF_1 |
8546 | #define DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1__SHIFT 0x0 |
8547 | #define DCHUBBUB_SDPIF_APER_DEF_1__SDPIF_APER_DEF_1_MASK 0x0000000FL |
8548 | //DCHUBBUB_SDPIF_MMIO_CNTRL_0 |
8549 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN__SHIFT 0x0 |
8550 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_0__SDPIF_IOMMU_EN_MASK 0x00000001L |
8551 | //DCHUBBUB_SDPIF_MMIO_CNTRL_1 |
8552 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN__SHIFT 0x8 |
8553 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_1__SDPIF_MARC_EN_MASK 0x00000100L |
8554 | //DCHUBBUB_SDPIF_MMIO_CNTRL_W |
8555 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS__SHIFT 0xd |
8556 | #define DCHUBBUB_SDPIF_MMIO_CNTRL_W__SDPIF_GMC_IOMMU_BYPASS_MASK 0x00002000L |
8557 | //DCHUBBUB_SDPIF_MARC_BASE_LO_0 |
8558 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0__SHIFT 0xc |
8559 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_0__SDPIF_MARC_BASE_LO_0_MASK 0xFFFFF000L |
8560 | //DCHUBBUB_SDPIF_MARC_BASE_HI_0 |
8561 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0__SHIFT 0x0 |
8562 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_0__SDPIF_MARC_BASE_HI_0_MASK 0x0000FFFFL |
8563 | //DCHUBBUB_SDPIF_MARC_RELOC_LO_0 |
8564 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0__SHIFT 0x0 |
8565 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0__SHIFT 0xc |
8566 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0_MASK 0x00000001L |
8567 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0_MASK 0xFFFFF000L |
8568 | //DCHUBBUB_SDPIF_MARC_RELOC_HI_0 |
8569 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0__SHIFT 0x0 |
8570 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_0__SDPIF_MARC_RELOC_HI_0_MASK 0x0000FFFFL |
8571 | //DCHUBBUB_SDPIF_MARC_LENGTH_LO_0 |
8572 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0__SHIFT 0xc |
8573 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0_MASK 0xFFFFF000L |
8574 | //DCHUBBUB_SDPIF_MARC_LENGTH_HI_0 |
8575 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0__SHIFT 0x0 |
8576 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_0__SDPIF_MARC_LENGTH_HI_0_MASK 0x0000FFFFL |
8577 | //DCHUBBUB_SDPIF_MARC_BASE_LO_1 |
8578 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1__SHIFT 0xc |
8579 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1_MASK 0xFFFFF000L |
8580 | //DCHUBBUB_SDPIF_MARC_BASE_HI_1 |
8581 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1__SHIFT 0x0 |
8582 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_1__SDPIF_MARC_BASE_HI_1_MASK 0x0000FFFFL |
8583 | //DCHUBBUB_SDPIF_MARC_RELOC_LO_1 |
8584 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1__SHIFT 0x0 |
8585 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1__SHIFT 0xc |
8586 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1_MASK 0x00000001L |
8587 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1_MASK 0xFFFFF000L |
8588 | //DCHUBBUB_SDPIF_MARC_RELOC_HI_1 |
8589 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1__SHIFT 0x0 |
8590 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_1__SDPIF_MARC_RELOC_HI_1_MASK 0x0000FFFFL |
8591 | //DCHUBBUB_SDPIF_MARC_LENGTH_LO_1 |
8592 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1__SHIFT 0xc |
8593 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1_MASK 0xFFFFF000L |
8594 | //DCHUBBUB_SDPIF_MARC_LENGTH_HI_1 |
8595 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1__SHIFT 0x0 |
8596 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_1__SDPIF_MARC_LENGTH_HI_1_MASK 0x0000FFFFL |
8597 | //DCHUBBUB_SDPIF_MARC_BASE_LO_2 |
8598 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2__SHIFT 0xc |
8599 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2_MASK 0xFFFFF000L |
8600 | //DCHUBBUB_SDPIF_MARC_BASE_HI_2 |
8601 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2__SHIFT 0x0 |
8602 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_2__SDPIF_MARC_BASE_HI_2_MASK 0x0000FFFFL |
8603 | //DCHUBBUB_SDPIF_MARC_RELOC_LO_2 |
8604 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2__SHIFT 0x0 |
8605 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2__SHIFT 0xc |
8606 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2_MASK 0x00000001L |
8607 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2_MASK 0xFFFFF000L |
8608 | //DCHUBBUB_SDPIF_MARC_RELOC_HI_2 |
8609 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2__SHIFT 0x0 |
8610 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_2__SDPIF_MARC_RELOC_HI_2_MASK 0x0000FFFFL |
8611 | //DCHUBBUB_SDPIF_MARC_LENGTH_LO_2 |
8612 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2__SHIFT 0xc |
8613 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2_MASK 0xFFFFF000L |
8614 | //DCHUBBUB_SDPIF_MARC_LENGTH_HI_2 |
8615 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2__SHIFT 0x0 |
8616 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_2__SDPIF_MARC_LENGTH_HI_2_MASK 0x0000FFFFL |
8617 | //DCHUBBUB_SDPIF_MARC_BASE_LO_3 |
8618 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3__SHIFT 0xc |
8619 | #define DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3_MASK 0xFFFFF000L |
8620 | //DCHUBBUB_SDPIF_MARC_BASE_HI_3 |
8621 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3__SHIFT 0x0 |
8622 | #define DCHUBBUB_SDPIF_MARC_BASE_HI_3__SDPIF_MARC_BASE_HI_3_MASK 0x0000FFFFL |
8623 | //DCHUBBUB_SDPIF_MARC_RELOC_LO_3 |
8624 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3__SHIFT 0x0 |
8625 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3__SHIFT 0xc |
8626 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3_MASK 0x00000001L |
8627 | #define DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3_MASK 0xFFFFF000L |
8628 | //DCHUBBUB_SDPIF_MARC_RELOC_HI_3 |
8629 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3__SHIFT 0x0 |
8630 | #define DCHUBBUB_SDPIF_MARC_RELOC_HI_3__SDPIF_MARC_RELOC_HI_3_MASK 0x0000FFFFL |
8631 | //DCHUBBUB_SDPIF_MARC_LENGTH_LO_3 |
8632 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3__SHIFT 0xc |
8633 | #define DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3_MASK 0xFFFFF000L |
8634 | //DCHUBBUB_SDPIF_MARC_LENGTH_HI_3 |
8635 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3__SHIFT 0x0 |
8636 | #define DCHUBBUB_SDPIF_MARC_LENGTH_HI_3__SDPIF_MARC_LENGTH_HI_3_MASK 0x0000FFFFL |
8637 | //DCHUBBUB_SDPIF_PIPE_SEC_LVL |
8638 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 |
8639 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 |
8640 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 |
8641 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 |
8642 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L |
8643 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L |
8644 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L |
8645 | #define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L |
8646 | //DCHUBBUB_SDPIF_MEM_PWR_CTRL |
8647 | #define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 |
8648 | #define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 |
8649 | #define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L |
8650 | #define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L |
8651 | //DCHUBBUB_SDPIF_MEM_PWR_STATUS |
8652 | #define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 |
8653 | #define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L |
8654 | |
8655 | |
8656 | // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec |
8657 | //DCHUBBUB_RET_PATH_DCC_CFG |
8658 | #define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 |
8659 | #define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L |
8660 | //DCHUBBUB_RET_PATH_DCC_CFG0_0 |
8661 | #define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 |
8662 | #define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL |
8663 | //DCHUBBUB_RET_PATH_DCC_CFG0_1 |
8664 | #define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 |
8665 | #define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL |
8666 | //DCHUBBUB_RET_PATH_DCC_CFG1_0 |
8667 | #define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 |
8668 | #define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL |
8669 | //DCHUBBUB_RET_PATH_DCC_CFG1_1 |
8670 | #define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 |
8671 | #define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL |
8672 | //DCHUBBUB_RET_PATH_DCC_CFG2_0 |
8673 | #define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 |
8674 | #define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL |
8675 | //DCHUBBUB_RET_PATH_DCC_CFG2_1 |
8676 | #define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 |
8677 | #define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL |
8678 | //DCHUBBUB_RET_PATH_DCC_CFG3_0 |
8679 | #define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 |
8680 | #define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL |
8681 | //DCHUBBUB_RET_PATH_DCC_CFG3_1 |
8682 | #define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 |
8683 | #define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL |
8684 | //DCHUBBUB_RET_PATH_DCC_CFG4_0 |
8685 | #define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0 |
8686 | #define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL |
8687 | //DCHUBBUB_RET_PATH_DCC_CFG4_1 |
8688 | #define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0 |
8689 | #define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL |
8690 | //DCHUBBUB_RET_PATH_DCC_CFG5_0 |
8691 | #define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0 |
8692 | #define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL |
8693 | //DCHUBBUB_RET_PATH_DCC_CFG5_1 |
8694 | #define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0 |
8695 | #define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL |
8696 | //DCHUBBUB_RET_PATH_DCC_CFG6_0 |
8697 | #define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0 |
8698 | #define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL |
8699 | //DCHUBBUB_RET_PATH_DCC_CFG6_1 |
8700 | #define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0 |
8701 | #define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL |
8702 | //DCHUBBUB_RET_PATH_DCC_CFG7_0 |
8703 | #define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0 |
8704 | #define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL |
8705 | //DCHUBBUB_RET_PATH_DCC_CFG7_1 |
8706 | #define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0 |
8707 | #define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL |
8708 | //DCHUBBUB_RET_PATH_MEM_PWR_CTRL |
8709 | #define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 |
8710 | #define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 |
8711 | #define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L |
8712 | #define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L |
8713 | //DCHUBBUB_RET_PATH_MEM_PWR_STATUS |
8714 | #define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 |
8715 | #define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L |
8716 | //DCHUBBUB_CRC_CTRL |
8717 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 |
8718 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 |
8719 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 |
8720 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 |
8721 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 |
8722 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 |
8723 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 |
8724 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc |
8725 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0xe |
8726 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L |
8727 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L |
8728 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L |
8729 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L |
8730 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L |
8731 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L |
8732 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L |
8733 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00003000L |
8734 | #define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00004000L |
8735 | //DCHUBBUB_CRC0_VAL_R_G |
8736 | #define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 |
8737 | #define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 |
8738 | #define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL |
8739 | #define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L |
8740 | //DCHUBBUB_CRC0_VAL_B_A |
8741 | #define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 |
8742 | #define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 |
8743 | #define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL |
8744 | #define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L |
8745 | //DCHUBBUB_CRC1_VAL_R_G |
8746 | #define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 |
8747 | #define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 |
8748 | #define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL |
8749 | #define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L |
8750 | //DCHUBBUB_CRC1_VAL_B_A |
8751 | #define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 |
8752 | #define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 |
8753 | #define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL |
8754 | #define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L |
8755 | |
8756 | |
8757 | // addressBlock: dce_dc_dchubbub_hubbub_dispdec |
8758 | //DCHUBBUB_ARB_DF_REQ_OUTSTAND |
8759 | #define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 |
8760 | #define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0x10 |
8761 | #define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL |
8762 | #define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x01FF0000L |
8763 | //DCHUBBUB_ARB_SAT_LEVEL |
8764 | #define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 |
8765 | #define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL |
8766 | //DCHUBBUB_ARB_QOS_FORCE |
8767 | #define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 |
8768 | #define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 |
8769 | #define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL |
8770 | #define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L |
8771 | //DCHUBBUB_ARB_DRAM_STATE_CNTL |
8772 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 |
8773 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 |
8774 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE__SHIFT 0x2 |
8775 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 |
8776 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 |
8777 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L |
8778 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L |
8779 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCED_CLEAR_DISABLE_MASK 0x00000004L |
8780 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L |
8781 | #define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L |
8782 | //DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A |
8783 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 |
8784 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x001FFFFFL |
8785 | //DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A |
8786 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__SHIFT 0x0 |
8787 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_MASK 0x001FFFFFL |
8788 | //DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A |
8789 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 |
8790 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x001FFFFFL |
8791 | //DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A |
8792 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 |
8793 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x001FFFFFL |
8794 | //DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A |
8795 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 |
8796 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x001FFFFFL |
8797 | //DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B |
8798 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 |
8799 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x001FFFFFL |
8800 | //DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B |
8801 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__SHIFT 0x0 |
8802 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_MASK 0x001FFFFFL |
8803 | //DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B |
8804 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 |
8805 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x001FFFFFL |
8806 | //DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B |
8807 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 |
8808 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x001FFFFFL |
8809 | //DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B |
8810 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 |
8811 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x001FFFFFL |
8812 | //DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C |
8813 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 |
8814 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x001FFFFFL |
8815 | //DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C |
8816 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__SHIFT 0x0 |
8817 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_MASK 0x001FFFFFL |
8818 | //DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C |
8819 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 |
8820 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x001FFFFFL |
8821 | //DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C |
8822 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 |
8823 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x001FFFFFL |
8824 | //DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C |
8825 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 |
8826 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x001FFFFFL |
8827 | //DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D |
8828 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 |
8829 | #define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x001FFFFFL |
8830 | //DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D |
8831 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__SHIFT 0x0 |
8832 | #define DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D__DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_MASK 0x001FFFFFL |
8833 | //DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D |
8834 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 |
8835 | #define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x001FFFFFL |
8836 | //DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D |
8837 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 |
8838 | #define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x001FFFFFL |
8839 | //DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D |
8840 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 |
8841 | #define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x001FFFFFL |
8842 | //DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL |
8843 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 |
8844 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 |
8845 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 |
8846 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK__SHIFT 0x6 |
8847 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 |
8848 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L |
8849 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L |
8850 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L |
8851 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_ACK_MASK 0x00000040L |
8852 | #define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L |
8853 | //DCHUBBUB_ARB_TIMEOUT_ENABLE |
8854 | #define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 |
8855 | #define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L |
8856 | //DCHUBBUB_GLOBAL_TIMER_CNTL |
8857 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 |
8858 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc |
8859 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 |
8860 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL |
8861 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L |
8862 | #define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L |
8863 | //SURFACE_CHECK0_ADDRESS_LSB |
8864 | #define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 |
8865 | #define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL |
8866 | //SURFACE_CHECK0_ADDRESS_MSB |
8867 | #define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 |
8868 | #define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f |
8869 | #define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL |
8870 | #define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L |
8871 | //SURFACE_CHECK1_ADDRESS_LSB |
8872 | #define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 |
8873 | #define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL |
8874 | //SURFACE_CHECK1_ADDRESS_MSB |
8875 | #define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 |
8876 | #define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f |
8877 | #define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL |
8878 | #define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L |
8879 | //SURFACE_CHECK2_ADDRESS_LSB |
8880 | #define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 |
8881 | #define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL |
8882 | //SURFACE_CHECK2_ADDRESS_MSB |
8883 | #define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 |
8884 | #define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f |
8885 | #define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL |
8886 | #define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L |
8887 | //SURFACE_CHECK3_ADDRESS_LSB |
8888 | #define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 |
8889 | #define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL |
8890 | //SURFACE_CHECK3_ADDRESS_MSB |
8891 | #define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 |
8892 | #define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f |
8893 | #define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL |
8894 | #define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L |
8895 | //VTG0_CONTROL |
8896 | #define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 |
8897 | #define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0xf |
8898 | #define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f |
8899 | #define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL |
8900 | #define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x3FFF8000L |
8901 | #define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L |
8902 | //VTG1_CONTROL |
8903 | #define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 |
8904 | #define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0xf |
8905 | #define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f |
8906 | #define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL |
8907 | #define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x3FFF8000L |
8908 | #define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L |
8909 | //VTG2_CONTROL |
8910 | #define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 |
8911 | #define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0xf |
8912 | #define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f |
8913 | #define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL |
8914 | #define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x3FFF8000L |
8915 | #define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L |
8916 | //VTG3_CONTROL |
8917 | #define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 |
8918 | #define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0xf |
8919 | #define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f |
8920 | #define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL |
8921 | #define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x3FFF8000L |
8922 | #define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L |
8923 | //VTG4_CONTROL |
8924 | #define VTG4_CONTROL__VTG4_FP2__SHIFT 0x0 |
8925 | #define VTG4_CONTROL__VTG4_VCOUNT_INIT__SHIFT 0xf |
8926 | #define VTG4_CONTROL__VTG4_ENABLE__SHIFT 0x1f |
8927 | #define VTG4_CONTROL__VTG4_FP2_MASK 0x00007FFFL |
8928 | #define VTG4_CONTROL__VTG4_VCOUNT_INIT_MASK 0x3FFF8000L |
8929 | #define VTG4_CONTROL__VTG4_ENABLE_MASK 0x80000000L |
8930 | //VTG5_CONTROL |
8931 | #define VTG5_CONTROL__VTG5_FP2__SHIFT 0x0 |
8932 | #define VTG5_CONTROL__VTG5_VCOUNT_INIT__SHIFT 0xf |
8933 | #define VTG5_CONTROL__VTG5_ENABLE__SHIFT 0x1f |
8934 | #define VTG5_CONTROL__VTG5_FP2_MASK 0x00007FFFL |
8935 | #define VTG5_CONTROL__VTG5_VCOUNT_INIT_MASK 0x3FFF8000L |
8936 | #define VTG5_CONTROL__VTG5_ENABLE_MASK 0x80000000L |
8937 | //DCHUBBUB_SOFT_RESET |
8938 | #define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 |
8939 | #define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 |
8940 | #define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 |
8941 | #define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L |
8942 | #define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L |
8943 | #define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L |
8944 | //DCHUBBUB_CLOCK_CNTL |
8945 | #define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 |
8946 | #define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 |
8947 | #define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 |
8948 | #define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL |
8949 | #define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L |
8950 | #define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L |
8951 | //DCFCLK_CNTL |
8952 | #define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 |
8953 | #define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 |
8954 | #define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f |
8955 | #define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL |
8956 | #define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L |
8957 | #define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L |
8958 | //DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL |
8959 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 |
8960 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 |
8961 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 |
8962 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa |
8963 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb |
8964 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL__SHIFT 0x15 |
8965 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f |
8966 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L |
8967 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L |
8968 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L |
8969 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L |
8970 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x001FF800L |
8971 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_MASK 0x7FE00000L |
8972 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L |
8973 | //DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 |
8974 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 |
8975 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 |
8976 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 |
8977 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc |
8978 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L |
8979 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL |
8980 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L |
8981 | #define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L |
8982 | //DCHUBBUB_VLINE_SNAPSHOT |
8983 | #define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 |
8984 | #define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L |
8985 | //DCHUBBUB_SPARE |
8986 | #define DCHUBBUB_SPARE__DCHUBBUB_SPARE__SHIFT 0x0 |
8987 | #define DCHUBBUB_SPARE__DCHUBBUB_SPARE_MASK 0xFFFFFFFFL |
8988 | |
8989 | |
8990 | // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec |
8991 | //DC_PERFMON7_PERFCOUNTER_CNTL |
8992 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
8993 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
8994 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
8995 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
8996 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
8997 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
8998 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
8999 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
9000 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
9001 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
9002 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
9003 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
9004 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
9005 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
9006 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
9007 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
9008 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
9009 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
9010 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
9011 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
9012 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
9013 | #define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
9014 | //DC_PERFMON7_PERFCOUNTER_CNTL2 |
9015 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
9016 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
9017 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
9018 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
9019 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
9020 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
9021 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
9022 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
9023 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
9024 | #define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
9025 | //DC_PERFMON7_PERFCOUNTER_STATE |
9026 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
9027 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
9028 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
9029 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
9030 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
9031 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
9032 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
9033 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
9034 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
9035 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
9036 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
9037 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
9038 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
9039 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
9040 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
9041 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
9042 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
9043 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
9044 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
9045 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
9046 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
9047 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
9048 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
9049 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
9050 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
9051 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
9052 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
9053 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
9054 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
9055 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
9056 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
9057 | #define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
9058 | //DC_PERFMON7_PERFMON_CNTL |
9059 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
9060 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
9061 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
9062 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
9063 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
9064 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
9065 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
9066 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
9067 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
9068 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
9069 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
9070 | #define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
9071 | //DC_PERFMON7_PERFMON_CNTL2 |
9072 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
9073 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
9074 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
9075 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
9076 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
9077 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
9078 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
9079 | #define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
9080 | //DC_PERFMON7_PERFMON_CVALUE_INT_MISC |
9081 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
9082 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
9083 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
9084 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
9085 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
9086 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
9087 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
9088 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
9089 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
9090 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
9091 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
9092 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
9093 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
9094 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
9095 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
9096 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
9097 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
9098 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
9099 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
9100 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
9101 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
9102 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
9103 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
9104 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
9105 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
9106 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
9107 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
9108 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
9109 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
9110 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
9111 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
9112 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
9113 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
9114 | #define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
9115 | //DC_PERFMON7_PERFMON_CVALUE_LOW |
9116 | #define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
9117 | #define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
9118 | //DC_PERFMON7_PERFMON_HI |
9119 | #define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
9120 | #define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
9121 | #define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
9122 | #define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
9123 | //DC_PERFMON7_PERFMON_LOW |
9124 | #define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
9125 | #define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
9126 | |
9127 | |
9128 | // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec |
9129 | //HUBP0_DCSURF_SURFACE_CONFIG |
9130 | #define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
9131 | #define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 |
9132 | #define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa |
9133 | #define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
9134 | #define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L |
9135 | #define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L |
9136 | //HUBP0_DCSURF_ADDR_CONFIG |
9137 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
9138 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 |
9139 | #define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 |
9140 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 |
9141 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa |
9142 | #define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc |
9143 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
9144 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L |
9145 | #define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L |
9146 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L |
9147 | #define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L |
9148 | #define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L |
9149 | //HUBP0_DCSURF_TILING_CONFIG |
9150 | #define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 |
9151 | #define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 |
9152 | #define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 |
9153 | #define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa |
9154 | #define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb |
9155 | #define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL |
9156 | #define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L |
9157 | #define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L |
9158 | #define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L |
9159 | #define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L |
9160 | //HUBP0_DCSURF_PRI_VIEWPORT_START |
9161 | #define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 |
9162 | #define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 |
9163 | #define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL |
9164 | #define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L |
9165 | //HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION |
9166 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 |
9167 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 |
9168 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL |
9169 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
9170 | //HUBP0_DCSURF_PRI_VIEWPORT_START_C |
9171 | #define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 |
9172 | #define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 |
9173 | #define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL |
9174 | #define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
9175 | //HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C |
9176 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 |
9177 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
9178 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
9179 | #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
9180 | //HUBP0_DCSURF_SEC_VIEWPORT_START |
9181 | #define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 |
9182 | #define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 |
9183 | #define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL |
9184 | #define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L |
9185 | //HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION |
9186 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 |
9187 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 |
9188 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL |
9189 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
9190 | //HUBP0_DCSURF_SEC_VIEWPORT_START_C |
9191 | #define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 |
9192 | #define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 |
9193 | #define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL |
9194 | #define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
9195 | //HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C |
9196 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 |
9197 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
9198 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
9199 | #define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
9200 | //HUBP0_DCHUBP_REQ_SIZE_CONFIG |
9201 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 |
9202 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 |
9203 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 |
9204 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb |
9205 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 |
9206 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 |
9207 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 |
9208 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 |
9209 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L |
9210 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L |
9211 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L |
9212 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L |
9213 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L |
9214 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L |
9215 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L |
9216 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L |
9217 | //HUBP0_DCHUBP_REQ_SIZE_CONFIG_C |
9218 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 |
9219 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 |
9220 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 |
9221 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb |
9222 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 |
9223 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 |
9224 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 |
9225 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 |
9226 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L |
9227 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L |
9228 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L |
9229 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L |
9230 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L |
9231 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L |
9232 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L |
9233 | #define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L |
9234 | //HUBP0_DCHUBP_CNTL |
9235 | #define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 |
9236 | #define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 |
9237 | #define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 |
9238 | #define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 |
9239 | #define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 |
9240 | #define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc |
9241 | #define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd |
9242 | #define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c |
9243 | #define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f |
9244 | #define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L |
9245 | #define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L |
9246 | #define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L |
9247 | #define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L |
9248 | #define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L |
9249 | #define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L |
9250 | #define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L |
9251 | #define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L |
9252 | #define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L |
9253 | //HUBP0_HUBP_CLK_CNTL |
9254 | #define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 |
9255 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 |
9256 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 |
9257 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc |
9258 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 |
9259 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 |
9260 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 |
9261 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 |
9262 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 |
9263 | #define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c |
9264 | #define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L |
9265 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L |
9266 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L |
9267 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L |
9268 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L |
9269 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L |
9270 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L |
9271 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L |
9272 | #define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L |
9273 | #define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L |
9274 | //HUBP0_DCHUBP_VMPG_CONFIG |
9275 | #define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 |
9276 | #define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L |
9277 | //HUBP0_HUBPREQ_DEBUG_DB |
9278 | #define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 |
9279 | #define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL |
9280 | //HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK |
9281 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 |
9282 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 |
9283 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc |
9284 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 |
9285 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c |
9286 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L |
9287 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L |
9288 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L |
9289 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L |
9290 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L |
9291 | //HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK |
9292 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 |
9293 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 |
9294 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 |
9295 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc |
9296 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 |
9297 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L |
9298 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L |
9299 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L |
9300 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L |
9301 | #define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L |
9302 | |
9303 | |
9304 | // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec |
9305 | //HUBPREQ0_DCSURF_SURFACE_PITCH |
9306 | #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 |
9307 | #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 |
9308 | #define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL |
9309 | #define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L |
9310 | //HUBPREQ0_DCSURF_SURFACE_PITCH_C |
9311 | #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 |
9312 | #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 |
9313 | #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL |
9314 | #define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L |
9315 | //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS |
9316 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 |
9317 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
9318 | //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH |
9319 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
9320 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9321 | //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C |
9322 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
9323 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
9324 | //HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C |
9325 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
9326 | #define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9327 | //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS |
9328 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 |
9329 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
9330 | //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH |
9331 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
9332 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9333 | //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C |
9334 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
9335 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
9336 | //HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C |
9337 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
9338 | #define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9339 | //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS |
9340 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
9341 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
9342 | //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH |
9343 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
9344 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9345 | //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C |
9346 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
9347 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
9348 | //HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C |
9349 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
9350 | #define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9351 | //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS |
9352 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
9353 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
9354 | //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH |
9355 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
9356 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9357 | //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C |
9358 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
9359 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
9360 | //HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C |
9361 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
9362 | #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9363 | //HUBPREQ0_DCSURF_SURFACE_CONTROL |
9364 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 |
9365 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 |
9366 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 |
9367 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 |
9368 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 |
9369 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 |
9370 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 |
9371 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa |
9372 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc |
9373 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd |
9374 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 |
9375 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x14 |
9376 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x18 |
9377 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1c |
9378 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L |
9379 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L |
9380 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L |
9381 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L |
9382 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L |
9383 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L |
9384 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L |
9385 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L |
9386 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L |
9387 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L |
9388 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L |
9389 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00100000L |
9390 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x01000000L |
9391 | #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x10000000L |
9392 | //HUBPREQ0_DCSURF_FLIP_CONTROL |
9393 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 |
9394 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 |
9395 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 |
9396 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc |
9397 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 |
9398 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 |
9399 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 |
9400 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 |
9401 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e |
9402 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f |
9403 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L |
9404 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L |
9405 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L |
9406 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L |
9407 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L |
9408 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L |
9409 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L |
9410 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L |
9411 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L |
9412 | #define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L |
9413 | //HUBPREQ0_DCSURF_FLIP_CONTROL2 |
9414 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 |
9415 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc |
9416 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd |
9417 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL |
9418 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L |
9419 | #define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L |
9420 | //HUBPREQ0_DCSURF_FRAME_PACING_CONTROL |
9421 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 |
9422 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 |
9423 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 |
9424 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 |
9425 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L |
9426 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L |
9427 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L |
9428 | #define HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L |
9429 | //HUBPREQ0_DCSURF_FRAME_PACING_TIME |
9430 | #define HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 |
9431 | #define HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL |
9432 | //HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT |
9433 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 |
9434 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 |
9435 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 |
9436 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 |
9437 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 |
9438 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 |
9439 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 |
9440 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 |
9441 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 |
9442 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 |
9443 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L |
9444 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L |
9445 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L |
9446 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L |
9447 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L |
9448 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L |
9449 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L |
9450 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L |
9451 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L |
9452 | #define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L |
9453 | //HUBPREQ0_DCSURF_SURFACE_INUSE |
9454 | #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 |
9455 | #define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
9456 | //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH |
9457 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
9458 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9459 | //HUBPREQ0_DCSURF_SURFACE_INUSE_C |
9460 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 |
9461 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
9462 | //HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C |
9463 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
9464 | #define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9465 | //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE |
9466 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 |
9467 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
9468 | //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH |
9469 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
9470 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9471 | //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C |
9472 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 |
9473 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
9474 | //HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C |
9475 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
9476 | #define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
9477 | //HUBPREQ0_DCN_EXPANSION_MODE |
9478 | #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 |
9479 | #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 |
9480 | #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 |
9481 | #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 |
9482 | #define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L |
9483 | #define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL |
9484 | #define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L |
9485 | #define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L |
9486 | //HUBPREQ0_DCN_TTU_QOS_WM |
9487 | #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 |
9488 | #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 |
9489 | #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL |
9490 | #define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L |
9491 | //HUBPREQ0_DCN_GLOBAL_TTU_CNTL |
9492 | #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 |
9493 | #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c |
9494 | #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL |
9495 | #define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L |
9496 | //HUBPREQ0_DCN_SURF0_TTU_CNTL0 |
9497 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
9498 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
9499 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
9500 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
9501 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
9502 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
9503 | //HUBPREQ0_DCN_SURF0_TTU_CNTL1 |
9504 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
9505 | #define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
9506 | //HUBPREQ0_DCN_SURF1_TTU_CNTL0 |
9507 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
9508 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
9509 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
9510 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
9511 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
9512 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
9513 | //HUBPREQ0_DCN_SURF1_TTU_CNTL1 |
9514 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
9515 | #define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
9516 | //HUBPREQ0_DCN_CUR0_TTU_CNTL0 |
9517 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
9518 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
9519 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
9520 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
9521 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
9522 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
9523 | //HUBPREQ0_DCN_CUR0_TTU_CNTL1 |
9524 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
9525 | #define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
9526 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB |
9527 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 |
9528 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL |
9529 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB |
9530 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 |
9531 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL |
9532 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB |
9533 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 |
9534 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL |
9535 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB |
9536 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 |
9537 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL |
9538 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
9539 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 |
9540 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
9541 | //HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
9542 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 |
9543 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c |
9544 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d |
9545 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
9546 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L |
9547 | #define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L |
9548 | //HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB |
9549 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 |
9550 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
9551 | //HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB |
9552 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 |
9553 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c |
9554 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d |
9555 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e |
9556 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
9557 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L |
9558 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L |
9559 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L |
9560 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB |
9561 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 |
9562 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL |
9563 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB |
9564 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 |
9565 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL |
9566 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB |
9567 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 |
9568 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL |
9569 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB |
9570 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 |
9571 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL |
9572 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB |
9573 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 |
9574 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL |
9575 | //HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB |
9576 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 |
9577 | #define HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL |
9578 | //HUBPREQ0_DCN_VM_CONTEXT0_STATUS |
9579 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 |
9580 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 |
9581 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e |
9582 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f |
9583 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL |
9584 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L |
9585 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L |
9586 | #define HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L |
9587 | //HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB |
9588 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 |
9589 | #define HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
9590 | //HUBPREQ0_DCN_VM_CONTEXT0_CNTL |
9591 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
9592 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 |
9593 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
9594 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc |
9595 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd |
9596 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
9597 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
9598 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
9599 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L |
9600 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
9601 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L |
9602 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L |
9603 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
9604 | #define HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
9605 | //HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL |
9606 | #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
9607 | #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
9608 | #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
9609 | #define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
9610 | //HUBPREQ0_BLANK_OFFSET_0 |
9611 | #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 |
9612 | #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 |
9613 | #define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL |
9614 | #define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L |
9615 | //HUBPREQ0_BLANK_OFFSET_1 |
9616 | #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 |
9617 | #define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL |
9618 | //HUBPREQ0_DST_DIMENSIONS |
9619 | #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 |
9620 | #define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL |
9621 | //HUBPREQ0_DST_AFTER_SCALER |
9622 | #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 |
9623 | #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 |
9624 | #define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL |
9625 | #define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L |
9626 | //HUBPREQ0_PREFETCH_SETTINS |
9627 | #define HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 |
9628 | #define HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 |
9629 | #define HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL |
9630 | #define HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L |
9631 | //HUBPREQ0_PREFETCH_SETTINS_C |
9632 | #define HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 |
9633 | #define HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL |
9634 | //HUBPREQ0_VBLANK_PARAMETERS_0 |
9635 | #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 |
9636 | #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 |
9637 | #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL |
9638 | #define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L |
9639 | //HUBPREQ0_VBLANK_PARAMETERS_1 |
9640 | #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 |
9641 | #define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL |
9642 | //HUBPREQ0_VBLANK_PARAMETERS_2 |
9643 | #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 |
9644 | #define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL |
9645 | //HUBPREQ0_VBLANK_PARAMETERS_3 |
9646 | #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 |
9647 | #define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL |
9648 | //HUBPREQ0_VBLANK_PARAMETERS_4 |
9649 | #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 |
9650 | #define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL |
9651 | //HUBPREQ0_NOM_PARAMETERS_0 |
9652 | #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 |
9653 | #define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL |
9654 | //HUBPREQ0_NOM_PARAMETERS_1 |
9655 | #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 |
9656 | #define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL |
9657 | //HUBPREQ0_NOM_PARAMETERS_2 |
9658 | #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 |
9659 | #define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL |
9660 | //HUBPREQ0_NOM_PARAMETERS_3 |
9661 | #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 |
9662 | #define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL |
9663 | //HUBPREQ0_NOM_PARAMETERS_4 |
9664 | #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 |
9665 | #define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL |
9666 | //HUBPREQ0_NOM_PARAMETERS_5 |
9667 | #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 |
9668 | #define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL |
9669 | //HUBPREQ0_NOM_PARAMETERS_6 |
9670 | #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 |
9671 | #define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL |
9672 | //HUBPREQ0_NOM_PARAMETERS_7 |
9673 | #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 |
9674 | #define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL |
9675 | //HUBPREQ0_PER_LINE_DELIVERY_PRE |
9676 | #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 |
9677 | #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 |
9678 | #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL |
9679 | #define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L |
9680 | //HUBPREQ0_PER_LINE_DELIVERY |
9681 | #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 |
9682 | #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 |
9683 | #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL |
9684 | #define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L |
9685 | //HUBPREQ0_CURSOR_SETTINS |
9686 | #define HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 |
9687 | #define HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 |
9688 | #define HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL |
9689 | #define HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L |
9690 | //HUBPREQ0_REF_FREQ_TO_PIX_FREQ |
9691 | #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 |
9692 | #define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL |
9693 | //HUBPREQ0_HUBPREQ_MEM_PWR_CTRL |
9694 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 |
9695 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 |
9696 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 |
9697 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 |
9698 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 |
9699 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa |
9700 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 |
9701 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 |
9702 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 |
9703 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 |
9704 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 |
9705 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L |
9706 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L |
9707 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L |
9708 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L |
9709 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L |
9710 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L |
9711 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L |
9712 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L |
9713 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L |
9714 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L |
9715 | #define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L |
9716 | //HUBPREQ0_HUBPREQ_MEM_PWR_STATUS |
9717 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 |
9718 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 |
9719 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 |
9720 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L |
9721 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL |
9722 | #define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L |
9723 | |
9724 | |
9725 | // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec |
9726 | //HUBPRET0_HUBPRET_CONTROL |
9727 | #define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 |
9728 | #define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc |
9729 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 |
9730 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 |
9731 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 |
9732 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 |
9733 | #define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 |
9734 | #define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL |
9735 | #define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L |
9736 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L |
9737 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L |
9738 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L |
9739 | #define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L |
9740 | #define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L |
9741 | //HUBPRET0_HUBPRET_MEM_PWR_CTRL |
9742 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 |
9743 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 |
9744 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 |
9745 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 |
9746 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L |
9747 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L |
9748 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L |
9749 | #define HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L |
9750 | //HUBPRET0_HUBPRET_MEM_PWR_STATUS |
9751 | #define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 |
9752 | #define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L |
9753 | //HUBPRET0_HUBPRET_READ_LINE_CTRL0 |
9754 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 |
9755 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 |
9756 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL |
9757 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L |
9758 | //HUBPRET0_HUBPRET_READ_LINE_CTRL1 |
9759 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 |
9760 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 |
9761 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL |
9762 | #define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L |
9763 | //HUBPRET0_HUBPRET_READ_LINE0 |
9764 | #define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 |
9765 | #define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 |
9766 | #define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL |
9767 | #define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L |
9768 | //HUBPRET0_HUBPRET_READ_LINE1 |
9769 | #define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 |
9770 | #define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 |
9771 | #define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL |
9772 | #define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L |
9773 | //HUBPRET0_HUBPRET_INTERRUPT |
9774 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 |
9775 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 |
9776 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 |
9777 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 |
9778 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 |
9779 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 |
9780 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 |
9781 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 |
9782 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa |
9783 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc |
9784 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd |
9785 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe |
9786 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 |
9787 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 |
9788 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 |
9789 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L |
9790 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L |
9791 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L |
9792 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L |
9793 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L |
9794 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L |
9795 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L |
9796 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L |
9797 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L |
9798 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L |
9799 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L |
9800 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L |
9801 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L |
9802 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L |
9803 | #define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L |
9804 | //HUBPRET0_HUBPRET_READ_LINE_VALUE |
9805 | #define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 |
9806 | #define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 |
9807 | #define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL |
9808 | #define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L |
9809 | //HUBPRET0_HUBPRET_READ_LINE_STATUS |
9810 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 |
9811 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 |
9812 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 |
9813 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 |
9814 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa |
9815 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L |
9816 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L |
9817 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L |
9818 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L |
9819 | #define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L |
9820 | |
9821 | |
9822 | // addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec |
9823 | //CURSOR0_CURSOR_CONTROL |
9824 | #define CURSOR0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 |
9825 | #define CURSOR0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
9826 | #define CURSOR0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd |
9827 | #define CURSOR0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe |
9828 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 |
9829 | #define CURSOR0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 |
9830 | #define CURSOR0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 |
9831 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e |
9832 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f |
9833 | #define CURSOR0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L |
9834 | #define CURSOR0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L |
9835 | #define CURSOR0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L |
9836 | #define CURSOR0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L |
9837 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L |
9838 | #define CURSOR0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L |
9839 | #define CURSOR0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L |
9840 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L |
9841 | #define CURSOR0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L |
9842 | //CURSOR0_CURSOR_SURFACE_ADDRESS |
9843 | #define CURSOR0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
9844 | #define CURSOR0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
9845 | //CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH |
9846 | #define CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
9847 | #define CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
9848 | //CURSOR0_CURSOR_SIZE |
9849 | #define CURSOR0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
9850 | #define CURSOR0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
9851 | #define CURSOR0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL |
9852 | #define CURSOR0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L |
9853 | //CURSOR0_CURSOR_POSITION |
9854 | #define CURSOR0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
9855 | #define CURSOR0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
9856 | #define CURSOR0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL |
9857 | #define CURSOR0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L |
9858 | //CURSOR0_CURSOR_HOT_SPOT |
9859 | #define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
9860 | #define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
9861 | #define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL |
9862 | #define CURSOR0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L |
9863 | //CURSOR0_CURSOR_STEREO_CONTROL |
9864 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
9865 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
9866 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 |
9867 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L |
9868 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L |
9869 | #define CURSOR0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L |
9870 | //CURSOR0_CURSOR_DST_OFFSET |
9871 | #define CURSOR0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 |
9872 | #define CURSOR0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL |
9873 | //CURSOR0_CURSOR_MEM_PWR_CTRL |
9874 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 |
9875 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 |
9876 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 |
9877 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L |
9878 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L |
9879 | #define CURSOR0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L |
9880 | //CURSOR0_CURSOR_MEM_PWR_STATUS |
9881 | #define CURSOR0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 |
9882 | #define CURSOR0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L |
9883 | |
9884 | |
9885 | // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
9886 | //DC_PERFMON8_PERFCOUNTER_CNTL |
9887 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
9888 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
9889 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
9890 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
9891 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
9892 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
9893 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
9894 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
9895 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
9896 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
9897 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
9898 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
9899 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
9900 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
9901 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
9902 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
9903 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
9904 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
9905 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
9906 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
9907 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
9908 | #define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
9909 | //DC_PERFMON8_PERFCOUNTER_CNTL2 |
9910 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
9911 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
9912 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
9913 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
9914 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
9915 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
9916 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
9917 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
9918 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
9919 | #define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
9920 | //DC_PERFMON8_PERFCOUNTER_STATE |
9921 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
9922 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
9923 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
9924 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
9925 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
9926 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
9927 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
9928 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
9929 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
9930 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
9931 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
9932 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
9933 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
9934 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
9935 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
9936 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
9937 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
9938 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
9939 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
9940 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
9941 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
9942 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
9943 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
9944 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
9945 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
9946 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
9947 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
9948 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
9949 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
9950 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
9951 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
9952 | #define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
9953 | //DC_PERFMON8_PERFMON_CNTL |
9954 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
9955 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
9956 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
9957 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
9958 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
9959 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
9960 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
9961 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
9962 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
9963 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
9964 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
9965 | #define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
9966 | //DC_PERFMON8_PERFMON_CNTL2 |
9967 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
9968 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
9969 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
9970 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
9971 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
9972 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
9973 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
9974 | #define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
9975 | //DC_PERFMON8_PERFMON_CVALUE_INT_MISC |
9976 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
9977 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
9978 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
9979 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
9980 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
9981 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
9982 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
9983 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
9984 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
9985 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
9986 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
9987 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
9988 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
9989 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
9990 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
9991 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
9992 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
9993 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
9994 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
9995 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
9996 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
9997 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
9998 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
9999 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
10000 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
10001 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
10002 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
10003 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
10004 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
10005 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
10006 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
10007 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
10008 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
10009 | #define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
10010 | //DC_PERFMON8_PERFMON_CVALUE_LOW |
10011 | #define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
10012 | #define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
10013 | //DC_PERFMON8_PERFMON_HI |
10014 | #define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
10015 | #define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
10016 | #define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
10017 | #define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
10018 | //DC_PERFMON8_PERFMON_LOW |
10019 | #define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
10020 | #define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
10021 | |
10022 | |
10023 | // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec |
10024 | //HUBP1_DCSURF_SURFACE_CONFIG |
10025 | #define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
10026 | #define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 |
10027 | #define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa |
10028 | #define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
10029 | #define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L |
10030 | #define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L |
10031 | //HUBP1_DCSURF_ADDR_CONFIG |
10032 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
10033 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 |
10034 | #define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 |
10035 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 |
10036 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa |
10037 | #define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc |
10038 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
10039 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L |
10040 | #define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L |
10041 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L |
10042 | #define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L |
10043 | #define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L |
10044 | //HUBP1_DCSURF_TILING_CONFIG |
10045 | #define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 |
10046 | #define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 |
10047 | #define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 |
10048 | #define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa |
10049 | #define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb |
10050 | #define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL |
10051 | #define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L |
10052 | #define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L |
10053 | #define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L |
10054 | #define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L |
10055 | //HUBP1_DCSURF_PRI_VIEWPORT_START |
10056 | #define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 |
10057 | #define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 |
10058 | #define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL |
10059 | #define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L |
10060 | //HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION |
10061 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 |
10062 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 |
10063 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL |
10064 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
10065 | //HUBP1_DCSURF_PRI_VIEWPORT_START_C |
10066 | #define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 |
10067 | #define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 |
10068 | #define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL |
10069 | #define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
10070 | //HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C |
10071 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 |
10072 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
10073 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
10074 | #define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
10075 | //HUBP1_DCSURF_SEC_VIEWPORT_START |
10076 | #define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 |
10077 | #define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 |
10078 | #define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL |
10079 | #define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L |
10080 | //HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION |
10081 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 |
10082 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 |
10083 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL |
10084 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
10085 | //HUBP1_DCSURF_SEC_VIEWPORT_START_C |
10086 | #define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 |
10087 | #define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 |
10088 | #define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL |
10089 | #define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
10090 | //HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C |
10091 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 |
10092 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
10093 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
10094 | #define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
10095 | //HUBP1_DCHUBP_REQ_SIZE_CONFIG |
10096 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 |
10097 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 |
10098 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 |
10099 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb |
10100 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 |
10101 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 |
10102 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 |
10103 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 |
10104 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L |
10105 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L |
10106 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L |
10107 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L |
10108 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L |
10109 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L |
10110 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L |
10111 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L |
10112 | //HUBP1_DCHUBP_REQ_SIZE_CONFIG_C |
10113 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 |
10114 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 |
10115 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 |
10116 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb |
10117 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 |
10118 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 |
10119 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 |
10120 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 |
10121 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L |
10122 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L |
10123 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L |
10124 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L |
10125 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L |
10126 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L |
10127 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L |
10128 | #define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L |
10129 | //HUBP1_DCHUBP_CNTL |
10130 | #define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 |
10131 | #define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 |
10132 | #define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 |
10133 | #define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 |
10134 | #define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 |
10135 | #define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc |
10136 | #define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd |
10137 | #define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c |
10138 | #define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f |
10139 | #define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L |
10140 | #define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L |
10141 | #define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L |
10142 | #define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L |
10143 | #define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L |
10144 | #define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L |
10145 | #define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L |
10146 | #define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L |
10147 | #define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L |
10148 | //HUBP1_HUBP_CLK_CNTL |
10149 | #define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 |
10150 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 |
10151 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 |
10152 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc |
10153 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 |
10154 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 |
10155 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 |
10156 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 |
10157 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 |
10158 | #define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c |
10159 | #define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L |
10160 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L |
10161 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L |
10162 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L |
10163 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L |
10164 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L |
10165 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L |
10166 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L |
10167 | #define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L |
10168 | #define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L |
10169 | //HUBP1_DCHUBP_VMPG_CONFIG |
10170 | #define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 |
10171 | #define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L |
10172 | //HUBP1_HUBPREQ_DEBUG_DB |
10173 | #define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 |
10174 | #define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL |
10175 | //HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK |
10176 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 |
10177 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 |
10178 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc |
10179 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 |
10180 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c |
10181 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L |
10182 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L |
10183 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L |
10184 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L |
10185 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L |
10186 | //HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK |
10187 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 |
10188 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 |
10189 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 |
10190 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc |
10191 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 |
10192 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L |
10193 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L |
10194 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L |
10195 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L |
10196 | #define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L |
10197 | |
10198 | |
10199 | // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec |
10200 | //HUBPREQ1_DCSURF_SURFACE_PITCH |
10201 | #define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 |
10202 | #define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 |
10203 | #define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL |
10204 | #define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L |
10205 | //HUBPREQ1_DCSURF_SURFACE_PITCH_C |
10206 | #define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 |
10207 | #define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 |
10208 | #define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL |
10209 | #define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L |
10210 | //HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS |
10211 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 |
10212 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
10213 | //HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH |
10214 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
10215 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10216 | //HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C |
10217 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
10218 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
10219 | //HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C |
10220 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
10221 | #define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10222 | //HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS |
10223 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 |
10224 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
10225 | //HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH |
10226 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
10227 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10228 | //HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C |
10229 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
10230 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
10231 | //HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C |
10232 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
10233 | #define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10234 | //HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS |
10235 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
10236 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
10237 | //HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH |
10238 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
10239 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10240 | //HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C |
10241 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
10242 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
10243 | //HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C |
10244 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
10245 | #define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10246 | //HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS |
10247 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
10248 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
10249 | //HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH |
10250 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
10251 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10252 | //HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C |
10253 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
10254 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
10255 | //HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C |
10256 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
10257 | #define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10258 | //HUBPREQ1_DCSURF_SURFACE_CONTROL |
10259 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 |
10260 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 |
10261 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 |
10262 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 |
10263 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa |
10264 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd |
10265 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L |
10266 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L |
10267 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L |
10268 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L |
10269 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L |
10270 | #define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L |
10271 | //HUBPREQ1_DCSURF_FLIP_CONTROL |
10272 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 |
10273 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 |
10274 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 |
10275 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc |
10276 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 |
10277 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 |
10278 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 |
10279 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 |
10280 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e |
10281 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f |
10282 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L |
10283 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L |
10284 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L |
10285 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L |
10286 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L |
10287 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L |
10288 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L |
10289 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L |
10290 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L |
10291 | #define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L |
10292 | //HUBPREQ1_DCSURF_FLIP_CONTROL2 |
10293 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 |
10294 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc |
10295 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd |
10296 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL |
10297 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L |
10298 | #define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L |
10299 | //HUBPREQ1_DCSURF_FRAME_PACING_CONTROL |
10300 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 |
10301 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 |
10302 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 |
10303 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 |
10304 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L |
10305 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L |
10306 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L |
10307 | #define HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L |
10308 | //HUBPREQ1_DCSURF_FRAME_PACING_TIME |
10309 | #define HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 |
10310 | #define HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL |
10311 | //HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT |
10312 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 |
10313 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 |
10314 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 |
10315 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 |
10316 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 |
10317 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 |
10318 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 |
10319 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 |
10320 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 |
10321 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 |
10322 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L |
10323 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L |
10324 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L |
10325 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L |
10326 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L |
10327 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L |
10328 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L |
10329 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L |
10330 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L |
10331 | #define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L |
10332 | //HUBPREQ1_DCSURF_SURFACE_INUSE |
10333 | #define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 |
10334 | #define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
10335 | //HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH |
10336 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
10337 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10338 | //HUBPREQ1_DCSURF_SURFACE_INUSE_C |
10339 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 |
10340 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
10341 | //HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C |
10342 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
10343 | #define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10344 | //HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE |
10345 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 |
10346 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
10347 | //HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH |
10348 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
10349 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10350 | //HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C |
10351 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 |
10352 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
10353 | //HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C |
10354 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
10355 | #define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
10356 | //HUBPREQ1_DCN_EXPANSION_MODE |
10357 | #define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 |
10358 | #define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 |
10359 | #define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 |
10360 | #define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 |
10361 | #define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L |
10362 | #define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL |
10363 | #define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L |
10364 | #define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L |
10365 | //HUBPREQ1_DCN_TTU_QOS_WM |
10366 | #define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 |
10367 | #define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 |
10368 | #define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL |
10369 | #define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L |
10370 | //HUBPREQ1_DCN_GLOBAL_TTU_CNTL |
10371 | #define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 |
10372 | #define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c |
10373 | #define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL |
10374 | #define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L |
10375 | //HUBPREQ1_DCN_SURF0_TTU_CNTL0 |
10376 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
10377 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
10378 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
10379 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
10380 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
10381 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
10382 | //HUBPREQ1_DCN_SURF0_TTU_CNTL1 |
10383 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
10384 | #define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
10385 | //HUBPREQ1_DCN_SURF1_TTU_CNTL0 |
10386 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
10387 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
10388 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
10389 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
10390 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
10391 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
10392 | //HUBPREQ1_DCN_SURF1_TTU_CNTL1 |
10393 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
10394 | #define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
10395 | //HUBPREQ1_DCN_CUR0_TTU_CNTL0 |
10396 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
10397 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
10398 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
10399 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
10400 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
10401 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
10402 | //HUBPREQ1_DCN_CUR0_TTU_CNTL1 |
10403 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
10404 | #define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
10405 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB |
10406 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 |
10407 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL |
10408 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB |
10409 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 |
10410 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL |
10411 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB |
10412 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 |
10413 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL |
10414 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB |
10415 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 |
10416 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL |
10417 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
10418 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 |
10419 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
10420 | //HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
10421 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 |
10422 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c |
10423 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d |
10424 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
10425 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L |
10426 | #define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L |
10427 | //HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB |
10428 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 |
10429 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
10430 | //HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB |
10431 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 |
10432 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c |
10433 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d |
10434 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e |
10435 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
10436 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L |
10437 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L |
10438 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L |
10439 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB |
10440 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 |
10441 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL |
10442 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB |
10443 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 |
10444 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL |
10445 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB |
10446 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 |
10447 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL |
10448 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB |
10449 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 |
10450 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL |
10451 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB |
10452 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 |
10453 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL |
10454 | //HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB |
10455 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 |
10456 | #define HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL |
10457 | //HUBPREQ1_DCN_VM_CONTEXT0_STATUS |
10458 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 |
10459 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 |
10460 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e |
10461 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f |
10462 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL |
10463 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L |
10464 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L |
10465 | #define HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L |
10466 | //HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB |
10467 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 |
10468 | #define HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
10469 | //HUBPREQ1_DCN_VM_CONTEXT0_CNTL |
10470 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
10471 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 |
10472 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
10473 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc |
10474 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd |
10475 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
10476 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
10477 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
10478 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L |
10479 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
10480 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L |
10481 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L |
10482 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
10483 | #define HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
10484 | //HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL |
10485 | #define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
10486 | #define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
10487 | #define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
10488 | #define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
10489 | //HUBPREQ1_BLANK_OFFSET_0 |
10490 | #define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 |
10491 | #define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 |
10492 | #define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL |
10493 | #define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L |
10494 | //HUBPREQ1_BLANK_OFFSET_1 |
10495 | #define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 |
10496 | #define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL |
10497 | //HUBPREQ1_DST_DIMENSIONS |
10498 | #define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 |
10499 | #define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL |
10500 | //HUBPREQ1_DST_AFTER_SCALER |
10501 | #define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 |
10502 | #define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 |
10503 | #define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL |
10504 | #define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L |
10505 | //HUBPREQ1_PREFETCH_SETTINS |
10506 | #define HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 |
10507 | #define HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 |
10508 | #define HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL |
10509 | #define HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L |
10510 | //HUBPREQ1_PREFETCH_SETTINS_C |
10511 | #define HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 |
10512 | #define HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL |
10513 | //HUBPREQ1_VBLANK_PARAMETERS_0 |
10514 | #define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 |
10515 | #define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 |
10516 | #define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL |
10517 | #define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L |
10518 | //HUBPREQ1_VBLANK_PARAMETERS_1 |
10519 | #define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 |
10520 | #define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL |
10521 | //HUBPREQ1_VBLANK_PARAMETERS_2 |
10522 | #define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 |
10523 | #define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL |
10524 | //HUBPREQ1_VBLANK_PARAMETERS_3 |
10525 | #define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 |
10526 | #define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL |
10527 | //HUBPREQ1_VBLANK_PARAMETERS_4 |
10528 | #define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 |
10529 | #define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL |
10530 | //HUBPREQ1_NOM_PARAMETERS_0 |
10531 | #define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 |
10532 | #define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL |
10533 | //HUBPREQ1_NOM_PARAMETERS_1 |
10534 | #define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 |
10535 | #define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL |
10536 | //HUBPREQ1_NOM_PARAMETERS_2 |
10537 | #define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 |
10538 | #define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL |
10539 | //HUBPREQ1_NOM_PARAMETERS_3 |
10540 | #define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 |
10541 | #define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL |
10542 | //HUBPREQ1_NOM_PARAMETERS_4 |
10543 | #define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 |
10544 | #define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL |
10545 | //HUBPREQ1_NOM_PARAMETERS_5 |
10546 | #define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 |
10547 | #define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL |
10548 | //HUBPREQ1_NOM_PARAMETERS_6 |
10549 | #define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 |
10550 | #define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL |
10551 | //HUBPREQ1_NOM_PARAMETERS_7 |
10552 | #define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 |
10553 | #define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL |
10554 | //HUBPREQ1_PER_LINE_DELIVERY_PRE |
10555 | #define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 |
10556 | #define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 |
10557 | #define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL |
10558 | #define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L |
10559 | //HUBPREQ1_PER_LINE_DELIVERY |
10560 | #define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 |
10561 | #define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 |
10562 | #define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL |
10563 | #define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L |
10564 | //HUBPREQ1_CURSOR_SETTINS |
10565 | #define HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 |
10566 | #define HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 |
10567 | #define HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL |
10568 | #define HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L |
10569 | //HUBPREQ1_REF_FREQ_TO_PIX_FREQ |
10570 | #define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 |
10571 | #define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL |
10572 | //HUBPREQ1_HUBPREQ_MEM_PWR_CTRL |
10573 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 |
10574 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 |
10575 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 |
10576 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 |
10577 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 |
10578 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa |
10579 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 |
10580 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 |
10581 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 |
10582 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 |
10583 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 |
10584 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L |
10585 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L |
10586 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L |
10587 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L |
10588 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L |
10589 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L |
10590 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L |
10591 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L |
10592 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L |
10593 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L |
10594 | #define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L |
10595 | //HUBPREQ1_HUBPREQ_MEM_PWR_STATUS |
10596 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 |
10597 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 |
10598 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 |
10599 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L |
10600 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL |
10601 | #define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L |
10602 | |
10603 | |
10604 | // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec |
10605 | //HUBPRET1_HUBPRET_CONTROL |
10606 | #define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 |
10607 | #define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc |
10608 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 |
10609 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 |
10610 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 |
10611 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 |
10612 | #define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 |
10613 | #define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL |
10614 | #define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L |
10615 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L |
10616 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L |
10617 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L |
10618 | #define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L |
10619 | #define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L |
10620 | //HUBPRET1_HUBPRET_MEM_PWR_CTRL |
10621 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 |
10622 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 |
10623 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 |
10624 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 |
10625 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L |
10626 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L |
10627 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L |
10628 | #define HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L |
10629 | //HUBPRET1_HUBPRET_MEM_PWR_STATUS |
10630 | #define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 |
10631 | #define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L |
10632 | //HUBPRET1_HUBPRET_READ_LINE_CTRL0 |
10633 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 |
10634 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 |
10635 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL |
10636 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L |
10637 | //HUBPRET1_HUBPRET_READ_LINE_CTRL1 |
10638 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 |
10639 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 |
10640 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL |
10641 | #define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L |
10642 | //HUBPRET1_HUBPRET_READ_LINE0 |
10643 | #define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 |
10644 | #define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 |
10645 | #define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL |
10646 | #define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L |
10647 | //HUBPRET1_HUBPRET_READ_LINE1 |
10648 | #define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 |
10649 | #define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 |
10650 | #define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL |
10651 | #define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L |
10652 | //HUBPRET1_HUBPRET_INTERRUPT |
10653 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 |
10654 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 |
10655 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 |
10656 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 |
10657 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 |
10658 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 |
10659 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 |
10660 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 |
10661 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa |
10662 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc |
10663 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd |
10664 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe |
10665 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 |
10666 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 |
10667 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 |
10668 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L |
10669 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L |
10670 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L |
10671 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L |
10672 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L |
10673 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L |
10674 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L |
10675 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L |
10676 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L |
10677 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L |
10678 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L |
10679 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L |
10680 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L |
10681 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L |
10682 | #define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L |
10683 | //HUBPRET1_HUBPRET_READ_LINE_VALUE |
10684 | #define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 |
10685 | #define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 |
10686 | #define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL |
10687 | #define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L |
10688 | //HUBPRET1_HUBPRET_READ_LINE_STATUS |
10689 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 |
10690 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 |
10691 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 |
10692 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 |
10693 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa |
10694 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L |
10695 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L |
10696 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L |
10697 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L |
10698 | #define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L |
10699 | |
10700 | |
10701 | // addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec |
10702 | //CURSOR1_CURSOR_CONTROL |
10703 | #define CURSOR1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 |
10704 | #define CURSOR1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
10705 | #define CURSOR1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd |
10706 | #define CURSOR1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe |
10707 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 |
10708 | #define CURSOR1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 |
10709 | #define CURSOR1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 |
10710 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e |
10711 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f |
10712 | #define CURSOR1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L |
10713 | #define CURSOR1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L |
10714 | #define CURSOR1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L |
10715 | #define CURSOR1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L |
10716 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L |
10717 | #define CURSOR1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L |
10718 | #define CURSOR1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L |
10719 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L |
10720 | #define CURSOR1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L |
10721 | //CURSOR1_CURSOR_SURFACE_ADDRESS |
10722 | #define CURSOR1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
10723 | #define CURSOR1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
10724 | //CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH |
10725 | #define CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
10726 | #define CURSOR1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
10727 | //CURSOR1_CURSOR_SIZE |
10728 | #define CURSOR1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
10729 | #define CURSOR1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
10730 | #define CURSOR1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL |
10731 | #define CURSOR1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L |
10732 | //CURSOR1_CURSOR_POSITION |
10733 | #define CURSOR1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
10734 | #define CURSOR1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
10735 | #define CURSOR1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL |
10736 | #define CURSOR1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L |
10737 | //CURSOR1_CURSOR_HOT_SPOT |
10738 | #define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
10739 | #define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
10740 | #define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL |
10741 | #define CURSOR1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L |
10742 | //CURSOR1_CURSOR_STEREO_CONTROL |
10743 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
10744 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
10745 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 |
10746 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L |
10747 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L |
10748 | #define CURSOR1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L |
10749 | //CURSOR1_CURSOR_DST_OFFSET |
10750 | #define CURSOR1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 |
10751 | #define CURSOR1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL |
10752 | //CURSOR1_CURSOR_MEM_PWR_CTRL |
10753 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 |
10754 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 |
10755 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 |
10756 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L |
10757 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L |
10758 | #define CURSOR1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L |
10759 | //CURSOR1_CURSOR_MEM_PWR_STATUS |
10760 | #define CURSOR1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 |
10761 | #define CURSOR1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L |
10762 | |
10763 | |
10764 | // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
10765 | //DC_PERFMON9_PERFCOUNTER_CNTL |
10766 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
10767 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
10768 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
10769 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
10770 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
10771 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
10772 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
10773 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
10774 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
10775 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
10776 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
10777 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
10778 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
10779 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
10780 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
10781 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
10782 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
10783 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
10784 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
10785 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
10786 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
10787 | #define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
10788 | //DC_PERFMON9_PERFCOUNTER_CNTL2 |
10789 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
10790 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
10791 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
10792 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
10793 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
10794 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
10795 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
10796 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
10797 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
10798 | #define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
10799 | //DC_PERFMON9_PERFCOUNTER_STATE |
10800 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
10801 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
10802 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
10803 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
10804 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
10805 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
10806 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
10807 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
10808 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
10809 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
10810 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
10811 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
10812 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
10813 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
10814 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
10815 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
10816 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
10817 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
10818 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
10819 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
10820 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
10821 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
10822 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
10823 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
10824 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
10825 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
10826 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
10827 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
10828 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
10829 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
10830 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
10831 | #define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
10832 | //DC_PERFMON9_PERFMON_CNTL |
10833 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
10834 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
10835 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
10836 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
10837 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
10838 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
10839 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
10840 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
10841 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
10842 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
10843 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
10844 | #define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
10845 | //DC_PERFMON9_PERFMON_CNTL2 |
10846 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
10847 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
10848 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
10849 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
10850 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
10851 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
10852 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
10853 | #define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
10854 | //DC_PERFMON9_PERFMON_CVALUE_INT_MISC |
10855 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
10856 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
10857 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
10858 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
10859 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
10860 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
10861 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
10862 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
10863 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
10864 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
10865 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
10866 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
10867 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
10868 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
10869 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
10870 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
10871 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
10872 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
10873 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
10874 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
10875 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
10876 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
10877 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
10878 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
10879 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
10880 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
10881 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
10882 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
10883 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
10884 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
10885 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
10886 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
10887 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
10888 | #define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
10889 | //DC_PERFMON9_PERFMON_CVALUE_LOW |
10890 | #define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
10891 | #define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
10892 | //DC_PERFMON9_PERFMON_HI |
10893 | #define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
10894 | #define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
10895 | #define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
10896 | #define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
10897 | //DC_PERFMON9_PERFMON_LOW |
10898 | #define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
10899 | #define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
10900 | |
10901 | |
10902 | // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec |
10903 | //HUBP2_DCSURF_SURFACE_CONFIG |
10904 | #define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
10905 | #define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 |
10906 | #define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa |
10907 | #define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
10908 | #define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L |
10909 | #define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L |
10910 | //HUBP2_DCSURF_ADDR_CONFIG |
10911 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
10912 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 |
10913 | #define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 |
10914 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 |
10915 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa |
10916 | #define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc |
10917 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
10918 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L |
10919 | #define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L |
10920 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L |
10921 | #define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L |
10922 | #define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L |
10923 | //HUBP2_DCSURF_TILING_CONFIG |
10924 | #define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 |
10925 | #define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 |
10926 | #define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 |
10927 | #define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa |
10928 | #define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb |
10929 | #define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL |
10930 | #define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L |
10931 | #define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L |
10932 | #define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L |
10933 | #define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L |
10934 | //HUBP2_DCSURF_PRI_VIEWPORT_START |
10935 | #define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 |
10936 | #define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 |
10937 | #define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL |
10938 | #define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L |
10939 | //HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION |
10940 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 |
10941 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 |
10942 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL |
10943 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
10944 | //HUBP2_DCSURF_PRI_VIEWPORT_START_C |
10945 | #define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 |
10946 | #define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 |
10947 | #define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL |
10948 | #define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
10949 | //HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C |
10950 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 |
10951 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
10952 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
10953 | #define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
10954 | //HUBP2_DCSURF_SEC_VIEWPORT_START |
10955 | #define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 |
10956 | #define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 |
10957 | #define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL |
10958 | #define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L |
10959 | //HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION |
10960 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 |
10961 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 |
10962 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL |
10963 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
10964 | //HUBP2_DCSURF_SEC_VIEWPORT_START_C |
10965 | #define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 |
10966 | #define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 |
10967 | #define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL |
10968 | #define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
10969 | //HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C |
10970 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 |
10971 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
10972 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
10973 | #define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
10974 | //HUBP2_DCHUBP_REQ_SIZE_CONFIG |
10975 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 |
10976 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 |
10977 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 |
10978 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb |
10979 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 |
10980 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 |
10981 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 |
10982 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 |
10983 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L |
10984 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L |
10985 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L |
10986 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L |
10987 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L |
10988 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L |
10989 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L |
10990 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L |
10991 | //HUBP2_DCHUBP_REQ_SIZE_CONFIG_C |
10992 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 |
10993 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 |
10994 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 |
10995 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb |
10996 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 |
10997 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 |
10998 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 |
10999 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 |
11000 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L |
11001 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L |
11002 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L |
11003 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L |
11004 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L |
11005 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L |
11006 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L |
11007 | #define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L |
11008 | //HUBP2_DCHUBP_CNTL |
11009 | #define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 |
11010 | #define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 |
11011 | #define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 |
11012 | #define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 |
11013 | #define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 |
11014 | #define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc |
11015 | #define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd |
11016 | #define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c |
11017 | #define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f |
11018 | #define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L |
11019 | #define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L |
11020 | #define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L |
11021 | #define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L |
11022 | #define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L |
11023 | #define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L |
11024 | #define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L |
11025 | #define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L |
11026 | #define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L |
11027 | //HUBP2_HUBP_CLK_CNTL |
11028 | #define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 |
11029 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 |
11030 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 |
11031 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc |
11032 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 |
11033 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 |
11034 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 |
11035 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 |
11036 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 |
11037 | #define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c |
11038 | #define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L |
11039 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L |
11040 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L |
11041 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L |
11042 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L |
11043 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L |
11044 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L |
11045 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L |
11046 | #define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L |
11047 | #define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L |
11048 | //HUBP2_DCHUBP_VMPG_CONFIG |
11049 | #define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 |
11050 | #define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L |
11051 | //HUBP2_HUBPREQ_DEBUG_DB |
11052 | #define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 |
11053 | #define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL |
11054 | //HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK |
11055 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 |
11056 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 |
11057 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc |
11058 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 |
11059 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c |
11060 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L |
11061 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L |
11062 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L |
11063 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L |
11064 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L |
11065 | //HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK |
11066 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 |
11067 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 |
11068 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 |
11069 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc |
11070 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 |
11071 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L |
11072 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L |
11073 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L |
11074 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L |
11075 | #define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L |
11076 | |
11077 | |
11078 | // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec |
11079 | //HUBPREQ2_DCSURF_SURFACE_PITCH |
11080 | #define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 |
11081 | #define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 |
11082 | #define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL |
11083 | #define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L |
11084 | //HUBPREQ2_DCSURF_SURFACE_PITCH_C |
11085 | #define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 |
11086 | #define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 |
11087 | #define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL |
11088 | #define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L |
11089 | //HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS |
11090 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 |
11091 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11092 | //HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH |
11093 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11094 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11095 | //HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C |
11096 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
11097 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11098 | //HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C |
11099 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11100 | #define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11101 | //HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS |
11102 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 |
11103 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11104 | //HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH |
11105 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11106 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11107 | //HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C |
11108 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
11109 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11110 | //HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C |
11111 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11112 | #define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11113 | //HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS |
11114 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
11115 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11116 | //HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH |
11117 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11118 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11119 | //HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C |
11120 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
11121 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11122 | //HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C |
11123 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11124 | #define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11125 | //HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS |
11126 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
11127 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11128 | //HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH |
11129 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11130 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11131 | //HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C |
11132 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
11133 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11134 | //HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C |
11135 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11136 | #define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11137 | //HUBPREQ2_DCSURF_SURFACE_CONTROL |
11138 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 |
11139 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 |
11140 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 |
11141 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 |
11142 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa |
11143 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd |
11144 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L |
11145 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L |
11146 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L |
11147 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L |
11148 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L |
11149 | #define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L |
11150 | //HUBPREQ2_DCSURF_FLIP_CONTROL |
11151 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 |
11152 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 |
11153 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 |
11154 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc |
11155 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 |
11156 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 |
11157 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 |
11158 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 |
11159 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e |
11160 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f |
11161 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L |
11162 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L |
11163 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L |
11164 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L |
11165 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L |
11166 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L |
11167 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L |
11168 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L |
11169 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L |
11170 | #define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L |
11171 | //HUBPREQ2_DCSURF_FLIP_CONTROL2 |
11172 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 |
11173 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc |
11174 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd |
11175 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL |
11176 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L |
11177 | #define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L |
11178 | //HUBPREQ2_DCSURF_FRAME_PACING_CONTROL |
11179 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 |
11180 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 |
11181 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 |
11182 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 |
11183 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L |
11184 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L |
11185 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L |
11186 | #define HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L |
11187 | //HUBPREQ2_DCSURF_FRAME_PACING_TIME |
11188 | #define HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 |
11189 | #define HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL |
11190 | //HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT |
11191 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 |
11192 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 |
11193 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 |
11194 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 |
11195 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 |
11196 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 |
11197 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 |
11198 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 |
11199 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 |
11200 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 |
11201 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L |
11202 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L |
11203 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L |
11204 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L |
11205 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L |
11206 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L |
11207 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L |
11208 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L |
11209 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L |
11210 | #define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L |
11211 | //HUBPREQ2_DCSURF_SURFACE_INUSE |
11212 | #define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 |
11213 | #define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
11214 | //HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH |
11215 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
11216 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11217 | //HUBPREQ2_DCSURF_SURFACE_INUSE_C |
11218 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 |
11219 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
11220 | //HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C |
11221 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
11222 | #define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11223 | //HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE |
11224 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 |
11225 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
11226 | //HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH |
11227 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
11228 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11229 | //HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C |
11230 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 |
11231 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
11232 | //HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C |
11233 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
11234 | #define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11235 | //HUBPREQ2_DCN_EXPANSION_MODE |
11236 | #define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 |
11237 | #define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 |
11238 | #define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 |
11239 | #define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 |
11240 | #define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L |
11241 | #define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL |
11242 | #define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L |
11243 | #define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L |
11244 | //HUBPREQ2_DCN_TTU_QOS_WM |
11245 | #define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 |
11246 | #define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 |
11247 | #define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL |
11248 | #define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L |
11249 | //HUBPREQ2_DCN_GLOBAL_TTU_CNTL |
11250 | #define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 |
11251 | #define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c |
11252 | #define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL |
11253 | #define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L |
11254 | //HUBPREQ2_DCN_SURF0_TTU_CNTL0 |
11255 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
11256 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
11257 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
11258 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
11259 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
11260 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
11261 | //HUBPREQ2_DCN_SURF0_TTU_CNTL1 |
11262 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
11263 | #define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
11264 | //HUBPREQ2_DCN_SURF1_TTU_CNTL0 |
11265 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
11266 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
11267 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
11268 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
11269 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
11270 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
11271 | //HUBPREQ2_DCN_SURF1_TTU_CNTL1 |
11272 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
11273 | #define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
11274 | //HUBPREQ2_DCN_CUR0_TTU_CNTL0 |
11275 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
11276 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
11277 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
11278 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
11279 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
11280 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
11281 | //HUBPREQ2_DCN_CUR0_TTU_CNTL1 |
11282 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
11283 | #define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
11284 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB |
11285 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 |
11286 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL |
11287 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB |
11288 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 |
11289 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL |
11290 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB |
11291 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 |
11292 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL |
11293 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB |
11294 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 |
11295 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL |
11296 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
11297 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 |
11298 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
11299 | //HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
11300 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 |
11301 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c |
11302 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d |
11303 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
11304 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L |
11305 | #define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L |
11306 | //HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB |
11307 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 |
11308 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
11309 | //HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB |
11310 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 |
11311 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c |
11312 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d |
11313 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e |
11314 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
11315 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L |
11316 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L |
11317 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L |
11318 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB |
11319 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 |
11320 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL |
11321 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB |
11322 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 |
11323 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL |
11324 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB |
11325 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 |
11326 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL |
11327 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB |
11328 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 |
11329 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL |
11330 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB |
11331 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 |
11332 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL |
11333 | //HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB |
11334 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 |
11335 | #define HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL |
11336 | //HUBPREQ2_DCN_VM_CONTEXT0_STATUS |
11337 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 |
11338 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 |
11339 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e |
11340 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f |
11341 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL |
11342 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L |
11343 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L |
11344 | #define HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L |
11345 | //HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB |
11346 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 |
11347 | #define HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
11348 | //HUBPREQ2_DCN_VM_CONTEXT0_CNTL |
11349 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11350 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 |
11351 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
11352 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc |
11353 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd |
11354 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11355 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11356 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11357 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L |
11358 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
11359 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L |
11360 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L |
11361 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11362 | #define HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11363 | //HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL |
11364 | #define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
11365 | #define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
11366 | #define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
11367 | #define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
11368 | //HUBPREQ2_BLANK_OFFSET_0 |
11369 | #define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 |
11370 | #define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 |
11371 | #define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL |
11372 | #define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L |
11373 | //HUBPREQ2_BLANK_OFFSET_1 |
11374 | #define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 |
11375 | #define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL |
11376 | //HUBPREQ2_DST_DIMENSIONS |
11377 | #define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 |
11378 | #define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL |
11379 | //HUBPREQ2_DST_AFTER_SCALER |
11380 | #define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 |
11381 | #define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 |
11382 | #define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL |
11383 | #define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L |
11384 | //HUBPREQ2_PREFETCH_SETTINS |
11385 | #define HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 |
11386 | #define HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 |
11387 | #define HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL |
11388 | #define HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L |
11389 | //HUBPREQ2_PREFETCH_SETTINS_C |
11390 | #define HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 |
11391 | #define HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL |
11392 | //HUBPREQ2_VBLANK_PARAMETERS_0 |
11393 | #define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 |
11394 | #define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 |
11395 | #define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL |
11396 | #define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L |
11397 | //HUBPREQ2_VBLANK_PARAMETERS_1 |
11398 | #define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 |
11399 | #define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL |
11400 | //HUBPREQ2_VBLANK_PARAMETERS_2 |
11401 | #define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 |
11402 | #define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL |
11403 | //HUBPREQ2_VBLANK_PARAMETERS_3 |
11404 | #define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 |
11405 | #define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL |
11406 | //HUBPREQ2_VBLANK_PARAMETERS_4 |
11407 | #define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 |
11408 | #define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL |
11409 | //HUBPREQ2_NOM_PARAMETERS_0 |
11410 | #define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 |
11411 | #define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL |
11412 | //HUBPREQ2_NOM_PARAMETERS_1 |
11413 | #define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 |
11414 | #define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL |
11415 | //HUBPREQ2_NOM_PARAMETERS_2 |
11416 | #define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 |
11417 | #define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL |
11418 | //HUBPREQ2_NOM_PARAMETERS_3 |
11419 | #define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 |
11420 | #define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL |
11421 | //HUBPREQ2_NOM_PARAMETERS_4 |
11422 | #define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 |
11423 | #define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL |
11424 | //HUBPREQ2_NOM_PARAMETERS_5 |
11425 | #define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 |
11426 | #define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL |
11427 | //HUBPREQ2_NOM_PARAMETERS_6 |
11428 | #define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 |
11429 | #define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL |
11430 | //HUBPREQ2_NOM_PARAMETERS_7 |
11431 | #define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 |
11432 | #define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL |
11433 | //HUBPREQ2_PER_LINE_DELIVERY_PRE |
11434 | #define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 |
11435 | #define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 |
11436 | #define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL |
11437 | #define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L |
11438 | //HUBPREQ2_PER_LINE_DELIVERY |
11439 | #define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 |
11440 | #define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 |
11441 | #define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL |
11442 | #define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L |
11443 | //HUBPREQ2_CURSOR_SETTINS |
11444 | #define HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 |
11445 | #define HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 |
11446 | #define HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL |
11447 | #define HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L |
11448 | //HUBPREQ2_REF_FREQ_TO_PIX_FREQ |
11449 | #define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 |
11450 | #define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL |
11451 | //HUBPREQ2_HUBPREQ_MEM_PWR_CTRL |
11452 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 |
11453 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 |
11454 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 |
11455 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 |
11456 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 |
11457 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa |
11458 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 |
11459 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 |
11460 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 |
11461 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 |
11462 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 |
11463 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L |
11464 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L |
11465 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L |
11466 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L |
11467 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L |
11468 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L |
11469 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L |
11470 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L |
11471 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L |
11472 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L |
11473 | #define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L |
11474 | //HUBPREQ2_HUBPREQ_MEM_PWR_STATUS |
11475 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 |
11476 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 |
11477 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 |
11478 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L |
11479 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL |
11480 | #define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L |
11481 | |
11482 | |
11483 | // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec |
11484 | //HUBPRET2_HUBPRET_CONTROL |
11485 | #define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 |
11486 | #define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc |
11487 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 |
11488 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 |
11489 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 |
11490 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 |
11491 | #define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 |
11492 | #define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL |
11493 | #define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L |
11494 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L |
11495 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L |
11496 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L |
11497 | #define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L |
11498 | #define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L |
11499 | //HUBPRET2_HUBPRET_MEM_PWR_CTRL |
11500 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 |
11501 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 |
11502 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 |
11503 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 |
11504 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L |
11505 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L |
11506 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L |
11507 | #define HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L |
11508 | //HUBPRET2_HUBPRET_MEM_PWR_STATUS |
11509 | #define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 |
11510 | #define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L |
11511 | //HUBPRET2_HUBPRET_READ_LINE_CTRL0 |
11512 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 |
11513 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 |
11514 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL |
11515 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L |
11516 | //HUBPRET2_HUBPRET_READ_LINE_CTRL1 |
11517 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 |
11518 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 |
11519 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL |
11520 | #define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L |
11521 | //HUBPRET2_HUBPRET_READ_LINE0 |
11522 | #define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 |
11523 | #define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 |
11524 | #define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL |
11525 | #define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L |
11526 | //HUBPRET2_HUBPRET_READ_LINE1 |
11527 | #define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 |
11528 | #define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 |
11529 | #define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL |
11530 | #define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L |
11531 | //HUBPRET2_HUBPRET_INTERRUPT |
11532 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 |
11533 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 |
11534 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 |
11535 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 |
11536 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 |
11537 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 |
11538 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 |
11539 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 |
11540 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa |
11541 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc |
11542 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd |
11543 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe |
11544 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 |
11545 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 |
11546 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 |
11547 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L |
11548 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L |
11549 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L |
11550 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L |
11551 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L |
11552 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L |
11553 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L |
11554 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L |
11555 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L |
11556 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L |
11557 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L |
11558 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L |
11559 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L |
11560 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L |
11561 | #define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L |
11562 | //HUBPRET2_HUBPRET_READ_LINE_VALUE |
11563 | #define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 |
11564 | #define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 |
11565 | #define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL |
11566 | #define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L |
11567 | //HUBPRET2_HUBPRET_READ_LINE_STATUS |
11568 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 |
11569 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 |
11570 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 |
11571 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 |
11572 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa |
11573 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L |
11574 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L |
11575 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L |
11576 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L |
11577 | #define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L |
11578 | |
11579 | |
11580 | // addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec |
11581 | //CURSOR2_CURSOR_CONTROL |
11582 | #define CURSOR2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 |
11583 | #define CURSOR2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
11584 | #define CURSOR2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd |
11585 | #define CURSOR2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe |
11586 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 |
11587 | #define CURSOR2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 |
11588 | #define CURSOR2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 |
11589 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e |
11590 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f |
11591 | #define CURSOR2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L |
11592 | #define CURSOR2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L |
11593 | #define CURSOR2_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L |
11594 | #define CURSOR2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L |
11595 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L |
11596 | #define CURSOR2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L |
11597 | #define CURSOR2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L |
11598 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L |
11599 | #define CURSOR2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L |
11600 | //CURSOR2_CURSOR_SURFACE_ADDRESS |
11601 | #define CURSOR2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
11602 | #define CURSOR2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11603 | //CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH |
11604 | #define CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11605 | #define CURSOR2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11606 | //CURSOR2_CURSOR_SIZE |
11607 | #define CURSOR2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
11608 | #define CURSOR2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
11609 | #define CURSOR2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL |
11610 | #define CURSOR2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L |
11611 | //CURSOR2_CURSOR_POSITION |
11612 | #define CURSOR2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
11613 | #define CURSOR2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
11614 | #define CURSOR2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL |
11615 | #define CURSOR2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L |
11616 | //CURSOR2_CURSOR_HOT_SPOT |
11617 | #define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
11618 | #define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
11619 | #define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL |
11620 | #define CURSOR2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L |
11621 | //CURSOR2_CURSOR_STEREO_CONTROL |
11622 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
11623 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
11624 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 |
11625 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L |
11626 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L |
11627 | #define CURSOR2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L |
11628 | //CURSOR2_CURSOR_DST_OFFSET |
11629 | #define CURSOR2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 |
11630 | #define CURSOR2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL |
11631 | //CURSOR2_CURSOR_MEM_PWR_CTRL |
11632 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 |
11633 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 |
11634 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 |
11635 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L |
11636 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L |
11637 | #define CURSOR2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L |
11638 | //CURSOR2_CURSOR_MEM_PWR_STATUS |
11639 | #define CURSOR2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 |
11640 | #define CURSOR2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L |
11641 | |
11642 | |
11643 | // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
11644 | //DC_PERFMON10_PERFCOUNTER_CNTL |
11645 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
11646 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
11647 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
11648 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
11649 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
11650 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
11651 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
11652 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
11653 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
11654 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
11655 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
11656 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
11657 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
11658 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
11659 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
11660 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
11661 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
11662 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
11663 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
11664 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
11665 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
11666 | #define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
11667 | //DC_PERFMON10_PERFCOUNTER_CNTL2 |
11668 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
11669 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
11670 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
11671 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
11672 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
11673 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
11674 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
11675 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
11676 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
11677 | #define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
11678 | //DC_PERFMON10_PERFCOUNTER_STATE |
11679 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
11680 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
11681 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
11682 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
11683 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
11684 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
11685 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
11686 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
11687 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
11688 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
11689 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
11690 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
11691 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
11692 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
11693 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
11694 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
11695 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
11696 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
11697 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
11698 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
11699 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
11700 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
11701 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
11702 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
11703 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
11704 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
11705 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
11706 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
11707 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
11708 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
11709 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
11710 | #define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
11711 | //DC_PERFMON10_PERFMON_CNTL |
11712 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
11713 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
11714 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
11715 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
11716 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
11717 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
11718 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
11719 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
11720 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
11721 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
11722 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
11723 | #define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
11724 | //DC_PERFMON10_PERFMON_CNTL2 |
11725 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
11726 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
11727 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
11728 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
11729 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
11730 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
11731 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
11732 | #define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
11733 | //DC_PERFMON10_PERFMON_CVALUE_INT_MISC |
11734 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
11735 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
11736 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
11737 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
11738 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
11739 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
11740 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
11741 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
11742 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
11743 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
11744 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
11745 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
11746 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
11747 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
11748 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
11749 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
11750 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
11751 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
11752 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
11753 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
11754 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
11755 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
11756 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
11757 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
11758 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
11759 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
11760 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
11761 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
11762 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
11763 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
11764 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
11765 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
11766 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
11767 | #define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
11768 | //DC_PERFMON10_PERFMON_CVALUE_LOW |
11769 | #define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
11770 | #define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
11771 | //DC_PERFMON10_PERFMON_HI |
11772 | #define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
11773 | #define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
11774 | #define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
11775 | #define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
11776 | //DC_PERFMON10_PERFMON_LOW |
11777 | #define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
11778 | #define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
11779 | |
11780 | |
11781 | // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec |
11782 | //HUBP3_DCSURF_SURFACE_CONFIG |
11783 | #define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
11784 | #define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 |
11785 | #define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa |
11786 | #define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
11787 | #define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L |
11788 | #define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L |
11789 | //HUBP3_DCSURF_ADDR_CONFIG |
11790 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
11791 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 |
11792 | #define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 |
11793 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 |
11794 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa |
11795 | #define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc |
11796 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
11797 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L |
11798 | #define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L |
11799 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L |
11800 | #define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L |
11801 | #define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L |
11802 | //HUBP3_DCSURF_TILING_CONFIG |
11803 | #define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 |
11804 | #define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 |
11805 | #define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 |
11806 | #define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa |
11807 | #define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb |
11808 | #define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL |
11809 | #define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L |
11810 | #define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L |
11811 | #define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L |
11812 | #define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L |
11813 | //HUBP3_DCSURF_PRI_VIEWPORT_START |
11814 | #define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 |
11815 | #define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 |
11816 | #define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL |
11817 | #define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L |
11818 | //HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION |
11819 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 |
11820 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 |
11821 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL |
11822 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
11823 | //HUBP3_DCSURF_PRI_VIEWPORT_START_C |
11824 | #define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 |
11825 | #define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 |
11826 | #define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL |
11827 | #define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
11828 | //HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C |
11829 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 |
11830 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
11831 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
11832 | #define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
11833 | //HUBP3_DCSURF_SEC_VIEWPORT_START |
11834 | #define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 |
11835 | #define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 |
11836 | #define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL |
11837 | #define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L |
11838 | //HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION |
11839 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 |
11840 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 |
11841 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL |
11842 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L |
11843 | //HUBP3_DCSURF_SEC_VIEWPORT_START_C |
11844 | #define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 |
11845 | #define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 |
11846 | #define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL |
11847 | #define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L |
11848 | //HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C |
11849 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 |
11850 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 |
11851 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL |
11852 | #define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L |
11853 | //HUBP3_DCHUBP_REQ_SIZE_CONFIG |
11854 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 |
11855 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 |
11856 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 |
11857 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb |
11858 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 |
11859 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 |
11860 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 |
11861 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT 0x18 |
11862 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L |
11863 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L |
11864 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L |
11865 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L |
11866 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L |
11867 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L |
11868 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L |
11869 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK 0x07000000L |
11870 | //HUBP3_DCHUBP_REQ_SIZE_CONFIG_C |
11871 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 |
11872 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 |
11873 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 |
11874 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb |
11875 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 |
11876 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 |
11877 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 |
11878 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT 0x18 |
11879 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L |
11880 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L |
11881 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L |
11882 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L |
11883 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L |
11884 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L |
11885 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L |
11886 | #define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK 0x07000000L |
11887 | //HUBP3_DCHUBP_CNTL |
11888 | #define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 |
11889 | #define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 |
11890 | #define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 |
11891 | #define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 |
11892 | #define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 |
11893 | #define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc |
11894 | #define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd |
11895 | #define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c |
11896 | #define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f |
11897 | #define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L |
11898 | #define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L |
11899 | #define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L |
11900 | #define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L |
11901 | #define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L |
11902 | #define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L |
11903 | #define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L |
11904 | #define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L |
11905 | #define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L |
11906 | //HUBP3_HUBP_CLK_CNTL |
11907 | #define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 |
11908 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 |
11909 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 |
11910 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc |
11911 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 |
11912 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 |
11913 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 |
11914 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 |
11915 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 |
11916 | #define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c |
11917 | #define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L |
11918 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L |
11919 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L |
11920 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L |
11921 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L |
11922 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L |
11923 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L |
11924 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L |
11925 | #define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L |
11926 | #define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L |
11927 | //HUBP3_DCHUBP_VMPG_CONFIG |
11928 | #define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 |
11929 | #define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L |
11930 | //HUBP3_HUBPREQ_DEBUG_DB |
11931 | #define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 |
11932 | #define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL |
11933 | //HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK |
11934 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 |
11935 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 |
11936 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc |
11937 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 |
11938 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c |
11939 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L |
11940 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L |
11941 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L |
11942 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L |
11943 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L |
11944 | //HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK |
11945 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 |
11946 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 |
11947 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 |
11948 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc |
11949 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 |
11950 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L |
11951 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L |
11952 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L |
11953 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L |
11954 | #define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L |
11955 | |
11956 | |
11957 | // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec |
11958 | //HUBPREQ3_DCSURF_SURFACE_PITCH |
11959 | #define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 |
11960 | #define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 |
11961 | #define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL |
11962 | #define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L |
11963 | //HUBPREQ3_DCSURF_SURFACE_PITCH_C |
11964 | #define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 |
11965 | #define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 |
11966 | #define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL |
11967 | #define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L |
11968 | //HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS |
11969 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 |
11970 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11971 | //HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH |
11972 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11973 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11974 | //HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C |
11975 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
11976 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11977 | //HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C |
11978 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11979 | #define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11980 | //HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS |
11981 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 |
11982 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11983 | //HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH |
11984 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11985 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11986 | //HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C |
11987 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 |
11988 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
11989 | //HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C |
11990 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
11991 | #define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
11992 | //HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS |
11993 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
11994 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
11995 | //HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH |
11996 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
11997 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
11998 | //HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C |
11999 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
12000 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
12001 | //HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C |
12002 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
12003 | #define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
12004 | //HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS |
12005 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 |
12006 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
12007 | //HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH |
12008 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
12009 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
12010 | //HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C |
12011 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 |
12012 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL |
12013 | //HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C |
12014 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 |
12015 | #define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
12016 | //HUBPREQ3_DCSURF_SURFACE_CONTROL |
12017 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 |
12018 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 |
12019 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 |
12020 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 |
12021 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa |
12022 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd |
12023 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L |
12024 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L |
12025 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L |
12026 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L |
12027 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L |
12028 | #define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L |
12029 | //HUBPREQ3_DCSURF_FLIP_CONTROL |
12030 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 |
12031 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 |
12032 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 |
12033 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc |
12034 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 |
12035 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 |
12036 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 |
12037 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 |
12038 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT 0x1e |
12039 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x1f |
12040 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L |
12041 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L |
12042 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L |
12043 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L |
12044 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L |
12045 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L |
12046 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L |
12047 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L |
12048 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK 0x40000000L |
12049 | #define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x80000000L |
12050 | //HUBPREQ3_DCSURF_FLIP_CONTROL2 |
12051 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 |
12052 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xc |
12053 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT 0xd |
12054 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL |
12055 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00001000L |
12056 | #define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK 0x00002000L |
12057 | //HUBPREQ3_DCSURF_FRAME_PACING_CONTROL |
12058 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT 0x0 |
12059 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT 0x1 |
12060 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT 0x8 |
12061 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT 0x18 |
12062 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK 0x00000001L |
12063 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK 0x00000002L |
12064 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK 0x00000100L |
12065 | #define HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK 0x07000000L |
12066 | //HUBPREQ3_DCSURF_FRAME_PACING_TIME |
12067 | #define HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT 0x0 |
12068 | #define HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK 0xFFFFFFFFL |
12069 | //HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT |
12070 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 |
12071 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 |
12072 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 |
12073 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 |
12074 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 |
12075 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 |
12076 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 |
12077 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 |
12078 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 |
12079 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 |
12080 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L |
12081 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L |
12082 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L |
12083 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L |
12084 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L |
12085 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L |
12086 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L |
12087 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L |
12088 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L |
12089 | #define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L |
12090 | //HUBPREQ3_DCSURF_SURFACE_INUSE |
12091 | #define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 |
12092 | #define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
12093 | //HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH |
12094 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
12095 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
12096 | //HUBPREQ3_DCSURF_SURFACE_INUSE_C |
12097 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 |
12098 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
12099 | //HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C |
12100 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
12101 | #define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
12102 | //HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE |
12103 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 |
12104 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL |
12105 | //HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH |
12106 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 |
12107 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL |
12108 | //HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C |
12109 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 |
12110 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL |
12111 | //HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C |
12112 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 |
12113 | #define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL |
12114 | //HUBPREQ3_DCN_EXPANSION_MODE |
12115 | #define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 |
12116 | #define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 |
12117 | #define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 |
12118 | #define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 |
12119 | #define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L |
12120 | #define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL |
12121 | #define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L |
12122 | #define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L |
12123 | //HUBPREQ3_DCN_TTU_QOS_WM |
12124 | #define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 |
12125 | #define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 |
12126 | #define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL |
12127 | #define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L |
12128 | //HUBPREQ3_DCN_GLOBAL_TTU_CNTL |
12129 | #define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 |
12130 | #define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c |
12131 | #define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL |
12132 | #define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L |
12133 | //HUBPREQ3_DCN_SURF0_TTU_CNTL0 |
12134 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
12135 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
12136 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
12137 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
12138 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
12139 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
12140 | //HUBPREQ3_DCN_SURF0_TTU_CNTL1 |
12141 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
12142 | #define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
12143 | //HUBPREQ3_DCN_SURF1_TTU_CNTL0 |
12144 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
12145 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
12146 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
12147 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
12148 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
12149 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
12150 | //HUBPREQ3_DCN_SURF1_TTU_CNTL1 |
12151 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
12152 | #define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
12153 | //HUBPREQ3_DCN_CUR0_TTU_CNTL0 |
12154 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 |
12155 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 |
12156 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c |
12157 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL |
12158 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L |
12159 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L |
12160 | //HUBPREQ3_DCN_CUR0_TTU_CNTL1 |
12161 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 |
12162 | #define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL |
12163 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB |
12164 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT 0x0 |
12165 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK 0xFFFFFFFFL |
12166 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB |
12167 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT 0x0 |
12168 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK 0x0000000FL |
12169 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB |
12170 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT 0x0 |
12171 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK 0xFFFFFFFFL |
12172 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB |
12173 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT 0x0 |
12174 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK 0x0000000FL |
12175 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
12176 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT 0x0 |
12177 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
12178 | //HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
12179 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT 0x0 |
12180 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT 0x1c |
12181 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT 0x1d |
12182 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
12183 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK 0x10000000L |
12184 | #define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK 0x20000000L |
12185 | //HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB |
12186 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT 0x0 |
12187 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
12188 | //HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB |
12189 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT 0x0 |
12190 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT 0x1c |
12191 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT 0x1d |
12192 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT 0x1e |
12193 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK 0x0000000FL |
12194 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK 0x10000000L |
12195 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK 0x20000000L |
12196 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK 0x40000000L |
12197 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB |
12198 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT 0x0 |
12199 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK 0xFFFFFFFFL |
12200 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB |
12201 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT 0x0 |
12202 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK 0xFFFFFFFFL |
12203 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB |
12204 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT 0x0 |
12205 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK 0xFFFFFFFFL |
12206 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB |
12207 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT 0x0 |
12208 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK 0x0000000FL |
12209 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB |
12210 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT 0x0 |
12211 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK 0xFFFFFFFFL |
12212 | //HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB |
12213 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT 0x0 |
12214 | #define HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK 0x0000000FL |
12215 | //HUBPREQ3_DCN_VM_CONTEXT0_STATUS |
12216 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT 0x0 |
12217 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT 0x18 |
12218 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT 0x1e |
12219 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT 0x1f |
12220 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK 0x0000FFFFL |
12221 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK 0x0F000000L |
12222 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK 0x40000000L |
12223 | #define HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK 0x80000000L |
12224 | //HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB |
12225 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT 0x0 |
12226 | #define HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL |
12227 | //HUBPREQ3_DCN_VM_CONTEXT0_CNTL |
12228 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12229 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 |
12230 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
12231 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc |
12232 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd |
12233 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12234 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12235 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12236 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L |
12237 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
12238 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L |
12239 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L |
12240 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12241 | #define HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12242 | //HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL |
12243 | #define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
12244 | #define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
12245 | #define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
12246 | #define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
12247 | //HUBPREQ3_BLANK_OFFSET_0 |
12248 | #define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 |
12249 | #define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 |
12250 | #define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL |
12251 | #define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L |
12252 | //HUBPREQ3_BLANK_OFFSET_1 |
12253 | #define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 |
12254 | #define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL |
12255 | //HUBPREQ3_DST_DIMENSIONS |
12256 | #define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 |
12257 | #define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL |
12258 | //HUBPREQ3_DST_AFTER_SCALER |
12259 | #define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 |
12260 | #define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 |
12261 | #define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL |
12262 | #define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L |
12263 | //HUBPREQ3_PREFETCH_SETTINS |
12264 | #define HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT 0x0 |
12265 | #define HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT 0x18 |
12266 | #define HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK 0x001FFFFFL |
12267 | #define HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK 0xFF000000L |
12268 | //HUBPREQ3_PREFETCH_SETTINS_C |
12269 | #define HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT 0x0 |
12270 | #define HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK 0x001FFFFFL |
12271 | //HUBPREQ3_VBLANK_PARAMETERS_0 |
12272 | #define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 |
12273 | #define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 |
12274 | #define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000001FL |
12275 | #define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L |
12276 | //HUBPREQ3_VBLANK_PARAMETERS_1 |
12277 | #define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 |
12278 | #define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL |
12279 | //HUBPREQ3_VBLANK_PARAMETERS_2 |
12280 | #define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 |
12281 | #define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL |
12282 | //HUBPREQ3_VBLANK_PARAMETERS_3 |
12283 | #define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 |
12284 | #define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL |
12285 | //HUBPREQ3_VBLANK_PARAMETERS_4 |
12286 | #define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 |
12287 | #define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL |
12288 | //HUBPREQ3_NOM_PARAMETERS_0 |
12289 | #define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 |
12290 | #define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL |
12291 | //HUBPREQ3_NOM_PARAMETERS_1 |
12292 | #define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 |
12293 | #define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL |
12294 | //HUBPREQ3_NOM_PARAMETERS_2 |
12295 | #define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 |
12296 | #define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL |
12297 | //HUBPREQ3_NOM_PARAMETERS_3 |
12298 | #define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 |
12299 | #define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL |
12300 | //HUBPREQ3_NOM_PARAMETERS_4 |
12301 | #define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 |
12302 | #define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL |
12303 | //HUBPREQ3_NOM_PARAMETERS_5 |
12304 | #define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 |
12305 | #define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL |
12306 | //HUBPREQ3_NOM_PARAMETERS_6 |
12307 | #define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 |
12308 | #define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL |
12309 | //HUBPREQ3_NOM_PARAMETERS_7 |
12310 | #define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 |
12311 | #define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL |
12312 | //HUBPREQ3_PER_LINE_DELIVERY_PRE |
12313 | #define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 |
12314 | #define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 |
12315 | #define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL |
12316 | #define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L |
12317 | //HUBPREQ3_PER_LINE_DELIVERY |
12318 | #define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 |
12319 | #define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 |
12320 | #define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL |
12321 | #define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L |
12322 | //HUBPREQ3_CURSOR_SETTINS |
12323 | #define HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 |
12324 | #define HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 |
12325 | #define HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL |
12326 | #define HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L |
12327 | //HUBPREQ3_REF_FREQ_TO_PIX_FREQ |
12328 | #define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 |
12329 | #define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL |
12330 | //HUBPREQ3_HUBPREQ_MEM_PWR_CTRL |
12331 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 |
12332 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 |
12333 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 |
12334 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 |
12335 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 |
12336 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa |
12337 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT 0x10 |
12338 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT 0x11 |
12339 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT 0x14 |
12340 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT 0x15 |
12341 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT 0x18 |
12342 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L |
12343 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L |
12344 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L |
12345 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L |
12346 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L |
12347 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L |
12348 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK 0x00010000L |
12349 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK 0x00020000L |
12350 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK 0x00100000L |
12351 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK 0x00200000L |
12352 | #define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK 0x01000000L |
12353 | //HUBPREQ3_HUBPREQ_MEM_PWR_STATUS |
12354 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 |
12355 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 |
12356 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 |
12357 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L |
12358 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL |
12359 | #define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L |
12360 | |
12361 | |
12362 | // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec |
12363 | //HUBPRET3_HUBPRET_CONTROL |
12364 | #define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 |
12365 | #define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc |
12366 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 |
12367 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 |
12368 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 |
12369 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 |
12370 | #define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 |
12371 | #define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL |
12372 | #define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L |
12373 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L |
12374 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L |
12375 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L |
12376 | #define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L |
12377 | #define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L |
12378 | //HUBPRET3_HUBPRET_MEM_PWR_CTRL |
12379 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 |
12380 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 |
12381 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 |
12382 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT 0x8 |
12383 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L |
12384 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L |
12385 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L |
12386 | #define HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK 0xFFFFFF00L |
12387 | //HUBPRET3_HUBPRET_MEM_PWR_STATUS |
12388 | #define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 |
12389 | #define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L |
12390 | //HUBPRET3_HUBPRET_READ_LINE_CTRL0 |
12391 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 |
12392 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 |
12393 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL |
12394 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L |
12395 | //HUBPRET3_HUBPRET_READ_LINE_CTRL1 |
12396 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 |
12397 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 |
12398 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL |
12399 | #define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L |
12400 | //HUBPRET3_HUBPRET_READ_LINE0 |
12401 | #define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 |
12402 | #define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 |
12403 | #define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL |
12404 | #define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L |
12405 | //HUBPRET3_HUBPRET_READ_LINE1 |
12406 | #define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 |
12407 | #define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 |
12408 | #define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL |
12409 | #define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L |
12410 | //HUBPRET3_HUBPRET_INTERRUPT |
12411 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 |
12412 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 |
12413 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 |
12414 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 |
12415 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 |
12416 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 |
12417 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 |
12418 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 |
12419 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa |
12420 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc |
12421 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd |
12422 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe |
12423 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 |
12424 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 |
12425 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 |
12426 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L |
12427 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L |
12428 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L |
12429 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L |
12430 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L |
12431 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L |
12432 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L |
12433 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L |
12434 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L |
12435 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L |
12436 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L |
12437 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L |
12438 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L |
12439 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L |
12440 | #define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L |
12441 | //HUBPRET3_HUBPRET_READ_LINE_VALUE |
12442 | #define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 |
12443 | #define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 |
12444 | #define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL |
12445 | #define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L |
12446 | //HUBPRET3_HUBPRET_READ_LINE_STATUS |
12447 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 |
12448 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 |
12449 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 |
12450 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 |
12451 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa |
12452 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L |
12453 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L |
12454 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L |
12455 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L |
12456 | #define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L |
12457 | |
12458 | |
12459 | // addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec |
12460 | //CURSOR3_CURSOR_CONTROL |
12461 | #define CURSOR3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 |
12462 | #define CURSOR3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
12463 | #define CURSOR3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd |
12464 | #define CURSOR3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe |
12465 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 |
12466 | #define CURSOR3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 |
12467 | #define CURSOR3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 |
12468 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e |
12469 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f |
12470 | #define CURSOR3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L |
12471 | #define CURSOR3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000300L |
12472 | #define CURSOR3_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L |
12473 | #define CURSOR3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L |
12474 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L |
12475 | #define CURSOR3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L |
12476 | #define CURSOR3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L |
12477 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L |
12478 | #define CURSOR3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L |
12479 | //CURSOR3_CURSOR_SURFACE_ADDRESS |
12480 | #define CURSOR3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
12481 | #define CURSOR3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL |
12482 | //CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH |
12483 | #define CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
12484 | #define CURSOR3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL |
12485 | //CURSOR3_CURSOR_SIZE |
12486 | #define CURSOR3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
12487 | #define CURSOR3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
12488 | #define CURSOR3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL |
12489 | #define CURSOR3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L |
12490 | //CURSOR3_CURSOR_POSITION |
12491 | #define CURSOR3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
12492 | #define CURSOR3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
12493 | #define CURSOR3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL |
12494 | #define CURSOR3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L |
12495 | //CURSOR3_CURSOR_HOT_SPOT |
12496 | #define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
12497 | #define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
12498 | #define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL |
12499 | #define CURSOR3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L |
12500 | //CURSOR3_CURSOR_STEREO_CONTROL |
12501 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
12502 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
12503 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 |
12504 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L |
12505 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L |
12506 | #define CURSOR3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L |
12507 | //CURSOR3_CURSOR_DST_OFFSET |
12508 | #define CURSOR3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 |
12509 | #define CURSOR3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL |
12510 | //CURSOR3_CURSOR_MEM_PWR_CTRL |
12511 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 |
12512 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 |
12513 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 |
12514 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L |
12515 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L |
12516 | #define CURSOR3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L |
12517 | //CURSOR3_CURSOR_MEM_PWR_STATUS |
12518 | #define CURSOR3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 |
12519 | #define CURSOR3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L |
12520 | |
12521 | |
12522 | // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
12523 | //DC_PERFMON11_PERFCOUNTER_CNTL |
12524 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
12525 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
12526 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
12527 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
12528 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
12529 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
12530 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
12531 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
12532 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
12533 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
12534 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
12535 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
12536 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
12537 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
12538 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
12539 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
12540 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
12541 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
12542 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
12543 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
12544 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
12545 | #define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
12546 | //DC_PERFMON11_PERFCOUNTER_CNTL2 |
12547 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
12548 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
12549 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
12550 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
12551 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
12552 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
12553 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
12554 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
12555 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
12556 | #define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
12557 | //DC_PERFMON11_PERFCOUNTER_STATE |
12558 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
12559 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
12560 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
12561 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
12562 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
12563 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
12564 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
12565 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
12566 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
12567 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
12568 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
12569 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
12570 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
12571 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
12572 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
12573 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
12574 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
12575 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
12576 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
12577 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
12578 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
12579 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
12580 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
12581 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
12582 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
12583 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
12584 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
12585 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
12586 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
12587 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
12588 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
12589 | #define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
12590 | //DC_PERFMON11_PERFMON_CNTL |
12591 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
12592 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
12593 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
12594 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
12595 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
12596 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
12597 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
12598 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
12599 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
12600 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
12601 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
12602 | #define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
12603 | //DC_PERFMON11_PERFMON_CNTL2 |
12604 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
12605 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
12606 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
12607 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
12608 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
12609 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
12610 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
12611 | #define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
12612 | //DC_PERFMON11_PERFMON_CVALUE_INT_MISC |
12613 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
12614 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
12615 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
12616 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
12617 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
12618 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
12619 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
12620 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
12621 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
12622 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
12623 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
12624 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
12625 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
12626 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
12627 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
12628 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
12629 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
12630 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
12631 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
12632 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
12633 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
12634 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
12635 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
12636 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
12637 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
12638 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
12639 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
12640 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
12641 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
12642 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
12643 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
12644 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
12645 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
12646 | #define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
12647 | //DC_PERFMON11_PERFMON_CVALUE_LOW |
12648 | #define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
12649 | #define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
12650 | //DC_PERFMON11_PERFMON_HI |
12651 | #define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
12652 | #define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
12653 | #define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
12654 | #define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
12655 | //DC_PERFMON11_PERFMON_LOW |
12656 | #define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
12657 | #define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
12658 | |
12659 | |
12660 | // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec |
12661 | //DPP_TOP0_DPP_CONTROL |
12662 | #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 |
12663 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 |
12664 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa |
12665 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc |
12666 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 |
12667 | #define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 |
12668 | #define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 |
12669 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 |
12670 | #define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c |
12671 | #define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L |
12672 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L |
12673 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L |
12674 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L |
12675 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L |
12676 | #define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L |
12677 | #define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L |
12678 | #define DPP_TOP0_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L |
12679 | #define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L |
12680 | //DPP_TOP0_DPP_SOFT_RESET |
12681 | #define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 |
12682 | #define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 |
12683 | #define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 |
12684 | #define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc |
12685 | #define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L |
12686 | #define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L |
12687 | #define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L |
12688 | #define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L |
12689 | //DPP_TOP0_DPP_CRC_VAL_R_G |
12690 | #define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 |
12691 | #define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 |
12692 | #define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL |
12693 | #define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L |
12694 | //DPP_TOP0_DPP_CRC_VAL_B_A |
12695 | #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 |
12696 | #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 |
12697 | #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL |
12698 | #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L |
12699 | //DPP_TOP0_DPP_CRC_CTRL |
12700 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 |
12701 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 |
12702 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 |
12703 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 |
12704 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 |
12705 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 |
12706 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 |
12707 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa |
12708 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc |
12709 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf |
12710 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 |
12711 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L |
12712 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L |
12713 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L |
12714 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L |
12715 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L |
12716 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L |
12717 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L |
12718 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L |
12719 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L |
12720 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L |
12721 | #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L |
12722 | //DPP_TOP0_HOST_READ_CONTROL |
12723 | #define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 |
12724 | #define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL |
12725 | |
12726 | |
12727 | // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec |
12728 | //CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT |
12729 | #define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
12730 | #define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
12731 | //CNVC_CFG0_FORMAT_CONTROL |
12732 | #define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 |
12733 | #define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 |
12734 | #define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 |
12735 | #define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc |
12736 | #define CNVC_CFG0_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 |
12737 | #define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 |
12738 | #define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L |
12739 | #define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L |
12740 | #define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L |
12741 | #define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L |
12742 | #define CNVC_CFG0_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L |
12743 | #define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L |
12744 | //CNVC_CFG0_FCNV_FP_SCALE_BIAS |
12745 | #define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 |
12746 | #define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 |
12747 | #define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL |
12748 | #define CNVC_CFG0_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L |
12749 | //CNVC_CFG0_DENORM_CONTROL |
12750 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 |
12751 | #define CNVC_CFG0_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf |
12752 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 |
12753 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f |
12754 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL |
12755 | #define CNVC_CFG0_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L |
12756 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L |
12757 | #define CNVC_CFG0_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L |
12758 | //CNVC_CFG0_COLOR_KEYER_CONTROL |
12759 | #define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 |
12760 | #define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 |
12761 | #define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L |
12762 | #define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L |
12763 | //CNVC_CFG0_COLOR_KEYER_ALPHA |
12764 | #define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 |
12765 | #define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 |
12766 | #define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL |
12767 | #define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L |
12768 | //CNVC_CFG0_COLOR_KEYER_RED |
12769 | #define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 |
12770 | #define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 |
12771 | #define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL |
12772 | #define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L |
12773 | //CNVC_CFG0_COLOR_KEYER_GREEN |
12774 | #define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 |
12775 | #define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 |
12776 | #define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL |
12777 | #define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L |
12778 | //CNVC_CFG0_COLOR_KEYER_BLUE |
12779 | #define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 |
12780 | #define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 |
12781 | #define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL |
12782 | #define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L |
12783 | |
12784 | |
12785 | // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec |
12786 | //CNVC_CUR0_CURSOR0_CONTROL |
12787 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 |
12788 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 |
12789 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 |
12790 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 |
12791 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 |
12792 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 |
12793 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 |
12794 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L |
12795 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L |
12796 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L |
12797 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L |
12798 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L |
12799 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L |
12800 | #define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L |
12801 | //CNVC_CUR0_CURSOR0_COLOR0 |
12802 | #define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 |
12803 | #define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL |
12804 | //CNVC_CUR0_CURSOR0_COLOR1 |
12805 | #define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 |
12806 | #define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL |
12807 | //CNVC_CUR0_CURSOR0_FP_SCALE_BIAS |
12808 | #define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 |
12809 | #define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 |
12810 | #define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL |
12811 | #define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L |
12812 | |
12813 | |
12814 | // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec |
12815 | //DSCL0_SCL_COEF_RAM_TAP_SELECT |
12816 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
12817 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 |
12818 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
12819 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L |
12820 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L |
12821 | #define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L |
12822 | //DSCL0_SCL_COEF_RAM_TAP_DATA |
12823 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
12824 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
12825 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
12826 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
12827 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
12828 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
12829 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
12830 | #define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
12831 | //DSCL0_SCL_MODE |
12832 | #define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 |
12833 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 |
12834 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc |
12835 | #define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 |
12836 | #define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 |
12837 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 |
12838 | #define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L |
12839 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L |
12840 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L |
12841 | #define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L |
12842 | #define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L |
12843 | #define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L |
12844 | //DSCL0_SCL_TAP_CONTROL |
12845 | #define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 |
12846 | #define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 |
12847 | #define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 |
12848 | #define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc |
12849 | #define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L |
12850 | #define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L |
12851 | #define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L |
12852 | #define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L |
12853 | //DSCL0_DSCL_CONTROL |
12854 | #define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
12855 | #define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L |
12856 | //DSCL0_DSCL_2TAP_CONTROL |
12857 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 |
12858 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 |
12859 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 |
12860 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 |
12861 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 |
12862 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 |
12863 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L |
12864 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L |
12865 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L |
12866 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L |
12867 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L |
12868 | #define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L |
12869 | //DSCL0_SCL_MANUAL_REPLICATE_CONTROL |
12870 | #define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
12871 | #define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
12872 | #define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL |
12873 | #define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L |
12874 | //DSCL0_SCL_HORZ_FILTER_SCALE_RATIO |
12875 | #define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
12876 | #define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL |
12877 | //DSCL0_SCL_HORZ_FILTER_INIT |
12878 | #define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
12879 | #define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
12880 | #define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL |
12881 | #define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L |
12882 | //DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C |
12883 | #define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 |
12884 | #define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL |
12885 | //DSCL0_SCL_HORZ_FILTER_INIT_C |
12886 | #define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 |
12887 | #define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 |
12888 | #define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL |
12889 | #define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L |
12890 | //DSCL0_SCL_VERT_FILTER_SCALE_RATIO |
12891 | #define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
12892 | #define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL |
12893 | //DSCL0_SCL_VERT_FILTER_INIT |
12894 | #define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
12895 | #define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
12896 | #define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL |
12897 | #define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L |
12898 | //DSCL0_SCL_VERT_FILTER_INIT_BOT |
12899 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
12900 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
12901 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL |
12902 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L |
12903 | //DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C |
12904 | #define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 |
12905 | #define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL |
12906 | //DSCL0_SCL_VERT_FILTER_INIT_C |
12907 | #define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 |
12908 | #define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 |
12909 | #define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL |
12910 | #define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L |
12911 | //DSCL0_SCL_VERT_FILTER_INIT_BOT_C |
12912 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 |
12913 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 |
12914 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL |
12915 | #define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L |
12916 | //DSCL0_SCL_BLACK_OFFSET |
12917 | #define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 |
12918 | #define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 |
12919 | #define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL |
12920 | #define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L |
12921 | //DSCL0_DSCL_UPDATE |
12922 | #define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
12923 | #define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L |
12924 | //DSCL0_DSCL_AUTOCAL |
12925 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 |
12926 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 |
12927 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc |
12928 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L |
12929 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L |
12930 | #define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L |
12931 | //DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT |
12932 | #define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
12933 | #define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
12934 | #define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL |
12935 | #define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L |
12936 | //DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM |
12937 | #define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
12938 | #define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
12939 | #define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL |
12940 | #define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L |
12941 | //DSCL0_OTG_H_BLANK |
12942 | #define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 |
12943 | #define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 |
12944 | #define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL |
12945 | #define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L |
12946 | //DSCL0_OTG_V_BLANK |
12947 | #define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 |
12948 | #define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 |
12949 | #define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL |
12950 | #define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L |
12951 | //DSCL0_RECOUT_START |
12952 | #define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 |
12953 | #define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 |
12954 | #define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL |
12955 | #define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L |
12956 | //DSCL0_RECOUT_SIZE |
12957 | #define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 |
12958 | #define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 |
12959 | #define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL |
12960 | #define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L |
12961 | //DSCL0_MPC_SIZE |
12962 | #define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 |
12963 | #define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 |
12964 | #define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL |
12965 | #define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L |
12966 | //DSCL0_LB_DATA_FORMAT |
12967 | #define DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
12968 | #define DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 |
12969 | #define DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc |
12970 | #define DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 |
12971 | #define DSCL0_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 |
12972 | #define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 |
12973 | #define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
12974 | #define DSCL0_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L |
12975 | #define DSCL0_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L |
12976 | #define DSCL0_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L |
12977 | #define DSCL0_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L |
12978 | #define DSCL0_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L |
12979 | #define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L |
12980 | #define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L |
12981 | //DSCL0_LB_MEMORY_CTRL |
12982 | #define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 |
12983 | #define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 |
12984 | #define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
12985 | #define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 |
12986 | #define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L |
12987 | #define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L |
12988 | #define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L |
12989 | #define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L |
12990 | //DSCL0_LB_V_COUNTER |
12991 | #define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
12992 | #define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 |
12993 | #define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL |
12994 | #define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L |
12995 | //DSCL0_DSCL_MEM_PWR_CTRL |
12996 | #define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 |
12997 | #define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 |
12998 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 |
12999 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 |
13000 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 |
13001 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa |
13002 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc |
13003 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe |
13004 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 |
13005 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 |
13006 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 |
13007 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 |
13008 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 |
13009 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a |
13010 | #define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L |
13011 | #define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L |
13012 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L |
13013 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L |
13014 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L |
13015 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L |
13016 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L |
13017 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L |
13018 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L |
13019 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L |
13020 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L |
13021 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L |
13022 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L |
13023 | #define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L |
13024 | //DSCL0_DSCL_MEM_PWR_STATUS |
13025 | #define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 |
13026 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 |
13027 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 |
13028 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 |
13029 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 |
13030 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa |
13031 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc |
13032 | #define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L |
13033 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL |
13034 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L |
13035 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L |
13036 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L |
13037 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L |
13038 | #define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L |
13039 | //DSCL0_OBUF_CONTROL |
13040 | #define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 |
13041 | #define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 |
13042 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 |
13043 | #define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc |
13044 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 |
13045 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 |
13046 | #define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c |
13047 | #define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L |
13048 | #define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L |
13049 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L |
13050 | #define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L |
13051 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L |
13052 | #define DSCL0_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L |
13053 | #define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L |
13054 | //DSCL0_OBUF_MEM_PWR_CTRL |
13055 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 |
13056 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 |
13057 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 |
13058 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L |
13059 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L |
13060 | #define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L |
13061 | |
13062 | |
13063 | // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec |
13064 | //CM0_CM_CONTROL |
13065 | #define CM0_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 |
13066 | #define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 |
13067 | #define CM0_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L |
13068 | #define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L |
13069 | //CM0_CM_COMA_C11_C12 |
13070 | #define CM0_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 |
13071 | #define CM0_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 |
13072 | #define CM0_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL |
13073 | #define CM0_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L |
13074 | //CM0_CM_COMA_C13_C14 |
13075 | #define CM0_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 |
13076 | #define CM0_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 |
13077 | #define CM0_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL |
13078 | #define CM0_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L |
13079 | //CM0_CM_COMA_C21_C22 |
13080 | #define CM0_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 |
13081 | #define CM0_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 |
13082 | #define CM0_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL |
13083 | #define CM0_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L |
13084 | //CM0_CM_COMA_C23_C24 |
13085 | #define CM0_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 |
13086 | #define CM0_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 |
13087 | #define CM0_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL |
13088 | #define CM0_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L |
13089 | //CM0_CM_COMA_C31_C32 |
13090 | #define CM0_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 |
13091 | #define CM0_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 |
13092 | #define CM0_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL |
13093 | #define CM0_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L |
13094 | //CM0_CM_COMA_C33_C34 |
13095 | #define CM0_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 |
13096 | #define CM0_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 |
13097 | #define CM0_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL |
13098 | #define CM0_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L |
13099 | //CM0_CM_COMB_C11_C12 |
13100 | #define CM0_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 |
13101 | #define CM0_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 |
13102 | #define CM0_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL |
13103 | #define CM0_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L |
13104 | //CM0_CM_COMB_C13_C14 |
13105 | #define CM0_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 |
13106 | #define CM0_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 |
13107 | #define CM0_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL |
13108 | #define CM0_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L |
13109 | //CM0_CM_COMB_C21_C22 |
13110 | #define CM0_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 |
13111 | #define CM0_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 |
13112 | #define CM0_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL |
13113 | #define CM0_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L |
13114 | //CM0_CM_COMB_C23_C24 |
13115 | #define CM0_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 |
13116 | #define CM0_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 |
13117 | #define CM0_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL |
13118 | #define CM0_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L |
13119 | //CM0_CM_COMB_C31_C32 |
13120 | #define CM0_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 |
13121 | #define CM0_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 |
13122 | #define CM0_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL |
13123 | #define CM0_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L |
13124 | //CM0_CM_COMB_C33_C34 |
13125 | #define CM0_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 |
13126 | #define CM0_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 |
13127 | #define CM0_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL |
13128 | #define CM0_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L |
13129 | //CM0_CM_IGAM_CONTROL |
13130 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 |
13131 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 |
13132 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 |
13133 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 |
13134 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 |
13135 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 |
13136 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd |
13137 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 |
13138 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 |
13139 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 |
13140 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 |
13141 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 |
13142 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 |
13143 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a |
13144 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L |
13145 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L |
13146 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L |
13147 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L |
13148 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L |
13149 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L |
13150 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L |
13151 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L |
13152 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L |
13153 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L |
13154 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L |
13155 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L |
13156 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L |
13157 | #define CM0_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L |
13158 | //CM0_CM_IGAM_LUT_RW_CONTROL |
13159 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 |
13160 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 |
13161 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 |
13162 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc |
13163 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 |
13164 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L |
13165 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L |
13166 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L |
13167 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L |
13168 | #define CM0_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L |
13169 | //CM0_CM_IGAM_LUT_RW_INDEX |
13170 | #define CM0_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 |
13171 | #define CM0_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL |
13172 | //CM0_CM_IGAM_LUT_SEQ_COLOR |
13173 | #define CM0_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 |
13174 | #define CM0_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL |
13175 | //CM0_CM_IGAM_LUT_30_COLOR |
13176 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 |
13177 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa |
13178 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 |
13179 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL |
13180 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L |
13181 | #define CM0_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L |
13182 | //CM0_CM_IGAM_LUT_PWL_DATA |
13183 | #define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 |
13184 | #define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 |
13185 | #define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL |
13186 | #define CM0_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L |
13187 | //CM0_CM_IGAM_LUT_AUTOFILL |
13188 | #define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 |
13189 | #define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 |
13190 | #define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L |
13191 | #define CM0_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L |
13192 | //CM0_CM_IGAM_LUT_BW_OFFSET_BLUE |
13193 | #define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
13194 | #define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 |
13195 | #define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL |
13196 | #define CM0_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L |
13197 | //CM0_CM_IGAM_LUT_BW_OFFSET_GREEN |
13198 | #define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
13199 | #define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 |
13200 | #define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL |
13201 | #define CM0_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L |
13202 | //CM0_CM_IGAM_LUT_BW_OFFSET_RED |
13203 | #define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
13204 | #define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 |
13205 | #define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL |
13206 | #define CM0_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L |
13207 | //CM0_CM_ICSC_CONTROL |
13208 | #define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 |
13209 | #define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L |
13210 | //CM0_CM_ICSC_C11_C12 |
13211 | #define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 |
13212 | #define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 |
13213 | #define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL |
13214 | #define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L |
13215 | //CM0_CM_ICSC_C13_C14 |
13216 | #define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 |
13217 | #define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 |
13218 | #define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL |
13219 | #define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L |
13220 | //CM0_CM_ICSC_C21_C22 |
13221 | #define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 |
13222 | #define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 |
13223 | #define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL |
13224 | #define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L |
13225 | //CM0_CM_ICSC_C23_C24 |
13226 | #define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 |
13227 | #define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 |
13228 | #define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL |
13229 | #define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L |
13230 | //CM0_CM_ICSC_C31_C32 |
13231 | #define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 |
13232 | #define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 |
13233 | #define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL |
13234 | #define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L |
13235 | //CM0_CM_ICSC_C33_C34 |
13236 | #define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 |
13237 | #define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 |
13238 | #define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL |
13239 | #define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L |
13240 | //CM0_CM_GAMUT_REMAP_CONTROL |
13241 | #define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 |
13242 | #define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L |
13243 | //CM0_CM_GAMUT_REMAP_C11_C12 |
13244 | #define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 |
13245 | #define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 |
13246 | #define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL |
13247 | #define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L |
13248 | //CM0_CM_GAMUT_REMAP_C13_C14 |
13249 | #define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 |
13250 | #define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 |
13251 | #define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL |
13252 | #define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L |
13253 | //CM0_CM_GAMUT_REMAP_C21_C22 |
13254 | #define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 |
13255 | #define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 |
13256 | #define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL |
13257 | #define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L |
13258 | //CM0_CM_GAMUT_REMAP_C23_C24 |
13259 | #define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 |
13260 | #define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 |
13261 | #define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL |
13262 | #define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L |
13263 | //CM0_CM_GAMUT_REMAP_C31_C32 |
13264 | #define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 |
13265 | #define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 |
13266 | #define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL |
13267 | #define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L |
13268 | //CM0_CM_GAMUT_REMAP_C33_C34 |
13269 | #define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 |
13270 | #define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 |
13271 | #define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL |
13272 | #define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L |
13273 | //CM0_CM_OCSC_CONTROL |
13274 | #define CM0_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 |
13275 | #define CM0_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L |
13276 | //CM0_CM_OCSC_C11_C12 |
13277 | #define CM0_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 |
13278 | #define CM0_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 |
13279 | #define CM0_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL |
13280 | #define CM0_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L |
13281 | //CM0_CM_OCSC_C13_C14 |
13282 | #define CM0_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 |
13283 | #define CM0_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 |
13284 | #define CM0_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL |
13285 | #define CM0_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L |
13286 | //CM0_CM_OCSC_C21_C22 |
13287 | #define CM0_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 |
13288 | #define CM0_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 |
13289 | #define CM0_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL |
13290 | #define CM0_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L |
13291 | //CM0_CM_OCSC_C23_C24 |
13292 | #define CM0_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 |
13293 | #define CM0_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 |
13294 | #define CM0_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL |
13295 | #define CM0_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L |
13296 | //CM0_CM_OCSC_C31_C32 |
13297 | #define CM0_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 |
13298 | #define CM0_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 |
13299 | #define CM0_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL |
13300 | #define CM0_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L |
13301 | //CM0_CM_OCSC_C33_C34 |
13302 | #define CM0_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 |
13303 | #define CM0_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 |
13304 | #define CM0_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL |
13305 | #define CM0_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L |
13306 | //CM0_CM_BNS_VALUES_R |
13307 | #define CM0_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 |
13308 | #define CM0_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 |
13309 | #define CM0_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL |
13310 | #define CM0_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L |
13311 | //CM0_CM_BNS_VALUES_G |
13312 | #define CM0_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 |
13313 | #define CM0_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 |
13314 | #define CM0_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL |
13315 | #define CM0_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L |
13316 | //CM0_CM_BNS_VALUES_B |
13317 | #define CM0_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 |
13318 | #define CM0_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 |
13319 | #define CM0_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL |
13320 | #define CM0_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L |
13321 | //CM0_CM_DGAM_CONTROL |
13322 | #define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 |
13323 | #define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L |
13324 | //CM0_CM_DGAM_LUT_INDEX |
13325 | #define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 |
13326 | #define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL |
13327 | //CM0_CM_DGAM_LUT_DATA |
13328 | #define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 |
13329 | #define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL |
13330 | //CM0_CM_DGAM_LUT_WRITE_EN_MASK |
13331 | #define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
13332 | #define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 |
13333 | #define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
13334 | #define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L |
13335 | //CM0_CM_DGAM_RAMA_START_CNTL_B |
13336 | #define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
13337 | #define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
13338 | #define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
13339 | #define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
13340 | //CM0_CM_DGAM_RAMA_START_CNTL_G |
13341 | #define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
13342 | #define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
13343 | #define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
13344 | #define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
13345 | //CM0_CM_DGAM_RAMA_START_CNTL_R |
13346 | #define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
13347 | #define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
13348 | #define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
13349 | #define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
13350 | //CM0_CM_DGAM_RAMA_SLOPE_CNTL_B |
13351 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
13352 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
13353 | //CM0_CM_DGAM_RAMA_SLOPE_CNTL_G |
13354 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
13355 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
13356 | //CM0_CM_DGAM_RAMA_SLOPE_CNTL_R |
13357 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
13358 | #define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
13359 | //CM0_CM_DGAM_RAMA_END_CNTL1_B |
13360 | #define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
13361 | #define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
13362 | //CM0_CM_DGAM_RAMA_END_CNTL2_B |
13363 | #define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
13364 | #define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
13365 | #define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
13366 | #define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
13367 | //CM0_CM_DGAM_RAMA_END_CNTL1_G |
13368 | #define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
13369 | #define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
13370 | //CM0_CM_DGAM_RAMA_END_CNTL2_G |
13371 | #define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
13372 | #define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
13373 | #define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
13374 | #define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
13375 | //CM0_CM_DGAM_RAMA_END_CNTL1_R |
13376 | #define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
13377 | #define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
13378 | //CM0_CM_DGAM_RAMA_END_CNTL2_R |
13379 | #define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
13380 | #define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
13381 | #define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
13382 | #define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
13383 | //CM0_CM_DGAM_RAMA_REGION_0_1 |
13384 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
13385 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
13386 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
13387 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
13388 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
13389 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
13390 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
13391 | #define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
13392 | //CM0_CM_DGAM_RAMA_REGION_2_3 |
13393 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
13394 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
13395 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
13396 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
13397 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
13398 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
13399 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
13400 | #define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
13401 | //CM0_CM_DGAM_RAMA_REGION_4_5 |
13402 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
13403 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
13404 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
13405 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
13406 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
13407 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
13408 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
13409 | #define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
13410 | //CM0_CM_DGAM_RAMA_REGION_6_7 |
13411 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
13412 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
13413 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
13414 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
13415 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
13416 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
13417 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
13418 | #define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
13419 | //CM0_CM_DGAM_RAMA_REGION_8_9 |
13420 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
13421 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
13422 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
13423 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
13424 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
13425 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
13426 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
13427 | #define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
13428 | //CM0_CM_DGAM_RAMA_REGION_10_11 |
13429 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
13430 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
13431 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
13432 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
13433 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
13434 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
13435 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
13436 | #define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
13437 | //CM0_CM_DGAM_RAMA_REGION_12_13 |
13438 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
13439 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
13440 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
13441 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
13442 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
13443 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
13444 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
13445 | #define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
13446 | //CM0_CM_DGAM_RAMA_REGION_14_15 |
13447 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
13448 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
13449 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
13450 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
13451 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
13452 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
13453 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
13454 | #define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
13455 | //CM0_CM_DGAM_RAMB_START_CNTL_B |
13456 | #define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
13457 | #define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
13458 | #define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
13459 | #define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
13460 | //CM0_CM_DGAM_RAMB_START_CNTL_G |
13461 | #define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
13462 | #define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
13463 | #define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
13464 | #define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
13465 | //CM0_CM_DGAM_RAMB_START_CNTL_R |
13466 | #define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
13467 | #define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
13468 | #define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
13469 | #define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
13470 | //CM0_CM_DGAM_RAMB_SLOPE_CNTL_B |
13471 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
13472 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
13473 | //CM0_CM_DGAM_RAMB_SLOPE_CNTL_G |
13474 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
13475 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
13476 | //CM0_CM_DGAM_RAMB_SLOPE_CNTL_R |
13477 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
13478 | #define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
13479 | //CM0_CM_DGAM_RAMB_END_CNTL1_B |
13480 | #define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
13481 | #define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
13482 | //CM0_CM_DGAM_RAMB_END_CNTL2_B |
13483 | #define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
13484 | #define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
13485 | #define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
13486 | #define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
13487 | //CM0_CM_DGAM_RAMB_END_CNTL1_G |
13488 | #define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
13489 | #define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
13490 | //CM0_CM_DGAM_RAMB_END_CNTL2_G |
13491 | #define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
13492 | #define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
13493 | #define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
13494 | #define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
13495 | //CM0_CM_DGAM_RAMB_END_CNTL1_R |
13496 | #define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
13497 | #define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
13498 | //CM0_CM_DGAM_RAMB_END_CNTL2_R |
13499 | #define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
13500 | #define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
13501 | #define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
13502 | #define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
13503 | //CM0_CM_DGAM_RAMB_REGION_0_1 |
13504 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
13505 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
13506 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
13507 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
13508 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
13509 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
13510 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
13511 | #define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
13512 | //CM0_CM_DGAM_RAMB_REGION_2_3 |
13513 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
13514 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
13515 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
13516 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
13517 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
13518 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
13519 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
13520 | #define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
13521 | //CM0_CM_DGAM_RAMB_REGION_4_5 |
13522 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
13523 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
13524 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
13525 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
13526 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
13527 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
13528 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
13529 | #define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
13530 | //CM0_CM_DGAM_RAMB_REGION_6_7 |
13531 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
13532 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
13533 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
13534 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
13535 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
13536 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
13537 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
13538 | #define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
13539 | //CM0_CM_DGAM_RAMB_REGION_8_9 |
13540 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
13541 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
13542 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
13543 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
13544 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
13545 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
13546 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
13547 | #define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
13548 | //CM0_CM_DGAM_RAMB_REGION_10_11 |
13549 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
13550 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
13551 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
13552 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
13553 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
13554 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
13555 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
13556 | #define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
13557 | //CM0_CM_DGAM_RAMB_REGION_12_13 |
13558 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
13559 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
13560 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
13561 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
13562 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
13563 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
13564 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
13565 | #define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
13566 | //CM0_CM_DGAM_RAMB_REGION_14_15 |
13567 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
13568 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
13569 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
13570 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
13571 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
13572 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
13573 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
13574 | #define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
13575 | //CM0_CM_RGAM_CONTROL |
13576 | #define CM0_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 |
13577 | #define CM0_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L |
13578 | //CM0_CM_RGAM_LUT_INDEX |
13579 | #define CM0_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 |
13580 | #define CM0_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL |
13581 | //CM0_CM_RGAM_LUT_DATA |
13582 | #define CM0_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 |
13583 | #define CM0_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL |
13584 | //CM0_CM_RGAM_LUT_WRITE_EN_MASK |
13585 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
13586 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 |
13587 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 |
13588 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
13589 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L |
13590 | #define CM0_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L |
13591 | //CM0_CM_RGAM_RAMA_START_CNTL_B |
13592 | #define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
13593 | #define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
13594 | #define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
13595 | #define CM0_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
13596 | //CM0_CM_RGAM_RAMA_START_CNTL_G |
13597 | #define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
13598 | #define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
13599 | #define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
13600 | #define CM0_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
13601 | //CM0_CM_RGAM_RAMA_START_CNTL_R |
13602 | #define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
13603 | #define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
13604 | #define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
13605 | #define CM0_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
13606 | //CM0_CM_RGAM_RAMA_SLOPE_CNTL_B |
13607 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
13608 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
13609 | //CM0_CM_RGAM_RAMA_SLOPE_CNTL_G |
13610 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
13611 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
13612 | //CM0_CM_RGAM_RAMA_SLOPE_CNTL_R |
13613 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
13614 | #define CM0_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
13615 | //CM0_CM_RGAM_RAMA_END_CNTL1_B |
13616 | #define CM0_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
13617 | #define CM0_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
13618 | //CM0_CM_RGAM_RAMA_END_CNTL2_B |
13619 | #define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
13620 | #define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
13621 | #define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
13622 | #define CM0_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
13623 | //CM0_CM_RGAM_RAMA_END_CNTL1_G |
13624 | #define CM0_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
13625 | #define CM0_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
13626 | //CM0_CM_RGAM_RAMA_END_CNTL2_G |
13627 | #define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
13628 | #define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
13629 | #define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
13630 | #define CM0_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
13631 | //CM0_CM_RGAM_RAMA_END_CNTL1_R |
13632 | #define CM0_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
13633 | #define CM0_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
13634 | //CM0_CM_RGAM_RAMA_END_CNTL2_R |
13635 | #define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
13636 | #define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
13637 | #define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
13638 | #define CM0_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
13639 | //CM0_CM_RGAM_RAMA_REGION_0_1 |
13640 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
13641 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
13642 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
13643 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
13644 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
13645 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
13646 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
13647 | #define CM0_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
13648 | //CM0_CM_RGAM_RAMA_REGION_2_3 |
13649 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
13650 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
13651 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
13652 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
13653 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
13654 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
13655 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
13656 | #define CM0_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
13657 | //CM0_CM_RGAM_RAMA_REGION_4_5 |
13658 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
13659 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
13660 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
13661 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
13662 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
13663 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
13664 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
13665 | #define CM0_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
13666 | //CM0_CM_RGAM_RAMA_REGION_6_7 |
13667 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
13668 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
13669 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
13670 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
13671 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
13672 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
13673 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
13674 | #define CM0_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
13675 | //CM0_CM_RGAM_RAMA_REGION_8_9 |
13676 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
13677 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
13678 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
13679 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
13680 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
13681 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
13682 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
13683 | #define CM0_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
13684 | //CM0_CM_RGAM_RAMA_REGION_10_11 |
13685 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
13686 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
13687 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
13688 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
13689 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
13690 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
13691 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
13692 | #define CM0_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
13693 | //CM0_CM_RGAM_RAMA_REGION_12_13 |
13694 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
13695 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
13696 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
13697 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
13698 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
13699 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
13700 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
13701 | #define CM0_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
13702 | //CM0_CM_RGAM_RAMA_REGION_14_15 |
13703 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
13704 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
13705 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
13706 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
13707 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
13708 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
13709 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
13710 | #define CM0_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
13711 | //CM0_CM_RGAM_RAMA_REGION_16_17 |
13712 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
13713 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
13714 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
13715 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
13716 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
13717 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
13718 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
13719 | #define CM0_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
13720 | //CM0_CM_RGAM_RAMA_REGION_18_19 |
13721 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
13722 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
13723 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
13724 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
13725 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
13726 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
13727 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
13728 | #define CM0_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
13729 | //CM0_CM_RGAM_RAMA_REGION_20_21 |
13730 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
13731 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
13732 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
13733 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
13734 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
13735 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
13736 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
13737 | #define CM0_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
13738 | //CM0_CM_RGAM_RAMA_REGION_22_23 |
13739 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
13740 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
13741 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
13742 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
13743 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
13744 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
13745 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
13746 | #define CM0_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
13747 | //CM0_CM_RGAM_RAMA_REGION_24_25 |
13748 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
13749 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
13750 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
13751 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
13752 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
13753 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
13754 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
13755 | #define CM0_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
13756 | //CM0_CM_RGAM_RAMA_REGION_26_27 |
13757 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
13758 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
13759 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
13760 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
13761 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
13762 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
13763 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
13764 | #define CM0_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
13765 | //CM0_CM_RGAM_RAMA_REGION_28_29 |
13766 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
13767 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
13768 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
13769 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
13770 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
13771 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
13772 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
13773 | #define CM0_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
13774 | //CM0_CM_RGAM_RAMA_REGION_30_31 |
13775 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
13776 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
13777 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
13778 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
13779 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
13780 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
13781 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
13782 | #define CM0_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
13783 | //CM0_CM_RGAM_RAMA_REGION_32_33 |
13784 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
13785 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
13786 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
13787 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
13788 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
13789 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
13790 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
13791 | #define CM0_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
13792 | //CM0_CM_RGAM_RAMB_START_CNTL_B |
13793 | #define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
13794 | #define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
13795 | #define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
13796 | #define CM0_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
13797 | //CM0_CM_RGAM_RAMB_START_CNTL_G |
13798 | #define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
13799 | #define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
13800 | #define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
13801 | #define CM0_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
13802 | //CM0_CM_RGAM_RAMB_START_CNTL_R |
13803 | #define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
13804 | #define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
13805 | #define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
13806 | #define CM0_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
13807 | //CM0_CM_RGAM_RAMB_SLOPE_CNTL_B |
13808 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
13809 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
13810 | //CM0_CM_RGAM_RAMB_SLOPE_CNTL_G |
13811 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
13812 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
13813 | //CM0_CM_RGAM_RAMB_SLOPE_CNTL_R |
13814 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
13815 | #define CM0_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
13816 | //CM0_CM_RGAM_RAMB_END_CNTL1_B |
13817 | #define CM0_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
13818 | #define CM0_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
13819 | //CM0_CM_RGAM_RAMB_END_CNTL2_B |
13820 | #define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
13821 | #define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
13822 | #define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
13823 | #define CM0_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
13824 | //CM0_CM_RGAM_RAMB_END_CNTL1_G |
13825 | #define CM0_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
13826 | #define CM0_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
13827 | //CM0_CM_RGAM_RAMB_END_CNTL2_G |
13828 | #define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
13829 | #define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
13830 | #define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
13831 | #define CM0_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
13832 | //CM0_CM_RGAM_RAMB_END_CNTL1_R |
13833 | #define CM0_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
13834 | #define CM0_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
13835 | //CM0_CM_RGAM_RAMB_END_CNTL2_R |
13836 | #define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
13837 | #define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
13838 | #define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
13839 | #define CM0_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
13840 | //CM0_CM_RGAM_RAMB_REGION_0_1 |
13841 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
13842 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
13843 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
13844 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
13845 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
13846 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
13847 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
13848 | #define CM0_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
13849 | //CM0_CM_RGAM_RAMB_REGION_2_3 |
13850 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
13851 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
13852 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
13853 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
13854 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
13855 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
13856 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
13857 | #define CM0_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
13858 | //CM0_CM_RGAM_RAMB_REGION_4_5 |
13859 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
13860 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
13861 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
13862 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
13863 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
13864 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
13865 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
13866 | #define CM0_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
13867 | //CM0_CM_RGAM_RAMB_REGION_6_7 |
13868 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
13869 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
13870 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
13871 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
13872 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
13873 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
13874 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
13875 | #define CM0_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
13876 | //CM0_CM_RGAM_RAMB_REGION_8_9 |
13877 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
13878 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
13879 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
13880 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
13881 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
13882 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
13883 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
13884 | #define CM0_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
13885 | //CM0_CM_RGAM_RAMB_REGION_10_11 |
13886 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
13887 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
13888 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
13889 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
13890 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
13891 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
13892 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
13893 | #define CM0_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
13894 | //CM0_CM_RGAM_RAMB_REGION_12_13 |
13895 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
13896 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
13897 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
13898 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
13899 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
13900 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
13901 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
13902 | #define CM0_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
13903 | //CM0_CM_RGAM_RAMB_REGION_14_15 |
13904 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
13905 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
13906 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
13907 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
13908 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
13909 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
13910 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
13911 | #define CM0_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
13912 | //CM0_CM_RGAM_RAMB_REGION_16_17 |
13913 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
13914 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
13915 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
13916 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
13917 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
13918 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
13919 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
13920 | #define CM0_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
13921 | //CM0_CM_RGAM_RAMB_REGION_18_19 |
13922 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
13923 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
13924 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
13925 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
13926 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
13927 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
13928 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
13929 | #define CM0_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
13930 | //CM0_CM_RGAM_RAMB_REGION_20_21 |
13931 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
13932 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
13933 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
13934 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
13935 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
13936 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
13937 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
13938 | #define CM0_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
13939 | //CM0_CM_RGAM_RAMB_REGION_22_23 |
13940 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
13941 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
13942 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
13943 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
13944 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
13945 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
13946 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
13947 | #define CM0_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
13948 | //CM0_CM_RGAM_RAMB_REGION_24_25 |
13949 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
13950 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
13951 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
13952 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
13953 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
13954 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
13955 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
13956 | #define CM0_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
13957 | //CM0_CM_RGAM_RAMB_REGION_26_27 |
13958 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
13959 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
13960 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
13961 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
13962 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
13963 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
13964 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
13965 | #define CM0_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
13966 | //CM0_CM_RGAM_RAMB_REGION_28_29 |
13967 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
13968 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
13969 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
13970 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
13971 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
13972 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
13973 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
13974 | #define CM0_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
13975 | //CM0_CM_RGAM_RAMB_REGION_30_31 |
13976 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
13977 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
13978 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
13979 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
13980 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
13981 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
13982 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
13983 | #define CM0_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
13984 | //CM0_CM_RGAM_RAMB_REGION_32_33 |
13985 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
13986 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
13987 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
13988 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
13989 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
13990 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
13991 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
13992 | #define CM0_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
13993 | //CM0_CM_HDR_MULT_COEF |
13994 | #define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 |
13995 | #define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL |
13996 | //CM0_CM_RANGE_CLAMP_CONTROL_R |
13997 | #define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 |
13998 | #define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 |
13999 | #define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL |
14000 | #define CM0_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L |
14001 | //CM0_CM_RANGE_CLAMP_CONTROL_G |
14002 | #define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 |
14003 | #define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 |
14004 | #define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL |
14005 | #define CM0_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L |
14006 | //CM0_CM_RANGE_CLAMP_CONTROL_B |
14007 | #define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 |
14008 | #define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 |
14009 | #define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL |
14010 | #define CM0_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L |
14011 | //CM0_CM_DENORM_CONTROL |
14012 | #define CM0_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 |
14013 | #define CM0_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 |
14014 | #define CM0_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L |
14015 | #define CM0_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L |
14016 | //CM0_CM_CMOUT_CONTROL |
14017 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
14018 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 |
14019 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 |
14020 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc |
14021 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 |
14022 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 |
14023 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 |
14024 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL |
14025 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L |
14026 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L |
14027 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L |
14028 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L |
14029 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L |
14030 | #define CM0_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L |
14031 | //CM0_CM_CMOUT_RANDOM_SEEDS |
14032 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 |
14033 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 |
14034 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 |
14035 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL |
14036 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L |
14037 | #define CM0_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L |
14038 | //CM0_CM_MEM_PWR_CTRL |
14039 | #define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 |
14040 | #define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 |
14041 | #define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 |
14042 | #define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 |
14043 | #define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L |
14044 | #define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L |
14045 | #define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L |
14046 | #define CM0_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L |
14047 | //CM0_CM_MEM_PWR_STATUS |
14048 | #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 |
14049 | #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 |
14050 | #define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L |
14051 | #define CM0_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL |
14052 | //CM0_CM_TEST_DEBUG_INDEX |
14053 | #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 |
14054 | #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
14055 | #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL |
14056 | #define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L |
14057 | //CM0_CM_TEST_DEBUG_DATA |
14058 | #define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 |
14059 | #define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL |
14060 | |
14061 | |
14062 | // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
14063 | //DC_PERFMON12_PERFCOUNTER_CNTL |
14064 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
14065 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
14066 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
14067 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
14068 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
14069 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
14070 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
14071 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
14072 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
14073 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
14074 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
14075 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
14076 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
14077 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
14078 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
14079 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
14080 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
14081 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
14082 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
14083 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
14084 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
14085 | #define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
14086 | //DC_PERFMON12_PERFCOUNTER_CNTL2 |
14087 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
14088 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
14089 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
14090 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
14091 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
14092 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
14093 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
14094 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
14095 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
14096 | #define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
14097 | //DC_PERFMON12_PERFCOUNTER_STATE |
14098 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
14099 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
14100 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
14101 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
14102 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
14103 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
14104 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
14105 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
14106 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
14107 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
14108 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
14109 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
14110 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
14111 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
14112 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
14113 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
14114 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
14115 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
14116 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
14117 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
14118 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
14119 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
14120 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
14121 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
14122 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
14123 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
14124 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
14125 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
14126 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
14127 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
14128 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
14129 | #define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
14130 | //DC_PERFMON12_PERFMON_CNTL |
14131 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
14132 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
14133 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
14134 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
14135 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
14136 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
14137 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
14138 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
14139 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
14140 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
14141 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
14142 | #define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
14143 | //DC_PERFMON12_PERFMON_CNTL2 |
14144 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
14145 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
14146 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
14147 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
14148 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
14149 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
14150 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
14151 | #define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
14152 | //DC_PERFMON12_PERFMON_CVALUE_INT_MISC |
14153 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
14154 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
14155 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
14156 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
14157 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
14158 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
14159 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
14160 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
14161 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
14162 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
14163 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
14164 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
14165 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
14166 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
14167 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
14168 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
14169 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
14170 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
14171 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
14172 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
14173 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
14174 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
14175 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
14176 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
14177 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
14178 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
14179 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
14180 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
14181 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
14182 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
14183 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
14184 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
14185 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
14186 | #define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
14187 | //DC_PERFMON12_PERFMON_CVALUE_LOW |
14188 | #define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
14189 | #define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
14190 | //DC_PERFMON12_PERFMON_HI |
14191 | #define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
14192 | #define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
14193 | #define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
14194 | #define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
14195 | //DC_PERFMON12_PERFMON_LOW |
14196 | #define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
14197 | #define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
14198 | |
14199 | |
14200 | // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec |
14201 | //DPP_TOP1_DPP_CONTROL |
14202 | #define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 |
14203 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 |
14204 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa |
14205 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc |
14206 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 |
14207 | #define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 |
14208 | #define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 |
14209 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 |
14210 | #define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c |
14211 | #define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L |
14212 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L |
14213 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L |
14214 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L |
14215 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L |
14216 | #define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L |
14217 | #define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L |
14218 | #define DPP_TOP1_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L |
14219 | #define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L |
14220 | //DPP_TOP1_DPP_SOFT_RESET |
14221 | #define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 |
14222 | #define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 |
14223 | #define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 |
14224 | #define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc |
14225 | #define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L |
14226 | #define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L |
14227 | #define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L |
14228 | #define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L |
14229 | //DPP_TOP1_DPP_CRC_VAL_R_G |
14230 | #define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 |
14231 | #define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 |
14232 | #define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL |
14233 | #define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L |
14234 | //DPP_TOP1_DPP_CRC_VAL_B_A |
14235 | #define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 |
14236 | #define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 |
14237 | #define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL |
14238 | #define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L |
14239 | //DPP_TOP1_DPP_CRC_CTRL |
14240 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 |
14241 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 |
14242 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 |
14243 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 |
14244 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 |
14245 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 |
14246 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 |
14247 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa |
14248 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc |
14249 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf |
14250 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 |
14251 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L |
14252 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L |
14253 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L |
14254 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L |
14255 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L |
14256 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L |
14257 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L |
14258 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L |
14259 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L |
14260 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L |
14261 | #define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L |
14262 | //DPP_TOP1_HOST_READ_CONTROL |
14263 | #define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 |
14264 | #define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL |
14265 | |
14266 | |
14267 | // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec |
14268 | //CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT |
14269 | #define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
14270 | #define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
14271 | //CNVC_CFG1_FORMAT_CONTROL |
14272 | #define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 |
14273 | #define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 |
14274 | #define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 |
14275 | #define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc |
14276 | #define CNVC_CFG1_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 |
14277 | #define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 |
14278 | #define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L |
14279 | #define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L |
14280 | #define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L |
14281 | #define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L |
14282 | #define CNVC_CFG1_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L |
14283 | #define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L |
14284 | //CNVC_CFG1_FCNV_FP_SCALE_BIAS |
14285 | #define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 |
14286 | #define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 |
14287 | #define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL |
14288 | #define CNVC_CFG1_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L |
14289 | //CNVC_CFG1_DENORM_CONTROL |
14290 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 |
14291 | #define CNVC_CFG1_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf |
14292 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 |
14293 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f |
14294 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL |
14295 | #define CNVC_CFG1_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L |
14296 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L |
14297 | #define CNVC_CFG1_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L |
14298 | //CNVC_CFG1_COLOR_KEYER_CONTROL |
14299 | #define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 |
14300 | #define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 |
14301 | #define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L |
14302 | #define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L |
14303 | //CNVC_CFG1_COLOR_KEYER_ALPHA |
14304 | #define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 |
14305 | #define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 |
14306 | #define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL |
14307 | #define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L |
14308 | //CNVC_CFG1_COLOR_KEYER_RED |
14309 | #define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 |
14310 | #define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 |
14311 | #define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL |
14312 | #define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L |
14313 | //CNVC_CFG1_COLOR_KEYER_GREEN |
14314 | #define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 |
14315 | #define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 |
14316 | #define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL |
14317 | #define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L |
14318 | //CNVC_CFG1_COLOR_KEYER_BLUE |
14319 | #define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 |
14320 | #define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 |
14321 | #define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL |
14322 | #define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L |
14323 | |
14324 | |
14325 | // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec |
14326 | //CNVC_CUR1_CURSOR0_CONTROL |
14327 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 |
14328 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 |
14329 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 |
14330 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 |
14331 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 |
14332 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 |
14333 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 |
14334 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L |
14335 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L |
14336 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L |
14337 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L |
14338 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L |
14339 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L |
14340 | #define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L |
14341 | //CNVC_CUR1_CURSOR0_COLOR0 |
14342 | #define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 |
14343 | #define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL |
14344 | //CNVC_CUR1_CURSOR0_COLOR1 |
14345 | #define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 |
14346 | #define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL |
14347 | //CNVC_CUR1_CURSOR0_FP_SCALE_BIAS |
14348 | #define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 |
14349 | #define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 |
14350 | #define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL |
14351 | #define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L |
14352 | |
14353 | |
14354 | // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec |
14355 | //DSCL1_SCL_COEF_RAM_TAP_SELECT |
14356 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
14357 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 |
14358 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
14359 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L |
14360 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L |
14361 | #define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L |
14362 | //DSCL1_SCL_COEF_RAM_TAP_DATA |
14363 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
14364 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
14365 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
14366 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
14367 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
14368 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
14369 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
14370 | #define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
14371 | //DSCL1_SCL_MODE |
14372 | #define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 |
14373 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 |
14374 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc |
14375 | #define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 |
14376 | #define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 |
14377 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 |
14378 | #define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L |
14379 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L |
14380 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L |
14381 | #define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L |
14382 | #define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L |
14383 | #define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L |
14384 | //DSCL1_SCL_TAP_CONTROL |
14385 | #define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 |
14386 | #define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 |
14387 | #define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 |
14388 | #define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc |
14389 | #define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L |
14390 | #define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L |
14391 | #define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L |
14392 | #define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L |
14393 | //DSCL1_DSCL_CONTROL |
14394 | #define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
14395 | #define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L |
14396 | //DSCL1_DSCL_2TAP_CONTROL |
14397 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 |
14398 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 |
14399 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 |
14400 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 |
14401 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 |
14402 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 |
14403 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L |
14404 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L |
14405 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L |
14406 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L |
14407 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L |
14408 | #define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L |
14409 | //DSCL1_SCL_MANUAL_REPLICATE_CONTROL |
14410 | #define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
14411 | #define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
14412 | #define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL |
14413 | #define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L |
14414 | //DSCL1_SCL_HORZ_FILTER_SCALE_RATIO |
14415 | #define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
14416 | #define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL |
14417 | //DSCL1_SCL_HORZ_FILTER_INIT |
14418 | #define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
14419 | #define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
14420 | #define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL |
14421 | #define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L |
14422 | //DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C |
14423 | #define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 |
14424 | #define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL |
14425 | //DSCL1_SCL_HORZ_FILTER_INIT_C |
14426 | #define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 |
14427 | #define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 |
14428 | #define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL |
14429 | #define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L |
14430 | //DSCL1_SCL_VERT_FILTER_SCALE_RATIO |
14431 | #define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
14432 | #define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL |
14433 | //DSCL1_SCL_VERT_FILTER_INIT |
14434 | #define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
14435 | #define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
14436 | #define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL |
14437 | #define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L |
14438 | //DSCL1_SCL_VERT_FILTER_INIT_BOT |
14439 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
14440 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
14441 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL |
14442 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L |
14443 | //DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C |
14444 | #define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 |
14445 | #define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL |
14446 | //DSCL1_SCL_VERT_FILTER_INIT_C |
14447 | #define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 |
14448 | #define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 |
14449 | #define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL |
14450 | #define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L |
14451 | //DSCL1_SCL_VERT_FILTER_INIT_BOT_C |
14452 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 |
14453 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 |
14454 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL |
14455 | #define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L |
14456 | //DSCL1_SCL_BLACK_OFFSET |
14457 | #define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 |
14458 | #define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 |
14459 | #define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL |
14460 | #define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L |
14461 | //DSCL1_DSCL_UPDATE |
14462 | #define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
14463 | #define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L |
14464 | //DSCL1_DSCL_AUTOCAL |
14465 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 |
14466 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 |
14467 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc |
14468 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L |
14469 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L |
14470 | #define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L |
14471 | //DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT |
14472 | #define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
14473 | #define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
14474 | #define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL |
14475 | #define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L |
14476 | //DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM |
14477 | #define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
14478 | #define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
14479 | #define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL |
14480 | #define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L |
14481 | //DSCL1_OTG_H_BLANK |
14482 | #define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 |
14483 | #define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 |
14484 | #define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL |
14485 | #define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L |
14486 | //DSCL1_OTG_V_BLANK |
14487 | #define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 |
14488 | #define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 |
14489 | #define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL |
14490 | #define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L |
14491 | //DSCL1_RECOUT_START |
14492 | #define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 |
14493 | #define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 |
14494 | #define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL |
14495 | #define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L |
14496 | //DSCL1_RECOUT_SIZE |
14497 | #define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 |
14498 | #define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 |
14499 | #define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL |
14500 | #define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L |
14501 | //DSCL1_MPC_SIZE |
14502 | #define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 |
14503 | #define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 |
14504 | #define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL |
14505 | #define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L |
14506 | //DSCL1_LB_DATA_FORMAT |
14507 | #define DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
14508 | #define DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 |
14509 | #define DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc |
14510 | #define DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 |
14511 | #define DSCL1_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 |
14512 | #define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 |
14513 | #define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
14514 | #define DSCL1_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L |
14515 | #define DSCL1_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L |
14516 | #define DSCL1_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L |
14517 | #define DSCL1_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L |
14518 | #define DSCL1_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L |
14519 | #define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L |
14520 | #define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L |
14521 | //DSCL1_LB_MEMORY_CTRL |
14522 | #define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 |
14523 | #define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 |
14524 | #define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
14525 | #define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 |
14526 | #define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L |
14527 | #define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L |
14528 | #define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L |
14529 | #define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L |
14530 | //DSCL1_LB_V_COUNTER |
14531 | #define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
14532 | #define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 |
14533 | #define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL |
14534 | #define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L |
14535 | //DSCL1_DSCL_MEM_PWR_CTRL |
14536 | #define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 |
14537 | #define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 |
14538 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 |
14539 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 |
14540 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 |
14541 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa |
14542 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc |
14543 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe |
14544 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 |
14545 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 |
14546 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 |
14547 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 |
14548 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 |
14549 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a |
14550 | #define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L |
14551 | #define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L |
14552 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L |
14553 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L |
14554 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L |
14555 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L |
14556 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L |
14557 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L |
14558 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L |
14559 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L |
14560 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L |
14561 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L |
14562 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L |
14563 | #define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L |
14564 | //DSCL1_DSCL_MEM_PWR_STATUS |
14565 | #define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 |
14566 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 |
14567 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 |
14568 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 |
14569 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 |
14570 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa |
14571 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc |
14572 | #define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L |
14573 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL |
14574 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L |
14575 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L |
14576 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L |
14577 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L |
14578 | #define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L |
14579 | //DSCL1_OBUF_CONTROL |
14580 | #define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 |
14581 | #define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 |
14582 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 |
14583 | #define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc |
14584 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 |
14585 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 |
14586 | #define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c |
14587 | #define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L |
14588 | #define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L |
14589 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L |
14590 | #define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L |
14591 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L |
14592 | #define DSCL1_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L |
14593 | #define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L |
14594 | //DSCL1_OBUF_MEM_PWR_CTRL |
14595 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 |
14596 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 |
14597 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 |
14598 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L |
14599 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L |
14600 | #define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L |
14601 | |
14602 | |
14603 | // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec |
14604 | //CM1_CM_CONTROL |
14605 | #define CM1_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 |
14606 | #define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 |
14607 | #define CM1_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L |
14608 | #define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L |
14609 | //CM1_CM_COMA_C11_C12 |
14610 | #define CM1_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 |
14611 | #define CM1_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 |
14612 | #define CM1_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL |
14613 | #define CM1_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L |
14614 | //CM1_CM_COMA_C13_C14 |
14615 | #define CM1_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 |
14616 | #define CM1_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 |
14617 | #define CM1_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL |
14618 | #define CM1_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L |
14619 | //CM1_CM_COMA_C21_C22 |
14620 | #define CM1_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 |
14621 | #define CM1_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 |
14622 | #define CM1_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL |
14623 | #define CM1_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L |
14624 | //CM1_CM_COMA_C23_C24 |
14625 | #define CM1_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 |
14626 | #define CM1_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 |
14627 | #define CM1_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL |
14628 | #define CM1_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L |
14629 | //CM1_CM_COMA_C31_C32 |
14630 | #define CM1_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 |
14631 | #define CM1_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 |
14632 | #define CM1_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL |
14633 | #define CM1_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L |
14634 | //CM1_CM_COMA_C33_C34 |
14635 | #define CM1_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 |
14636 | #define CM1_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 |
14637 | #define CM1_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL |
14638 | #define CM1_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L |
14639 | //CM1_CM_COMB_C11_C12 |
14640 | #define CM1_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 |
14641 | #define CM1_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 |
14642 | #define CM1_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL |
14643 | #define CM1_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L |
14644 | //CM1_CM_COMB_C13_C14 |
14645 | #define CM1_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 |
14646 | #define CM1_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 |
14647 | #define CM1_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL |
14648 | #define CM1_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L |
14649 | //CM1_CM_COMB_C21_C22 |
14650 | #define CM1_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 |
14651 | #define CM1_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 |
14652 | #define CM1_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL |
14653 | #define CM1_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L |
14654 | //CM1_CM_COMB_C23_C24 |
14655 | #define CM1_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 |
14656 | #define CM1_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 |
14657 | #define CM1_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL |
14658 | #define CM1_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L |
14659 | //CM1_CM_COMB_C31_C32 |
14660 | #define CM1_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 |
14661 | #define CM1_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 |
14662 | #define CM1_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL |
14663 | #define CM1_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L |
14664 | //CM1_CM_COMB_C33_C34 |
14665 | #define CM1_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 |
14666 | #define CM1_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 |
14667 | #define CM1_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL |
14668 | #define CM1_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L |
14669 | //CM1_CM_IGAM_CONTROL |
14670 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 |
14671 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 |
14672 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 |
14673 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 |
14674 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 |
14675 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 |
14676 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd |
14677 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 |
14678 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 |
14679 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 |
14680 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 |
14681 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 |
14682 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 |
14683 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a |
14684 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L |
14685 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L |
14686 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L |
14687 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L |
14688 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L |
14689 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L |
14690 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L |
14691 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L |
14692 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L |
14693 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L |
14694 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L |
14695 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L |
14696 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L |
14697 | #define CM1_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L |
14698 | //CM1_CM_IGAM_LUT_RW_CONTROL |
14699 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 |
14700 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 |
14701 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 |
14702 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc |
14703 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 |
14704 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L |
14705 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L |
14706 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L |
14707 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L |
14708 | #define CM1_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L |
14709 | //CM1_CM_IGAM_LUT_RW_INDEX |
14710 | #define CM1_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 |
14711 | #define CM1_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL |
14712 | //CM1_CM_IGAM_LUT_SEQ_COLOR |
14713 | #define CM1_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 |
14714 | #define CM1_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL |
14715 | //CM1_CM_IGAM_LUT_30_COLOR |
14716 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 |
14717 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa |
14718 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 |
14719 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL |
14720 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L |
14721 | #define CM1_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L |
14722 | //CM1_CM_IGAM_LUT_PWL_DATA |
14723 | #define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 |
14724 | #define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 |
14725 | #define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL |
14726 | #define CM1_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L |
14727 | //CM1_CM_IGAM_LUT_AUTOFILL |
14728 | #define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 |
14729 | #define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 |
14730 | #define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L |
14731 | #define CM1_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L |
14732 | //CM1_CM_IGAM_LUT_BW_OFFSET_BLUE |
14733 | #define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
14734 | #define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 |
14735 | #define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL |
14736 | #define CM1_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L |
14737 | //CM1_CM_IGAM_LUT_BW_OFFSET_GREEN |
14738 | #define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
14739 | #define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 |
14740 | #define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL |
14741 | #define CM1_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L |
14742 | //CM1_CM_IGAM_LUT_BW_OFFSET_RED |
14743 | #define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
14744 | #define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 |
14745 | #define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL |
14746 | #define CM1_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L |
14747 | //CM1_CM_ICSC_CONTROL |
14748 | #define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 |
14749 | #define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L |
14750 | //CM1_CM_ICSC_C11_C12 |
14751 | #define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 |
14752 | #define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 |
14753 | #define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL |
14754 | #define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L |
14755 | //CM1_CM_ICSC_C13_C14 |
14756 | #define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 |
14757 | #define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 |
14758 | #define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL |
14759 | #define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L |
14760 | //CM1_CM_ICSC_C21_C22 |
14761 | #define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 |
14762 | #define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 |
14763 | #define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL |
14764 | #define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L |
14765 | //CM1_CM_ICSC_C23_C24 |
14766 | #define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 |
14767 | #define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 |
14768 | #define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL |
14769 | #define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L |
14770 | //CM1_CM_ICSC_C31_C32 |
14771 | #define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 |
14772 | #define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 |
14773 | #define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL |
14774 | #define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L |
14775 | //CM1_CM_ICSC_C33_C34 |
14776 | #define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 |
14777 | #define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 |
14778 | #define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL |
14779 | #define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L |
14780 | //CM1_CM_GAMUT_REMAP_CONTROL |
14781 | #define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 |
14782 | #define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L |
14783 | //CM1_CM_GAMUT_REMAP_C11_C12 |
14784 | #define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 |
14785 | #define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 |
14786 | #define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL |
14787 | #define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L |
14788 | //CM1_CM_GAMUT_REMAP_C13_C14 |
14789 | #define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 |
14790 | #define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 |
14791 | #define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL |
14792 | #define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L |
14793 | //CM1_CM_GAMUT_REMAP_C21_C22 |
14794 | #define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 |
14795 | #define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 |
14796 | #define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL |
14797 | #define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L |
14798 | //CM1_CM_GAMUT_REMAP_C23_C24 |
14799 | #define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 |
14800 | #define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 |
14801 | #define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL |
14802 | #define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L |
14803 | //CM1_CM_GAMUT_REMAP_C31_C32 |
14804 | #define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 |
14805 | #define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 |
14806 | #define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL |
14807 | #define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L |
14808 | //CM1_CM_GAMUT_REMAP_C33_C34 |
14809 | #define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 |
14810 | #define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 |
14811 | #define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL |
14812 | #define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L |
14813 | //CM1_CM_OCSC_CONTROL |
14814 | #define CM1_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 |
14815 | #define CM1_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L |
14816 | //CM1_CM_OCSC_C11_C12 |
14817 | #define CM1_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 |
14818 | #define CM1_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 |
14819 | #define CM1_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL |
14820 | #define CM1_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L |
14821 | //CM1_CM_OCSC_C13_C14 |
14822 | #define CM1_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 |
14823 | #define CM1_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 |
14824 | #define CM1_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL |
14825 | #define CM1_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L |
14826 | //CM1_CM_OCSC_C21_C22 |
14827 | #define CM1_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 |
14828 | #define CM1_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 |
14829 | #define CM1_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL |
14830 | #define CM1_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L |
14831 | //CM1_CM_OCSC_C23_C24 |
14832 | #define CM1_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 |
14833 | #define CM1_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 |
14834 | #define CM1_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL |
14835 | #define CM1_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L |
14836 | //CM1_CM_OCSC_C31_C32 |
14837 | #define CM1_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 |
14838 | #define CM1_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 |
14839 | #define CM1_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL |
14840 | #define CM1_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L |
14841 | //CM1_CM_OCSC_C33_C34 |
14842 | #define CM1_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 |
14843 | #define CM1_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 |
14844 | #define CM1_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL |
14845 | #define CM1_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L |
14846 | //CM1_CM_BNS_VALUES_R |
14847 | #define CM1_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 |
14848 | #define CM1_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 |
14849 | #define CM1_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL |
14850 | #define CM1_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L |
14851 | //CM1_CM_BNS_VALUES_G |
14852 | #define CM1_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 |
14853 | #define CM1_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 |
14854 | #define CM1_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL |
14855 | #define CM1_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L |
14856 | //CM1_CM_BNS_VALUES_B |
14857 | #define CM1_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 |
14858 | #define CM1_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 |
14859 | #define CM1_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL |
14860 | #define CM1_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L |
14861 | //CM1_CM_DGAM_CONTROL |
14862 | #define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 |
14863 | #define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L |
14864 | //CM1_CM_DGAM_LUT_INDEX |
14865 | #define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 |
14866 | #define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL |
14867 | //CM1_CM_DGAM_LUT_DATA |
14868 | #define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 |
14869 | #define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL |
14870 | //CM1_CM_DGAM_LUT_WRITE_EN_MASK |
14871 | #define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
14872 | #define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 |
14873 | #define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
14874 | #define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L |
14875 | //CM1_CM_DGAM_RAMA_START_CNTL_B |
14876 | #define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
14877 | #define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
14878 | #define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
14879 | #define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
14880 | //CM1_CM_DGAM_RAMA_START_CNTL_G |
14881 | #define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
14882 | #define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
14883 | #define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
14884 | #define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
14885 | //CM1_CM_DGAM_RAMA_START_CNTL_R |
14886 | #define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
14887 | #define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
14888 | #define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
14889 | #define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
14890 | //CM1_CM_DGAM_RAMA_SLOPE_CNTL_B |
14891 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
14892 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
14893 | //CM1_CM_DGAM_RAMA_SLOPE_CNTL_G |
14894 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
14895 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
14896 | //CM1_CM_DGAM_RAMA_SLOPE_CNTL_R |
14897 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
14898 | #define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
14899 | //CM1_CM_DGAM_RAMA_END_CNTL1_B |
14900 | #define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
14901 | #define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
14902 | //CM1_CM_DGAM_RAMA_END_CNTL2_B |
14903 | #define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
14904 | #define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
14905 | #define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
14906 | #define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
14907 | //CM1_CM_DGAM_RAMA_END_CNTL1_G |
14908 | #define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
14909 | #define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
14910 | //CM1_CM_DGAM_RAMA_END_CNTL2_G |
14911 | #define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
14912 | #define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
14913 | #define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
14914 | #define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
14915 | //CM1_CM_DGAM_RAMA_END_CNTL1_R |
14916 | #define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
14917 | #define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
14918 | //CM1_CM_DGAM_RAMA_END_CNTL2_R |
14919 | #define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
14920 | #define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
14921 | #define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
14922 | #define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
14923 | //CM1_CM_DGAM_RAMA_REGION_0_1 |
14924 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
14925 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
14926 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
14927 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
14928 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
14929 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
14930 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
14931 | #define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
14932 | //CM1_CM_DGAM_RAMA_REGION_2_3 |
14933 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
14934 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
14935 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
14936 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
14937 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
14938 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
14939 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
14940 | #define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
14941 | //CM1_CM_DGAM_RAMA_REGION_4_5 |
14942 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
14943 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
14944 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
14945 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
14946 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
14947 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
14948 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
14949 | #define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
14950 | //CM1_CM_DGAM_RAMA_REGION_6_7 |
14951 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
14952 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
14953 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
14954 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
14955 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
14956 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
14957 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
14958 | #define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
14959 | //CM1_CM_DGAM_RAMA_REGION_8_9 |
14960 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
14961 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
14962 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
14963 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
14964 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
14965 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
14966 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
14967 | #define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
14968 | //CM1_CM_DGAM_RAMA_REGION_10_11 |
14969 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
14970 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
14971 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
14972 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
14973 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
14974 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
14975 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
14976 | #define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
14977 | //CM1_CM_DGAM_RAMA_REGION_12_13 |
14978 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
14979 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
14980 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
14981 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
14982 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
14983 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
14984 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
14985 | #define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
14986 | //CM1_CM_DGAM_RAMA_REGION_14_15 |
14987 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
14988 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
14989 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
14990 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
14991 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
14992 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
14993 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
14994 | #define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
14995 | //CM1_CM_DGAM_RAMB_START_CNTL_B |
14996 | #define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
14997 | #define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
14998 | #define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
14999 | #define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
15000 | //CM1_CM_DGAM_RAMB_START_CNTL_G |
15001 | #define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
15002 | #define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
15003 | #define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
15004 | #define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
15005 | //CM1_CM_DGAM_RAMB_START_CNTL_R |
15006 | #define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
15007 | #define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
15008 | #define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
15009 | #define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
15010 | //CM1_CM_DGAM_RAMB_SLOPE_CNTL_B |
15011 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
15012 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
15013 | //CM1_CM_DGAM_RAMB_SLOPE_CNTL_G |
15014 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
15015 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
15016 | //CM1_CM_DGAM_RAMB_SLOPE_CNTL_R |
15017 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
15018 | #define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
15019 | //CM1_CM_DGAM_RAMB_END_CNTL1_B |
15020 | #define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
15021 | #define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
15022 | //CM1_CM_DGAM_RAMB_END_CNTL2_B |
15023 | #define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
15024 | #define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
15025 | #define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
15026 | #define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
15027 | //CM1_CM_DGAM_RAMB_END_CNTL1_G |
15028 | #define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
15029 | #define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
15030 | //CM1_CM_DGAM_RAMB_END_CNTL2_G |
15031 | #define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
15032 | #define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
15033 | #define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
15034 | #define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
15035 | //CM1_CM_DGAM_RAMB_END_CNTL1_R |
15036 | #define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
15037 | #define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
15038 | //CM1_CM_DGAM_RAMB_END_CNTL2_R |
15039 | #define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
15040 | #define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
15041 | #define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
15042 | #define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
15043 | //CM1_CM_DGAM_RAMB_REGION_0_1 |
15044 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
15045 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
15046 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
15047 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
15048 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
15049 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
15050 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
15051 | #define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
15052 | //CM1_CM_DGAM_RAMB_REGION_2_3 |
15053 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
15054 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
15055 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
15056 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
15057 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
15058 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
15059 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
15060 | #define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
15061 | //CM1_CM_DGAM_RAMB_REGION_4_5 |
15062 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
15063 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
15064 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
15065 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
15066 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
15067 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
15068 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
15069 | #define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
15070 | //CM1_CM_DGAM_RAMB_REGION_6_7 |
15071 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
15072 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
15073 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
15074 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
15075 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
15076 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
15077 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
15078 | #define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
15079 | //CM1_CM_DGAM_RAMB_REGION_8_9 |
15080 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
15081 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
15082 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
15083 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
15084 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
15085 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
15086 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
15087 | #define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
15088 | //CM1_CM_DGAM_RAMB_REGION_10_11 |
15089 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
15090 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
15091 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
15092 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
15093 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
15094 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
15095 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
15096 | #define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
15097 | //CM1_CM_DGAM_RAMB_REGION_12_13 |
15098 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
15099 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
15100 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
15101 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
15102 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
15103 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
15104 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
15105 | #define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
15106 | //CM1_CM_DGAM_RAMB_REGION_14_15 |
15107 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
15108 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
15109 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
15110 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
15111 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
15112 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
15113 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
15114 | #define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
15115 | //CM1_CM_RGAM_CONTROL |
15116 | #define CM1_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 |
15117 | #define CM1_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L |
15118 | //CM1_CM_RGAM_LUT_INDEX |
15119 | #define CM1_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 |
15120 | #define CM1_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL |
15121 | //CM1_CM_RGAM_LUT_DATA |
15122 | #define CM1_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 |
15123 | #define CM1_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL |
15124 | //CM1_CM_RGAM_LUT_WRITE_EN_MASK |
15125 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
15126 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 |
15127 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 |
15128 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
15129 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L |
15130 | #define CM1_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L |
15131 | //CM1_CM_RGAM_RAMA_START_CNTL_B |
15132 | #define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
15133 | #define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
15134 | #define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
15135 | #define CM1_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
15136 | //CM1_CM_RGAM_RAMA_START_CNTL_G |
15137 | #define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
15138 | #define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
15139 | #define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
15140 | #define CM1_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
15141 | //CM1_CM_RGAM_RAMA_START_CNTL_R |
15142 | #define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
15143 | #define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
15144 | #define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
15145 | #define CM1_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
15146 | //CM1_CM_RGAM_RAMA_SLOPE_CNTL_B |
15147 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
15148 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
15149 | //CM1_CM_RGAM_RAMA_SLOPE_CNTL_G |
15150 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
15151 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
15152 | //CM1_CM_RGAM_RAMA_SLOPE_CNTL_R |
15153 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
15154 | #define CM1_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
15155 | //CM1_CM_RGAM_RAMA_END_CNTL1_B |
15156 | #define CM1_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
15157 | #define CM1_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
15158 | //CM1_CM_RGAM_RAMA_END_CNTL2_B |
15159 | #define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
15160 | #define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
15161 | #define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
15162 | #define CM1_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
15163 | //CM1_CM_RGAM_RAMA_END_CNTL1_G |
15164 | #define CM1_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
15165 | #define CM1_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
15166 | //CM1_CM_RGAM_RAMA_END_CNTL2_G |
15167 | #define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
15168 | #define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
15169 | #define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
15170 | #define CM1_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
15171 | //CM1_CM_RGAM_RAMA_END_CNTL1_R |
15172 | #define CM1_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
15173 | #define CM1_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
15174 | //CM1_CM_RGAM_RAMA_END_CNTL2_R |
15175 | #define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
15176 | #define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
15177 | #define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
15178 | #define CM1_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
15179 | //CM1_CM_RGAM_RAMA_REGION_0_1 |
15180 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
15181 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
15182 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
15183 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
15184 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
15185 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
15186 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
15187 | #define CM1_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
15188 | //CM1_CM_RGAM_RAMA_REGION_2_3 |
15189 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
15190 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
15191 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
15192 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
15193 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
15194 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
15195 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
15196 | #define CM1_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
15197 | //CM1_CM_RGAM_RAMA_REGION_4_5 |
15198 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
15199 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
15200 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
15201 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
15202 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
15203 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
15204 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
15205 | #define CM1_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
15206 | //CM1_CM_RGAM_RAMA_REGION_6_7 |
15207 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
15208 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
15209 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
15210 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
15211 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
15212 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
15213 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
15214 | #define CM1_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
15215 | //CM1_CM_RGAM_RAMA_REGION_8_9 |
15216 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
15217 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
15218 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
15219 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
15220 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
15221 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
15222 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
15223 | #define CM1_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
15224 | //CM1_CM_RGAM_RAMA_REGION_10_11 |
15225 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
15226 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
15227 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
15228 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
15229 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
15230 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
15231 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
15232 | #define CM1_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
15233 | //CM1_CM_RGAM_RAMA_REGION_12_13 |
15234 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
15235 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
15236 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
15237 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
15238 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
15239 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
15240 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
15241 | #define CM1_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
15242 | //CM1_CM_RGAM_RAMA_REGION_14_15 |
15243 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
15244 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
15245 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
15246 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
15247 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
15248 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
15249 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
15250 | #define CM1_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
15251 | //CM1_CM_RGAM_RAMA_REGION_16_17 |
15252 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
15253 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
15254 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
15255 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
15256 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
15257 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
15258 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
15259 | #define CM1_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
15260 | //CM1_CM_RGAM_RAMA_REGION_18_19 |
15261 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
15262 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
15263 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
15264 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
15265 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
15266 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
15267 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
15268 | #define CM1_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
15269 | //CM1_CM_RGAM_RAMA_REGION_20_21 |
15270 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
15271 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
15272 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
15273 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
15274 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
15275 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
15276 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
15277 | #define CM1_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
15278 | //CM1_CM_RGAM_RAMA_REGION_22_23 |
15279 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
15280 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
15281 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
15282 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
15283 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
15284 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
15285 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
15286 | #define CM1_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
15287 | //CM1_CM_RGAM_RAMA_REGION_24_25 |
15288 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
15289 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
15290 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
15291 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
15292 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
15293 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
15294 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
15295 | #define CM1_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
15296 | //CM1_CM_RGAM_RAMA_REGION_26_27 |
15297 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
15298 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
15299 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
15300 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
15301 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
15302 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
15303 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
15304 | #define CM1_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
15305 | //CM1_CM_RGAM_RAMA_REGION_28_29 |
15306 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
15307 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
15308 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
15309 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
15310 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
15311 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
15312 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
15313 | #define CM1_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
15314 | //CM1_CM_RGAM_RAMA_REGION_30_31 |
15315 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
15316 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
15317 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
15318 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
15319 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
15320 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
15321 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
15322 | #define CM1_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
15323 | //CM1_CM_RGAM_RAMA_REGION_32_33 |
15324 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
15325 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
15326 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
15327 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
15328 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
15329 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
15330 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
15331 | #define CM1_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
15332 | //CM1_CM_RGAM_RAMB_START_CNTL_B |
15333 | #define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
15334 | #define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
15335 | #define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
15336 | #define CM1_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
15337 | //CM1_CM_RGAM_RAMB_START_CNTL_G |
15338 | #define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
15339 | #define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
15340 | #define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
15341 | #define CM1_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
15342 | //CM1_CM_RGAM_RAMB_START_CNTL_R |
15343 | #define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
15344 | #define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
15345 | #define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
15346 | #define CM1_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
15347 | //CM1_CM_RGAM_RAMB_SLOPE_CNTL_B |
15348 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
15349 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
15350 | //CM1_CM_RGAM_RAMB_SLOPE_CNTL_G |
15351 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
15352 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
15353 | //CM1_CM_RGAM_RAMB_SLOPE_CNTL_R |
15354 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
15355 | #define CM1_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
15356 | //CM1_CM_RGAM_RAMB_END_CNTL1_B |
15357 | #define CM1_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
15358 | #define CM1_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
15359 | //CM1_CM_RGAM_RAMB_END_CNTL2_B |
15360 | #define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
15361 | #define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
15362 | #define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
15363 | #define CM1_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
15364 | //CM1_CM_RGAM_RAMB_END_CNTL1_G |
15365 | #define CM1_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
15366 | #define CM1_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
15367 | //CM1_CM_RGAM_RAMB_END_CNTL2_G |
15368 | #define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
15369 | #define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
15370 | #define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
15371 | #define CM1_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
15372 | //CM1_CM_RGAM_RAMB_END_CNTL1_R |
15373 | #define CM1_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
15374 | #define CM1_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
15375 | //CM1_CM_RGAM_RAMB_END_CNTL2_R |
15376 | #define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
15377 | #define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
15378 | #define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
15379 | #define CM1_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
15380 | //CM1_CM_RGAM_RAMB_REGION_0_1 |
15381 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
15382 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
15383 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
15384 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
15385 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
15386 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
15387 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
15388 | #define CM1_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
15389 | //CM1_CM_RGAM_RAMB_REGION_2_3 |
15390 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
15391 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
15392 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
15393 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
15394 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
15395 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
15396 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
15397 | #define CM1_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
15398 | //CM1_CM_RGAM_RAMB_REGION_4_5 |
15399 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
15400 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
15401 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
15402 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
15403 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
15404 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
15405 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
15406 | #define CM1_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
15407 | //CM1_CM_RGAM_RAMB_REGION_6_7 |
15408 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
15409 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
15410 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
15411 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
15412 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
15413 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
15414 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
15415 | #define CM1_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
15416 | //CM1_CM_RGAM_RAMB_REGION_8_9 |
15417 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
15418 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
15419 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
15420 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
15421 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
15422 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
15423 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
15424 | #define CM1_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
15425 | //CM1_CM_RGAM_RAMB_REGION_10_11 |
15426 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
15427 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
15428 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
15429 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
15430 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
15431 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
15432 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
15433 | #define CM1_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
15434 | //CM1_CM_RGAM_RAMB_REGION_12_13 |
15435 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
15436 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
15437 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
15438 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
15439 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
15440 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
15441 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
15442 | #define CM1_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
15443 | //CM1_CM_RGAM_RAMB_REGION_14_15 |
15444 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
15445 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
15446 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
15447 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
15448 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
15449 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
15450 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
15451 | #define CM1_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
15452 | //CM1_CM_RGAM_RAMB_REGION_16_17 |
15453 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
15454 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
15455 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
15456 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
15457 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
15458 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
15459 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
15460 | #define CM1_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
15461 | //CM1_CM_RGAM_RAMB_REGION_18_19 |
15462 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
15463 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
15464 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
15465 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
15466 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
15467 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
15468 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
15469 | #define CM1_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
15470 | //CM1_CM_RGAM_RAMB_REGION_20_21 |
15471 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
15472 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
15473 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
15474 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
15475 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
15476 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
15477 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
15478 | #define CM1_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
15479 | //CM1_CM_RGAM_RAMB_REGION_22_23 |
15480 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
15481 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
15482 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
15483 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
15484 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
15485 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
15486 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
15487 | #define CM1_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
15488 | //CM1_CM_RGAM_RAMB_REGION_24_25 |
15489 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
15490 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
15491 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
15492 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
15493 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
15494 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
15495 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
15496 | #define CM1_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
15497 | //CM1_CM_RGAM_RAMB_REGION_26_27 |
15498 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
15499 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
15500 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
15501 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
15502 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
15503 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
15504 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
15505 | #define CM1_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
15506 | //CM1_CM_RGAM_RAMB_REGION_28_29 |
15507 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
15508 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
15509 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
15510 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
15511 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
15512 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
15513 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
15514 | #define CM1_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
15515 | //CM1_CM_RGAM_RAMB_REGION_30_31 |
15516 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
15517 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
15518 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
15519 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
15520 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
15521 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
15522 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
15523 | #define CM1_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
15524 | //CM1_CM_RGAM_RAMB_REGION_32_33 |
15525 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
15526 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
15527 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
15528 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
15529 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
15530 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
15531 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
15532 | #define CM1_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
15533 | //CM1_CM_HDR_MULT_COEF |
15534 | #define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 |
15535 | #define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL |
15536 | //CM1_CM_RANGE_CLAMP_CONTROL_R |
15537 | #define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 |
15538 | #define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 |
15539 | #define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL |
15540 | #define CM1_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L |
15541 | //CM1_CM_RANGE_CLAMP_CONTROL_G |
15542 | #define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 |
15543 | #define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 |
15544 | #define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL |
15545 | #define CM1_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L |
15546 | //CM1_CM_RANGE_CLAMP_CONTROL_B |
15547 | #define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 |
15548 | #define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 |
15549 | #define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL |
15550 | #define CM1_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L |
15551 | //CM1_CM_DENORM_CONTROL |
15552 | #define CM1_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 |
15553 | #define CM1_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 |
15554 | #define CM1_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L |
15555 | #define CM1_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L |
15556 | //CM1_CM_CMOUT_CONTROL |
15557 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
15558 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 |
15559 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 |
15560 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc |
15561 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 |
15562 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 |
15563 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 |
15564 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL |
15565 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L |
15566 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L |
15567 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L |
15568 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L |
15569 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L |
15570 | #define CM1_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L |
15571 | //CM1_CM_CMOUT_RANDOM_SEEDS |
15572 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 |
15573 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 |
15574 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 |
15575 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL |
15576 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L |
15577 | #define CM1_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L |
15578 | //CM1_CM_MEM_PWR_CTRL |
15579 | #define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 |
15580 | #define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 |
15581 | #define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 |
15582 | #define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 |
15583 | #define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L |
15584 | #define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L |
15585 | #define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L |
15586 | #define CM1_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L |
15587 | //CM1_CM_MEM_PWR_STATUS |
15588 | #define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 |
15589 | #define CM1_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 |
15590 | #define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L |
15591 | #define CM1_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL |
15592 | |
15593 | |
15594 | // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
15595 | //DC_PERFMON13_PERFCOUNTER_CNTL |
15596 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
15597 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
15598 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
15599 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
15600 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
15601 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
15602 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
15603 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
15604 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
15605 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
15606 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
15607 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
15608 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
15609 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
15610 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
15611 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
15612 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
15613 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
15614 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
15615 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
15616 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
15617 | #define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
15618 | //DC_PERFMON13_PERFCOUNTER_CNTL2 |
15619 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
15620 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
15621 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
15622 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
15623 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
15624 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
15625 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
15626 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
15627 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
15628 | #define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
15629 | //DC_PERFMON13_PERFCOUNTER_STATE |
15630 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
15631 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
15632 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
15633 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
15634 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
15635 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
15636 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
15637 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
15638 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
15639 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
15640 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
15641 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
15642 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
15643 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
15644 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
15645 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
15646 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
15647 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
15648 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
15649 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
15650 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
15651 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
15652 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
15653 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
15654 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
15655 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
15656 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
15657 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
15658 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
15659 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
15660 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
15661 | #define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
15662 | //DC_PERFMON13_PERFMON_CNTL |
15663 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
15664 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
15665 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
15666 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
15667 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
15668 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
15669 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
15670 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
15671 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
15672 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
15673 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
15674 | #define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
15675 | //DC_PERFMON13_PERFMON_CNTL2 |
15676 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
15677 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
15678 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
15679 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
15680 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
15681 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
15682 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
15683 | #define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
15684 | //DC_PERFMON13_PERFMON_CVALUE_INT_MISC |
15685 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
15686 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
15687 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
15688 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
15689 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
15690 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
15691 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
15692 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
15693 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
15694 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
15695 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
15696 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
15697 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
15698 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
15699 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
15700 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
15701 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
15702 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
15703 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
15704 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
15705 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
15706 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
15707 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
15708 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
15709 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
15710 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
15711 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
15712 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
15713 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
15714 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
15715 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
15716 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
15717 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
15718 | #define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
15719 | //DC_PERFMON13_PERFMON_CVALUE_LOW |
15720 | #define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
15721 | #define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
15722 | //DC_PERFMON13_PERFMON_HI |
15723 | #define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
15724 | #define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
15725 | #define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
15726 | #define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
15727 | //DC_PERFMON13_PERFMON_LOW |
15728 | #define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
15729 | #define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
15730 | |
15731 | |
15732 | // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec |
15733 | //DPP_TOP2_DPP_CONTROL |
15734 | #define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 |
15735 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 |
15736 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa |
15737 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc |
15738 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 |
15739 | #define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 |
15740 | #define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 |
15741 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 |
15742 | #define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c |
15743 | #define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L |
15744 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L |
15745 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L |
15746 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L |
15747 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L |
15748 | #define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L |
15749 | #define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L |
15750 | #define DPP_TOP2_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L |
15751 | #define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L |
15752 | //DPP_TOP2_DPP_SOFT_RESET |
15753 | #define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 |
15754 | #define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 |
15755 | #define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 |
15756 | #define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc |
15757 | #define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L |
15758 | #define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L |
15759 | #define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L |
15760 | #define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L |
15761 | //DPP_TOP2_DPP_CRC_VAL_R_G |
15762 | #define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 |
15763 | #define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 |
15764 | #define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL |
15765 | #define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L |
15766 | //DPP_TOP2_DPP_CRC_VAL_B_A |
15767 | #define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 |
15768 | #define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 |
15769 | #define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL |
15770 | #define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L |
15771 | //DPP_TOP2_DPP_CRC_CTRL |
15772 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 |
15773 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 |
15774 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 |
15775 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 |
15776 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 |
15777 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 |
15778 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 |
15779 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa |
15780 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc |
15781 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf |
15782 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 |
15783 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L |
15784 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L |
15785 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L |
15786 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L |
15787 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L |
15788 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L |
15789 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L |
15790 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L |
15791 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L |
15792 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L |
15793 | #define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L |
15794 | //DPP_TOP2_HOST_READ_CONTROL |
15795 | #define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 |
15796 | #define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL |
15797 | |
15798 | |
15799 | // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec |
15800 | //CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT |
15801 | #define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
15802 | #define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
15803 | //CNVC_CFG2_FORMAT_CONTROL |
15804 | #define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 |
15805 | #define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 |
15806 | #define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 |
15807 | #define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc |
15808 | #define CNVC_CFG2_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 |
15809 | #define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 |
15810 | #define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L |
15811 | #define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L |
15812 | #define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L |
15813 | #define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L |
15814 | #define CNVC_CFG2_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L |
15815 | #define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L |
15816 | //CNVC_CFG2_FCNV_FP_SCALE_BIAS |
15817 | #define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 |
15818 | #define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 |
15819 | #define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL |
15820 | #define CNVC_CFG2_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L |
15821 | //CNVC_CFG2_DENORM_CONTROL |
15822 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 |
15823 | #define CNVC_CFG2_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf |
15824 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 |
15825 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f |
15826 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL |
15827 | #define CNVC_CFG2_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L |
15828 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L |
15829 | #define CNVC_CFG2_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L |
15830 | //CNVC_CFG2_COLOR_KEYER_CONTROL |
15831 | #define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 |
15832 | #define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 |
15833 | #define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L |
15834 | #define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L |
15835 | //CNVC_CFG2_COLOR_KEYER_ALPHA |
15836 | #define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 |
15837 | #define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 |
15838 | #define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL |
15839 | #define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L |
15840 | //CNVC_CFG2_COLOR_KEYER_RED |
15841 | #define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 |
15842 | #define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 |
15843 | #define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL |
15844 | #define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L |
15845 | //CNVC_CFG2_COLOR_KEYER_GREEN |
15846 | #define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 |
15847 | #define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 |
15848 | #define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL |
15849 | #define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L |
15850 | //CNVC_CFG2_COLOR_KEYER_BLUE |
15851 | #define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 |
15852 | #define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 |
15853 | #define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL |
15854 | #define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L |
15855 | |
15856 | |
15857 | // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec |
15858 | //CNVC_CUR2_CURSOR0_CONTROL |
15859 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 |
15860 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 |
15861 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 |
15862 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 |
15863 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 |
15864 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 |
15865 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 |
15866 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L |
15867 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L |
15868 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L |
15869 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L |
15870 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L |
15871 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L |
15872 | #define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L |
15873 | //CNVC_CUR2_CURSOR0_COLOR0 |
15874 | #define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 |
15875 | #define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL |
15876 | //CNVC_CUR2_CURSOR0_COLOR1 |
15877 | #define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 |
15878 | #define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL |
15879 | //CNVC_CUR2_CURSOR0_FP_SCALE_BIAS |
15880 | #define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 |
15881 | #define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 |
15882 | #define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL |
15883 | #define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L |
15884 | |
15885 | |
15886 | // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec |
15887 | //DSCL2_SCL_COEF_RAM_TAP_SELECT |
15888 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
15889 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 |
15890 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
15891 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L |
15892 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L |
15893 | #define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L |
15894 | //DSCL2_SCL_COEF_RAM_TAP_DATA |
15895 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
15896 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
15897 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
15898 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
15899 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
15900 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
15901 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
15902 | #define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
15903 | //DSCL2_SCL_MODE |
15904 | #define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 |
15905 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 |
15906 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc |
15907 | #define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 |
15908 | #define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 |
15909 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 |
15910 | #define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L |
15911 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L |
15912 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L |
15913 | #define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L |
15914 | #define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L |
15915 | #define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L |
15916 | //DSCL2_SCL_TAP_CONTROL |
15917 | #define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 |
15918 | #define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 |
15919 | #define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 |
15920 | #define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc |
15921 | #define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L |
15922 | #define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L |
15923 | #define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L |
15924 | #define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L |
15925 | //DSCL2_DSCL_CONTROL |
15926 | #define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
15927 | #define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L |
15928 | //DSCL2_DSCL_2TAP_CONTROL |
15929 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 |
15930 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 |
15931 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 |
15932 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 |
15933 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 |
15934 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 |
15935 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L |
15936 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L |
15937 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L |
15938 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L |
15939 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L |
15940 | #define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L |
15941 | //DSCL2_SCL_MANUAL_REPLICATE_CONTROL |
15942 | #define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
15943 | #define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
15944 | #define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL |
15945 | #define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L |
15946 | //DSCL2_SCL_HORZ_FILTER_SCALE_RATIO |
15947 | #define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
15948 | #define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL |
15949 | //DSCL2_SCL_HORZ_FILTER_INIT |
15950 | #define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
15951 | #define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
15952 | #define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL |
15953 | #define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L |
15954 | //DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C |
15955 | #define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 |
15956 | #define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL |
15957 | //DSCL2_SCL_HORZ_FILTER_INIT_C |
15958 | #define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 |
15959 | #define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 |
15960 | #define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL |
15961 | #define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L |
15962 | //DSCL2_SCL_VERT_FILTER_SCALE_RATIO |
15963 | #define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
15964 | #define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL |
15965 | //DSCL2_SCL_VERT_FILTER_INIT |
15966 | #define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
15967 | #define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
15968 | #define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL |
15969 | #define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L |
15970 | //DSCL2_SCL_VERT_FILTER_INIT_BOT |
15971 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
15972 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
15973 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL |
15974 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L |
15975 | //DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C |
15976 | #define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 |
15977 | #define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL |
15978 | //DSCL2_SCL_VERT_FILTER_INIT_C |
15979 | #define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 |
15980 | #define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 |
15981 | #define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL |
15982 | #define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L |
15983 | //DSCL2_SCL_VERT_FILTER_INIT_BOT_C |
15984 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 |
15985 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 |
15986 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL |
15987 | #define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L |
15988 | //DSCL2_SCL_BLACK_OFFSET |
15989 | #define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 |
15990 | #define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 |
15991 | #define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL |
15992 | #define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L |
15993 | //DSCL2_DSCL_UPDATE |
15994 | #define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
15995 | #define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L |
15996 | //DSCL2_DSCL_AUTOCAL |
15997 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 |
15998 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 |
15999 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc |
16000 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L |
16001 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L |
16002 | #define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L |
16003 | //DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT |
16004 | #define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
16005 | #define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
16006 | #define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL |
16007 | #define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L |
16008 | //DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM |
16009 | #define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
16010 | #define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
16011 | #define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL |
16012 | #define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L |
16013 | //DSCL2_OTG_H_BLANK |
16014 | #define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 |
16015 | #define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 |
16016 | #define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL |
16017 | #define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L |
16018 | //DSCL2_OTG_V_BLANK |
16019 | #define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 |
16020 | #define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 |
16021 | #define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL |
16022 | #define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L |
16023 | //DSCL2_RECOUT_START |
16024 | #define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 |
16025 | #define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 |
16026 | #define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL |
16027 | #define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L |
16028 | //DSCL2_RECOUT_SIZE |
16029 | #define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 |
16030 | #define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 |
16031 | #define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL |
16032 | #define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L |
16033 | //DSCL2_MPC_SIZE |
16034 | #define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 |
16035 | #define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 |
16036 | #define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL |
16037 | #define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L |
16038 | //DSCL2_LB_DATA_FORMAT |
16039 | #define DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
16040 | #define DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 |
16041 | #define DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc |
16042 | #define DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 |
16043 | #define DSCL2_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 |
16044 | #define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 |
16045 | #define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
16046 | #define DSCL2_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L |
16047 | #define DSCL2_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L |
16048 | #define DSCL2_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L |
16049 | #define DSCL2_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L |
16050 | #define DSCL2_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L |
16051 | #define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L |
16052 | #define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L |
16053 | //DSCL2_LB_MEMORY_CTRL |
16054 | #define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 |
16055 | #define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 |
16056 | #define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
16057 | #define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 |
16058 | #define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L |
16059 | #define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L |
16060 | #define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L |
16061 | #define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L |
16062 | //DSCL2_LB_V_COUNTER |
16063 | #define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
16064 | #define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 |
16065 | #define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL |
16066 | #define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L |
16067 | //DSCL2_DSCL_MEM_PWR_CTRL |
16068 | #define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 |
16069 | #define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 |
16070 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 |
16071 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 |
16072 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 |
16073 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa |
16074 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc |
16075 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe |
16076 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 |
16077 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 |
16078 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 |
16079 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 |
16080 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 |
16081 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a |
16082 | #define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L |
16083 | #define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L |
16084 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L |
16085 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L |
16086 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L |
16087 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L |
16088 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L |
16089 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L |
16090 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L |
16091 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L |
16092 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L |
16093 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L |
16094 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L |
16095 | #define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L |
16096 | //DSCL2_DSCL_MEM_PWR_STATUS |
16097 | #define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 |
16098 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 |
16099 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 |
16100 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 |
16101 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 |
16102 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa |
16103 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc |
16104 | #define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L |
16105 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL |
16106 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L |
16107 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L |
16108 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L |
16109 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L |
16110 | #define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L |
16111 | //DSCL2_OBUF_CONTROL |
16112 | #define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 |
16113 | #define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 |
16114 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 |
16115 | #define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc |
16116 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 |
16117 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 |
16118 | #define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c |
16119 | #define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L |
16120 | #define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L |
16121 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L |
16122 | #define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L |
16123 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L |
16124 | #define DSCL2_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L |
16125 | #define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L |
16126 | //DSCL2_OBUF_MEM_PWR_CTRL |
16127 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 |
16128 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 |
16129 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 |
16130 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L |
16131 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L |
16132 | #define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L |
16133 | |
16134 | |
16135 | // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec |
16136 | //CM2_CM_CONTROL |
16137 | #define CM2_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 |
16138 | #define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 |
16139 | #define CM2_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L |
16140 | #define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L |
16141 | //CM2_CM_COMA_C11_C12 |
16142 | #define CM2_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 |
16143 | #define CM2_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 |
16144 | #define CM2_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL |
16145 | #define CM2_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L |
16146 | //CM2_CM_COMA_C13_C14 |
16147 | #define CM2_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 |
16148 | #define CM2_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 |
16149 | #define CM2_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL |
16150 | #define CM2_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L |
16151 | //CM2_CM_COMA_C21_C22 |
16152 | #define CM2_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 |
16153 | #define CM2_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 |
16154 | #define CM2_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL |
16155 | #define CM2_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L |
16156 | //CM2_CM_COMA_C23_C24 |
16157 | #define CM2_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 |
16158 | #define CM2_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 |
16159 | #define CM2_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL |
16160 | #define CM2_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L |
16161 | //CM2_CM_COMA_C31_C32 |
16162 | #define CM2_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 |
16163 | #define CM2_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 |
16164 | #define CM2_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL |
16165 | #define CM2_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L |
16166 | //CM2_CM_COMA_C33_C34 |
16167 | #define CM2_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 |
16168 | #define CM2_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 |
16169 | #define CM2_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL |
16170 | #define CM2_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L |
16171 | //CM2_CM_COMB_C11_C12 |
16172 | #define CM2_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 |
16173 | #define CM2_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 |
16174 | #define CM2_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL |
16175 | #define CM2_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L |
16176 | //CM2_CM_COMB_C13_C14 |
16177 | #define CM2_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 |
16178 | #define CM2_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 |
16179 | #define CM2_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL |
16180 | #define CM2_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L |
16181 | //CM2_CM_COMB_C21_C22 |
16182 | #define CM2_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 |
16183 | #define CM2_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 |
16184 | #define CM2_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL |
16185 | #define CM2_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L |
16186 | //CM2_CM_COMB_C23_C24 |
16187 | #define CM2_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 |
16188 | #define CM2_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 |
16189 | #define CM2_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL |
16190 | #define CM2_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L |
16191 | //CM2_CM_COMB_C31_C32 |
16192 | #define CM2_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 |
16193 | #define CM2_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 |
16194 | #define CM2_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL |
16195 | #define CM2_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L |
16196 | //CM2_CM_COMB_C33_C34 |
16197 | #define CM2_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 |
16198 | #define CM2_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 |
16199 | #define CM2_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL |
16200 | #define CM2_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L |
16201 | //CM2_CM_IGAM_CONTROL |
16202 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 |
16203 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 |
16204 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 |
16205 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 |
16206 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 |
16207 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 |
16208 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd |
16209 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 |
16210 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 |
16211 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 |
16212 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 |
16213 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 |
16214 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 |
16215 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a |
16216 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L |
16217 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L |
16218 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L |
16219 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L |
16220 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L |
16221 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L |
16222 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L |
16223 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L |
16224 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L |
16225 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L |
16226 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L |
16227 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L |
16228 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L |
16229 | #define CM2_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L |
16230 | //CM2_CM_IGAM_LUT_RW_CONTROL |
16231 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 |
16232 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 |
16233 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 |
16234 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc |
16235 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 |
16236 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L |
16237 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L |
16238 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L |
16239 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L |
16240 | #define CM2_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L |
16241 | //CM2_CM_IGAM_LUT_RW_INDEX |
16242 | #define CM2_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 |
16243 | #define CM2_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL |
16244 | //CM2_CM_IGAM_LUT_SEQ_COLOR |
16245 | #define CM2_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 |
16246 | #define CM2_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL |
16247 | //CM2_CM_IGAM_LUT_30_COLOR |
16248 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 |
16249 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa |
16250 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 |
16251 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL |
16252 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L |
16253 | #define CM2_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L |
16254 | //CM2_CM_IGAM_LUT_PWL_DATA |
16255 | #define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 |
16256 | #define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 |
16257 | #define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL |
16258 | #define CM2_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L |
16259 | //CM2_CM_IGAM_LUT_AUTOFILL |
16260 | #define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 |
16261 | #define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 |
16262 | #define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L |
16263 | #define CM2_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L |
16264 | //CM2_CM_IGAM_LUT_BW_OFFSET_BLUE |
16265 | #define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
16266 | #define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 |
16267 | #define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL |
16268 | #define CM2_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L |
16269 | //CM2_CM_IGAM_LUT_BW_OFFSET_GREEN |
16270 | #define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
16271 | #define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 |
16272 | #define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL |
16273 | #define CM2_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L |
16274 | //CM2_CM_IGAM_LUT_BW_OFFSET_RED |
16275 | #define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
16276 | #define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 |
16277 | #define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL |
16278 | #define CM2_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L |
16279 | //CM2_CM_ICSC_CONTROL |
16280 | #define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 |
16281 | #define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L |
16282 | //CM2_CM_ICSC_C11_C12 |
16283 | #define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 |
16284 | #define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 |
16285 | #define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL |
16286 | #define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L |
16287 | //CM2_CM_ICSC_C13_C14 |
16288 | #define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 |
16289 | #define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 |
16290 | #define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL |
16291 | #define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L |
16292 | //CM2_CM_ICSC_C21_C22 |
16293 | #define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 |
16294 | #define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 |
16295 | #define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL |
16296 | #define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L |
16297 | //CM2_CM_ICSC_C23_C24 |
16298 | #define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 |
16299 | #define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 |
16300 | #define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL |
16301 | #define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L |
16302 | //CM2_CM_ICSC_C31_C32 |
16303 | #define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 |
16304 | #define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 |
16305 | #define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL |
16306 | #define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L |
16307 | //CM2_CM_ICSC_C33_C34 |
16308 | #define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 |
16309 | #define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 |
16310 | #define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL |
16311 | #define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L |
16312 | //CM2_CM_GAMUT_REMAP_CONTROL |
16313 | #define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 |
16314 | #define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L |
16315 | //CM2_CM_GAMUT_REMAP_C11_C12 |
16316 | #define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 |
16317 | #define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 |
16318 | #define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL |
16319 | #define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L |
16320 | //CM2_CM_GAMUT_REMAP_C13_C14 |
16321 | #define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 |
16322 | #define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 |
16323 | #define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL |
16324 | #define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L |
16325 | //CM2_CM_GAMUT_REMAP_C21_C22 |
16326 | #define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 |
16327 | #define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 |
16328 | #define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL |
16329 | #define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L |
16330 | //CM2_CM_GAMUT_REMAP_C23_C24 |
16331 | #define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 |
16332 | #define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 |
16333 | #define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL |
16334 | #define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L |
16335 | //CM2_CM_GAMUT_REMAP_C31_C32 |
16336 | #define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 |
16337 | #define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 |
16338 | #define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL |
16339 | #define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L |
16340 | //CM2_CM_GAMUT_REMAP_C33_C34 |
16341 | #define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 |
16342 | #define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 |
16343 | #define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL |
16344 | #define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L |
16345 | //CM2_CM_OCSC_CONTROL |
16346 | #define CM2_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 |
16347 | #define CM2_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L |
16348 | //CM2_CM_OCSC_C11_C12 |
16349 | #define CM2_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 |
16350 | #define CM2_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 |
16351 | #define CM2_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL |
16352 | #define CM2_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L |
16353 | //CM2_CM_OCSC_C13_C14 |
16354 | #define CM2_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 |
16355 | #define CM2_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 |
16356 | #define CM2_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL |
16357 | #define CM2_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L |
16358 | //CM2_CM_OCSC_C21_C22 |
16359 | #define CM2_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 |
16360 | #define CM2_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 |
16361 | #define CM2_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL |
16362 | #define CM2_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L |
16363 | //CM2_CM_OCSC_C23_C24 |
16364 | #define CM2_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 |
16365 | #define CM2_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 |
16366 | #define CM2_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL |
16367 | #define CM2_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L |
16368 | //CM2_CM_OCSC_C31_C32 |
16369 | #define CM2_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 |
16370 | #define CM2_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 |
16371 | #define CM2_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL |
16372 | #define CM2_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L |
16373 | //CM2_CM_OCSC_C33_C34 |
16374 | #define CM2_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 |
16375 | #define CM2_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 |
16376 | #define CM2_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL |
16377 | #define CM2_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L |
16378 | //CM2_CM_BNS_VALUES_R |
16379 | #define CM2_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 |
16380 | #define CM2_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 |
16381 | #define CM2_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL |
16382 | #define CM2_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L |
16383 | //CM2_CM_BNS_VALUES_G |
16384 | #define CM2_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 |
16385 | #define CM2_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 |
16386 | #define CM2_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL |
16387 | #define CM2_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L |
16388 | //CM2_CM_BNS_VALUES_B |
16389 | #define CM2_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 |
16390 | #define CM2_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 |
16391 | #define CM2_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL |
16392 | #define CM2_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L |
16393 | //CM2_CM_DGAM_CONTROL |
16394 | #define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 |
16395 | #define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L |
16396 | //CM2_CM_DGAM_LUT_INDEX |
16397 | #define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 |
16398 | #define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL |
16399 | //CM2_CM_DGAM_LUT_DATA |
16400 | #define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 |
16401 | #define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL |
16402 | //CM2_CM_DGAM_LUT_WRITE_EN_MASK |
16403 | #define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
16404 | #define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 |
16405 | #define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
16406 | #define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L |
16407 | //CM2_CM_DGAM_RAMA_START_CNTL_B |
16408 | #define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
16409 | #define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
16410 | #define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
16411 | #define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
16412 | //CM2_CM_DGAM_RAMA_START_CNTL_G |
16413 | #define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
16414 | #define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
16415 | #define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
16416 | #define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
16417 | //CM2_CM_DGAM_RAMA_START_CNTL_R |
16418 | #define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
16419 | #define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
16420 | #define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
16421 | #define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
16422 | //CM2_CM_DGAM_RAMA_SLOPE_CNTL_B |
16423 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
16424 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
16425 | //CM2_CM_DGAM_RAMA_SLOPE_CNTL_G |
16426 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
16427 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
16428 | //CM2_CM_DGAM_RAMA_SLOPE_CNTL_R |
16429 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
16430 | #define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
16431 | //CM2_CM_DGAM_RAMA_END_CNTL1_B |
16432 | #define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
16433 | #define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
16434 | //CM2_CM_DGAM_RAMA_END_CNTL2_B |
16435 | #define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
16436 | #define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
16437 | #define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
16438 | #define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
16439 | //CM2_CM_DGAM_RAMA_END_CNTL1_G |
16440 | #define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
16441 | #define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
16442 | //CM2_CM_DGAM_RAMA_END_CNTL2_G |
16443 | #define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
16444 | #define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
16445 | #define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
16446 | #define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
16447 | //CM2_CM_DGAM_RAMA_END_CNTL1_R |
16448 | #define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
16449 | #define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
16450 | //CM2_CM_DGAM_RAMA_END_CNTL2_R |
16451 | #define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
16452 | #define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
16453 | #define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
16454 | #define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
16455 | //CM2_CM_DGAM_RAMA_REGION_0_1 |
16456 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
16457 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
16458 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
16459 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
16460 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
16461 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
16462 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
16463 | #define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
16464 | //CM2_CM_DGAM_RAMA_REGION_2_3 |
16465 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
16466 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
16467 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
16468 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
16469 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
16470 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
16471 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
16472 | #define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
16473 | //CM2_CM_DGAM_RAMA_REGION_4_5 |
16474 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
16475 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
16476 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
16477 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
16478 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
16479 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
16480 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
16481 | #define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
16482 | //CM2_CM_DGAM_RAMA_REGION_6_7 |
16483 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
16484 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
16485 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
16486 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
16487 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
16488 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
16489 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
16490 | #define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
16491 | //CM2_CM_DGAM_RAMA_REGION_8_9 |
16492 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
16493 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
16494 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
16495 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
16496 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
16497 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
16498 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
16499 | #define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
16500 | //CM2_CM_DGAM_RAMA_REGION_10_11 |
16501 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
16502 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
16503 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
16504 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
16505 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
16506 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
16507 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
16508 | #define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
16509 | //CM2_CM_DGAM_RAMA_REGION_12_13 |
16510 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
16511 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
16512 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
16513 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
16514 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
16515 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
16516 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
16517 | #define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
16518 | //CM2_CM_DGAM_RAMA_REGION_14_15 |
16519 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
16520 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
16521 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
16522 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
16523 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
16524 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
16525 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
16526 | #define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
16527 | //CM2_CM_DGAM_RAMB_START_CNTL_B |
16528 | #define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
16529 | #define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
16530 | #define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
16531 | #define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
16532 | //CM2_CM_DGAM_RAMB_START_CNTL_G |
16533 | #define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
16534 | #define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
16535 | #define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
16536 | #define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
16537 | //CM2_CM_DGAM_RAMB_START_CNTL_R |
16538 | #define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
16539 | #define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
16540 | #define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
16541 | #define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
16542 | //CM2_CM_DGAM_RAMB_SLOPE_CNTL_B |
16543 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
16544 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
16545 | //CM2_CM_DGAM_RAMB_SLOPE_CNTL_G |
16546 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
16547 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
16548 | //CM2_CM_DGAM_RAMB_SLOPE_CNTL_R |
16549 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
16550 | #define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
16551 | //CM2_CM_DGAM_RAMB_END_CNTL1_B |
16552 | #define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
16553 | #define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
16554 | //CM2_CM_DGAM_RAMB_END_CNTL2_B |
16555 | #define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
16556 | #define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
16557 | #define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
16558 | #define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
16559 | //CM2_CM_DGAM_RAMB_END_CNTL1_G |
16560 | #define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
16561 | #define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
16562 | //CM2_CM_DGAM_RAMB_END_CNTL2_G |
16563 | #define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
16564 | #define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
16565 | #define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
16566 | #define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
16567 | //CM2_CM_DGAM_RAMB_END_CNTL1_R |
16568 | #define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
16569 | #define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
16570 | //CM2_CM_DGAM_RAMB_END_CNTL2_R |
16571 | #define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
16572 | #define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
16573 | #define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
16574 | #define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
16575 | //CM2_CM_DGAM_RAMB_REGION_0_1 |
16576 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
16577 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
16578 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
16579 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
16580 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
16581 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
16582 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
16583 | #define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
16584 | //CM2_CM_DGAM_RAMB_REGION_2_3 |
16585 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
16586 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
16587 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
16588 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
16589 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
16590 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
16591 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
16592 | #define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
16593 | //CM2_CM_DGAM_RAMB_REGION_4_5 |
16594 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
16595 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
16596 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
16597 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
16598 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
16599 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
16600 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
16601 | #define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
16602 | //CM2_CM_DGAM_RAMB_REGION_6_7 |
16603 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
16604 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
16605 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
16606 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
16607 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
16608 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
16609 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
16610 | #define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
16611 | //CM2_CM_DGAM_RAMB_REGION_8_9 |
16612 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
16613 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
16614 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
16615 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
16616 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
16617 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
16618 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
16619 | #define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
16620 | //CM2_CM_DGAM_RAMB_REGION_10_11 |
16621 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
16622 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
16623 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
16624 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
16625 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
16626 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
16627 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
16628 | #define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
16629 | //CM2_CM_DGAM_RAMB_REGION_12_13 |
16630 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
16631 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
16632 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
16633 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
16634 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
16635 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
16636 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
16637 | #define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
16638 | //CM2_CM_DGAM_RAMB_REGION_14_15 |
16639 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
16640 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
16641 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
16642 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
16643 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
16644 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
16645 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
16646 | #define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
16647 | //CM2_CM_RGAM_CONTROL |
16648 | #define CM2_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 |
16649 | #define CM2_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L |
16650 | //CM2_CM_RGAM_LUT_INDEX |
16651 | #define CM2_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 |
16652 | #define CM2_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL |
16653 | //CM2_CM_RGAM_LUT_DATA |
16654 | #define CM2_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 |
16655 | #define CM2_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL |
16656 | //CM2_CM_RGAM_LUT_WRITE_EN_MASK |
16657 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
16658 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 |
16659 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 |
16660 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
16661 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L |
16662 | #define CM2_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L |
16663 | //CM2_CM_RGAM_RAMA_START_CNTL_B |
16664 | #define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
16665 | #define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
16666 | #define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
16667 | #define CM2_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
16668 | //CM2_CM_RGAM_RAMA_START_CNTL_G |
16669 | #define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
16670 | #define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
16671 | #define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
16672 | #define CM2_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
16673 | //CM2_CM_RGAM_RAMA_START_CNTL_R |
16674 | #define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
16675 | #define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
16676 | #define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
16677 | #define CM2_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
16678 | //CM2_CM_RGAM_RAMA_SLOPE_CNTL_B |
16679 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
16680 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
16681 | //CM2_CM_RGAM_RAMA_SLOPE_CNTL_G |
16682 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
16683 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
16684 | //CM2_CM_RGAM_RAMA_SLOPE_CNTL_R |
16685 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
16686 | #define CM2_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
16687 | //CM2_CM_RGAM_RAMA_END_CNTL1_B |
16688 | #define CM2_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
16689 | #define CM2_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
16690 | //CM2_CM_RGAM_RAMA_END_CNTL2_B |
16691 | #define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
16692 | #define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
16693 | #define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
16694 | #define CM2_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
16695 | //CM2_CM_RGAM_RAMA_END_CNTL1_G |
16696 | #define CM2_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
16697 | #define CM2_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
16698 | //CM2_CM_RGAM_RAMA_END_CNTL2_G |
16699 | #define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
16700 | #define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
16701 | #define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
16702 | #define CM2_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
16703 | //CM2_CM_RGAM_RAMA_END_CNTL1_R |
16704 | #define CM2_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
16705 | #define CM2_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
16706 | //CM2_CM_RGAM_RAMA_END_CNTL2_R |
16707 | #define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
16708 | #define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
16709 | #define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
16710 | #define CM2_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
16711 | //CM2_CM_RGAM_RAMA_REGION_0_1 |
16712 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
16713 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
16714 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
16715 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
16716 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
16717 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
16718 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
16719 | #define CM2_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
16720 | //CM2_CM_RGAM_RAMA_REGION_2_3 |
16721 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
16722 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
16723 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
16724 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
16725 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
16726 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
16727 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
16728 | #define CM2_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
16729 | //CM2_CM_RGAM_RAMA_REGION_4_5 |
16730 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
16731 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
16732 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
16733 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
16734 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
16735 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
16736 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
16737 | #define CM2_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
16738 | //CM2_CM_RGAM_RAMA_REGION_6_7 |
16739 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
16740 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
16741 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
16742 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
16743 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
16744 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
16745 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
16746 | #define CM2_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
16747 | //CM2_CM_RGAM_RAMA_REGION_8_9 |
16748 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
16749 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
16750 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
16751 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
16752 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
16753 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
16754 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
16755 | #define CM2_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
16756 | //CM2_CM_RGAM_RAMA_REGION_10_11 |
16757 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
16758 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
16759 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
16760 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
16761 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
16762 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
16763 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
16764 | #define CM2_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
16765 | //CM2_CM_RGAM_RAMA_REGION_12_13 |
16766 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
16767 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
16768 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
16769 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
16770 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
16771 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
16772 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
16773 | #define CM2_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
16774 | //CM2_CM_RGAM_RAMA_REGION_14_15 |
16775 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
16776 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
16777 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
16778 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
16779 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
16780 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
16781 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
16782 | #define CM2_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
16783 | //CM2_CM_RGAM_RAMA_REGION_16_17 |
16784 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
16785 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
16786 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
16787 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
16788 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
16789 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
16790 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
16791 | #define CM2_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
16792 | //CM2_CM_RGAM_RAMA_REGION_18_19 |
16793 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
16794 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
16795 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
16796 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
16797 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
16798 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
16799 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
16800 | #define CM2_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
16801 | //CM2_CM_RGAM_RAMA_REGION_20_21 |
16802 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
16803 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
16804 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
16805 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
16806 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
16807 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
16808 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
16809 | #define CM2_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
16810 | //CM2_CM_RGAM_RAMA_REGION_22_23 |
16811 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
16812 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
16813 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
16814 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
16815 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
16816 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
16817 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
16818 | #define CM2_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
16819 | //CM2_CM_RGAM_RAMA_REGION_24_25 |
16820 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
16821 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
16822 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
16823 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
16824 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
16825 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
16826 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
16827 | #define CM2_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
16828 | //CM2_CM_RGAM_RAMA_REGION_26_27 |
16829 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
16830 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
16831 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
16832 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
16833 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
16834 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
16835 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
16836 | #define CM2_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
16837 | //CM2_CM_RGAM_RAMA_REGION_28_29 |
16838 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
16839 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
16840 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
16841 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
16842 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
16843 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
16844 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
16845 | #define CM2_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
16846 | //CM2_CM_RGAM_RAMA_REGION_30_31 |
16847 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
16848 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
16849 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
16850 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
16851 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
16852 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
16853 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
16854 | #define CM2_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
16855 | //CM2_CM_RGAM_RAMA_REGION_32_33 |
16856 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
16857 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
16858 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
16859 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
16860 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
16861 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
16862 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
16863 | #define CM2_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
16864 | //CM2_CM_RGAM_RAMB_START_CNTL_B |
16865 | #define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
16866 | #define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
16867 | #define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
16868 | #define CM2_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
16869 | //CM2_CM_RGAM_RAMB_START_CNTL_G |
16870 | #define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
16871 | #define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
16872 | #define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
16873 | #define CM2_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
16874 | //CM2_CM_RGAM_RAMB_START_CNTL_R |
16875 | #define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
16876 | #define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
16877 | #define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
16878 | #define CM2_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
16879 | //CM2_CM_RGAM_RAMB_SLOPE_CNTL_B |
16880 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
16881 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
16882 | //CM2_CM_RGAM_RAMB_SLOPE_CNTL_G |
16883 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
16884 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
16885 | //CM2_CM_RGAM_RAMB_SLOPE_CNTL_R |
16886 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
16887 | #define CM2_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
16888 | //CM2_CM_RGAM_RAMB_END_CNTL1_B |
16889 | #define CM2_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
16890 | #define CM2_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
16891 | //CM2_CM_RGAM_RAMB_END_CNTL2_B |
16892 | #define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
16893 | #define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
16894 | #define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
16895 | #define CM2_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
16896 | //CM2_CM_RGAM_RAMB_END_CNTL1_G |
16897 | #define CM2_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
16898 | #define CM2_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
16899 | //CM2_CM_RGAM_RAMB_END_CNTL2_G |
16900 | #define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
16901 | #define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
16902 | #define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
16903 | #define CM2_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
16904 | //CM2_CM_RGAM_RAMB_END_CNTL1_R |
16905 | #define CM2_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
16906 | #define CM2_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
16907 | //CM2_CM_RGAM_RAMB_END_CNTL2_R |
16908 | #define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
16909 | #define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
16910 | #define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
16911 | #define CM2_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
16912 | //CM2_CM_RGAM_RAMB_REGION_0_1 |
16913 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
16914 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
16915 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
16916 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
16917 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
16918 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
16919 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
16920 | #define CM2_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
16921 | //CM2_CM_RGAM_RAMB_REGION_2_3 |
16922 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
16923 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
16924 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
16925 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
16926 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
16927 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
16928 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
16929 | #define CM2_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
16930 | //CM2_CM_RGAM_RAMB_REGION_4_5 |
16931 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
16932 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
16933 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
16934 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
16935 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
16936 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
16937 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
16938 | #define CM2_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
16939 | //CM2_CM_RGAM_RAMB_REGION_6_7 |
16940 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
16941 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
16942 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
16943 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
16944 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
16945 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
16946 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
16947 | #define CM2_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
16948 | //CM2_CM_RGAM_RAMB_REGION_8_9 |
16949 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
16950 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
16951 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
16952 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
16953 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
16954 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
16955 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
16956 | #define CM2_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
16957 | //CM2_CM_RGAM_RAMB_REGION_10_11 |
16958 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
16959 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
16960 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
16961 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
16962 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
16963 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
16964 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
16965 | #define CM2_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
16966 | //CM2_CM_RGAM_RAMB_REGION_12_13 |
16967 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
16968 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
16969 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
16970 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
16971 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
16972 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
16973 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
16974 | #define CM2_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
16975 | //CM2_CM_RGAM_RAMB_REGION_14_15 |
16976 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
16977 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
16978 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
16979 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
16980 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
16981 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
16982 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
16983 | #define CM2_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
16984 | //CM2_CM_RGAM_RAMB_REGION_16_17 |
16985 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
16986 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
16987 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
16988 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
16989 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
16990 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
16991 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
16992 | #define CM2_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
16993 | //CM2_CM_RGAM_RAMB_REGION_18_19 |
16994 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
16995 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
16996 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
16997 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
16998 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
16999 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
17000 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
17001 | #define CM2_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
17002 | //CM2_CM_RGAM_RAMB_REGION_20_21 |
17003 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
17004 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
17005 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
17006 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
17007 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
17008 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
17009 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
17010 | #define CM2_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
17011 | //CM2_CM_RGAM_RAMB_REGION_22_23 |
17012 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
17013 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
17014 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
17015 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
17016 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
17017 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
17018 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
17019 | #define CM2_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
17020 | //CM2_CM_RGAM_RAMB_REGION_24_25 |
17021 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
17022 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
17023 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
17024 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
17025 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
17026 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
17027 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
17028 | #define CM2_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
17029 | //CM2_CM_RGAM_RAMB_REGION_26_27 |
17030 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
17031 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
17032 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
17033 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
17034 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
17035 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
17036 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
17037 | #define CM2_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
17038 | //CM2_CM_RGAM_RAMB_REGION_28_29 |
17039 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
17040 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
17041 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
17042 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
17043 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
17044 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
17045 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
17046 | #define CM2_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
17047 | //CM2_CM_RGAM_RAMB_REGION_30_31 |
17048 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
17049 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
17050 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
17051 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
17052 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
17053 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
17054 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
17055 | #define CM2_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
17056 | //CM2_CM_RGAM_RAMB_REGION_32_33 |
17057 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
17058 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
17059 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
17060 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
17061 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
17062 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
17063 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
17064 | #define CM2_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
17065 | //CM2_CM_HDR_MULT_COEF |
17066 | #define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 |
17067 | #define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL |
17068 | //CM2_CM_RANGE_CLAMP_CONTROL_R |
17069 | #define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 |
17070 | #define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 |
17071 | #define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL |
17072 | #define CM2_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L |
17073 | //CM2_CM_RANGE_CLAMP_CONTROL_G |
17074 | #define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 |
17075 | #define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 |
17076 | #define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL |
17077 | #define CM2_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L |
17078 | //CM2_CM_RANGE_CLAMP_CONTROL_B |
17079 | #define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 |
17080 | #define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 |
17081 | #define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL |
17082 | #define CM2_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L |
17083 | //CM2_CM_DENORM_CONTROL |
17084 | #define CM2_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 |
17085 | #define CM2_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 |
17086 | #define CM2_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L |
17087 | #define CM2_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L |
17088 | //CM2_CM_CMOUT_CONTROL |
17089 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
17090 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 |
17091 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 |
17092 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc |
17093 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 |
17094 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 |
17095 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 |
17096 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL |
17097 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L |
17098 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L |
17099 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L |
17100 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L |
17101 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L |
17102 | #define CM2_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L |
17103 | //CM2_CM_CMOUT_RANDOM_SEEDS |
17104 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 |
17105 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 |
17106 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 |
17107 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL |
17108 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L |
17109 | #define CM2_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L |
17110 | //CM2_CM_MEM_PWR_CTRL |
17111 | #define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 |
17112 | #define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 |
17113 | #define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 |
17114 | #define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 |
17115 | #define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L |
17116 | #define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L |
17117 | #define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L |
17118 | #define CM2_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L |
17119 | //CM2_CM_MEM_PWR_STATUS |
17120 | #define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 |
17121 | #define CM2_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 |
17122 | #define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L |
17123 | #define CM2_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL |
17124 | |
17125 | |
17126 | // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
17127 | //DC_PERFMON14_PERFCOUNTER_CNTL |
17128 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
17129 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
17130 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
17131 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
17132 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
17133 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
17134 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
17135 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
17136 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
17137 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
17138 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
17139 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
17140 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
17141 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
17142 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
17143 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
17144 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
17145 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
17146 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
17147 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
17148 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
17149 | #define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
17150 | //DC_PERFMON14_PERFCOUNTER_CNTL2 |
17151 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
17152 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
17153 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
17154 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
17155 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
17156 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
17157 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
17158 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
17159 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
17160 | #define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
17161 | //DC_PERFMON14_PERFCOUNTER_STATE |
17162 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
17163 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
17164 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
17165 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
17166 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
17167 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
17168 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
17169 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
17170 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
17171 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
17172 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
17173 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
17174 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
17175 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
17176 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
17177 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
17178 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
17179 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
17180 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
17181 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
17182 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
17183 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
17184 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
17185 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
17186 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
17187 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
17188 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
17189 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
17190 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
17191 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
17192 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
17193 | #define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
17194 | //DC_PERFMON14_PERFMON_CNTL |
17195 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
17196 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
17197 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
17198 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
17199 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
17200 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
17201 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
17202 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
17203 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
17204 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
17205 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
17206 | #define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
17207 | //DC_PERFMON14_PERFMON_CNTL2 |
17208 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
17209 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
17210 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
17211 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
17212 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
17213 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
17214 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
17215 | #define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
17216 | //DC_PERFMON14_PERFMON_CVALUE_INT_MISC |
17217 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
17218 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
17219 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
17220 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
17221 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
17222 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
17223 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
17224 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
17225 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
17226 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
17227 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
17228 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
17229 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
17230 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
17231 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
17232 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
17233 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
17234 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
17235 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
17236 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
17237 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
17238 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
17239 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
17240 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
17241 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
17242 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
17243 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
17244 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
17245 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
17246 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
17247 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
17248 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
17249 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
17250 | #define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
17251 | //DC_PERFMON14_PERFMON_CVALUE_LOW |
17252 | #define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
17253 | #define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
17254 | //DC_PERFMON14_PERFMON_HI |
17255 | #define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
17256 | #define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
17257 | #define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
17258 | #define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
17259 | //DC_PERFMON14_PERFMON_LOW |
17260 | #define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
17261 | #define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
17262 | |
17263 | |
17264 | // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec |
17265 | //DPP_TOP3_DPP_CONTROL |
17266 | #define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 |
17267 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 |
17268 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa |
17269 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc |
17270 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 |
17271 | #define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 |
17272 | #define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 |
17273 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL__SHIFT 0x18 |
17274 | #define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c |
17275 | #define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L |
17276 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L |
17277 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L |
17278 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L |
17279 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L |
17280 | #define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L |
17281 | #define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L |
17282 | #define DPP_TOP3_DPP_CONTROL__DPPCLK_RATE_CONTROL_MASK 0x01000000L |
17283 | #define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L |
17284 | //DPP_TOP3_DPP_SOFT_RESET |
17285 | #define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 |
17286 | #define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 |
17287 | #define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 |
17288 | #define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc |
17289 | #define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L |
17290 | #define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L |
17291 | #define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L |
17292 | #define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L |
17293 | //DPP_TOP3_DPP_CRC_VAL_R_G |
17294 | #define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 |
17295 | #define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 |
17296 | #define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL |
17297 | #define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L |
17298 | //DPP_TOP3_DPP_CRC_VAL_B_A |
17299 | #define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 |
17300 | #define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 |
17301 | #define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL |
17302 | #define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L |
17303 | //DPP_TOP3_DPP_CRC_CTRL |
17304 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 |
17305 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 |
17306 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 |
17307 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 |
17308 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 |
17309 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 |
17310 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 |
17311 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa |
17312 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc |
17313 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf |
17314 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 |
17315 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L |
17316 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L |
17317 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L |
17318 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L |
17319 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L |
17320 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L |
17321 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L |
17322 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L |
17323 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L |
17324 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L |
17325 | #define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L |
17326 | //DPP_TOP3_HOST_READ_CONTROL |
17327 | #define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 |
17328 | #define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL |
17329 | |
17330 | |
17331 | // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec |
17332 | //CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT |
17333 | #define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 |
17334 | #define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL |
17335 | //CNVC_CFG3_FORMAT_CONTROL |
17336 | #define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 |
17337 | #define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 |
17338 | #define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 |
17339 | #define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc |
17340 | #define CNVC_CFG3_FORMAT_CONTROL__OUTPUT_FP__SHIFT 0x10 |
17341 | #define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 |
17342 | #define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L |
17343 | #define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L |
17344 | #define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L |
17345 | #define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L |
17346 | #define CNVC_CFG3_FORMAT_CONTROL__OUTPUT_FP_MASK 0x00010000L |
17347 | #define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L |
17348 | //CNVC_CFG3_FCNV_FP_SCALE_BIAS |
17349 | #define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE__SHIFT 0x0 |
17350 | #define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS__SHIFT 0x10 |
17351 | #define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_SCALE_MASK 0x0000FFFFL |
17352 | #define CNVC_CFG3_FCNV_FP_SCALE_BIAS__FCNV_FP_BIAS_MASK 0xFFFF0000L |
17353 | //CNVC_CFG3_DENORM_CONTROL |
17354 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_SCALE__SHIFT 0x0 |
17355 | #define CNVC_CFG3_DENORM_CONTROL__CLAMP_POSITIVE__SHIFT 0xf |
17356 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_BIAS__SHIFT 0x10 |
17357 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_TRUNCATE__SHIFT 0x1f |
17358 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_SCALE_MASK 0x00007FFFL |
17359 | #define CNVC_CFG3_DENORM_CONTROL__CLAMP_POSITIVE_MASK 0x00008000L |
17360 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_BIAS_MASK 0x7FFF0000L |
17361 | #define CNVC_CFG3_DENORM_CONTROL__DENORM_TRUNCATE_MASK 0x80000000L |
17362 | //CNVC_CFG3_COLOR_KEYER_CONTROL |
17363 | #define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 |
17364 | #define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 |
17365 | #define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L |
17366 | #define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L |
17367 | //CNVC_CFG3_COLOR_KEYER_ALPHA |
17368 | #define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 |
17369 | #define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 |
17370 | #define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL |
17371 | #define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L |
17372 | //CNVC_CFG3_COLOR_KEYER_RED |
17373 | #define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 |
17374 | #define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 |
17375 | #define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL |
17376 | #define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L |
17377 | //CNVC_CFG3_COLOR_KEYER_GREEN |
17378 | #define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 |
17379 | #define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 |
17380 | #define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL |
17381 | #define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L |
17382 | //CNVC_CFG3_COLOR_KEYER_BLUE |
17383 | #define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 |
17384 | #define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 |
17385 | #define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL |
17386 | #define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L |
17387 | |
17388 | |
17389 | // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec |
17390 | //CNVC_CUR3_CURSOR0_CONTROL |
17391 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 |
17392 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 |
17393 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_INVERT_MODE__SHIFT 0x2 |
17394 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 |
17395 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x6 |
17396 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MAX__SHIFT 0x8 |
17397 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MIN__SHIFT 0x14 |
17398 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L |
17399 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L |
17400 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_INVERT_MODE_MASK 0x00000004L |
17401 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000030L |
17402 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00000040L |
17403 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MAX_MASK 0x000FFF00L |
17404 | #define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MIN_MASK 0xFFF00000L |
17405 | //CNVC_CUR3_CURSOR0_COLOR0 |
17406 | #define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 |
17407 | #define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL |
17408 | //CNVC_CUR3_CURSOR0_COLOR1 |
17409 | #define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 |
17410 | #define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL |
17411 | //CNVC_CUR3_CURSOR0_FP_SCALE_BIAS |
17412 | #define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 |
17413 | #define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 |
17414 | #define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL |
17415 | #define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L |
17416 | |
17417 | |
17418 | // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec |
17419 | //DSCL3_SCL_COEF_RAM_TAP_SELECT |
17420 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
17421 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 |
17422 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
17423 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L |
17424 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L |
17425 | #define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L |
17426 | //DSCL3_SCL_COEF_RAM_TAP_DATA |
17427 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
17428 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
17429 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
17430 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
17431 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL |
17432 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L |
17433 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L |
17434 | #define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L |
17435 | //DSCL3_SCL_MODE |
17436 | #define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 |
17437 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 |
17438 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc |
17439 | #define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 |
17440 | #define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 |
17441 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 |
17442 | #define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L |
17443 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L |
17444 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L |
17445 | #define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L |
17446 | #define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L |
17447 | #define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L |
17448 | //DSCL3_SCL_TAP_CONTROL |
17449 | #define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 |
17450 | #define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 |
17451 | #define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 |
17452 | #define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc |
17453 | #define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L |
17454 | #define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L |
17455 | #define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L |
17456 | #define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L |
17457 | //DSCL3_DSCL_CONTROL |
17458 | #define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
17459 | #define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L |
17460 | //DSCL3_DSCL_2TAP_CONTROL |
17461 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 |
17462 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 |
17463 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 |
17464 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 |
17465 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 |
17466 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 |
17467 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L |
17468 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L |
17469 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L |
17470 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L |
17471 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L |
17472 | #define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L |
17473 | //DSCL3_SCL_MANUAL_REPLICATE_CONTROL |
17474 | #define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
17475 | #define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
17476 | #define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL |
17477 | #define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L |
17478 | //DSCL3_SCL_HORZ_FILTER_SCALE_RATIO |
17479 | #define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
17480 | #define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL |
17481 | //DSCL3_SCL_HORZ_FILTER_INIT |
17482 | #define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
17483 | #define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
17484 | #define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL |
17485 | #define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L |
17486 | //DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C |
17487 | #define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 |
17488 | #define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL |
17489 | //DSCL3_SCL_HORZ_FILTER_INIT_C |
17490 | #define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 |
17491 | #define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 |
17492 | #define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL |
17493 | #define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L |
17494 | //DSCL3_SCL_VERT_FILTER_SCALE_RATIO |
17495 | #define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
17496 | #define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL |
17497 | //DSCL3_SCL_VERT_FILTER_INIT |
17498 | #define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
17499 | #define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
17500 | #define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL |
17501 | #define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L |
17502 | //DSCL3_SCL_VERT_FILTER_INIT_BOT |
17503 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
17504 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
17505 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL |
17506 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L |
17507 | //DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C |
17508 | #define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 |
17509 | #define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL |
17510 | //DSCL3_SCL_VERT_FILTER_INIT_C |
17511 | #define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 |
17512 | #define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 |
17513 | #define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL |
17514 | #define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L |
17515 | //DSCL3_SCL_VERT_FILTER_INIT_BOT_C |
17516 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 |
17517 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 |
17518 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL |
17519 | #define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L |
17520 | //DSCL3_SCL_BLACK_OFFSET |
17521 | #define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 |
17522 | #define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 |
17523 | #define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL |
17524 | #define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L |
17525 | //DSCL3_DSCL_UPDATE |
17526 | #define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
17527 | #define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L |
17528 | //DSCL3_DSCL_AUTOCAL |
17529 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 |
17530 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 |
17531 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc |
17532 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L |
17533 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L |
17534 | #define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L |
17535 | //DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT |
17536 | #define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
17537 | #define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
17538 | #define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL |
17539 | #define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L |
17540 | //DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM |
17541 | #define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
17542 | #define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
17543 | #define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL |
17544 | #define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L |
17545 | //DSCL3_OTG_H_BLANK |
17546 | #define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 |
17547 | #define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 |
17548 | #define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL |
17549 | #define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L |
17550 | //DSCL3_OTG_V_BLANK |
17551 | #define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 |
17552 | #define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 |
17553 | #define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL |
17554 | #define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L |
17555 | //DSCL3_RECOUT_START |
17556 | #define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 |
17557 | #define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 |
17558 | #define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL |
17559 | #define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L |
17560 | //DSCL3_RECOUT_SIZE |
17561 | #define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 |
17562 | #define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 |
17563 | #define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL |
17564 | #define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L |
17565 | //DSCL3_MPC_SIZE |
17566 | #define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 |
17567 | #define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 |
17568 | #define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL |
17569 | #define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L |
17570 | //DSCL3_LB_DATA_FORMAT |
17571 | #define DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
17572 | #define DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x8 |
17573 | #define DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0xc |
17574 | #define DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x10 |
17575 | #define DSCL3_LB_DATA_FORMAT__DITHER_EN__SHIFT 0x14 |
17576 | #define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x18 |
17577 | #define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
17578 | #define DSCL3_LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x00000003L |
17579 | #define DSCL3_LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x00000100L |
17580 | #define DSCL3_LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x00001000L |
17581 | #define DSCL3_LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x00010000L |
17582 | #define DSCL3_LB_DATA_FORMAT__DITHER_EN_MASK 0x00100000L |
17583 | #define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x01000000L |
17584 | #define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000L |
17585 | //DSCL3_LB_MEMORY_CTRL |
17586 | #define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 |
17587 | #define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 |
17588 | #define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
17589 | #define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 |
17590 | #define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L |
17591 | #define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L |
17592 | #define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L |
17593 | #define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L |
17594 | //DSCL3_LB_V_COUNTER |
17595 | #define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
17596 | #define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 |
17597 | #define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL |
17598 | #define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L |
17599 | //DSCL3_DSCL_MEM_PWR_CTRL |
17600 | #define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 |
17601 | #define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 |
17602 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 |
17603 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 |
17604 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 |
17605 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa |
17606 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc |
17607 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe |
17608 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 |
17609 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 |
17610 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 |
17611 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 |
17612 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 |
17613 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a |
17614 | #define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L |
17615 | #define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L |
17616 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L |
17617 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L |
17618 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L |
17619 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L |
17620 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L |
17621 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L |
17622 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L |
17623 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L |
17624 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L |
17625 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L |
17626 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L |
17627 | #define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L |
17628 | //DSCL3_DSCL_MEM_PWR_STATUS |
17629 | #define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 |
17630 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 |
17631 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 |
17632 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 |
17633 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 |
17634 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa |
17635 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc |
17636 | #define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L |
17637 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL |
17638 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L |
17639 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L |
17640 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L |
17641 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L |
17642 | #define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L |
17643 | //DSCL3_OBUF_CONTROL |
17644 | #define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 |
17645 | #define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 |
17646 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN__SHIFT 0x8 |
17647 | #define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc |
17648 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL__SHIFT 0x10 |
17649 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL__SHIFT 0x18 |
17650 | #define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c |
17651 | #define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L |
17652 | #define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L |
17653 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_UPSCALE_EN_MASK 0x00000100L |
17654 | #define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L |
17655 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE0_SEL_MASK 0x00010000L |
17656 | #define DSCL3_OBUF_CONTROL__OBUF_H_2X_COEF_PHASE1_SEL_MASK 0x01000000L |
17657 | #define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L |
17658 | //DSCL3_OBUF_MEM_PWR_CTRL |
17659 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 |
17660 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 |
17661 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 |
17662 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L |
17663 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L |
17664 | #define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L |
17665 | |
17666 | |
17667 | // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec |
17668 | //CM3_CM_CONTROL |
17669 | #define CM3_CM_CONTROL__CM_BYPASS_EN__SHIFT 0x0 |
17670 | #define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 |
17671 | #define CM3_CM_CONTROL__CM_BYPASS_EN_MASK 0x00000001L |
17672 | #define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L |
17673 | //CM3_CM_COMA_C11_C12 |
17674 | #define CM3_CM_COMA_C11_C12__CM_COMA_C11__SHIFT 0x0 |
17675 | #define CM3_CM_COMA_C11_C12__CM_COMA_C12__SHIFT 0x10 |
17676 | #define CM3_CM_COMA_C11_C12__CM_COMA_C11_MASK 0x0000FFFFL |
17677 | #define CM3_CM_COMA_C11_C12__CM_COMA_C12_MASK 0xFFFF0000L |
17678 | //CM3_CM_COMA_C13_C14 |
17679 | #define CM3_CM_COMA_C13_C14__CM_COMA_C13__SHIFT 0x0 |
17680 | #define CM3_CM_COMA_C13_C14__CM_COMA_C14__SHIFT 0x10 |
17681 | #define CM3_CM_COMA_C13_C14__CM_COMA_C13_MASK 0x0000FFFFL |
17682 | #define CM3_CM_COMA_C13_C14__CM_COMA_C14_MASK 0xFFFF0000L |
17683 | //CM3_CM_COMA_C21_C22 |
17684 | #define CM3_CM_COMA_C21_C22__CM_COMA_C21__SHIFT 0x0 |
17685 | #define CM3_CM_COMA_C21_C22__CM_COMA_C22__SHIFT 0x10 |
17686 | #define CM3_CM_COMA_C21_C22__CM_COMA_C21_MASK 0x0000FFFFL |
17687 | #define CM3_CM_COMA_C21_C22__CM_COMA_C22_MASK 0xFFFF0000L |
17688 | //CM3_CM_COMA_C23_C24 |
17689 | #define CM3_CM_COMA_C23_C24__CM_COMA_C23__SHIFT 0x0 |
17690 | #define CM3_CM_COMA_C23_C24__CM_COMA_C24__SHIFT 0x10 |
17691 | #define CM3_CM_COMA_C23_C24__CM_COMA_C23_MASK 0x0000FFFFL |
17692 | #define CM3_CM_COMA_C23_C24__CM_COMA_C24_MASK 0xFFFF0000L |
17693 | //CM3_CM_COMA_C31_C32 |
17694 | #define CM3_CM_COMA_C31_C32__CM_COMA_C31__SHIFT 0x0 |
17695 | #define CM3_CM_COMA_C31_C32__CM_COMA_C32__SHIFT 0x10 |
17696 | #define CM3_CM_COMA_C31_C32__CM_COMA_C31_MASK 0x0000FFFFL |
17697 | #define CM3_CM_COMA_C31_C32__CM_COMA_C32_MASK 0xFFFF0000L |
17698 | //CM3_CM_COMA_C33_C34 |
17699 | #define CM3_CM_COMA_C33_C34__CM_COMA_C33__SHIFT 0x0 |
17700 | #define CM3_CM_COMA_C33_C34__CM_COMA_C34__SHIFT 0x10 |
17701 | #define CM3_CM_COMA_C33_C34__CM_COMA_C33_MASK 0x0000FFFFL |
17702 | #define CM3_CM_COMA_C33_C34__CM_COMA_C34_MASK 0xFFFF0000L |
17703 | //CM3_CM_COMB_C11_C12 |
17704 | #define CM3_CM_COMB_C11_C12__CM_COMB_C11__SHIFT 0x0 |
17705 | #define CM3_CM_COMB_C11_C12__CM_COMB_C12__SHIFT 0x10 |
17706 | #define CM3_CM_COMB_C11_C12__CM_COMB_C11_MASK 0x0000FFFFL |
17707 | #define CM3_CM_COMB_C11_C12__CM_COMB_C12_MASK 0xFFFF0000L |
17708 | //CM3_CM_COMB_C13_C14 |
17709 | #define CM3_CM_COMB_C13_C14__CM_COMB_C13__SHIFT 0x0 |
17710 | #define CM3_CM_COMB_C13_C14__CM_COMB_C14__SHIFT 0x10 |
17711 | #define CM3_CM_COMB_C13_C14__CM_COMB_C13_MASK 0x0000FFFFL |
17712 | #define CM3_CM_COMB_C13_C14__CM_COMB_C14_MASK 0xFFFF0000L |
17713 | //CM3_CM_COMB_C21_C22 |
17714 | #define CM3_CM_COMB_C21_C22__CM_COMB_C21__SHIFT 0x0 |
17715 | #define CM3_CM_COMB_C21_C22__CM_COMB_C22__SHIFT 0x10 |
17716 | #define CM3_CM_COMB_C21_C22__CM_COMB_C21_MASK 0x0000FFFFL |
17717 | #define CM3_CM_COMB_C21_C22__CM_COMB_C22_MASK 0xFFFF0000L |
17718 | //CM3_CM_COMB_C23_C24 |
17719 | #define CM3_CM_COMB_C23_C24__CM_COMB_C23__SHIFT 0x0 |
17720 | #define CM3_CM_COMB_C23_C24__CM_COMB_C24__SHIFT 0x10 |
17721 | #define CM3_CM_COMB_C23_C24__CM_COMB_C23_MASK 0x0000FFFFL |
17722 | #define CM3_CM_COMB_C23_C24__CM_COMB_C24_MASK 0xFFFF0000L |
17723 | //CM3_CM_COMB_C31_C32 |
17724 | #define CM3_CM_COMB_C31_C32__CM_COMB_C31__SHIFT 0x0 |
17725 | #define CM3_CM_COMB_C31_C32__CM_COMB_C32__SHIFT 0x10 |
17726 | #define CM3_CM_COMB_C31_C32__CM_COMB_C31_MASK 0x0000FFFFL |
17727 | #define CM3_CM_COMB_C31_C32__CM_COMB_C32_MASK 0xFFFF0000L |
17728 | //CM3_CM_COMB_C33_C34 |
17729 | #define CM3_CM_COMB_C33_C34__CM_COMB_C33__SHIFT 0x0 |
17730 | #define CM3_CM_COMB_C33_C34__CM_COMB_C34__SHIFT 0x10 |
17731 | #define CM3_CM_COMB_C33_C34__CM_COMB_C33_MASK 0x0000FFFFL |
17732 | #define CM3_CM_COMB_C33_C34__CM_COMB_C34_MASK 0xFFFF0000L |
17733 | //CM3_CM_IGAM_CONTROL |
17734 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE__SHIFT 0x0 |
17735 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B__SHIFT 0x2 |
17736 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G__SHIFT 0x3 |
17737 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R__SHIFT 0x4 |
17738 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B__SHIFT 0x5 |
17739 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G__SHIFT 0x9 |
17740 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R__SHIFT 0xd |
17741 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B__SHIFT 0x11 |
17742 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G__SHIFT 0x13 |
17743 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R__SHIFT 0x15 |
17744 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN__SHIFT 0x17 |
17745 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN__SHIFT 0x18 |
17746 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN__SHIFT 0x19 |
17747 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT__SHIFT 0x1a |
17748 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_MODE_MASK 0x00000003L |
17749 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_B_MASK 0x00000004L |
17750 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_G_MASK 0x00000008L |
17751 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_DATA_SIGNED_EN_R_MASK 0x00000010L |
17752 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_B_MASK 0x000001E0L |
17753 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_G_MASK 0x00001E00L |
17754 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_INC_R_MASK 0x0001E000L |
17755 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_B_MASK 0x00060000L |
17756 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_G_MASK 0x00180000L |
17757 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_FORMAT_R_MASK 0x00600000L |
17758 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_B_FLOAT_POINT_EN_MASK 0x00800000L |
17759 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_G_FLOAT_POINT_EN_MASK 0x01000000L |
17760 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_LUT_R_FLOAT_POINT_EN_MASK 0x02000000L |
17761 | #define CM3_CM_IGAM_CONTROL__CM_IGAM_INPUT_FORMAT_MASK 0x0C000000L |
17762 | //CM3_CM_IGAM_LUT_RW_CONTROL |
17763 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE__SHIFT 0x0 |
17764 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK__SHIFT 0x4 |
17765 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL__SHIFT 0x8 |
17766 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN__SHIFT 0xc |
17767 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS__SHIFT 0x10 |
17768 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_RW_MODE_MASK 0x00000001L |
17769 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_WRITE_EN_MASK_MASK 0x00000070L |
17770 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_SEL_MASK 0x00000100L |
17771 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_LUT_HOST_EN_MASK 0x00001000L |
17772 | #define CM3_CM_IGAM_LUT_RW_CONTROL__CM_IGAM_DGAM_CONFIG_STATUS_MASK 0x000F0000L |
17773 | //CM3_CM_IGAM_LUT_RW_INDEX |
17774 | #define CM3_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX__SHIFT 0x0 |
17775 | #define CM3_CM_IGAM_LUT_RW_INDEX__CM_IGAM_LUT_RW_INDEX_MASK 0x000000FFL |
17776 | //CM3_CM_IGAM_LUT_SEQ_COLOR |
17777 | #define CM3_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR__SHIFT 0x0 |
17778 | #define CM3_CM_IGAM_LUT_SEQ_COLOR__CM_IGAM_LUT_SEQ_COLOR_MASK 0x0000FFFFL |
17779 | //CM3_CM_IGAM_LUT_30_COLOR |
17780 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE__SHIFT 0x0 |
17781 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN__SHIFT 0xa |
17782 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED__SHIFT 0x14 |
17783 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_BLUE_MASK 0x000003FFL |
17784 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_GREEN_MASK 0x000FFC00L |
17785 | #define CM3_CM_IGAM_LUT_30_COLOR__CM_IGAM_LUT_10_RED_MASK 0x3FF00000L |
17786 | //CM3_CM_IGAM_LUT_PWL_DATA |
17787 | #define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE__SHIFT 0x0 |
17788 | #define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA__SHIFT 0x10 |
17789 | #define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_BASE_MASK 0x0000FFFFL |
17790 | #define CM3_CM_IGAM_LUT_PWL_DATA__CM_IGAM_LUT_PWL_DELTA_MASK 0xFFFF0000L |
17791 | //CM3_CM_IGAM_LUT_AUTOFILL |
17792 | #define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL__SHIFT 0x0 |
17793 | #define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE__SHIFT 0x4 |
17794 | #define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_MASK 0x00000001L |
17795 | #define CM3_CM_IGAM_LUT_AUTOFILL__CM_IGAM_LUT_AUTOFILL_DONE_MASK 0x00000010L |
17796 | //CM3_CM_IGAM_LUT_BW_OFFSET_BLUE |
17797 | #define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
17798 | #define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE__SHIFT 0x10 |
17799 | #define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_BLACK_OFFSET_BLUE_MASK 0x0000FFFFL |
17800 | #define CM3_CM_IGAM_LUT_BW_OFFSET_BLUE__CM_IGAM_LUT_WHITE_OFFSET_BLUE_MASK 0xFFFF0000L |
17801 | //CM3_CM_IGAM_LUT_BW_OFFSET_GREEN |
17802 | #define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
17803 | #define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN__SHIFT 0x10 |
17804 | #define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_BLACK_OFFSET_GREEN_MASK 0x0000FFFFL |
17805 | #define CM3_CM_IGAM_LUT_BW_OFFSET_GREEN__CM_IGAM_LUT_WHITE_OFFSET_GREEN_MASK 0xFFFF0000L |
17806 | //CM3_CM_IGAM_LUT_BW_OFFSET_RED |
17807 | #define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
17808 | #define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED__SHIFT 0x10 |
17809 | #define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_BLACK_OFFSET_RED_MASK 0x0000FFFFL |
17810 | #define CM3_CM_IGAM_LUT_BW_OFFSET_RED__CM_IGAM_LUT_WHITE_OFFSET_RED_MASK 0xFFFF0000L |
17811 | //CM3_CM_ICSC_CONTROL |
17812 | #define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 |
17813 | #define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L |
17814 | //CM3_CM_ICSC_C11_C12 |
17815 | #define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 |
17816 | #define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 |
17817 | #define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL |
17818 | #define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L |
17819 | //CM3_CM_ICSC_C13_C14 |
17820 | #define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 |
17821 | #define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 |
17822 | #define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL |
17823 | #define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L |
17824 | //CM3_CM_ICSC_C21_C22 |
17825 | #define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 |
17826 | #define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 |
17827 | #define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL |
17828 | #define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L |
17829 | //CM3_CM_ICSC_C23_C24 |
17830 | #define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 |
17831 | #define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 |
17832 | #define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL |
17833 | #define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L |
17834 | //CM3_CM_ICSC_C31_C32 |
17835 | #define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 |
17836 | #define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 |
17837 | #define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL |
17838 | #define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L |
17839 | //CM3_CM_ICSC_C33_C34 |
17840 | #define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 |
17841 | #define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 |
17842 | #define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL |
17843 | #define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L |
17844 | //CM3_CM_GAMUT_REMAP_CONTROL |
17845 | #define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 |
17846 | #define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L |
17847 | //CM3_CM_GAMUT_REMAP_C11_C12 |
17848 | #define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 |
17849 | #define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 |
17850 | #define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL |
17851 | #define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L |
17852 | //CM3_CM_GAMUT_REMAP_C13_C14 |
17853 | #define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 |
17854 | #define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 |
17855 | #define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL |
17856 | #define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L |
17857 | //CM3_CM_GAMUT_REMAP_C21_C22 |
17858 | #define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 |
17859 | #define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 |
17860 | #define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL |
17861 | #define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L |
17862 | //CM3_CM_GAMUT_REMAP_C23_C24 |
17863 | #define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 |
17864 | #define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 |
17865 | #define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL |
17866 | #define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L |
17867 | //CM3_CM_GAMUT_REMAP_C31_C32 |
17868 | #define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 |
17869 | #define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 |
17870 | #define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL |
17871 | #define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L |
17872 | //CM3_CM_GAMUT_REMAP_C33_C34 |
17873 | #define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 |
17874 | #define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 |
17875 | #define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL |
17876 | #define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L |
17877 | //CM3_CM_OCSC_CONTROL |
17878 | #define CM3_CM_OCSC_CONTROL__CM_OCSC_MODE__SHIFT 0x0 |
17879 | #define CM3_CM_OCSC_CONTROL__CM_OCSC_MODE_MASK 0x00000007L |
17880 | //CM3_CM_OCSC_C11_C12 |
17881 | #define CM3_CM_OCSC_C11_C12__CM_OCSC_C11__SHIFT 0x0 |
17882 | #define CM3_CM_OCSC_C11_C12__CM_OCSC_C12__SHIFT 0x10 |
17883 | #define CM3_CM_OCSC_C11_C12__CM_OCSC_C11_MASK 0x0000FFFFL |
17884 | #define CM3_CM_OCSC_C11_C12__CM_OCSC_C12_MASK 0xFFFF0000L |
17885 | //CM3_CM_OCSC_C13_C14 |
17886 | #define CM3_CM_OCSC_C13_C14__CM_OCSC_C13__SHIFT 0x0 |
17887 | #define CM3_CM_OCSC_C13_C14__CM_OCSC_C14__SHIFT 0x10 |
17888 | #define CM3_CM_OCSC_C13_C14__CM_OCSC_C13_MASK 0x0000FFFFL |
17889 | #define CM3_CM_OCSC_C13_C14__CM_OCSC_C14_MASK 0xFFFF0000L |
17890 | //CM3_CM_OCSC_C21_C22 |
17891 | #define CM3_CM_OCSC_C21_C22__CM_OCSC_C21__SHIFT 0x0 |
17892 | #define CM3_CM_OCSC_C21_C22__CM_OCSC_C22__SHIFT 0x10 |
17893 | #define CM3_CM_OCSC_C21_C22__CM_OCSC_C21_MASK 0x0000FFFFL |
17894 | #define CM3_CM_OCSC_C21_C22__CM_OCSC_C22_MASK 0xFFFF0000L |
17895 | //CM3_CM_OCSC_C23_C24 |
17896 | #define CM3_CM_OCSC_C23_C24__CM_OCSC_C23__SHIFT 0x0 |
17897 | #define CM3_CM_OCSC_C23_C24__CM_OCSC_C24__SHIFT 0x10 |
17898 | #define CM3_CM_OCSC_C23_C24__CM_OCSC_C23_MASK 0x0000FFFFL |
17899 | #define CM3_CM_OCSC_C23_C24__CM_OCSC_C24_MASK 0xFFFF0000L |
17900 | //CM3_CM_OCSC_C31_C32 |
17901 | #define CM3_CM_OCSC_C31_C32__CM_OCSC_C31__SHIFT 0x0 |
17902 | #define CM3_CM_OCSC_C31_C32__CM_OCSC_C32__SHIFT 0x10 |
17903 | #define CM3_CM_OCSC_C31_C32__CM_OCSC_C31_MASK 0x0000FFFFL |
17904 | #define CM3_CM_OCSC_C31_C32__CM_OCSC_C32_MASK 0xFFFF0000L |
17905 | //CM3_CM_OCSC_C33_C34 |
17906 | #define CM3_CM_OCSC_C33_C34__CM_OCSC_C33__SHIFT 0x0 |
17907 | #define CM3_CM_OCSC_C33_C34__CM_OCSC_C34__SHIFT 0x10 |
17908 | #define CM3_CM_OCSC_C33_C34__CM_OCSC_C33_MASK 0x0000FFFFL |
17909 | #define CM3_CM_OCSC_C33_C34__CM_OCSC_C34_MASK 0xFFFF0000L |
17910 | //CM3_CM_BNS_VALUES_R |
17911 | #define CM3_CM_BNS_VALUES_R__CM_BNS_BIAS_R__SHIFT 0x0 |
17912 | #define CM3_CM_BNS_VALUES_R__CM_BNS_SCALE_R__SHIFT 0x10 |
17913 | #define CM3_CM_BNS_VALUES_R__CM_BNS_BIAS_R_MASK 0x0000FFFFL |
17914 | #define CM3_CM_BNS_VALUES_R__CM_BNS_SCALE_R_MASK 0xFFFF0000L |
17915 | //CM3_CM_BNS_VALUES_G |
17916 | #define CM3_CM_BNS_VALUES_G__CM_BNS_BIAS_G__SHIFT 0x0 |
17917 | #define CM3_CM_BNS_VALUES_G__CM_BNS_SCALE_G__SHIFT 0x10 |
17918 | #define CM3_CM_BNS_VALUES_G__CM_BNS_BIAS_G_MASK 0x0000FFFFL |
17919 | #define CM3_CM_BNS_VALUES_G__CM_BNS_SCALE_G_MASK 0xFFFF0000L |
17920 | //CM3_CM_BNS_VALUES_B |
17921 | #define CM3_CM_BNS_VALUES_B__CM_BNS_BIAS_B__SHIFT 0x0 |
17922 | #define CM3_CM_BNS_VALUES_B__CM_BNS_SCALE_B__SHIFT 0x10 |
17923 | #define CM3_CM_BNS_VALUES_B__CM_BNS_BIAS_B_MASK 0x0000FFFFL |
17924 | #define CM3_CM_BNS_VALUES_B__CM_BNS_SCALE_B_MASK 0xFFFF0000L |
17925 | //CM3_CM_DGAM_CONTROL |
17926 | #define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 |
17927 | #define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L |
17928 | //CM3_CM_DGAM_LUT_INDEX |
17929 | #define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 |
17930 | #define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL |
17931 | //CM3_CM_DGAM_LUT_DATA |
17932 | #define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 |
17933 | #define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL |
17934 | //CM3_CM_DGAM_LUT_WRITE_EN_MASK |
17935 | #define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
17936 | #define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 |
17937 | #define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
17938 | #define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L |
17939 | //CM3_CM_DGAM_RAMA_START_CNTL_B |
17940 | #define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
17941 | #define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
17942 | #define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
17943 | #define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
17944 | //CM3_CM_DGAM_RAMA_START_CNTL_G |
17945 | #define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
17946 | #define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
17947 | #define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
17948 | #define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
17949 | //CM3_CM_DGAM_RAMA_START_CNTL_R |
17950 | #define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
17951 | #define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
17952 | #define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
17953 | #define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
17954 | //CM3_CM_DGAM_RAMA_SLOPE_CNTL_B |
17955 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
17956 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
17957 | //CM3_CM_DGAM_RAMA_SLOPE_CNTL_G |
17958 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
17959 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
17960 | //CM3_CM_DGAM_RAMA_SLOPE_CNTL_R |
17961 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
17962 | #define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
17963 | //CM3_CM_DGAM_RAMA_END_CNTL1_B |
17964 | #define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
17965 | #define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
17966 | //CM3_CM_DGAM_RAMA_END_CNTL2_B |
17967 | #define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
17968 | #define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
17969 | #define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
17970 | #define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
17971 | //CM3_CM_DGAM_RAMA_END_CNTL1_G |
17972 | #define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
17973 | #define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
17974 | //CM3_CM_DGAM_RAMA_END_CNTL2_G |
17975 | #define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
17976 | #define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
17977 | #define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
17978 | #define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
17979 | //CM3_CM_DGAM_RAMA_END_CNTL1_R |
17980 | #define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
17981 | #define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
17982 | //CM3_CM_DGAM_RAMA_END_CNTL2_R |
17983 | #define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
17984 | #define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
17985 | #define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
17986 | #define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
17987 | //CM3_CM_DGAM_RAMA_REGION_0_1 |
17988 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
17989 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
17990 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
17991 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
17992 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
17993 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
17994 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
17995 | #define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
17996 | //CM3_CM_DGAM_RAMA_REGION_2_3 |
17997 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
17998 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
17999 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
18000 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
18001 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
18002 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
18003 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
18004 | #define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
18005 | //CM3_CM_DGAM_RAMA_REGION_4_5 |
18006 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
18007 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
18008 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
18009 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
18010 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
18011 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
18012 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
18013 | #define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
18014 | //CM3_CM_DGAM_RAMA_REGION_6_7 |
18015 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
18016 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
18017 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
18018 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
18019 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
18020 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
18021 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
18022 | #define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
18023 | //CM3_CM_DGAM_RAMA_REGION_8_9 |
18024 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
18025 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
18026 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
18027 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
18028 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
18029 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
18030 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
18031 | #define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
18032 | //CM3_CM_DGAM_RAMA_REGION_10_11 |
18033 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
18034 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
18035 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
18036 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
18037 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
18038 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
18039 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
18040 | #define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
18041 | //CM3_CM_DGAM_RAMA_REGION_12_13 |
18042 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
18043 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
18044 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
18045 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
18046 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
18047 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
18048 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
18049 | #define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
18050 | //CM3_CM_DGAM_RAMA_REGION_14_15 |
18051 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
18052 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
18053 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
18054 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
18055 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
18056 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
18057 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
18058 | #define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
18059 | //CM3_CM_DGAM_RAMB_START_CNTL_B |
18060 | #define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
18061 | #define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
18062 | #define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
18063 | #define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
18064 | //CM3_CM_DGAM_RAMB_START_CNTL_G |
18065 | #define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
18066 | #define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
18067 | #define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
18068 | #define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
18069 | //CM3_CM_DGAM_RAMB_START_CNTL_R |
18070 | #define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
18071 | #define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
18072 | #define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
18073 | #define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
18074 | //CM3_CM_DGAM_RAMB_SLOPE_CNTL_B |
18075 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
18076 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
18077 | //CM3_CM_DGAM_RAMB_SLOPE_CNTL_G |
18078 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
18079 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
18080 | //CM3_CM_DGAM_RAMB_SLOPE_CNTL_R |
18081 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
18082 | #define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
18083 | //CM3_CM_DGAM_RAMB_END_CNTL1_B |
18084 | #define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
18085 | #define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
18086 | //CM3_CM_DGAM_RAMB_END_CNTL2_B |
18087 | #define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
18088 | #define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
18089 | #define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
18090 | #define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
18091 | //CM3_CM_DGAM_RAMB_END_CNTL1_G |
18092 | #define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
18093 | #define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
18094 | //CM3_CM_DGAM_RAMB_END_CNTL2_G |
18095 | #define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
18096 | #define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
18097 | #define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
18098 | #define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
18099 | //CM3_CM_DGAM_RAMB_END_CNTL1_R |
18100 | #define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
18101 | #define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
18102 | //CM3_CM_DGAM_RAMB_END_CNTL2_R |
18103 | #define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
18104 | #define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
18105 | #define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
18106 | #define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
18107 | //CM3_CM_DGAM_RAMB_REGION_0_1 |
18108 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
18109 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
18110 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
18111 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
18112 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
18113 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
18114 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
18115 | #define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
18116 | //CM3_CM_DGAM_RAMB_REGION_2_3 |
18117 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
18118 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
18119 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
18120 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
18121 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
18122 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
18123 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
18124 | #define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
18125 | //CM3_CM_DGAM_RAMB_REGION_4_5 |
18126 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
18127 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
18128 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
18129 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
18130 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
18131 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
18132 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
18133 | #define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
18134 | //CM3_CM_DGAM_RAMB_REGION_6_7 |
18135 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
18136 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
18137 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
18138 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
18139 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
18140 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
18141 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
18142 | #define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
18143 | //CM3_CM_DGAM_RAMB_REGION_8_9 |
18144 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
18145 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
18146 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
18147 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
18148 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
18149 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
18150 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
18151 | #define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
18152 | //CM3_CM_DGAM_RAMB_REGION_10_11 |
18153 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
18154 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
18155 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
18156 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
18157 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
18158 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
18159 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
18160 | #define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
18161 | //CM3_CM_DGAM_RAMB_REGION_12_13 |
18162 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
18163 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
18164 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
18165 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
18166 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
18167 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
18168 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
18169 | #define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
18170 | //CM3_CM_DGAM_RAMB_REGION_14_15 |
18171 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
18172 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
18173 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
18174 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
18175 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
18176 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
18177 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
18178 | #define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
18179 | //CM3_CM_RGAM_CONTROL |
18180 | #define CM3_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE__SHIFT 0x0 |
18181 | #define CM3_CM_RGAM_CONTROL__CM_RGAM_LUT_MODE_MASK 0x00000007L |
18182 | //CM3_CM_RGAM_LUT_INDEX |
18183 | #define CM3_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX__SHIFT 0x0 |
18184 | #define CM3_CM_RGAM_LUT_INDEX__CM_RGAM_LUT_INDEX_MASK 0x000001FFL |
18185 | //CM3_CM_RGAM_LUT_DATA |
18186 | #define CM3_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA__SHIFT 0x0 |
18187 | #define CM3_CM_RGAM_LUT_DATA__CM_RGAM_LUT_DATA_MASK 0x0007FFFFL |
18188 | //CM3_CM_RGAM_LUT_WRITE_EN_MASK |
18189 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 |
18190 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL__SHIFT 0x4 |
18191 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS__SHIFT 0x8 |
18192 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L |
18193 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_LUT_WRITE_SEL_MASK 0x00000010L |
18194 | #define CM3_CM_RGAM_LUT_WRITE_EN_MASK__CM_RGAM_CONFIG_STATUS_MASK 0x00000700L |
18195 | //CM3_CM_RGAM_RAMA_START_CNTL_B |
18196 | #define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 |
18197 | #define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
18198 | #define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL |
18199 | #define CM3_CM_RGAM_RAMA_START_CNTL_B__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
18200 | //CM3_CM_RGAM_RAMA_START_CNTL_G |
18201 | #define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 |
18202 | #define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
18203 | #define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL |
18204 | #define CM3_CM_RGAM_RAMA_START_CNTL_G__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
18205 | //CM3_CM_RGAM_RAMA_START_CNTL_R |
18206 | #define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 |
18207 | #define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
18208 | #define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL |
18209 | #define CM3_CM_RGAM_RAMA_START_CNTL_R__CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
18210 | //CM3_CM_RGAM_RAMA_SLOPE_CNTL_B |
18211 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
18212 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_B__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
18213 | //CM3_CM_RGAM_RAMA_SLOPE_CNTL_G |
18214 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
18215 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_G__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
18216 | //CM3_CM_RGAM_RAMA_SLOPE_CNTL_R |
18217 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
18218 | #define CM3_CM_RGAM_RAMA_SLOPE_CNTL_R__CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
18219 | //CM3_CM_RGAM_RAMA_END_CNTL1_B |
18220 | #define CM3_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 |
18221 | #define CM3_CM_RGAM_RAMA_END_CNTL1_B__CM_RGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL |
18222 | //CM3_CM_RGAM_RAMA_END_CNTL2_B |
18223 | #define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
18224 | #define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 |
18225 | #define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
18226 | #define CM3_CM_RGAM_RAMA_END_CNTL2_B__CM_RGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
18227 | //CM3_CM_RGAM_RAMA_END_CNTL1_G |
18228 | #define CM3_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 |
18229 | #define CM3_CM_RGAM_RAMA_END_CNTL1_G__CM_RGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL |
18230 | //CM3_CM_RGAM_RAMA_END_CNTL2_G |
18231 | #define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
18232 | #define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 |
18233 | #define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
18234 | #define CM3_CM_RGAM_RAMA_END_CNTL2_G__CM_RGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
18235 | //CM3_CM_RGAM_RAMA_END_CNTL1_R |
18236 | #define CM3_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 |
18237 | #define CM3_CM_RGAM_RAMA_END_CNTL1_R__CM_RGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL |
18238 | //CM3_CM_RGAM_RAMA_END_CNTL2_R |
18239 | #define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
18240 | #define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 |
18241 | #define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
18242 | #define CM3_CM_RGAM_RAMA_END_CNTL2_R__CM_RGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
18243 | //CM3_CM_RGAM_RAMA_REGION_0_1 |
18244 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
18245 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
18246 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
18247 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
18248 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
18249 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
18250 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
18251 | #define CM3_CM_RGAM_RAMA_REGION_0_1__CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
18252 | //CM3_CM_RGAM_RAMA_REGION_2_3 |
18253 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
18254 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
18255 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
18256 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
18257 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
18258 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
18259 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
18260 | #define CM3_CM_RGAM_RAMA_REGION_2_3__CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
18261 | //CM3_CM_RGAM_RAMA_REGION_4_5 |
18262 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
18263 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
18264 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
18265 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
18266 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
18267 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
18268 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
18269 | #define CM3_CM_RGAM_RAMA_REGION_4_5__CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
18270 | //CM3_CM_RGAM_RAMA_REGION_6_7 |
18271 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
18272 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
18273 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
18274 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
18275 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
18276 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
18277 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
18278 | #define CM3_CM_RGAM_RAMA_REGION_6_7__CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
18279 | //CM3_CM_RGAM_RAMA_REGION_8_9 |
18280 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
18281 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
18282 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
18283 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
18284 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
18285 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
18286 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
18287 | #define CM3_CM_RGAM_RAMA_REGION_8_9__CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
18288 | //CM3_CM_RGAM_RAMA_REGION_10_11 |
18289 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
18290 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
18291 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
18292 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
18293 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
18294 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
18295 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
18296 | #define CM3_CM_RGAM_RAMA_REGION_10_11__CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
18297 | //CM3_CM_RGAM_RAMA_REGION_12_13 |
18298 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
18299 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
18300 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
18301 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
18302 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
18303 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
18304 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
18305 | #define CM3_CM_RGAM_RAMA_REGION_12_13__CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
18306 | //CM3_CM_RGAM_RAMA_REGION_14_15 |
18307 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
18308 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
18309 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
18310 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
18311 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
18312 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
18313 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
18314 | #define CM3_CM_RGAM_RAMA_REGION_14_15__CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
18315 | //CM3_CM_RGAM_RAMA_REGION_16_17 |
18316 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
18317 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
18318 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
18319 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
18320 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
18321 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
18322 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
18323 | #define CM3_CM_RGAM_RAMA_REGION_16_17__CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
18324 | //CM3_CM_RGAM_RAMA_REGION_18_19 |
18325 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
18326 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
18327 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
18328 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
18329 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
18330 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
18331 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
18332 | #define CM3_CM_RGAM_RAMA_REGION_18_19__CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
18333 | //CM3_CM_RGAM_RAMA_REGION_20_21 |
18334 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
18335 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
18336 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
18337 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
18338 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
18339 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
18340 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
18341 | #define CM3_CM_RGAM_RAMA_REGION_20_21__CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
18342 | //CM3_CM_RGAM_RAMA_REGION_22_23 |
18343 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
18344 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
18345 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
18346 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
18347 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
18348 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
18349 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
18350 | #define CM3_CM_RGAM_RAMA_REGION_22_23__CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
18351 | //CM3_CM_RGAM_RAMA_REGION_24_25 |
18352 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
18353 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
18354 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
18355 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
18356 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
18357 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
18358 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
18359 | #define CM3_CM_RGAM_RAMA_REGION_24_25__CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
18360 | //CM3_CM_RGAM_RAMA_REGION_26_27 |
18361 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
18362 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
18363 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
18364 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
18365 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
18366 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
18367 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
18368 | #define CM3_CM_RGAM_RAMA_REGION_26_27__CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
18369 | //CM3_CM_RGAM_RAMA_REGION_28_29 |
18370 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
18371 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
18372 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
18373 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
18374 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
18375 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
18376 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
18377 | #define CM3_CM_RGAM_RAMA_REGION_28_29__CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
18378 | //CM3_CM_RGAM_RAMA_REGION_30_31 |
18379 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
18380 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
18381 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
18382 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
18383 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
18384 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
18385 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
18386 | #define CM3_CM_RGAM_RAMA_REGION_30_31__CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
18387 | //CM3_CM_RGAM_RAMA_REGION_32_33 |
18388 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
18389 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
18390 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
18391 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
18392 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
18393 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
18394 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
18395 | #define CM3_CM_RGAM_RAMA_REGION_32_33__CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
18396 | //CM3_CM_RGAM_RAMB_START_CNTL_B |
18397 | #define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 |
18398 | #define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 |
18399 | #define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL |
18400 | #define CM3_CM_RGAM_RAMB_START_CNTL_B__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L |
18401 | //CM3_CM_RGAM_RAMB_START_CNTL_G |
18402 | #define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 |
18403 | #define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 |
18404 | #define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL |
18405 | #define CM3_CM_RGAM_RAMB_START_CNTL_G__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L |
18406 | //CM3_CM_RGAM_RAMB_START_CNTL_R |
18407 | #define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 |
18408 | #define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 |
18409 | #define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL |
18410 | #define CM3_CM_RGAM_RAMB_START_CNTL_R__CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L |
18411 | //CM3_CM_RGAM_RAMB_SLOPE_CNTL_B |
18412 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 |
18413 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_B__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL |
18414 | //CM3_CM_RGAM_RAMB_SLOPE_CNTL_G |
18415 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 |
18416 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_G__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL |
18417 | //CM3_CM_RGAM_RAMB_SLOPE_CNTL_R |
18418 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 |
18419 | #define CM3_CM_RGAM_RAMB_SLOPE_CNTL_R__CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL |
18420 | //CM3_CM_RGAM_RAMB_END_CNTL1_B |
18421 | #define CM3_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 |
18422 | #define CM3_CM_RGAM_RAMB_END_CNTL1_B__CM_RGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL |
18423 | //CM3_CM_RGAM_RAMB_END_CNTL2_B |
18424 | #define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 |
18425 | #define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 |
18426 | #define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL |
18427 | #define CM3_CM_RGAM_RAMB_END_CNTL2_B__CM_RGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L |
18428 | //CM3_CM_RGAM_RAMB_END_CNTL1_G |
18429 | #define CM3_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 |
18430 | #define CM3_CM_RGAM_RAMB_END_CNTL1_G__CM_RGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL |
18431 | //CM3_CM_RGAM_RAMB_END_CNTL2_G |
18432 | #define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 |
18433 | #define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 |
18434 | #define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL |
18435 | #define CM3_CM_RGAM_RAMB_END_CNTL2_G__CM_RGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L |
18436 | //CM3_CM_RGAM_RAMB_END_CNTL1_R |
18437 | #define CM3_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 |
18438 | #define CM3_CM_RGAM_RAMB_END_CNTL1_R__CM_RGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL |
18439 | //CM3_CM_RGAM_RAMB_END_CNTL2_R |
18440 | #define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 |
18441 | #define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 |
18442 | #define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL |
18443 | #define CM3_CM_RGAM_RAMB_END_CNTL2_R__CM_RGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L |
18444 | //CM3_CM_RGAM_RAMB_REGION_0_1 |
18445 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
18446 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
18447 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
18448 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
18449 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL |
18450 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L |
18451 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L |
18452 | #define CM3_CM_RGAM_RAMB_REGION_0_1__CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L |
18453 | //CM3_CM_RGAM_RAMB_REGION_2_3 |
18454 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
18455 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
18456 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
18457 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
18458 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL |
18459 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L |
18460 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L |
18461 | #define CM3_CM_RGAM_RAMB_REGION_2_3__CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L |
18462 | //CM3_CM_RGAM_RAMB_REGION_4_5 |
18463 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
18464 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
18465 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
18466 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
18467 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL |
18468 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L |
18469 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L |
18470 | #define CM3_CM_RGAM_RAMB_REGION_4_5__CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L |
18471 | //CM3_CM_RGAM_RAMB_REGION_6_7 |
18472 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
18473 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
18474 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
18475 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
18476 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL |
18477 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L |
18478 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L |
18479 | #define CM3_CM_RGAM_RAMB_REGION_6_7__CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L |
18480 | //CM3_CM_RGAM_RAMB_REGION_8_9 |
18481 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
18482 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
18483 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
18484 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
18485 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL |
18486 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L |
18487 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L |
18488 | #define CM3_CM_RGAM_RAMB_REGION_8_9__CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L |
18489 | //CM3_CM_RGAM_RAMB_REGION_10_11 |
18490 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
18491 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
18492 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
18493 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
18494 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL |
18495 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L |
18496 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L |
18497 | #define CM3_CM_RGAM_RAMB_REGION_10_11__CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L |
18498 | //CM3_CM_RGAM_RAMB_REGION_12_13 |
18499 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
18500 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
18501 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
18502 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
18503 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL |
18504 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L |
18505 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L |
18506 | #define CM3_CM_RGAM_RAMB_REGION_12_13__CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L |
18507 | //CM3_CM_RGAM_RAMB_REGION_14_15 |
18508 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
18509 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
18510 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
18511 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
18512 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL |
18513 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L |
18514 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L |
18515 | #define CM3_CM_RGAM_RAMB_REGION_14_15__CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L |
18516 | //CM3_CM_RGAM_RAMB_REGION_16_17 |
18517 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 |
18518 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc |
18519 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 |
18520 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c |
18521 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL |
18522 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L |
18523 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L |
18524 | #define CM3_CM_RGAM_RAMB_REGION_16_17__CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L |
18525 | //CM3_CM_RGAM_RAMB_REGION_18_19 |
18526 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 |
18527 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc |
18528 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 |
18529 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c |
18530 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL |
18531 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L |
18532 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L |
18533 | #define CM3_CM_RGAM_RAMB_REGION_18_19__CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L |
18534 | //CM3_CM_RGAM_RAMB_REGION_20_21 |
18535 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 |
18536 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc |
18537 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 |
18538 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c |
18539 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL |
18540 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L |
18541 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L |
18542 | #define CM3_CM_RGAM_RAMB_REGION_20_21__CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L |
18543 | //CM3_CM_RGAM_RAMB_REGION_22_23 |
18544 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 |
18545 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc |
18546 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 |
18547 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c |
18548 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL |
18549 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L |
18550 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L |
18551 | #define CM3_CM_RGAM_RAMB_REGION_22_23__CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L |
18552 | //CM3_CM_RGAM_RAMB_REGION_24_25 |
18553 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 |
18554 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc |
18555 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 |
18556 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c |
18557 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL |
18558 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L |
18559 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L |
18560 | #define CM3_CM_RGAM_RAMB_REGION_24_25__CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L |
18561 | //CM3_CM_RGAM_RAMB_REGION_26_27 |
18562 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 |
18563 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc |
18564 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 |
18565 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c |
18566 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL |
18567 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L |
18568 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L |
18569 | #define CM3_CM_RGAM_RAMB_REGION_26_27__CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L |
18570 | //CM3_CM_RGAM_RAMB_REGION_28_29 |
18571 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 |
18572 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc |
18573 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 |
18574 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c |
18575 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL |
18576 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L |
18577 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L |
18578 | #define CM3_CM_RGAM_RAMB_REGION_28_29__CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L |
18579 | //CM3_CM_RGAM_RAMB_REGION_30_31 |
18580 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 |
18581 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc |
18582 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 |
18583 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c |
18584 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL |
18585 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L |
18586 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L |
18587 | #define CM3_CM_RGAM_RAMB_REGION_30_31__CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L |
18588 | //CM3_CM_RGAM_RAMB_REGION_32_33 |
18589 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 |
18590 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc |
18591 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 |
18592 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c |
18593 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL |
18594 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L |
18595 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L |
18596 | #define CM3_CM_RGAM_RAMB_REGION_32_33__CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L |
18597 | //CM3_CM_HDR_MULT_COEF |
18598 | #define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 |
18599 | #define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL |
18600 | //CM3_CM_RANGE_CLAMP_CONTROL_R |
18601 | #define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R__SHIFT 0x0 |
18602 | #define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R__SHIFT 0x10 |
18603 | #define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MAX_R_MASK 0x0000FFFFL |
18604 | #define CM3_CM_RANGE_CLAMP_CONTROL_R__CM_RANGE_CLAMP_MIN_R_MASK 0xFFFF0000L |
18605 | //CM3_CM_RANGE_CLAMP_CONTROL_G |
18606 | #define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G__SHIFT 0x0 |
18607 | #define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G__SHIFT 0x10 |
18608 | #define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MAX_G_MASK 0x0000FFFFL |
18609 | #define CM3_CM_RANGE_CLAMP_CONTROL_G__CM_RANGE_CLAMP_MIN_G_MASK 0xFFFF0000L |
18610 | //CM3_CM_RANGE_CLAMP_CONTROL_B |
18611 | #define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B__SHIFT 0x0 |
18612 | #define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B__SHIFT 0x10 |
18613 | #define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MAX_B_MASK 0x0000FFFFL |
18614 | #define CM3_CM_RANGE_CLAMP_CONTROL_B__CM_RANGE_CLAMP_MIN_B_MASK 0xFFFF0000L |
18615 | //CM3_CM_DENORM_CONTROL |
18616 | #define CM3_CM_DENORM_CONTROL__CM_DENORM_MODE__SHIFT 0x0 |
18617 | #define CM3_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP__SHIFT 0x4 |
18618 | #define CM3_CM_DENORM_CONTROL__CM_DENORM_MODE_MASK 0x00000007L |
18619 | #define CM3_CM_DENORM_CONTROL__CM_DENORM_ROUND_CLAMP_MASK 0x00000010L |
18620 | //CM3_CM_CMOUT_CONTROL |
18621 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
18622 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN__SHIFT 0x4 |
18623 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE__SHIFT 0x8 |
18624 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH__SHIFT 0xc |
18625 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE__SHIFT 0x10 |
18626 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN__SHIFT 0x14 |
18627 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x18 |
18628 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_ROUND_TRUNC_MODE_MASK 0x0000000FL |
18629 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_EN_MASK 0x00000010L |
18630 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_MODE_MASK 0x00000300L |
18631 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_SPATIAL_DITHER_DEPTH_MASK 0x00003000L |
18632 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_FRAME_RANDOM_ENABLE_MASK 0x00010000L |
18633 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_RGB_RANDOM_EN_MASK 0x00100000L |
18634 | #define CM3_CM_CMOUT_CONTROL__CM_CMOUT_HIGHPASS_RANDOM_ENABLE_MASK 0x01000000L |
18635 | //CM3_CM_CMOUT_RANDOM_SEEDS |
18636 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED__SHIFT 0x0 |
18637 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED__SHIFT 0x8 |
18638 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED__SHIFT 0x10 |
18639 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_R_SEED_MASK 0x000000FFL |
18640 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_G_SEED_MASK 0x0000FF00L |
18641 | #define CM3_CM_CMOUT_RANDOM_SEEDS__CM_CMOUT_RAND_B_SEED_MASK 0x00FF0000L |
18642 | //CM3_CM_MEM_PWR_CTRL |
18643 | #define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 |
18644 | #define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 |
18645 | #define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE__SHIFT 0x4 |
18646 | #define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS__SHIFT 0x6 |
18647 | #define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L |
18648 | #define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L |
18649 | #define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_FORCE_MASK 0x00000030L |
18650 | #define CM3_CM_MEM_PWR_CTRL__RGAM_MEM_PWR_DIS_MASK 0x00000040L |
18651 | //CM3_CM_MEM_PWR_STATUS |
18652 | #define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 |
18653 | #define CM3_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE__SHIFT 0x2 |
18654 | #define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L |
18655 | #define CM3_CM_MEM_PWR_STATUS__RGAM_MEM_PWR_STATE_MASK 0x0000000CL |
18656 | |
18657 | |
18658 | // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
18659 | //DC_PERFMON15_PERFCOUNTER_CNTL |
18660 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
18661 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
18662 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
18663 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
18664 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
18665 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
18666 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
18667 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
18668 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
18669 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
18670 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
18671 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
18672 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
18673 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
18674 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
18675 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
18676 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
18677 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
18678 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
18679 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
18680 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
18681 | #define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
18682 | //DC_PERFMON15_PERFCOUNTER_CNTL2 |
18683 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
18684 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
18685 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
18686 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
18687 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
18688 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
18689 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
18690 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
18691 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
18692 | #define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
18693 | //DC_PERFMON15_PERFCOUNTER_STATE |
18694 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
18695 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
18696 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
18697 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
18698 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
18699 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
18700 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
18701 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
18702 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
18703 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
18704 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
18705 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
18706 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
18707 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
18708 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
18709 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
18710 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
18711 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
18712 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
18713 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
18714 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
18715 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
18716 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
18717 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
18718 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
18719 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
18720 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
18721 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
18722 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
18723 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
18724 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
18725 | #define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
18726 | //DC_PERFMON15_PERFMON_CNTL |
18727 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
18728 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
18729 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
18730 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
18731 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
18732 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
18733 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
18734 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
18735 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
18736 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
18737 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
18738 | #define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
18739 | //DC_PERFMON15_PERFMON_CNTL2 |
18740 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
18741 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
18742 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
18743 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
18744 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
18745 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
18746 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
18747 | #define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
18748 | //DC_PERFMON15_PERFMON_CVALUE_INT_MISC |
18749 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
18750 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
18751 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
18752 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
18753 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
18754 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
18755 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
18756 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
18757 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
18758 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
18759 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
18760 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
18761 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
18762 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
18763 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
18764 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
18765 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
18766 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
18767 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
18768 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
18769 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
18770 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
18771 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
18772 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
18773 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
18774 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
18775 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
18776 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
18777 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
18778 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
18779 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
18780 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
18781 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
18782 | #define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
18783 | //DC_PERFMON15_PERFMON_CVALUE_LOW |
18784 | #define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
18785 | #define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
18786 | //DC_PERFMON15_PERFMON_HI |
18787 | #define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
18788 | #define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
18789 | #define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
18790 | #define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
18791 | //DC_PERFMON15_PERFMON_LOW |
18792 | #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
18793 | #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
18794 | |
18795 | |
18796 | // addressBlock: dce_dc_mpc_mpcc0_dispdec |
18797 | //MPCC0_MPCC_TOP_SEL |
18798 | #define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 |
18799 | #define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL |
18800 | //MPCC0_MPCC_BOT_SEL |
18801 | #define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 |
18802 | #define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL |
18803 | //MPCC0_MPCC_OPP_ID |
18804 | #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 |
18805 | #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL |
18806 | //MPCC0_MPCC_CONTROL |
18807 | #define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 |
18808 | #define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 |
18809 | #define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 |
18810 | #define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 |
18811 | #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 |
18812 | #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 |
18813 | #define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L |
18814 | #define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L |
18815 | #define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L |
18816 | #define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L |
18817 | #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L |
18818 | #define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L |
18819 | //MPCC0_MPCC_SM_CONTROL |
18820 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 |
18821 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 |
18822 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 |
18823 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 |
18824 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
18825 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
18826 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 |
18827 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L |
18828 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL |
18829 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L |
18830 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L |
18831 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L |
18832 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L |
18833 | #define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L |
18834 | //MPCC0_MPCC_UPDATE_LOCK_SEL |
18835 | #define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 |
18836 | #define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 |
18837 | #define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL |
18838 | #define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L |
18839 | //MPCC0_MPCC_TOP_OFFSET |
18840 | #define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 |
18841 | #define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 |
18842 | #define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL |
18843 | #define MPCC0_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L |
18844 | //MPCC0_MPCC_BOT_OFFSET |
18845 | #define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 |
18846 | #define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 |
18847 | #define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL |
18848 | #define MPCC0_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L |
18849 | //MPCC0_MPCC_OFFSET |
18850 | #define MPCC0_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 |
18851 | #define MPCC0_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 |
18852 | #define MPCC0_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL |
18853 | #define MPCC0_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L |
18854 | //MPCC0_MPCC_BG_R_CR |
18855 | #define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 |
18856 | #define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL |
18857 | //MPCC0_MPCC_BG_G_Y |
18858 | #define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 |
18859 | #define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL |
18860 | //MPCC0_MPCC_BG_B_CB |
18861 | #define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 |
18862 | #define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL |
18863 | //MPCC0_MPCC_STALL_STATUS |
18864 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 |
18865 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 |
18866 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc |
18867 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 |
18868 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L |
18869 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L |
18870 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L |
18871 | #define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L |
18872 | //MPCC0_MPCC_STATUS |
18873 | #define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 |
18874 | #define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 |
18875 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 |
18876 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 |
18877 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 |
18878 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 |
18879 | #define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 |
18880 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 |
18881 | #define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 |
18882 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 |
18883 | #define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e |
18884 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f |
18885 | #define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L |
18886 | #define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L |
18887 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L |
18888 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L |
18889 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L |
18890 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L |
18891 | #define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L |
18892 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L |
18893 | #define MPCC0_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L |
18894 | #define MPCC0_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L |
18895 | #define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L |
18896 | #define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L |
18897 | |
18898 | |
18899 | // addressBlock: dce_dc_mpc_mpcc1_dispdec |
18900 | //MPCC1_MPCC_TOP_SEL |
18901 | #define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 |
18902 | #define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL |
18903 | //MPCC1_MPCC_BOT_SEL |
18904 | #define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 |
18905 | #define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL |
18906 | //MPCC1_MPCC_OPP_ID |
18907 | #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 |
18908 | #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL |
18909 | //MPCC1_MPCC_CONTROL |
18910 | #define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 |
18911 | #define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 |
18912 | #define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 |
18913 | #define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 |
18914 | #define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 |
18915 | #define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 |
18916 | #define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L |
18917 | #define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L |
18918 | #define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L |
18919 | #define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L |
18920 | #define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L |
18921 | #define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L |
18922 | //MPCC1_MPCC_SM_CONTROL |
18923 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 |
18924 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 |
18925 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 |
18926 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 |
18927 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
18928 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
18929 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 |
18930 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L |
18931 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL |
18932 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L |
18933 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L |
18934 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L |
18935 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L |
18936 | #define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L |
18937 | //MPCC1_MPCC_UPDATE_LOCK_SEL |
18938 | #define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 |
18939 | #define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 |
18940 | #define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL |
18941 | #define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L |
18942 | //MPCC1_MPCC_TOP_OFFSET |
18943 | #define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 |
18944 | #define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 |
18945 | #define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL |
18946 | #define MPCC1_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L |
18947 | //MPCC1_MPCC_BOT_OFFSET |
18948 | #define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 |
18949 | #define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 |
18950 | #define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL |
18951 | #define MPCC1_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L |
18952 | //MPCC1_MPCC_OFFSET |
18953 | #define MPCC1_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 |
18954 | #define MPCC1_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 |
18955 | #define MPCC1_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL |
18956 | #define MPCC1_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L |
18957 | //MPCC1_MPCC_BG_R_CR |
18958 | #define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 |
18959 | #define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL |
18960 | //MPCC1_MPCC_BG_G_Y |
18961 | #define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 |
18962 | #define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL |
18963 | //MPCC1_MPCC_BG_B_CB |
18964 | #define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 |
18965 | #define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL |
18966 | //MPCC1_MPCC_STALL_STATUS |
18967 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 |
18968 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 |
18969 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc |
18970 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 |
18971 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L |
18972 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L |
18973 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L |
18974 | #define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L |
18975 | //MPCC1_MPCC_STATUS |
18976 | #define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 |
18977 | #define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 |
18978 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 |
18979 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 |
18980 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 |
18981 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 |
18982 | #define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 |
18983 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 |
18984 | #define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 |
18985 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 |
18986 | #define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e |
18987 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f |
18988 | #define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L |
18989 | #define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L |
18990 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L |
18991 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L |
18992 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L |
18993 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L |
18994 | #define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L |
18995 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L |
18996 | #define MPCC1_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L |
18997 | #define MPCC1_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L |
18998 | #define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L |
18999 | #define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L |
19000 | |
19001 | |
19002 | // addressBlock: dce_dc_mpc_mpcc2_dispdec |
19003 | //MPCC2_MPCC_TOP_SEL |
19004 | #define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 |
19005 | #define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL |
19006 | //MPCC2_MPCC_BOT_SEL |
19007 | #define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 |
19008 | #define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL |
19009 | //MPCC2_MPCC_OPP_ID |
19010 | #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 |
19011 | #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL |
19012 | //MPCC2_MPCC_CONTROL |
19013 | #define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 |
19014 | #define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 |
19015 | #define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 |
19016 | #define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 |
19017 | #define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 |
19018 | #define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 |
19019 | #define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L |
19020 | #define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L |
19021 | #define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L |
19022 | #define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L |
19023 | #define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L |
19024 | #define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L |
19025 | //MPCC2_MPCC_SM_CONTROL |
19026 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 |
19027 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 |
19028 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 |
19029 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 |
19030 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
19031 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
19032 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 |
19033 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L |
19034 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL |
19035 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L |
19036 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L |
19037 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L |
19038 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L |
19039 | #define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L |
19040 | //MPCC2_MPCC_UPDATE_LOCK_SEL |
19041 | #define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 |
19042 | #define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 |
19043 | #define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL |
19044 | #define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L |
19045 | //MPCC2_MPCC_TOP_OFFSET |
19046 | #define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 |
19047 | #define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 |
19048 | #define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL |
19049 | #define MPCC2_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L |
19050 | //MPCC2_MPCC_BOT_OFFSET |
19051 | #define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 |
19052 | #define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 |
19053 | #define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL |
19054 | #define MPCC2_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L |
19055 | //MPCC2_MPCC_OFFSET |
19056 | #define MPCC2_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 |
19057 | #define MPCC2_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 |
19058 | #define MPCC2_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL |
19059 | #define MPCC2_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L |
19060 | //MPCC2_MPCC_BG_R_CR |
19061 | #define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 |
19062 | #define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL |
19063 | //MPCC2_MPCC_BG_G_Y |
19064 | #define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 |
19065 | #define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL |
19066 | //MPCC2_MPCC_BG_B_CB |
19067 | #define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 |
19068 | #define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL |
19069 | //MPCC2_MPCC_STALL_STATUS |
19070 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 |
19071 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 |
19072 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc |
19073 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 |
19074 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L |
19075 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L |
19076 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L |
19077 | #define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L |
19078 | //MPCC2_MPCC_STATUS |
19079 | #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 |
19080 | #define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 |
19081 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 |
19082 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 |
19083 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 |
19084 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 |
19085 | #define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 |
19086 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 |
19087 | #define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 |
19088 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 |
19089 | #define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e |
19090 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f |
19091 | #define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L |
19092 | #define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L |
19093 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L |
19094 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L |
19095 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L |
19096 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L |
19097 | #define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L |
19098 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L |
19099 | #define MPCC2_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L |
19100 | #define MPCC2_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L |
19101 | #define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L |
19102 | #define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L |
19103 | |
19104 | |
19105 | // addressBlock: dce_dc_mpc_mpcc3_dispdec |
19106 | //MPCC3_MPCC_TOP_SEL |
19107 | #define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 |
19108 | #define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL |
19109 | //MPCC3_MPCC_BOT_SEL |
19110 | #define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 |
19111 | #define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL |
19112 | //MPCC3_MPCC_OPP_ID |
19113 | #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 |
19114 | #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL |
19115 | //MPCC3_MPCC_CONTROL |
19116 | #define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 |
19117 | #define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 |
19118 | #define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 |
19119 | #define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 |
19120 | #define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 |
19121 | #define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 |
19122 | #define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L |
19123 | #define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L |
19124 | #define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L |
19125 | #define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L |
19126 | #define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L |
19127 | #define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L |
19128 | //MPCC3_MPCC_SM_CONTROL |
19129 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 |
19130 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 |
19131 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 |
19132 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 |
19133 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
19134 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
19135 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 |
19136 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L |
19137 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL |
19138 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L |
19139 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L |
19140 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L |
19141 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L |
19142 | #define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L |
19143 | //MPCC3_MPCC_UPDATE_LOCK_SEL |
19144 | #define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 |
19145 | #define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 |
19146 | #define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL |
19147 | #define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x000000F0L |
19148 | //MPCC3_MPCC_TOP_OFFSET |
19149 | #define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L__SHIFT 0x0 |
19150 | #define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C__SHIFT 0x10 |
19151 | #define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_L_MASK 0x00000FFFL |
19152 | #define MPCC3_MPCC_TOP_OFFSET__MPCC_TOP_OFFSET_C_MASK 0x0FFF0000L |
19153 | //MPCC3_MPCC_BOT_OFFSET |
19154 | #define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L__SHIFT 0x0 |
19155 | #define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C__SHIFT 0x10 |
19156 | #define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_L_MASK 0x00000FFFL |
19157 | #define MPCC3_MPCC_BOT_OFFSET__MPCC_BOT_OFFSET_C_MASK 0x0FFF0000L |
19158 | //MPCC3_MPCC_OFFSET |
19159 | #define MPCC3_MPCC_OFFSET__MPCC_OFFSET_L__SHIFT 0x0 |
19160 | #define MPCC3_MPCC_OFFSET__MPCC_OFFSET_C__SHIFT 0x10 |
19161 | #define MPCC3_MPCC_OFFSET__MPCC_OFFSET_L_MASK 0x00000FFFL |
19162 | #define MPCC3_MPCC_OFFSET__MPCC_OFFSET_C_MASK 0x0FFF0000L |
19163 | //MPCC3_MPCC_BG_R_CR |
19164 | #define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 |
19165 | #define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL |
19166 | //MPCC3_MPCC_BG_G_Y |
19167 | #define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 |
19168 | #define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL |
19169 | //MPCC3_MPCC_BG_B_CB |
19170 | #define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 |
19171 | #define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL |
19172 | //MPCC3_MPCC_STALL_STATUS |
19173 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 |
19174 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 |
19175 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc |
19176 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INFO__SHIFT 0x10 |
19177 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L |
19178 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L |
19179 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L |
19180 | #define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INFO_MASK 0x00030000L |
19181 | //MPCC3_MPCC_STATUS |
19182 | #define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 |
19183 | #define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 |
19184 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EOL_MISSED__SHIFT 0x10 |
19185 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOL__SHIFT 0x11 |
19186 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EOF_MISSED__SHIFT 0x12 |
19187 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOF__SHIFT 0x13 |
19188 | #define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_PIXEL__SHIFT 0x14 |
19189 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_PIXEL__SHIFT 0x15 |
19190 | #define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_LINES__SHIFT 0x16 |
19191 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_LINES__SHIFT 0x17 |
19192 | #define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e |
19193 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f |
19194 | #define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L |
19195 | #define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L |
19196 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EOL_MISSED_MASK 0x00010000L |
19197 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOL_MASK 0x00020000L |
19198 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EOF_MISSED_MASK 0x00040000L |
19199 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MULTI_EOF_MASK 0x00080000L |
19200 | #define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_PIXEL_MASK 0x00100000L |
19201 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_PIXEL_MASK 0x00200000L |
19202 | #define MPCC3_MPCC_STATUS__DPP_MPCC_LESS_LINES_MASK 0x00400000L |
19203 | #define MPCC3_MPCC_STATUS__DPP_MPCC_MORE_LINES_MASK 0x00800000L |
19204 | #define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L |
19205 | #define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L |
19206 | |
19207 | |
19208 | // addressBlock: dce_dc_mpc_mpc_cfg_dispdec |
19209 | //MPC_CLOCK_CONTROL |
19210 | #define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 |
19211 | #define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 |
19212 | #define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L |
19213 | #define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L |
19214 | //MPC_SOFT_RESET |
19215 | #define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 |
19216 | #define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 |
19217 | #define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 |
19218 | #define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 |
19219 | #define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa |
19220 | #define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb |
19221 | #define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc |
19222 | #define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd |
19223 | #define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 |
19224 | #define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 |
19225 | #define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 |
19226 | #define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 |
19227 | #define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f |
19228 | #define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L |
19229 | #define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L |
19230 | #define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L |
19231 | #define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L |
19232 | #define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L |
19233 | #define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L |
19234 | #define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L |
19235 | #define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L |
19236 | #define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L |
19237 | #define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L |
19238 | #define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L |
19239 | #define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L |
19240 | #define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L |
19241 | //MPC_CRC_CTRL |
19242 | #define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 |
19243 | #define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 |
19244 | #define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 |
19245 | #define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa |
19246 | #define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc |
19247 | #define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 |
19248 | #define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
19249 | #define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f |
19250 | #define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L |
19251 | #define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L |
19252 | #define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L |
19253 | #define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L |
19254 | #define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L |
19255 | #define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L |
19256 | #define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
19257 | #define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L |
19258 | //MPC_CRC_SEL_CONTROL |
19259 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 |
19260 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 |
19261 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 |
19262 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL |
19263 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L |
19264 | #define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L |
19265 | //MPC_CRC_RESULT_AR |
19266 | #define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 |
19267 | #define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 |
19268 | #define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL |
19269 | #define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L |
19270 | //MPC_CRC_RESULT_GB |
19271 | #define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 |
19272 | #define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 |
19273 | #define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL |
19274 | #define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L |
19275 | //MPC_CRC_RESULT_C |
19276 | #define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 |
19277 | #define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL |
19278 | //MPC_PERFMON_EVENT_CTRL |
19279 | #define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 |
19280 | #define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L |
19281 | //MPC_BYPASS_BG_AR |
19282 | #define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 |
19283 | #define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 |
19284 | #define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL |
19285 | #define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L |
19286 | //MPC_BYPASS_BG_GB |
19287 | #define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 |
19288 | #define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 |
19289 | #define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL |
19290 | #define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L |
19291 | //MPC_OUT0_MUX |
19292 | #define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 |
19293 | #define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL |
19294 | //MPC_OUT1_MUX |
19295 | #define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 |
19296 | #define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL |
19297 | //MPC_OUT2_MUX |
19298 | #define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 |
19299 | #define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL |
19300 | //MPC_OUT3_MUX |
19301 | #define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 |
19302 | #define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL |
19303 | //MPC_STALL_GRACE_WINDOW |
19304 | #define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT 0x0 |
19305 | #define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK 0x000000FFL |
19306 | //ADR_CFG_VUPDATE_LOCK_SET0 |
19307 | #define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 |
19308 | #define ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 |
19309 | #define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L |
19310 | #define ADR_CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L |
19311 | //ADR_VUPDATE_LOCK_SET0 |
19312 | #define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 |
19313 | #define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L |
19314 | //CUR0_VUPDATE_LOCK_SET0 |
19315 | #define CUR0_VUPDATE_LOCK_SET0__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 |
19316 | #define CUR0_VUPDATE_LOCK_SET0__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L |
19317 | //CUR1_VUPDATE_LOCK_SET0 |
19318 | #define CUR1_VUPDATE_LOCK_SET0__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 |
19319 | #define CUR1_VUPDATE_LOCK_SET0__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L |
19320 | //ADR_CFG_VUPDATE_LOCK_SET1 |
19321 | #define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 |
19322 | #define ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 |
19323 | #define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L |
19324 | #define ADR_CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L |
19325 | //ADR_VUPDATE_LOCK_SET1 |
19326 | #define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 |
19327 | #define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L |
19328 | //CUR0_VUPDATE_LOCK_SET1 |
19329 | #define CUR0_VUPDATE_LOCK_SET1__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 |
19330 | #define CUR0_VUPDATE_LOCK_SET1__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L |
19331 | //CUR1_VUPDATE_LOCK_SET1 |
19332 | #define CUR1_VUPDATE_LOCK_SET1__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 |
19333 | #define CUR1_VUPDATE_LOCK_SET1__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L |
19334 | //ADR_CFG_VUPDATE_LOCK_SET2 |
19335 | #define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 |
19336 | #define ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 |
19337 | #define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L |
19338 | #define ADR_CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L |
19339 | //ADR_VUPDATE_LOCK_SET2 |
19340 | #define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 |
19341 | #define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L |
19342 | //CUR0_VUPDATE_LOCK_SET2 |
19343 | #define CUR0_VUPDATE_LOCK_SET2__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 |
19344 | #define CUR0_VUPDATE_LOCK_SET2__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L |
19345 | //CUR1_VUPDATE_LOCK_SET2 |
19346 | #define CUR1_VUPDATE_LOCK_SET2__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 |
19347 | #define CUR1_VUPDATE_LOCK_SET2__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L |
19348 | //ADR_CFG_VUPDATE_LOCK_SET3 |
19349 | #define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 |
19350 | #define ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x4 |
19351 | #define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L |
19352 | #define ADR_CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000010L |
19353 | //ADR_VUPDATE_LOCK_SET3 |
19354 | #define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 |
19355 | #define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L |
19356 | //CUR0_VUPDATE_LOCK_SET3 |
19357 | #define CUR0_VUPDATE_LOCK_SET3__CUR0_VUPDATE_LOCK_SET__SHIFT 0x0 |
19358 | #define CUR0_VUPDATE_LOCK_SET3__CUR0_VUPDATE_LOCK_SET_MASK 0x00000001L |
19359 | //CUR1_VUPDATE_LOCK_SET3 |
19360 | #define CUR1_VUPDATE_LOCK_SET3__CUR1_VUPDATE_LOCK_SET__SHIFT 0x0 |
19361 | #define CUR1_VUPDATE_LOCK_SET3__CUR1_VUPDATE_LOCK_SET_MASK 0x00000001L |
19362 | |
19363 | |
19364 | // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec |
19365 | //DC_PERFMON16_PERFCOUNTER_CNTL |
19366 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
19367 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
19368 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
19369 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
19370 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
19371 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
19372 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
19373 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
19374 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
19375 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
19376 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
19377 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
19378 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
19379 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
19380 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
19381 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
19382 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
19383 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
19384 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
19385 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
19386 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
19387 | #define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
19388 | //DC_PERFMON16_PERFCOUNTER_CNTL2 |
19389 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
19390 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
19391 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
19392 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
19393 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
19394 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
19395 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
19396 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
19397 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
19398 | #define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
19399 | //DC_PERFMON16_PERFCOUNTER_STATE |
19400 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
19401 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
19402 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
19403 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
19404 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
19405 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
19406 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
19407 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
19408 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
19409 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
19410 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
19411 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
19412 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
19413 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
19414 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
19415 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
19416 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
19417 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
19418 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
19419 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
19420 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
19421 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
19422 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
19423 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
19424 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
19425 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
19426 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
19427 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
19428 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
19429 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
19430 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
19431 | #define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
19432 | //DC_PERFMON16_PERFMON_CNTL |
19433 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
19434 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
19435 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
19436 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
19437 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
19438 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
19439 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
19440 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
19441 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
19442 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
19443 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
19444 | #define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
19445 | //DC_PERFMON16_PERFMON_CNTL2 |
19446 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
19447 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
19448 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
19449 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
19450 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
19451 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
19452 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
19453 | #define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
19454 | //DC_PERFMON16_PERFMON_CVALUE_INT_MISC |
19455 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
19456 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
19457 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
19458 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
19459 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
19460 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
19461 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
19462 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
19463 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
19464 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
19465 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
19466 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
19467 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
19468 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
19469 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
19470 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
19471 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
19472 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
19473 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
19474 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
19475 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
19476 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
19477 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
19478 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
19479 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
19480 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
19481 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
19482 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
19483 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
19484 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
19485 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
19486 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
19487 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
19488 | #define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
19489 | //DC_PERFMON16_PERFMON_CVALUE_LOW |
19490 | #define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
19491 | #define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
19492 | //DC_PERFMON16_PERFMON_HI |
19493 | #define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
19494 | #define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
19495 | #define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
19496 | #define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
19497 | //DC_PERFMON16_PERFMON_LOW |
19498 | #define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
19499 | #define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
19500 | |
19501 | |
19502 | // addressBlock: dce_dc_opp_abm0_dispdec |
19503 | //ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL |
19504 | #define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 |
19505 | #define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL |
19506 | //ABM0_BL1_PWM_USER_LEVEL |
19507 | #define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 |
19508 | #define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL |
19509 | //ABM0_BL1_PWM_TARGET_ABM_LEVEL |
19510 | #define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 |
19511 | #define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL |
19512 | //ABM0_BL1_PWM_CURRENT_ABM_LEVEL |
19513 | #define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 |
19514 | #define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL |
19515 | //ABM0_BL1_PWM_FINAL_DUTY_CYCLE |
19516 | #define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 |
19517 | #define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL |
19518 | //ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE |
19519 | #define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 |
19520 | #define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL |
19521 | //ABM0_BL1_PWM_ABM_CNTL |
19522 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 |
19523 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 |
19524 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 |
19525 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 |
19526 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 |
19527 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L |
19528 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L |
19529 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L |
19530 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L |
19531 | #define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L |
19532 | //ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE |
19533 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
19534 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
19535 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
19536 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
19537 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19538 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
19539 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
19540 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
19541 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
19542 | #define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19543 | //ABM0_BL1_PWM_GRP2_REG_LOCK |
19544 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 |
19545 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 |
19546 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 |
19547 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 |
19548 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
19549 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
19550 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L |
19551 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L |
19552 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L |
19553 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L |
19554 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L |
19555 | #define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L |
19556 | //ABM0_DC_ABM1_CNTL |
19557 | #define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 |
19558 | #define ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 |
19559 | #define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L |
19560 | #define ABM0_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L |
19561 | //ABM0_DC_ABM1_IPCSC_COEFF_SEL |
19562 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 |
19563 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 |
19564 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 |
19565 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19566 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL |
19567 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L |
19568 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L |
19569 | #define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19570 | //ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 |
19571 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 |
19572 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 |
19573 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f |
19574 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL |
19575 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L |
19576 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L |
19577 | //ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 |
19578 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 |
19579 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 |
19580 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f |
19581 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL |
19582 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L |
19583 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L |
19584 | //ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 |
19585 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 |
19586 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 |
19587 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f |
19588 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL |
19589 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L |
19590 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L |
19591 | //ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 |
19592 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 |
19593 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 |
19594 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f |
19595 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL |
19596 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L |
19597 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L |
19598 | //ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 |
19599 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 |
19600 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 |
19601 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f |
19602 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL |
19603 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L |
19604 | #define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L |
19605 | //ABM0_DC_ABM1_ACE_THRES_12 |
19606 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 |
19607 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 |
19608 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f |
19609 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL |
19610 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L |
19611 | #define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L |
19612 | //ABM0_DC_ABM1_ACE_THRES_34 |
19613 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 |
19614 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 |
19615 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c |
19616 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d |
19617 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e |
19618 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f |
19619 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL |
19620 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L |
19621 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L |
19622 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L |
19623 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L |
19624 | #define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L |
19625 | //ABM0_DC_ABM1_ACE_CNTL_MISC |
19626 | #define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 |
19627 | #define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 |
19628 | #define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L |
19629 | #define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L |
19630 | //ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS |
19631 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 |
19632 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 |
19633 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 |
19634 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 |
19635 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 |
19636 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa |
19637 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 |
19638 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 |
19639 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f |
19640 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L |
19641 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L |
19642 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L |
19643 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L |
19644 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L |
19645 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L |
19646 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L |
19647 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L |
19648 | #define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L |
19649 | //ABM0_DC_ABM1_HG_MISC_CTRL |
19650 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 |
19651 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 |
19652 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc |
19653 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 |
19654 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 |
19655 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 |
19656 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 |
19657 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c |
19658 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d |
19659 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e |
19660 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19661 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L |
19662 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L |
19663 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L |
19664 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L |
19665 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L |
19666 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L |
19667 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L |
19668 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L |
19669 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L |
19670 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L |
19671 | #define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19672 | //ABM0_DC_ABM1_LS_SUM_OF_LUMA |
19673 | #define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 |
19674 | #define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL |
19675 | //ABM0_DC_ABM1_LS_MIN_MAX_LUMA |
19676 | #define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 |
19677 | #define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 |
19678 | #define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL |
19679 | #define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L |
19680 | //ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA |
19681 | #define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 |
19682 | #define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 |
19683 | #define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL |
19684 | #define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L |
19685 | //ABM0_DC_ABM1_LS_PIXEL_COUNT |
19686 | #define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 |
19687 | #define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 |
19688 | #define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL |
19689 | #define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L |
19690 | //ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES |
19691 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 |
19692 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 |
19693 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19694 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL |
19695 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L |
19696 | #define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19697 | //ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT |
19698 | #define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 |
19699 | #define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL |
19700 | //ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT |
19701 | #define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 |
19702 | #define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL |
19703 | //ABM0_DC_ABM1_HG_SAMPLE_RATE |
19704 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
19705 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
19706 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
19707 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
19708 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19709 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
19710 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
19711 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
19712 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
19713 | #define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19714 | //ABM0_DC_ABM1_LS_SAMPLE_RATE |
19715 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
19716 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
19717 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
19718 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
19719 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19720 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
19721 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
19722 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
19723 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
19724 | #define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19725 | //ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG |
19726 | #define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 |
19727 | #define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL |
19728 | //ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX |
19729 | #define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 |
19730 | #define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL |
19731 | //ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX |
19732 | #define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 |
19733 | #define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL |
19734 | //ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX |
19735 | #define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 |
19736 | #define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL |
19737 | //ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX |
19738 | #define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 |
19739 | #define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL |
19740 | //ABM0_DC_ABM1_HG_RESULT_1 |
19741 | #define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 |
19742 | #define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL |
19743 | //ABM0_DC_ABM1_HG_RESULT_2 |
19744 | #define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 |
19745 | #define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL |
19746 | //ABM0_DC_ABM1_HG_RESULT_3 |
19747 | #define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 |
19748 | #define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL |
19749 | //ABM0_DC_ABM1_HG_RESULT_4 |
19750 | #define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 |
19751 | #define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL |
19752 | //ABM0_DC_ABM1_HG_RESULT_5 |
19753 | #define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 |
19754 | #define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL |
19755 | //ABM0_DC_ABM1_HG_RESULT_6 |
19756 | #define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 |
19757 | #define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL |
19758 | //ABM0_DC_ABM1_HG_RESULT_7 |
19759 | #define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 |
19760 | #define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL |
19761 | //ABM0_DC_ABM1_HG_RESULT_8 |
19762 | #define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 |
19763 | #define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL |
19764 | //ABM0_DC_ABM1_HG_RESULT_9 |
19765 | #define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 |
19766 | #define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL |
19767 | //ABM0_DC_ABM1_HG_RESULT_10 |
19768 | #define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 |
19769 | #define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL |
19770 | //ABM0_DC_ABM1_HG_RESULT_11 |
19771 | #define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 |
19772 | #define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL |
19773 | //ABM0_DC_ABM1_HG_RESULT_12 |
19774 | #define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 |
19775 | #define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL |
19776 | //ABM0_DC_ABM1_HG_RESULT_13 |
19777 | #define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 |
19778 | #define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL |
19779 | //ABM0_DC_ABM1_HG_RESULT_14 |
19780 | #define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 |
19781 | #define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL |
19782 | //ABM0_DC_ABM1_HG_RESULT_15 |
19783 | #define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 |
19784 | #define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL |
19785 | //ABM0_DC_ABM1_HG_RESULT_16 |
19786 | #define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 |
19787 | #define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL |
19788 | //ABM0_DC_ABM1_HG_RESULT_17 |
19789 | #define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 |
19790 | #define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL |
19791 | //ABM0_DC_ABM1_HG_RESULT_18 |
19792 | #define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 |
19793 | #define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL |
19794 | //ABM0_DC_ABM1_HG_RESULT_19 |
19795 | #define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 |
19796 | #define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL |
19797 | //ABM0_DC_ABM1_HG_RESULT_20 |
19798 | #define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 |
19799 | #define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL |
19800 | //ABM0_DC_ABM1_HG_RESULT_21 |
19801 | #define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 |
19802 | #define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL |
19803 | //ABM0_DC_ABM1_HG_RESULT_22 |
19804 | #define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 |
19805 | #define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL |
19806 | //ABM0_DC_ABM1_HG_RESULT_23 |
19807 | #define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 |
19808 | #define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL |
19809 | //ABM0_DC_ABM1_HG_RESULT_24 |
19810 | #define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 |
19811 | #define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL |
19812 | //ABM0_DC_ABM1_BL_MASTER_LOCK |
19813 | #define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f |
19814 | #define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L |
19815 | |
19816 | |
19817 | // addressBlock: dce_dc_opp_abm1_dispdec |
19818 | //ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL |
19819 | #define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 |
19820 | #define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL |
19821 | //ABM1_BL1_PWM_USER_LEVEL |
19822 | #define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 |
19823 | #define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL |
19824 | //ABM1_BL1_PWM_TARGET_ABM_LEVEL |
19825 | #define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 |
19826 | #define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL |
19827 | //ABM1_BL1_PWM_CURRENT_ABM_LEVEL |
19828 | #define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 |
19829 | #define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL |
19830 | //ABM1_BL1_PWM_FINAL_DUTY_CYCLE |
19831 | #define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 |
19832 | #define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL |
19833 | //ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE |
19834 | #define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 |
19835 | #define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL |
19836 | //ABM1_BL1_PWM_ABM_CNTL |
19837 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 |
19838 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 |
19839 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 |
19840 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 |
19841 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 |
19842 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L |
19843 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L |
19844 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L |
19845 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L |
19846 | #define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L |
19847 | //ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE |
19848 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
19849 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
19850 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
19851 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
19852 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19853 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
19854 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
19855 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
19856 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
19857 | #define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19858 | //ABM1_BL1_PWM_GRP2_REG_LOCK |
19859 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 |
19860 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 |
19861 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 |
19862 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 |
19863 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
19864 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
19865 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L |
19866 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L |
19867 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L |
19868 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L |
19869 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L |
19870 | #define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L |
19871 | //ABM1_DC_ABM1_CNTL |
19872 | #define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 |
19873 | #define ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 |
19874 | #define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L |
19875 | #define ABM1_DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L |
19876 | //ABM1_DC_ABM1_IPCSC_COEFF_SEL |
19877 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 |
19878 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 |
19879 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 |
19880 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19881 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL |
19882 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L |
19883 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L |
19884 | #define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19885 | //ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 |
19886 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 |
19887 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 |
19888 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f |
19889 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL |
19890 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L |
19891 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L |
19892 | //ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 |
19893 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 |
19894 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 |
19895 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f |
19896 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL |
19897 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L |
19898 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L |
19899 | //ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 |
19900 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 |
19901 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 |
19902 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f |
19903 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL |
19904 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L |
19905 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L |
19906 | //ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 |
19907 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 |
19908 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 |
19909 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f |
19910 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL |
19911 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L |
19912 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L |
19913 | //ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 |
19914 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 |
19915 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 |
19916 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f |
19917 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL |
19918 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L |
19919 | #define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L |
19920 | //ABM1_DC_ABM1_ACE_THRES_12 |
19921 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 |
19922 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 |
19923 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f |
19924 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL |
19925 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L |
19926 | #define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L |
19927 | //ABM1_DC_ABM1_ACE_THRES_34 |
19928 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 |
19929 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 |
19930 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c |
19931 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d |
19932 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e |
19933 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f |
19934 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL |
19935 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L |
19936 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L |
19937 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L |
19938 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L |
19939 | #define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L |
19940 | //ABM1_DC_ABM1_ACE_CNTL_MISC |
19941 | #define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 |
19942 | #define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 |
19943 | #define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L |
19944 | #define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L |
19945 | //ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS |
19946 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 |
19947 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 |
19948 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 |
19949 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 |
19950 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 |
19951 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa |
19952 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 |
19953 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 |
19954 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f |
19955 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L |
19956 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L |
19957 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L |
19958 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L |
19959 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L |
19960 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L |
19961 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L |
19962 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L |
19963 | #define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L |
19964 | //ABM1_DC_ABM1_HG_MISC_CTRL |
19965 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 |
19966 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 |
19967 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc |
19968 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 |
19969 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 |
19970 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 |
19971 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 |
19972 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c |
19973 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d |
19974 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e |
19975 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
19976 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L |
19977 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L |
19978 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L |
19979 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L |
19980 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L |
19981 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L |
19982 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L |
19983 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L |
19984 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L |
19985 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L |
19986 | #define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
19987 | //ABM1_DC_ABM1_LS_SUM_OF_LUMA |
19988 | #define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 |
19989 | #define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL |
19990 | //ABM1_DC_ABM1_LS_MIN_MAX_LUMA |
19991 | #define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 |
19992 | #define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 |
19993 | #define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL |
19994 | #define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L |
19995 | //ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA |
19996 | #define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 |
19997 | #define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 |
19998 | #define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL |
19999 | #define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L |
20000 | //ABM1_DC_ABM1_LS_PIXEL_COUNT |
20001 | #define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 |
20002 | #define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 |
20003 | #define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL |
20004 | #define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L |
20005 | //ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES |
20006 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 |
20007 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 |
20008 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
20009 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL |
20010 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L |
20011 | #define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
20012 | //ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT |
20013 | #define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 |
20014 | #define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL |
20015 | //ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT |
20016 | #define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 |
20017 | #define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL |
20018 | //ABM1_DC_ABM1_HG_SAMPLE_RATE |
20019 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
20020 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
20021 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
20022 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
20023 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
20024 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
20025 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
20026 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
20027 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
20028 | #define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
20029 | //ABM1_DC_ABM1_LS_SAMPLE_RATE |
20030 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
20031 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
20032 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
20033 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
20034 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
20035 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L |
20036 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L |
20037 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L |
20038 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L |
20039 | #define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L |
20040 | //ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG |
20041 | #define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 |
20042 | #define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL |
20043 | //ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX |
20044 | #define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 |
20045 | #define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL |
20046 | //ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX |
20047 | #define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 |
20048 | #define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL |
20049 | //ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX |
20050 | #define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 |
20051 | #define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL |
20052 | //ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX |
20053 | #define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 |
20054 | #define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL |
20055 | //ABM1_DC_ABM1_HG_RESULT_1 |
20056 | #define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 |
20057 | #define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL |
20058 | //ABM1_DC_ABM1_HG_RESULT_2 |
20059 | #define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 |
20060 | #define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL |
20061 | //ABM1_DC_ABM1_HG_RESULT_3 |
20062 | #define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 |
20063 | #define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL |
20064 | //ABM1_DC_ABM1_HG_RESULT_4 |
20065 | #define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 |
20066 | #define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL |
20067 | //ABM1_DC_ABM1_HG_RESULT_5 |
20068 | #define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 |
20069 | #define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL |
20070 | //ABM1_DC_ABM1_HG_RESULT_6 |
20071 | #define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 |
20072 | #define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL |
20073 | //ABM1_DC_ABM1_HG_RESULT_7 |
20074 | #define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 |
20075 | #define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL |
20076 | //ABM1_DC_ABM1_HG_RESULT_8 |
20077 | #define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 |
20078 | #define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL |
20079 | //ABM1_DC_ABM1_HG_RESULT_9 |
20080 | #define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 |
20081 | #define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL |
20082 | //ABM1_DC_ABM1_HG_RESULT_10 |
20083 | #define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 |
20084 | #define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL |
20085 | //ABM1_DC_ABM1_HG_RESULT_11 |
20086 | #define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 |
20087 | #define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL |
20088 | //ABM1_DC_ABM1_HG_RESULT_12 |
20089 | #define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 |
20090 | #define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL |
20091 | //ABM1_DC_ABM1_HG_RESULT_13 |
20092 | #define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 |
20093 | #define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL |
20094 | //ABM1_DC_ABM1_HG_RESULT_14 |
20095 | #define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 |
20096 | #define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL |
20097 | //ABM1_DC_ABM1_HG_RESULT_15 |
20098 | #define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 |
20099 | #define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL |
20100 | //ABM1_DC_ABM1_HG_RESULT_16 |
20101 | #define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 |
20102 | #define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL |
20103 | //ABM1_DC_ABM1_HG_RESULT_17 |
20104 | #define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 |
20105 | #define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL |
20106 | //ABM1_DC_ABM1_HG_RESULT_18 |
20107 | #define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 |
20108 | #define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL |
20109 | //ABM1_DC_ABM1_HG_RESULT_19 |
20110 | #define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 |
20111 | #define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL |
20112 | //ABM1_DC_ABM1_HG_RESULT_20 |
20113 | #define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 |
20114 | #define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL |
20115 | //ABM1_DC_ABM1_HG_RESULT_21 |
20116 | #define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 |
20117 | #define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL |
20118 | //ABM1_DC_ABM1_HG_RESULT_22 |
20119 | #define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 |
20120 | #define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL |
20121 | //ABM1_DC_ABM1_HG_RESULT_23 |
20122 | #define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 |
20123 | #define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL |
20124 | //ABM1_DC_ABM1_HG_RESULT_24 |
20125 | #define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 |
20126 | #define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL |
20127 | //ABM1_DC_ABM1_BL_MASTER_LOCK |
20128 | #define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f |
20129 | #define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L |
20130 | |
20131 | |
20132 | // addressBlock: dce_dc_opp_fmt0_dispdec |
20133 | //FMT0_FMT_CLAMP_COMPONENT_R |
20134 | #define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
20135 | #define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
20136 | #define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
20137 | #define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
20138 | //FMT0_FMT_CLAMP_COMPONENT_G |
20139 | #define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
20140 | #define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
20141 | #define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
20142 | #define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
20143 | //FMT0_FMT_CLAMP_COMPONENT_B |
20144 | #define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
20145 | #define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
20146 | #define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
20147 | #define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
20148 | //FMT0_FMT_DYNAMIC_EXP_CNTL |
20149 | #define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
20150 | #define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
20151 | #define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
20152 | #define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
20153 | //FMT0_FMT_CONTROL |
20154 | #define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
20155 | #define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
20156 | #define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
20157 | #define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
20158 | #define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
20159 | #define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
20160 | #define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
20161 | #define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
20162 | #define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
20163 | #define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
20164 | #define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
20165 | #define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
20166 | #define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
20167 | #define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
20168 | #define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
20169 | #define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
20170 | //FMT0_FMT_BIT_DEPTH_CONTROL |
20171 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
20172 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
20173 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
20174 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
20175 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
20176 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
20177 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
20178 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
20179 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
20180 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
20181 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
20182 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
20183 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
20184 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
20185 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
20186 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
20187 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
20188 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
20189 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
20190 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
20191 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
20192 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
20193 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
20194 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
20195 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
20196 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
20197 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
20198 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
20199 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
20200 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
20201 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
20202 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
20203 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
20204 | #define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
20205 | //FMT0_FMT_DITHER_RAND_R_SEED |
20206 | #define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
20207 | #define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
20208 | #define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
20209 | #define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
20210 | //FMT0_FMT_DITHER_RAND_G_SEED |
20211 | #define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
20212 | #define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
20213 | #define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
20214 | #define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
20215 | //FMT0_FMT_DITHER_RAND_B_SEED |
20216 | #define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
20217 | #define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
20218 | #define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
20219 | #define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
20220 | //FMT0_FMT_CLAMP_CNTL |
20221 | #define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
20222 | #define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
20223 | #define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
20224 | #define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
20225 | //FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
20226 | #define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
20227 | #define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
20228 | //FMT0_FMT_MAP420_MEMORY_CONTROL |
20229 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
20230 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
20231 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
20232 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
20233 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
20234 | #define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
20235 | |
20236 | |
20237 | // addressBlock: dce_dc_opp_oppbuf0_dispdec |
20238 | //OPPBUF0_OPPBUF_CONTROL |
20239 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
20240 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
20241 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
20242 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
20243 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
20244 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
20245 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
20246 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
20247 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
20248 | #define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
20249 | //OPPBUF0_OPPBUF_3D_PARAMETERS_0 |
20250 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
20251 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
20252 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
20253 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
20254 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
20255 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
20256 | //OPPBUF0_OPPBUF_3D_PARAMETERS_1 |
20257 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
20258 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
20259 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
20260 | #define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
20261 | |
20262 | |
20263 | // addressBlock: dce_dc_opp_opp_pipe0_dispdec |
20264 | //OPP_PIPE0_OPP_PIPE_CONTROL |
20265 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
20266 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
20267 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
20268 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
20269 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
20270 | #define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
20271 | |
20272 | |
20273 | // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec |
20274 | //OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL |
20275 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
20276 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
20277 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
20278 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
20279 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
20280 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
20281 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
20282 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
20283 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
20284 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
20285 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
20286 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
20287 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
20288 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
20289 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
20290 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
20291 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
20292 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
20293 | //OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK |
20294 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
20295 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
20296 | //OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 |
20297 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
20298 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
20299 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
20300 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
20301 | //OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 |
20302 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
20303 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
20304 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
20305 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
20306 | //OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 |
20307 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
20308 | #define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
20309 | |
20310 | |
20311 | // addressBlock: dce_dc_opp_fmt1_dispdec |
20312 | //FMT1_FMT_CLAMP_COMPONENT_R |
20313 | #define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
20314 | #define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
20315 | #define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
20316 | #define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
20317 | //FMT1_FMT_CLAMP_COMPONENT_G |
20318 | #define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
20319 | #define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
20320 | #define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
20321 | #define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
20322 | //FMT1_FMT_CLAMP_COMPONENT_B |
20323 | #define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
20324 | #define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
20325 | #define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
20326 | #define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
20327 | //FMT1_FMT_DYNAMIC_EXP_CNTL |
20328 | #define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
20329 | #define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
20330 | #define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
20331 | #define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
20332 | //FMT1_FMT_CONTROL |
20333 | #define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
20334 | #define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
20335 | #define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
20336 | #define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
20337 | #define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
20338 | #define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
20339 | #define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
20340 | #define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
20341 | #define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
20342 | #define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
20343 | #define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
20344 | #define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
20345 | #define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
20346 | #define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
20347 | #define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
20348 | #define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
20349 | //FMT1_FMT_BIT_DEPTH_CONTROL |
20350 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
20351 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
20352 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
20353 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
20354 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
20355 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
20356 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
20357 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
20358 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
20359 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
20360 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
20361 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
20362 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
20363 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
20364 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
20365 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
20366 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
20367 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
20368 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
20369 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
20370 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
20371 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
20372 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
20373 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
20374 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
20375 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
20376 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
20377 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
20378 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
20379 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
20380 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
20381 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
20382 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
20383 | #define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
20384 | //FMT1_FMT_DITHER_RAND_R_SEED |
20385 | #define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
20386 | #define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
20387 | #define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
20388 | #define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
20389 | //FMT1_FMT_DITHER_RAND_G_SEED |
20390 | #define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
20391 | #define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
20392 | #define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
20393 | #define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
20394 | //FMT1_FMT_DITHER_RAND_B_SEED |
20395 | #define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
20396 | #define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
20397 | #define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
20398 | #define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
20399 | //FMT1_FMT_CLAMP_CNTL |
20400 | #define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
20401 | #define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
20402 | #define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
20403 | #define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
20404 | //FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
20405 | #define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
20406 | #define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
20407 | //FMT1_FMT_MAP420_MEMORY_CONTROL |
20408 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
20409 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
20410 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
20411 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
20412 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
20413 | #define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
20414 | |
20415 | |
20416 | // addressBlock: dce_dc_opp_oppbuf1_dispdec |
20417 | //OPPBUF1_OPPBUF_CONTROL |
20418 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
20419 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
20420 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
20421 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
20422 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
20423 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
20424 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
20425 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
20426 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
20427 | #define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
20428 | //OPPBUF1_OPPBUF_3D_PARAMETERS_0 |
20429 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
20430 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
20431 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
20432 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
20433 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
20434 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
20435 | //OPPBUF1_OPPBUF_3D_PARAMETERS_1 |
20436 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
20437 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
20438 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
20439 | #define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
20440 | |
20441 | |
20442 | // addressBlock: dce_dc_opp_opp_pipe1_dispdec |
20443 | //OPP_PIPE1_OPP_PIPE_CONTROL |
20444 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
20445 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
20446 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
20447 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
20448 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
20449 | #define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
20450 | |
20451 | |
20452 | // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec |
20453 | //OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL |
20454 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
20455 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
20456 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
20457 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
20458 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
20459 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
20460 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
20461 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
20462 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
20463 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
20464 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
20465 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
20466 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
20467 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
20468 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
20469 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
20470 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
20471 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
20472 | //OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK |
20473 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
20474 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
20475 | //OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 |
20476 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
20477 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
20478 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
20479 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
20480 | //OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 |
20481 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
20482 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
20483 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
20484 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
20485 | //OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 |
20486 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
20487 | #define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
20488 | |
20489 | |
20490 | // addressBlock: dce_dc_opp_fmt2_dispdec |
20491 | //FMT2_FMT_CLAMP_COMPONENT_R |
20492 | #define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
20493 | #define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
20494 | #define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
20495 | #define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
20496 | //FMT2_FMT_CLAMP_COMPONENT_G |
20497 | #define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
20498 | #define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
20499 | #define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
20500 | #define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
20501 | //FMT2_FMT_CLAMP_COMPONENT_B |
20502 | #define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
20503 | #define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
20504 | #define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
20505 | #define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
20506 | //FMT2_FMT_DYNAMIC_EXP_CNTL |
20507 | #define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
20508 | #define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
20509 | #define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
20510 | #define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
20511 | //FMT2_FMT_CONTROL |
20512 | #define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
20513 | #define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
20514 | #define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
20515 | #define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
20516 | #define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
20517 | #define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
20518 | #define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
20519 | #define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
20520 | #define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
20521 | #define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
20522 | #define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
20523 | #define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
20524 | #define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
20525 | #define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
20526 | #define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
20527 | #define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
20528 | //FMT2_FMT_BIT_DEPTH_CONTROL |
20529 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
20530 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
20531 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
20532 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
20533 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
20534 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
20535 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
20536 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
20537 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
20538 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
20539 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
20540 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
20541 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
20542 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
20543 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
20544 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
20545 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
20546 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
20547 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
20548 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
20549 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
20550 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
20551 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
20552 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
20553 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
20554 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
20555 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
20556 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
20557 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
20558 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
20559 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
20560 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
20561 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
20562 | #define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
20563 | //FMT2_FMT_DITHER_RAND_R_SEED |
20564 | #define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
20565 | #define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
20566 | #define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
20567 | #define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
20568 | //FMT2_FMT_DITHER_RAND_G_SEED |
20569 | #define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
20570 | #define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
20571 | #define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
20572 | #define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
20573 | //FMT2_FMT_DITHER_RAND_B_SEED |
20574 | #define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
20575 | #define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
20576 | #define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
20577 | #define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
20578 | //FMT2_FMT_CLAMP_CNTL |
20579 | #define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
20580 | #define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
20581 | #define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
20582 | #define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
20583 | //FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
20584 | #define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
20585 | #define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
20586 | //FMT2_FMT_MAP420_MEMORY_CONTROL |
20587 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
20588 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
20589 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
20590 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
20591 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
20592 | #define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
20593 | |
20594 | |
20595 | // addressBlock: dce_dc_opp_oppbuf2_dispdec |
20596 | //OPPBUF2_OPPBUF_CONTROL |
20597 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
20598 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
20599 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
20600 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
20601 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
20602 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
20603 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
20604 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
20605 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
20606 | #define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
20607 | //OPPBUF2_OPPBUF_3D_PARAMETERS_0 |
20608 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
20609 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
20610 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
20611 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
20612 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
20613 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
20614 | //OPPBUF2_OPPBUF_3D_PARAMETERS_1 |
20615 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
20616 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
20617 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
20618 | #define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
20619 | |
20620 | |
20621 | // addressBlock: dce_dc_opp_opp_pipe2_dispdec |
20622 | //OPP_PIPE2_OPP_PIPE_CONTROL |
20623 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
20624 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
20625 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
20626 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
20627 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
20628 | #define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
20629 | |
20630 | |
20631 | // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec |
20632 | //OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL |
20633 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
20634 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
20635 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
20636 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
20637 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
20638 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
20639 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
20640 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
20641 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
20642 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
20643 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
20644 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
20645 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
20646 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
20647 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
20648 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
20649 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
20650 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
20651 | //OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK |
20652 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
20653 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
20654 | //OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 |
20655 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
20656 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
20657 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
20658 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
20659 | //OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 |
20660 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
20661 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
20662 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
20663 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
20664 | //OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 |
20665 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
20666 | #define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
20667 | |
20668 | |
20669 | // addressBlock: dce_dc_opp_fmt3_dispdec |
20670 | //FMT3_FMT_CLAMP_COMPONENT_R |
20671 | #define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
20672 | #define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
20673 | #define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
20674 | #define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
20675 | //FMT3_FMT_CLAMP_COMPONENT_G |
20676 | #define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
20677 | #define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
20678 | #define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
20679 | #define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
20680 | //FMT3_FMT_CLAMP_COMPONENT_B |
20681 | #define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
20682 | #define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
20683 | #define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
20684 | #define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
20685 | //FMT3_FMT_DYNAMIC_EXP_CNTL |
20686 | #define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
20687 | #define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
20688 | #define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
20689 | #define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
20690 | //FMT3_FMT_CONTROL |
20691 | #define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
20692 | #define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
20693 | #define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
20694 | #define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
20695 | #define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
20696 | #define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
20697 | #define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
20698 | #define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
20699 | #define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
20700 | #define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
20701 | #define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
20702 | #define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
20703 | #define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
20704 | #define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
20705 | #define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
20706 | #define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
20707 | //FMT3_FMT_BIT_DEPTH_CONTROL |
20708 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
20709 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
20710 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
20711 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
20712 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
20713 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
20714 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
20715 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
20716 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
20717 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
20718 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
20719 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
20720 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
20721 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
20722 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
20723 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
20724 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
20725 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
20726 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
20727 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
20728 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
20729 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
20730 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
20731 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
20732 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
20733 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
20734 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
20735 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
20736 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
20737 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
20738 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
20739 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
20740 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
20741 | #define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
20742 | //FMT3_FMT_DITHER_RAND_R_SEED |
20743 | #define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
20744 | #define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
20745 | #define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
20746 | #define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
20747 | //FMT3_FMT_DITHER_RAND_G_SEED |
20748 | #define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
20749 | #define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
20750 | #define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
20751 | #define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
20752 | //FMT3_FMT_DITHER_RAND_B_SEED |
20753 | #define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
20754 | #define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
20755 | #define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
20756 | #define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
20757 | //FMT3_FMT_CLAMP_CNTL |
20758 | #define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
20759 | #define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
20760 | #define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
20761 | #define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
20762 | //FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
20763 | #define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
20764 | #define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
20765 | //FMT3_FMT_MAP420_MEMORY_CONTROL |
20766 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
20767 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
20768 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
20769 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
20770 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
20771 | #define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
20772 | |
20773 | |
20774 | // addressBlock: dce_dc_opp_oppbuf3_dispdec |
20775 | //OPPBUF3_OPPBUF_CONTROL |
20776 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
20777 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
20778 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
20779 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
20780 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
20781 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
20782 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
20783 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
20784 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
20785 | #define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
20786 | //OPPBUF3_OPPBUF_3D_PARAMETERS_0 |
20787 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
20788 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
20789 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
20790 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
20791 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
20792 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
20793 | //OPPBUF3_OPPBUF_3D_PARAMETERS_1 |
20794 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
20795 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
20796 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
20797 | #define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
20798 | |
20799 | |
20800 | // addressBlock: dce_dc_opp_opp_pipe3_dispdec |
20801 | //OPP_PIPE3_OPP_PIPE_CONTROL |
20802 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
20803 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
20804 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
20805 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
20806 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
20807 | #define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
20808 | |
20809 | |
20810 | // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec |
20811 | //OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL |
20812 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
20813 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
20814 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
20815 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
20816 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
20817 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
20818 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
20819 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
20820 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
20821 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
20822 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
20823 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
20824 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
20825 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
20826 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
20827 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
20828 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
20829 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
20830 | //OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK |
20831 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
20832 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
20833 | //OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 |
20834 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
20835 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
20836 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
20837 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
20838 | //OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 |
20839 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
20840 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
20841 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
20842 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
20843 | //OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 |
20844 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
20845 | #define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
20846 | |
20847 | |
20848 | // addressBlock: dce_dc_opp_fmt4_dispdec |
20849 | //FMT4_FMT_CLAMP_COMPONENT_R |
20850 | #define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
20851 | #define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
20852 | #define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
20853 | #define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
20854 | //FMT4_FMT_CLAMP_COMPONENT_G |
20855 | #define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
20856 | #define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
20857 | #define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
20858 | #define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
20859 | //FMT4_FMT_CLAMP_COMPONENT_B |
20860 | #define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
20861 | #define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
20862 | #define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
20863 | #define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
20864 | //FMT4_FMT_DYNAMIC_EXP_CNTL |
20865 | #define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
20866 | #define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
20867 | #define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
20868 | #define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
20869 | //FMT4_FMT_CONTROL |
20870 | #define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
20871 | #define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
20872 | #define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
20873 | #define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
20874 | #define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
20875 | #define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
20876 | #define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
20877 | #define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
20878 | #define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
20879 | #define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
20880 | #define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
20881 | #define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
20882 | #define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
20883 | #define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
20884 | #define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
20885 | #define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
20886 | //FMT4_FMT_BIT_DEPTH_CONTROL |
20887 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
20888 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
20889 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
20890 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
20891 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
20892 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
20893 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
20894 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
20895 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
20896 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
20897 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
20898 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
20899 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
20900 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
20901 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
20902 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
20903 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
20904 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
20905 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
20906 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
20907 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
20908 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
20909 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
20910 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
20911 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
20912 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
20913 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
20914 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
20915 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
20916 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
20917 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
20918 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
20919 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
20920 | #define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
20921 | //FMT4_FMT_DITHER_RAND_R_SEED |
20922 | #define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
20923 | #define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
20924 | #define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
20925 | #define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
20926 | //FMT4_FMT_DITHER_RAND_G_SEED |
20927 | #define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
20928 | #define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
20929 | #define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
20930 | #define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
20931 | //FMT4_FMT_DITHER_RAND_B_SEED |
20932 | #define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
20933 | #define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
20934 | #define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
20935 | #define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
20936 | //FMT4_FMT_CLAMP_CNTL |
20937 | #define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
20938 | #define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
20939 | #define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
20940 | #define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
20941 | //FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
20942 | #define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
20943 | #define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
20944 | //FMT4_FMT_MAP420_MEMORY_CONTROL |
20945 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
20946 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
20947 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
20948 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
20949 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
20950 | #define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
20951 | |
20952 | |
20953 | // addressBlock: dce_dc_opp_oppbuf4_dispdec |
20954 | //OPPBUF4_OPPBUF_CONTROL |
20955 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
20956 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
20957 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
20958 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
20959 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
20960 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
20961 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
20962 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
20963 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
20964 | #define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
20965 | //OPPBUF4_OPPBUF_3D_PARAMETERS_0 |
20966 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
20967 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
20968 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
20969 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
20970 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
20971 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
20972 | //OPPBUF4_OPPBUF_3D_PARAMETERS_1 |
20973 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
20974 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
20975 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
20976 | #define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
20977 | |
20978 | |
20979 | // addressBlock: dce_dc_opp_opp_pipe4_dispdec |
20980 | //OPP_PIPE4_OPP_PIPE_CONTROL |
20981 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
20982 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
20983 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
20984 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
20985 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
20986 | #define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
20987 | |
20988 | |
20989 | // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec |
20990 | //OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL |
20991 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
20992 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
20993 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
20994 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
20995 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
20996 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
20997 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
20998 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
20999 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
21000 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
21001 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
21002 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
21003 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
21004 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
21005 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
21006 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
21007 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
21008 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
21009 | //OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK |
21010 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
21011 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
21012 | //OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 |
21013 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
21014 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
21015 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
21016 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
21017 | //OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 |
21018 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
21019 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
21020 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
21021 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
21022 | //OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 |
21023 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
21024 | #define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
21025 | |
21026 | |
21027 | // addressBlock: dce_dc_opp_fmt5_dispdec |
21028 | //FMT5_FMT_CLAMP_COMPONENT_R |
21029 | #define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
21030 | #define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
21031 | #define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL |
21032 | #define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L |
21033 | //FMT5_FMT_CLAMP_COMPONENT_G |
21034 | #define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
21035 | #define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
21036 | #define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL |
21037 | #define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L |
21038 | //FMT5_FMT_CLAMP_COMPONENT_B |
21039 | #define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
21040 | #define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
21041 | #define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL |
21042 | #define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L |
21043 | //FMT5_FMT_DYNAMIC_EXP_CNTL |
21044 | #define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
21045 | #define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
21046 | #define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L |
21047 | #define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L |
21048 | //FMT5_FMT_CONTROL |
21049 | #define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
21050 | #define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 |
21051 | #define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc |
21052 | #define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
21053 | #define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 |
21054 | #define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 |
21055 | #define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 |
21056 | #define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 |
21057 | #define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L |
21058 | #define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L |
21059 | #define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L |
21060 | #define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L |
21061 | #define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L |
21062 | #define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L |
21063 | #define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L |
21064 | #define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L |
21065 | //FMT5_FMT_BIT_DEPTH_CONTROL |
21066 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
21067 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
21068 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
21069 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
21070 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
21071 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
21072 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
21073 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
21074 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
21075 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
21076 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
21077 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
21078 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
21079 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
21080 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
21081 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
21082 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
21083 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L |
21084 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L |
21085 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L |
21086 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L |
21087 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L |
21088 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L |
21089 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L |
21090 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L |
21091 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L |
21092 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L |
21093 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L |
21094 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L |
21095 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L |
21096 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L |
21097 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L |
21098 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L |
21099 | #define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L |
21100 | //FMT5_FMT_DITHER_RAND_R_SEED |
21101 | #define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
21102 | #define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
21103 | #define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL |
21104 | #define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L |
21105 | //FMT5_FMT_DITHER_RAND_G_SEED |
21106 | #define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
21107 | #define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
21108 | #define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL |
21109 | #define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L |
21110 | //FMT5_FMT_DITHER_RAND_B_SEED |
21111 | #define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
21112 | #define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
21113 | #define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL |
21114 | #define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L |
21115 | //FMT5_FMT_CLAMP_CNTL |
21116 | #define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
21117 | #define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
21118 | #define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L |
21119 | #define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L |
21120 | //FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL |
21121 | #define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 |
21122 | #define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL |
21123 | //FMT5_FMT_MAP420_MEMORY_CONTROL |
21124 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 |
21125 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 |
21126 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 |
21127 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L |
21128 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L |
21129 | #define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L |
21130 | |
21131 | |
21132 | // addressBlock: dce_dc_opp_oppbuf5_dispdec |
21133 | //OPPBUF5_OPPBUF_CONTROL |
21134 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 |
21135 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 |
21136 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 |
21137 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 |
21138 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c |
21139 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL |
21140 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L |
21141 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L |
21142 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L |
21143 | #define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L |
21144 | //OPPBUF5_OPPBUF_3D_PARAMETERS_0 |
21145 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 |
21146 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa |
21147 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 |
21148 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL |
21149 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L |
21150 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L |
21151 | //OPPBUF5_OPPBUF_3D_PARAMETERS_1 |
21152 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 |
21153 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 |
21154 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL |
21155 | #define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L |
21156 | |
21157 | |
21158 | // addressBlock: dce_dc_opp_opp_pipe5_dispdec |
21159 | //OPP_PIPE5_OPP_PIPE_CONTROL |
21160 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 |
21161 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 |
21162 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 |
21163 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L |
21164 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L |
21165 | #define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L |
21166 | |
21167 | |
21168 | // addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec |
21169 | //OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL |
21170 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 |
21171 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 |
21172 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 |
21173 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa |
21174 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc |
21175 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe |
21176 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 |
21177 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 |
21178 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c |
21179 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L |
21180 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L |
21181 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L |
21182 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L |
21183 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L |
21184 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L |
21185 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L |
21186 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L |
21187 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L |
21188 | //OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK |
21189 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 |
21190 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL |
21191 | //OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 |
21192 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 |
21193 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 |
21194 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL |
21195 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L |
21196 | //OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 |
21197 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 |
21198 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 |
21199 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL |
21200 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L |
21201 | //OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 |
21202 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 |
21203 | #define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL |
21204 | |
21205 | |
21206 | // addressBlock: dce_dc_opp_opp_top_dispdec |
21207 | //OPP_TOP_CLK_CONTROL |
21208 | #define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 |
21209 | #define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 |
21210 | #define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 |
21211 | #define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc |
21212 | #define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd |
21213 | #define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L |
21214 | #define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L |
21215 | #define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L |
21216 | #define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L |
21217 | #define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L |
21218 | |
21219 | |
21220 | // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec |
21221 | //DC_PERFMON17_PERFCOUNTER_CNTL |
21222 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
21223 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
21224 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
21225 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
21226 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
21227 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
21228 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
21229 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
21230 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
21231 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
21232 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
21233 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
21234 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
21235 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
21236 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
21237 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
21238 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
21239 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
21240 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
21241 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
21242 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
21243 | #define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
21244 | //DC_PERFMON17_PERFCOUNTER_CNTL2 |
21245 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
21246 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
21247 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
21248 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
21249 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
21250 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
21251 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
21252 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
21253 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
21254 | #define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
21255 | //DC_PERFMON17_PERFCOUNTER_STATE |
21256 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
21257 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
21258 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
21259 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
21260 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
21261 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
21262 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
21263 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
21264 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
21265 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
21266 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
21267 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
21268 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
21269 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
21270 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
21271 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
21272 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
21273 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
21274 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
21275 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
21276 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
21277 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
21278 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
21279 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
21280 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
21281 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
21282 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
21283 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
21284 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
21285 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
21286 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
21287 | #define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
21288 | //DC_PERFMON17_PERFMON_CNTL |
21289 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
21290 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
21291 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
21292 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
21293 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
21294 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
21295 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
21296 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
21297 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
21298 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
21299 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
21300 | #define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
21301 | //DC_PERFMON17_PERFMON_CNTL2 |
21302 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
21303 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
21304 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
21305 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
21306 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
21307 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
21308 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
21309 | #define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
21310 | //DC_PERFMON17_PERFMON_CVALUE_INT_MISC |
21311 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
21312 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
21313 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
21314 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
21315 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
21316 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
21317 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
21318 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
21319 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
21320 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
21321 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
21322 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
21323 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
21324 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
21325 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
21326 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
21327 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
21328 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
21329 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
21330 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
21331 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
21332 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
21333 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
21334 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
21335 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
21336 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
21337 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
21338 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
21339 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
21340 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
21341 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
21342 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
21343 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
21344 | #define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
21345 | //DC_PERFMON17_PERFMON_CVALUE_LOW |
21346 | #define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
21347 | #define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
21348 | //DC_PERFMON17_PERFMON_HI |
21349 | #define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
21350 | #define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
21351 | #define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
21352 | #define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
21353 | //DC_PERFMON17_PERFMON_LOW |
21354 | #define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
21355 | #define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
21356 | |
21357 | |
21358 | // addressBlock: dce_dc_optc_odm0_dispdec |
21359 | //ODM0_OPTC_INPUT_GLOBAL_CONTROL |
21360 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21361 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21362 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21363 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21364 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21365 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21366 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21367 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21368 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21369 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21370 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21371 | #define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21372 | //ODM0_OPTC_DATA_SOURCE_SELECT |
21373 | #define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21374 | #define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21375 | //ODM0_OPTC_INPUT_CLOCK_CONTROL |
21376 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21377 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21378 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21379 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21380 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21381 | #define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21382 | //ODM0_OPTC_INPUT_SPARE_REGISTER |
21383 | #define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21384 | #define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21385 | |
21386 | |
21387 | // addressBlock: dce_dc_optc_odm1_dispdec |
21388 | //ODM1_OPTC_INPUT_GLOBAL_CONTROL |
21389 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21390 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21391 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21392 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21393 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21394 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21395 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21396 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21397 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21398 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21399 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21400 | #define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21401 | //ODM1_OPTC_DATA_SOURCE_SELECT |
21402 | #define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21403 | #define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21404 | //ODM1_OPTC_INPUT_CLOCK_CONTROL |
21405 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21406 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21407 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21408 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21409 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21410 | #define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21411 | //ODM1_OPTC_INPUT_SPARE_REGISTER |
21412 | #define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21413 | #define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21414 | |
21415 | |
21416 | // addressBlock: dce_dc_optc_odm2_dispdec |
21417 | //ODM2_OPTC_INPUT_GLOBAL_CONTROL |
21418 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21419 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21420 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21421 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21422 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21423 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21424 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21425 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21426 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21427 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21428 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21429 | #define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21430 | //ODM2_OPTC_DATA_SOURCE_SELECT |
21431 | #define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21432 | #define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21433 | //ODM2_OPTC_INPUT_CLOCK_CONTROL |
21434 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21435 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21436 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21437 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21438 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21439 | #define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21440 | //ODM2_OPTC_INPUT_SPARE_REGISTER |
21441 | #define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21442 | #define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21443 | |
21444 | |
21445 | // addressBlock: dce_dc_optc_odm3_dispdec |
21446 | //ODM3_OPTC_INPUT_GLOBAL_CONTROL |
21447 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21448 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21449 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21450 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21451 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21452 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21453 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21454 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21455 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21456 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21457 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21458 | #define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21459 | //ODM3_OPTC_DATA_SOURCE_SELECT |
21460 | #define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21461 | #define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21462 | //ODM3_OPTC_INPUT_CLOCK_CONTROL |
21463 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21464 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21465 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21466 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21467 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21468 | #define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21469 | //ODM3_OPTC_INPUT_SPARE_REGISTER |
21470 | #define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21471 | #define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21472 | |
21473 | |
21474 | // addressBlock: dce_dc_optc_odm4_dispdec |
21475 | //ODM4_OPTC_INPUT_GLOBAL_CONTROL |
21476 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21477 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21478 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21479 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21480 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21481 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21482 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21483 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21484 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21485 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21486 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21487 | #define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21488 | //ODM4_OPTC_DATA_SOURCE_SELECT |
21489 | #define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21490 | #define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21491 | //ODM4_OPTC_INPUT_CLOCK_CONTROL |
21492 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21493 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21494 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21495 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21496 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21497 | #define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21498 | //ODM4_OPTC_INPUT_SPARE_REGISTER |
21499 | #define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21500 | #define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21501 | |
21502 | |
21503 | // addressBlock: dce_dc_optc_odm5_dispdec |
21504 | //ODM5_OPTC_INPUT_GLOBAL_CONTROL |
21505 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 |
21506 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 |
21507 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 |
21508 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa |
21509 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb |
21510 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc |
21511 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L |
21512 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L |
21513 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L |
21514 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L |
21515 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L |
21516 | #define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L |
21517 | //ODM5_OPTC_DATA_SOURCE_SELECT |
21518 | #define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT 0x8 |
21519 | #define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK 0x00000700L |
21520 | //ODM5_OPTC_INPUT_CLOCK_CONTROL |
21521 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 |
21522 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 |
21523 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 |
21524 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L |
21525 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L |
21526 | #define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L |
21527 | //ODM5_OPTC_INPUT_SPARE_REGISTER |
21528 | #define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 |
21529 | #define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL |
21530 | |
21531 | |
21532 | // addressBlock: dce_dc_optc_otg0_dispdec |
21533 | //OTG0_OTG_H_TOTAL |
21534 | #define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
21535 | #define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
21536 | //OTG0_OTG_H_BLANK_START_END |
21537 | #define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
21538 | #define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
21539 | #define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
21540 | #define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
21541 | //OTG0_OTG_H_SYNC_A |
21542 | #define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
21543 | #define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
21544 | #define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
21545 | #define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
21546 | //OTG0_OTG_H_SYNC_A_CNTL |
21547 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
21548 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
21549 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
21550 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
21551 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
21552 | #define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
21553 | //OTG0_OTG_H_TIMING_CNTL |
21554 | #define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
21555 | #define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
21556 | #define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
21557 | #define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
21558 | //OTG0_OTG_V_TOTAL |
21559 | #define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
21560 | #define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
21561 | //OTG0_OTG_V_TOTAL_MIN |
21562 | #define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
21563 | #define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
21564 | //OTG0_OTG_V_TOTAL_MAX |
21565 | #define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
21566 | #define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
21567 | //OTG0_OTG_V_TOTAL_MID |
21568 | #define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
21569 | #define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
21570 | //OTG0_OTG_V_TOTAL_CONTROL |
21571 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
21572 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
21573 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
21574 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
21575 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
21576 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
21577 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
21578 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
21579 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
21580 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
21581 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
21582 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
21583 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
21584 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
21585 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
21586 | #define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
21587 | //OTG0_OTG_V_TOTAL_INT_STATUS |
21588 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
21589 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
21590 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
21591 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
21592 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
21593 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
21594 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
21595 | #define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
21596 | //OTG0_OTG_VSYNC_NOM_INT_STATUS |
21597 | #define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
21598 | #define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
21599 | #define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
21600 | #define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
21601 | //OTG0_OTG_V_BLANK_START_END |
21602 | #define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
21603 | #define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
21604 | #define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
21605 | #define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
21606 | //OTG0_OTG_V_SYNC_A |
21607 | #define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
21608 | #define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
21609 | #define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
21610 | #define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
21611 | //OTG0_OTG_V_SYNC_A_CNTL |
21612 | #define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
21613 | #define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
21614 | //OTG0_OTG_TRIGA_CNTL |
21615 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
21616 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
21617 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
21618 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
21619 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
21620 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
21621 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
21622 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
21623 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
21624 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
21625 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
21626 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
21627 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
21628 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
21629 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
21630 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
21631 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
21632 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
21633 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
21634 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
21635 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
21636 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
21637 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
21638 | #define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
21639 | //OTG0_OTG_TRIGA_MANUAL_TRIG |
21640 | #define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
21641 | #define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
21642 | //OTG0_OTG_TRIGB_CNTL |
21643 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
21644 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
21645 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
21646 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
21647 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
21648 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
21649 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
21650 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
21651 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
21652 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
21653 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
21654 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
21655 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
21656 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
21657 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
21658 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
21659 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
21660 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
21661 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
21662 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
21663 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
21664 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
21665 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
21666 | #define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
21667 | //OTG0_OTG_TRIGB_MANUAL_TRIG |
21668 | #define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
21669 | #define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
21670 | //OTG0_OTG_FORCE_COUNT_NOW_CNTL |
21671 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
21672 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
21673 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
21674 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
21675 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
21676 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
21677 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
21678 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
21679 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
21680 | #define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
21681 | //OTG0_OTG_FLOW_CONTROL |
21682 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
21683 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
21684 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
21685 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
21686 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
21687 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
21688 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
21689 | #define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
21690 | //OTG0_OTG_STEREO_FORCE_NEXT_EYE |
21691 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
21692 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
21693 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
21694 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
21695 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
21696 | #define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
21697 | //OTG0_OTG_AVSYNC_COUNTER |
21698 | #define OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
21699 | #define OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
21700 | //OTG0_OTG_CONTROL |
21701 | #define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
21702 | #define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
21703 | #define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
21704 | #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
21705 | #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
21706 | #define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
21707 | #define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
21708 | #define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
21709 | #define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
21710 | #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
21711 | #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
21712 | #define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
21713 | //OTG0_OTG_BLANK_CONTROL |
21714 | #define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
21715 | #define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
21716 | #define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
21717 | #define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
21718 | #define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
21719 | #define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
21720 | //OTG0_OTG_PIPE_ABORT_CONTROL |
21721 | #define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
21722 | #define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
21723 | #define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
21724 | #define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
21725 | //OTG0_OTG_INTERLACE_CONTROL |
21726 | #define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
21727 | #define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
21728 | #define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
21729 | #define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
21730 | //OTG0_OTG_INTERLACE_STATUS |
21731 | #define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
21732 | #define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
21733 | #define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
21734 | #define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
21735 | //OTG0_OTG_FIELD_INDICATION_CONTROL |
21736 | #define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
21737 | #define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
21738 | #define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
21739 | #define OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
21740 | //OTG0_OTG_PIXEL_DATA_READBACK0 |
21741 | #define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
21742 | #define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
21743 | #define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
21744 | #define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
21745 | //OTG0_OTG_PIXEL_DATA_READBACK1 |
21746 | #define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
21747 | #define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
21748 | //OTG0_OTG_STATUS |
21749 | #define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
21750 | #define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
21751 | #define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
21752 | #define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
21753 | #define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
21754 | #define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
21755 | #define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
21756 | #define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
21757 | #define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
21758 | #define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
21759 | #define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
21760 | #define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
21761 | #define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
21762 | #define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
21763 | #define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
21764 | #define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
21765 | //OTG0_OTG_STATUS_POSITION |
21766 | #define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
21767 | #define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
21768 | #define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
21769 | #define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
21770 | //OTG0_OTG_NOM_VERT_POSITION |
21771 | #define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
21772 | #define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
21773 | //OTG0_OTG_STATUS_FRAME_COUNT |
21774 | #define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
21775 | #define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
21776 | //OTG0_OTG_STATUS_VF_COUNT |
21777 | #define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
21778 | #define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
21779 | //OTG0_OTG_STATUS_HV_COUNT |
21780 | #define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
21781 | #define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
21782 | //OTG0_OTG_COUNT_CONTROL |
21783 | #define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
21784 | #define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
21785 | #define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
21786 | #define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
21787 | //OTG0_OTG_COUNT_RESET |
21788 | #define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
21789 | #define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
21790 | //OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
21791 | #define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
21792 | #define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
21793 | //OTG0_OTG_VERT_SYNC_CONTROL |
21794 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
21795 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
21796 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
21797 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
21798 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
21799 | #define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
21800 | //OTG0_OTG_STEREO_STATUS |
21801 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
21802 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
21803 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
21804 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
21805 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
21806 | #define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
21807 | #define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
21808 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
21809 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
21810 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
21811 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
21812 | #define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
21813 | #define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
21814 | #define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
21815 | //OTG0_OTG_STEREO_CONTROL |
21816 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
21817 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
21818 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
21819 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
21820 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
21821 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
21822 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
21823 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
21824 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
21825 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
21826 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
21827 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
21828 | #define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
21829 | #define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
21830 | //OTG0_OTG_SNAPSHOT_STATUS |
21831 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
21832 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
21833 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
21834 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
21835 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
21836 | #define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
21837 | //OTG0_OTG_SNAPSHOT_CONTROL |
21838 | #define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
21839 | #define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
21840 | //OTG0_OTG_SNAPSHOT_POSITION |
21841 | #define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
21842 | #define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
21843 | #define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
21844 | #define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
21845 | //OTG0_OTG_SNAPSHOT_FRAME |
21846 | #define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
21847 | #define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
21848 | //OTG0_OTG_INTERRUPT_CONTROL |
21849 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
21850 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
21851 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
21852 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
21853 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
21854 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
21855 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
21856 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
21857 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
21858 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
21859 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
21860 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
21861 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
21862 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
21863 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
21864 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
21865 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
21866 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
21867 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
21868 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
21869 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
21870 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
21871 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
21872 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
21873 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
21874 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
21875 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
21876 | #define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
21877 | //OTG0_OTG_UPDATE_LOCK |
21878 | #define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
21879 | #define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
21880 | //OTG0_OTG_DOUBLE_BUFFER_CONTROL |
21881 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
21882 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
21883 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
21884 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
21885 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
21886 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
21887 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
21888 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
21889 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
21890 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
21891 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
21892 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
21893 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
21894 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
21895 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
21896 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
21897 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
21898 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
21899 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
21900 | #define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
21901 | //OTG0_OTG_TEST_PATTERN_CONTROL |
21902 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
21903 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
21904 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
21905 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
21906 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
21907 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
21908 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
21909 | #define OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
21910 | //OTG0_OTG_TEST_PATTERN_PARAMETERS |
21911 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
21912 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
21913 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
21914 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
21915 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
21916 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
21917 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
21918 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
21919 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
21920 | #define OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
21921 | //OTG0_OTG_TEST_PATTERN_COLOR |
21922 | #define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
21923 | #define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
21924 | #define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
21925 | #define OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
21926 | //OTG0_OTG_MASTER_EN |
21927 | #define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
21928 | #define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
21929 | //OTG0_OTG_BLANK_DATA_COLOR |
21930 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
21931 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
21932 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
21933 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
21934 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
21935 | #define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
21936 | //OTG0_OTG_BLANK_DATA_COLOR_EXT |
21937 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
21938 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
21939 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
21940 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
21941 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
21942 | #define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
21943 | //OTG0_OTG_BLACK_COLOR |
21944 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
21945 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
21946 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
21947 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
21948 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
21949 | #define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
21950 | //OTG0_OTG_BLACK_COLOR_EXT |
21951 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
21952 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
21953 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
21954 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
21955 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
21956 | #define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
21957 | //OTG0_OTG_VERTICAL_INTERRUPT0_POSITION |
21958 | #define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
21959 | #define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
21960 | #define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
21961 | #define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
21962 | //OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL |
21963 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
21964 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
21965 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
21966 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
21967 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
21968 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
21969 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
21970 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
21971 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
21972 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
21973 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
21974 | #define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
21975 | //OTG0_OTG_VERTICAL_INTERRUPT1_POSITION |
21976 | #define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
21977 | #define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
21978 | //OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL |
21979 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
21980 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
21981 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
21982 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
21983 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
21984 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
21985 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
21986 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
21987 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
21988 | #define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
21989 | //OTG0_OTG_VERTICAL_INTERRUPT2_POSITION |
21990 | #define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
21991 | #define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
21992 | //OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL |
21993 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
21994 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
21995 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
21996 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
21997 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
21998 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
21999 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
22000 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
22001 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
22002 | #define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
22003 | //OTG0_OTG_CRC_CNTL |
22004 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
22005 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
22006 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
22007 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
22008 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
22009 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
22010 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
22011 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
22012 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
22013 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
22014 | #define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
22015 | #define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
22016 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
22017 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
22018 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
22019 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
22020 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
22021 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
22022 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
22023 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
22024 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
22025 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
22026 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
22027 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
22028 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
22029 | #define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
22030 | #define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
22031 | #define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
22032 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
22033 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
22034 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
22035 | #define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
22036 | //OTG0_OTG_CRC0_WINDOWA_X_CONTROL |
22037 | #define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
22038 | #define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
22039 | #define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
22040 | #define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
22041 | //OTG0_OTG_CRC0_WINDOWA_Y_CONTROL |
22042 | #define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
22043 | #define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
22044 | #define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
22045 | #define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
22046 | //OTG0_OTG_CRC0_WINDOWB_X_CONTROL |
22047 | #define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
22048 | #define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
22049 | #define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
22050 | #define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
22051 | //OTG0_OTG_CRC0_WINDOWB_Y_CONTROL |
22052 | #define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
22053 | #define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
22054 | #define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
22055 | #define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
22056 | //OTG0_OTG_CRC0_DATA_RG |
22057 | #define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
22058 | #define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
22059 | #define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
22060 | #define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
22061 | //OTG0_OTG_CRC0_DATA_B |
22062 | #define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
22063 | #define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
22064 | #define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
22065 | #define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
22066 | //OTG0_OTG_CRC1_WINDOWA_X_CONTROL |
22067 | #define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
22068 | #define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
22069 | #define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
22070 | #define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
22071 | //OTG0_OTG_CRC1_WINDOWA_Y_CONTROL |
22072 | #define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
22073 | #define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
22074 | #define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
22075 | #define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
22076 | //OTG0_OTG_CRC1_WINDOWB_X_CONTROL |
22077 | #define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
22078 | #define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
22079 | #define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
22080 | #define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
22081 | //OTG0_OTG_CRC1_WINDOWB_Y_CONTROL |
22082 | #define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
22083 | #define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
22084 | #define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
22085 | #define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
22086 | //OTG0_OTG_CRC1_DATA_RG |
22087 | #define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
22088 | #define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
22089 | #define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
22090 | #define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
22091 | //OTG0_OTG_CRC1_DATA_B |
22092 | #define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
22093 | #define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
22094 | #define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
22095 | #define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
22096 | //OTG0_OTG_CRC2_DATA_RG |
22097 | #define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
22098 | #define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
22099 | #define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
22100 | #define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
22101 | //OTG0_OTG_CRC2_DATA_B |
22102 | #define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
22103 | #define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
22104 | #define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
22105 | #define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
22106 | //OTG0_OTG_CRC3_DATA_RG |
22107 | #define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
22108 | #define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
22109 | #define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
22110 | #define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
22111 | //OTG0_OTG_CRC3_DATA_B |
22112 | #define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
22113 | #define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
22114 | #define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
22115 | #define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
22116 | //OTG0_OTG_CRC_SIG_RED_GREEN_MASK |
22117 | #define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
22118 | #define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
22119 | #define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
22120 | #define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
22121 | //OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK |
22122 | #define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
22123 | #define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
22124 | #define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
22125 | #define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
22126 | //OTG0_OTG_STATIC_SCREEN_CONTROL |
22127 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
22128 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
22129 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
22130 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
22131 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
22132 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
22133 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
22134 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
22135 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
22136 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
22137 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
22138 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
22139 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
22140 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
22141 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
22142 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
22143 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
22144 | #define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
22145 | //OTG0_OTG_3D_STRUCTURE_CONTROL |
22146 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
22147 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
22148 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
22149 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
22150 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
22151 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
22152 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
22153 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
22154 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
22155 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
22156 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
22157 | #define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
22158 | //OTG0_OTG_GSL_VSYNC_GAP |
22159 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
22160 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
22161 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
22162 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
22163 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
22164 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
22165 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
22166 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
22167 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
22168 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
22169 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
22170 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
22171 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
22172 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
22173 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
22174 | #define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
22175 | //OTG0_OTG_MASTER_UPDATE_MODE |
22176 | #define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
22177 | #define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
22178 | //OTG0_OTG_CLOCK_CONTROL |
22179 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
22180 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
22181 | #define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
22182 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
22183 | #define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
22184 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
22185 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
22186 | #define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
22187 | #define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
22188 | #define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
22189 | //OTG0_OTG_VSTARTUP_PARAM |
22190 | #define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
22191 | #define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
22192 | //OTG0_OTG_VUPDATE_PARAM |
22193 | #define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
22194 | #define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
22195 | #define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
22196 | #define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
22197 | //OTG0_OTG_VREADY_PARAM |
22198 | #define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
22199 | #define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
22200 | //OTG0_OTG_GLOBAL_SYNC_STATUS |
22201 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
22202 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
22203 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
22204 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
22205 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
22206 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
22207 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
22208 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
22209 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
22210 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
22211 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
22212 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
22213 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
22214 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
22215 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
22216 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
22217 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
22218 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
22219 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
22220 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
22221 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
22222 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
22223 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
22224 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
22225 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
22226 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
22227 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
22228 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
22229 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
22230 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
22231 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
22232 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
22233 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
22234 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
22235 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
22236 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
22237 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
22238 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
22239 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
22240 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
22241 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
22242 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
22243 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
22244 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
22245 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
22246 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
22247 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
22248 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
22249 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
22250 | #define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
22251 | //OTG0_OTG_MASTER_UPDATE_LOCK |
22252 | #define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
22253 | #define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
22254 | #define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
22255 | #define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
22256 | //OTG0_OTG_GSL_CONTROL |
22257 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
22258 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
22259 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
22260 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
22261 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
22262 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
22263 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
22264 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
22265 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
22266 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
22267 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
22268 | #define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
22269 | //OTG0_OTG_GSL_WINDOW_X |
22270 | #define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
22271 | #define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
22272 | #define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
22273 | #define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
22274 | //OTG0_OTG_GSL_WINDOW_Y |
22275 | #define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
22276 | #define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
22277 | #define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
22278 | #define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
22279 | //OTG0_OTG_VUPDATE_KEEPOUT |
22280 | #define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
22281 | #define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
22282 | #define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
22283 | #define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
22284 | #define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
22285 | #define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
22286 | //OTG0_OTG_GLOBAL_CONTROL0 |
22287 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
22288 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
22289 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
22290 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
22291 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
22292 | #define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
22293 | //OTG0_OTG_GLOBAL_CONTROL1 |
22294 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
22295 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
22296 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
22297 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
22298 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
22299 | #define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
22300 | //OTG0_OTG_GLOBAL_CONTROL2 |
22301 | #define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
22302 | #define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
22303 | #define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
22304 | #define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
22305 | #define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
22306 | #define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
22307 | #define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
22308 | #define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
22309 | //OTG0_OTG_GLOBAL_CONTROL3 |
22310 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
22311 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
22312 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
22313 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
22314 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
22315 | #define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
22316 | //OTG0_OTG_TRIG_MANUAL_CONTROL |
22317 | #define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
22318 | #define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
22319 | //OTG0_OTG_MANUAL_FLOW_CONTROL |
22320 | #define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
22321 | #define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
22322 | //OTG0_OTG_RANGE_TIMING_INT_STATUS |
22323 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
22324 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
22325 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
22326 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
22327 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
22328 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
22329 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
22330 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
22331 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
22332 | #define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
22333 | //OTG0_OTG_DRR_CONTROL |
22334 | #define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
22335 | #define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
22336 | #define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
22337 | #define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
22338 | //OTG0_OTG_REQUEST_CONTROL |
22339 | #define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
22340 | #define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
22341 | //OTG0_OTG_SPARE_REGISTER |
22342 | #define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
22343 | #define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
22344 | |
22345 | |
22346 | // addressBlock: dce_dc_optc_otg1_dispdec |
22347 | //OTG1_OTG_H_TOTAL |
22348 | #define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
22349 | #define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
22350 | //OTG1_OTG_H_BLANK_START_END |
22351 | #define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
22352 | #define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
22353 | #define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
22354 | #define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
22355 | //OTG1_OTG_H_SYNC_A |
22356 | #define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
22357 | #define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
22358 | #define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
22359 | #define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
22360 | //OTG1_OTG_H_SYNC_A_CNTL |
22361 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
22362 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
22363 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
22364 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
22365 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
22366 | #define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
22367 | //OTG1_OTG_H_TIMING_CNTL |
22368 | #define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
22369 | #define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
22370 | #define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
22371 | #define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
22372 | //OTG1_OTG_V_TOTAL |
22373 | #define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
22374 | #define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
22375 | //OTG1_OTG_V_TOTAL_MIN |
22376 | #define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
22377 | #define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
22378 | //OTG1_OTG_V_TOTAL_MAX |
22379 | #define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
22380 | #define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
22381 | //OTG1_OTG_V_TOTAL_MID |
22382 | #define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
22383 | #define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
22384 | //OTG1_OTG_V_TOTAL_CONTROL |
22385 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
22386 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
22387 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
22388 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
22389 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
22390 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
22391 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
22392 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
22393 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
22394 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
22395 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
22396 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
22397 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
22398 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
22399 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
22400 | #define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
22401 | //OTG1_OTG_V_TOTAL_INT_STATUS |
22402 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
22403 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
22404 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
22405 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
22406 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
22407 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
22408 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
22409 | #define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
22410 | //OTG1_OTG_VSYNC_NOM_INT_STATUS |
22411 | #define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
22412 | #define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
22413 | #define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
22414 | #define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
22415 | //OTG1_OTG_V_BLANK_START_END |
22416 | #define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
22417 | #define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
22418 | #define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
22419 | #define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
22420 | //OTG1_OTG_V_SYNC_A |
22421 | #define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
22422 | #define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
22423 | #define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
22424 | #define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
22425 | //OTG1_OTG_V_SYNC_A_CNTL |
22426 | #define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
22427 | #define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
22428 | //OTG1_OTG_TRIGA_CNTL |
22429 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
22430 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
22431 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
22432 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
22433 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
22434 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
22435 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
22436 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
22437 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
22438 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
22439 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
22440 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
22441 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
22442 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
22443 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
22444 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
22445 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
22446 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
22447 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
22448 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
22449 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
22450 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
22451 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
22452 | #define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
22453 | //OTG1_OTG_TRIGA_MANUAL_TRIG |
22454 | #define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
22455 | #define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
22456 | //OTG1_OTG_TRIGB_CNTL |
22457 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
22458 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
22459 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
22460 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
22461 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
22462 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
22463 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
22464 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
22465 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
22466 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
22467 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
22468 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
22469 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
22470 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
22471 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
22472 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
22473 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
22474 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
22475 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
22476 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
22477 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
22478 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
22479 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
22480 | #define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
22481 | //OTG1_OTG_TRIGB_MANUAL_TRIG |
22482 | #define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
22483 | #define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
22484 | //OTG1_OTG_FORCE_COUNT_NOW_CNTL |
22485 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
22486 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
22487 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
22488 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
22489 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
22490 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
22491 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
22492 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
22493 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
22494 | #define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
22495 | //OTG1_OTG_FLOW_CONTROL |
22496 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
22497 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
22498 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
22499 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
22500 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
22501 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
22502 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
22503 | #define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
22504 | //OTG1_OTG_STEREO_FORCE_NEXT_EYE |
22505 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
22506 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
22507 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
22508 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
22509 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
22510 | #define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
22511 | //OTG1_OTG_AVSYNC_COUNTER |
22512 | #define OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
22513 | #define OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
22514 | //OTG1_OTG_CONTROL |
22515 | #define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
22516 | #define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
22517 | #define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
22518 | #define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
22519 | #define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
22520 | #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
22521 | #define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
22522 | #define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
22523 | #define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
22524 | #define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
22525 | #define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
22526 | #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
22527 | //OTG1_OTG_BLANK_CONTROL |
22528 | #define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
22529 | #define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
22530 | #define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
22531 | #define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
22532 | #define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
22533 | #define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
22534 | //OTG1_OTG_PIPE_ABORT_CONTROL |
22535 | #define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
22536 | #define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
22537 | #define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
22538 | #define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
22539 | //OTG1_OTG_INTERLACE_CONTROL |
22540 | #define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
22541 | #define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
22542 | #define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
22543 | #define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
22544 | //OTG1_OTG_INTERLACE_STATUS |
22545 | #define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
22546 | #define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
22547 | #define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
22548 | #define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
22549 | //OTG1_OTG_FIELD_INDICATION_CONTROL |
22550 | #define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
22551 | #define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
22552 | #define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
22553 | #define OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
22554 | //OTG1_OTG_PIXEL_DATA_READBACK0 |
22555 | #define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
22556 | #define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
22557 | #define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
22558 | #define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
22559 | //OTG1_OTG_PIXEL_DATA_READBACK1 |
22560 | #define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
22561 | #define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
22562 | //OTG1_OTG_STATUS |
22563 | #define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
22564 | #define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
22565 | #define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
22566 | #define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
22567 | #define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
22568 | #define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
22569 | #define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
22570 | #define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
22571 | #define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
22572 | #define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
22573 | #define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
22574 | #define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
22575 | #define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
22576 | #define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
22577 | #define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
22578 | #define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
22579 | //OTG1_OTG_STATUS_POSITION |
22580 | #define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
22581 | #define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
22582 | #define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
22583 | #define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
22584 | //OTG1_OTG_NOM_VERT_POSITION |
22585 | #define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
22586 | #define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
22587 | //OTG1_OTG_STATUS_FRAME_COUNT |
22588 | #define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
22589 | #define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
22590 | //OTG1_OTG_STATUS_VF_COUNT |
22591 | #define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
22592 | #define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
22593 | //OTG1_OTG_STATUS_HV_COUNT |
22594 | #define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
22595 | #define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
22596 | //OTG1_OTG_COUNT_CONTROL |
22597 | #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
22598 | #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
22599 | #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
22600 | #define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
22601 | //OTG1_OTG_COUNT_RESET |
22602 | #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
22603 | #define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
22604 | //OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
22605 | #define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
22606 | #define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
22607 | //OTG1_OTG_VERT_SYNC_CONTROL |
22608 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
22609 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
22610 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
22611 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
22612 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
22613 | #define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
22614 | //OTG1_OTG_STEREO_STATUS |
22615 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
22616 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
22617 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
22618 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
22619 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
22620 | #define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
22621 | #define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
22622 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
22623 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
22624 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
22625 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
22626 | #define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
22627 | #define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
22628 | #define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
22629 | //OTG1_OTG_STEREO_CONTROL |
22630 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
22631 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
22632 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
22633 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
22634 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
22635 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
22636 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
22637 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
22638 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
22639 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
22640 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
22641 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
22642 | #define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
22643 | #define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
22644 | //OTG1_OTG_SNAPSHOT_STATUS |
22645 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
22646 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
22647 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
22648 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
22649 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
22650 | #define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
22651 | //OTG1_OTG_SNAPSHOT_CONTROL |
22652 | #define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
22653 | #define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
22654 | //OTG1_OTG_SNAPSHOT_POSITION |
22655 | #define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
22656 | #define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
22657 | #define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
22658 | #define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
22659 | //OTG1_OTG_SNAPSHOT_FRAME |
22660 | #define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
22661 | #define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
22662 | //OTG1_OTG_INTERRUPT_CONTROL |
22663 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
22664 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
22665 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
22666 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
22667 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
22668 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
22669 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
22670 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
22671 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
22672 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
22673 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
22674 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
22675 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
22676 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
22677 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
22678 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
22679 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
22680 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
22681 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
22682 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
22683 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
22684 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
22685 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
22686 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
22687 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
22688 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
22689 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
22690 | #define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
22691 | //OTG1_OTG_UPDATE_LOCK |
22692 | #define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
22693 | #define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
22694 | //OTG1_OTG_DOUBLE_BUFFER_CONTROL |
22695 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
22696 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
22697 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
22698 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
22699 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
22700 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
22701 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
22702 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
22703 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
22704 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
22705 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
22706 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
22707 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
22708 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
22709 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
22710 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
22711 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
22712 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
22713 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
22714 | #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
22715 | //OTG1_OTG_TEST_PATTERN_CONTROL |
22716 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
22717 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
22718 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
22719 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
22720 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
22721 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
22722 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
22723 | #define OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
22724 | //OTG1_OTG_TEST_PATTERN_PARAMETERS |
22725 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
22726 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
22727 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
22728 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
22729 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
22730 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
22731 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
22732 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
22733 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
22734 | #define OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
22735 | //OTG1_OTG_TEST_PATTERN_COLOR |
22736 | #define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
22737 | #define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
22738 | #define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
22739 | #define OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
22740 | //OTG1_OTG_MASTER_EN |
22741 | #define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
22742 | #define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
22743 | //OTG1_OTG_BLANK_DATA_COLOR |
22744 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
22745 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
22746 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
22747 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
22748 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
22749 | #define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
22750 | //OTG1_OTG_BLANK_DATA_COLOR_EXT |
22751 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
22752 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
22753 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
22754 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
22755 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
22756 | #define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
22757 | //OTG1_OTG_BLACK_COLOR |
22758 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
22759 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
22760 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
22761 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
22762 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
22763 | #define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
22764 | //OTG1_OTG_BLACK_COLOR_EXT |
22765 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
22766 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
22767 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
22768 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
22769 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
22770 | #define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
22771 | //OTG1_OTG_VERTICAL_INTERRUPT0_POSITION |
22772 | #define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
22773 | #define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
22774 | #define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
22775 | #define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
22776 | //OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL |
22777 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
22778 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
22779 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
22780 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
22781 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
22782 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
22783 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
22784 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
22785 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
22786 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
22787 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
22788 | #define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
22789 | //OTG1_OTG_VERTICAL_INTERRUPT1_POSITION |
22790 | #define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
22791 | #define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
22792 | //OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL |
22793 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
22794 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
22795 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
22796 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
22797 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
22798 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
22799 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
22800 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
22801 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
22802 | #define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
22803 | //OTG1_OTG_VERTICAL_INTERRUPT2_POSITION |
22804 | #define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
22805 | #define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
22806 | //OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL |
22807 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
22808 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
22809 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
22810 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
22811 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
22812 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
22813 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
22814 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
22815 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
22816 | #define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
22817 | //OTG1_OTG_CRC_CNTL |
22818 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
22819 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
22820 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
22821 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
22822 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
22823 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
22824 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
22825 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
22826 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
22827 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
22828 | #define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
22829 | #define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
22830 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
22831 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
22832 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
22833 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
22834 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
22835 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
22836 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
22837 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
22838 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
22839 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
22840 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
22841 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
22842 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
22843 | #define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
22844 | #define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
22845 | #define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
22846 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
22847 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
22848 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
22849 | #define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
22850 | //OTG1_OTG_CRC0_WINDOWA_X_CONTROL |
22851 | #define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
22852 | #define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
22853 | #define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
22854 | #define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
22855 | //OTG1_OTG_CRC0_WINDOWA_Y_CONTROL |
22856 | #define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
22857 | #define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
22858 | #define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
22859 | #define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
22860 | //OTG1_OTG_CRC0_WINDOWB_X_CONTROL |
22861 | #define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
22862 | #define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
22863 | #define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
22864 | #define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
22865 | //OTG1_OTG_CRC0_WINDOWB_Y_CONTROL |
22866 | #define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
22867 | #define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
22868 | #define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
22869 | #define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
22870 | //OTG1_OTG_CRC0_DATA_RG |
22871 | #define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
22872 | #define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
22873 | #define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
22874 | #define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
22875 | //OTG1_OTG_CRC0_DATA_B |
22876 | #define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
22877 | #define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
22878 | #define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
22879 | #define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
22880 | //OTG1_OTG_CRC1_WINDOWA_X_CONTROL |
22881 | #define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
22882 | #define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
22883 | #define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
22884 | #define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
22885 | //OTG1_OTG_CRC1_WINDOWA_Y_CONTROL |
22886 | #define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
22887 | #define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
22888 | #define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
22889 | #define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
22890 | //OTG1_OTG_CRC1_WINDOWB_X_CONTROL |
22891 | #define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
22892 | #define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
22893 | #define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
22894 | #define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
22895 | //OTG1_OTG_CRC1_WINDOWB_Y_CONTROL |
22896 | #define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
22897 | #define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
22898 | #define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
22899 | #define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
22900 | //OTG1_OTG_CRC1_DATA_RG |
22901 | #define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
22902 | #define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
22903 | #define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
22904 | #define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
22905 | //OTG1_OTG_CRC1_DATA_B |
22906 | #define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
22907 | #define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
22908 | #define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
22909 | #define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
22910 | //OTG1_OTG_CRC2_DATA_RG |
22911 | #define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
22912 | #define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
22913 | #define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
22914 | #define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
22915 | //OTG1_OTG_CRC2_DATA_B |
22916 | #define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
22917 | #define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
22918 | #define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
22919 | #define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
22920 | //OTG1_OTG_CRC3_DATA_RG |
22921 | #define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
22922 | #define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
22923 | #define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
22924 | #define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
22925 | //OTG1_OTG_CRC3_DATA_B |
22926 | #define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
22927 | #define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
22928 | #define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
22929 | #define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
22930 | //OTG1_OTG_CRC_SIG_RED_GREEN_MASK |
22931 | #define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
22932 | #define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
22933 | #define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
22934 | #define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
22935 | //OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK |
22936 | #define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
22937 | #define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
22938 | #define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
22939 | #define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
22940 | //OTG1_OTG_STATIC_SCREEN_CONTROL |
22941 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
22942 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
22943 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
22944 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
22945 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
22946 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
22947 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
22948 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
22949 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
22950 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
22951 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
22952 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
22953 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
22954 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
22955 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
22956 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
22957 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
22958 | #define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
22959 | //OTG1_OTG_3D_STRUCTURE_CONTROL |
22960 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
22961 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
22962 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
22963 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
22964 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
22965 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
22966 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
22967 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
22968 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
22969 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
22970 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
22971 | #define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
22972 | //OTG1_OTG_GSL_VSYNC_GAP |
22973 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
22974 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
22975 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
22976 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
22977 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
22978 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
22979 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
22980 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
22981 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
22982 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
22983 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
22984 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
22985 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
22986 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
22987 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
22988 | #define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
22989 | //OTG1_OTG_MASTER_UPDATE_MODE |
22990 | #define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
22991 | #define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
22992 | //OTG1_OTG_CLOCK_CONTROL |
22993 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
22994 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
22995 | #define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
22996 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
22997 | #define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
22998 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
22999 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
23000 | #define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
23001 | #define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
23002 | #define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
23003 | //OTG1_OTG_VSTARTUP_PARAM |
23004 | #define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
23005 | #define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
23006 | //OTG1_OTG_VUPDATE_PARAM |
23007 | #define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
23008 | #define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
23009 | #define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
23010 | #define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
23011 | //OTG1_OTG_VREADY_PARAM |
23012 | #define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
23013 | #define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
23014 | //OTG1_OTG_GLOBAL_SYNC_STATUS |
23015 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
23016 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
23017 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
23018 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
23019 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
23020 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
23021 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
23022 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
23023 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
23024 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
23025 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
23026 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
23027 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
23028 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
23029 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
23030 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
23031 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
23032 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
23033 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
23034 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
23035 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
23036 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
23037 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
23038 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
23039 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
23040 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
23041 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
23042 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
23043 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
23044 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
23045 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
23046 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
23047 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
23048 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
23049 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
23050 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
23051 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
23052 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
23053 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
23054 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
23055 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
23056 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
23057 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
23058 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
23059 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
23060 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
23061 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
23062 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
23063 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
23064 | #define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
23065 | //OTG1_OTG_MASTER_UPDATE_LOCK |
23066 | #define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
23067 | #define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
23068 | #define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
23069 | #define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
23070 | //OTG1_OTG_GSL_CONTROL |
23071 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
23072 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
23073 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
23074 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
23075 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
23076 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
23077 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
23078 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
23079 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
23080 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
23081 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
23082 | #define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
23083 | //OTG1_OTG_GSL_WINDOW_X |
23084 | #define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
23085 | #define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
23086 | #define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
23087 | #define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
23088 | //OTG1_OTG_GSL_WINDOW_Y |
23089 | #define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
23090 | #define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
23091 | #define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
23092 | #define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
23093 | //OTG1_OTG_VUPDATE_KEEPOUT |
23094 | #define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
23095 | #define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
23096 | #define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
23097 | #define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
23098 | #define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
23099 | #define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
23100 | //OTG1_OTG_GLOBAL_CONTROL0 |
23101 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
23102 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
23103 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
23104 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
23105 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
23106 | #define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
23107 | //OTG1_OTG_GLOBAL_CONTROL1 |
23108 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
23109 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
23110 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
23111 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
23112 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
23113 | #define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
23114 | //OTG1_OTG_GLOBAL_CONTROL2 |
23115 | #define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
23116 | #define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
23117 | #define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
23118 | #define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
23119 | #define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
23120 | #define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
23121 | #define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
23122 | #define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
23123 | //OTG1_OTG_GLOBAL_CONTROL3 |
23124 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
23125 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
23126 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
23127 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
23128 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
23129 | #define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
23130 | //OTG1_OTG_TRIG_MANUAL_CONTROL |
23131 | #define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
23132 | #define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
23133 | //OTG1_OTG_MANUAL_FLOW_CONTROL |
23134 | #define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
23135 | #define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
23136 | //OTG1_OTG_RANGE_TIMING_INT_STATUS |
23137 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
23138 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
23139 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
23140 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
23141 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
23142 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
23143 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
23144 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
23145 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
23146 | #define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
23147 | //OTG1_OTG_DRR_CONTROL |
23148 | #define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
23149 | #define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
23150 | #define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
23151 | #define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
23152 | //OTG1_OTG_REQUEST_CONTROL |
23153 | #define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
23154 | #define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
23155 | //OTG1_OTG_SPARE_REGISTER |
23156 | #define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
23157 | #define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
23158 | |
23159 | |
23160 | // addressBlock: dce_dc_optc_otg2_dispdec |
23161 | //OTG2_OTG_H_TOTAL |
23162 | #define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
23163 | #define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
23164 | //OTG2_OTG_H_BLANK_START_END |
23165 | #define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
23166 | #define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
23167 | #define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
23168 | #define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
23169 | //OTG2_OTG_H_SYNC_A |
23170 | #define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
23171 | #define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
23172 | #define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
23173 | #define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
23174 | //OTG2_OTG_H_SYNC_A_CNTL |
23175 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
23176 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
23177 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
23178 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
23179 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
23180 | #define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
23181 | //OTG2_OTG_H_TIMING_CNTL |
23182 | #define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
23183 | #define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
23184 | #define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
23185 | #define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
23186 | //OTG2_OTG_V_TOTAL |
23187 | #define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
23188 | #define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
23189 | //OTG2_OTG_V_TOTAL_MIN |
23190 | #define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
23191 | #define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
23192 | //OTG2_OTG_V_TOTAL_MAX |
23193 | #define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
23194 | #define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
23195 | //OTG2_OTG_V_TOTAL_MID |
23196 | #define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
23197 | #define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
23198 | //OTG2_OTG_V_TOTAL_CONTROL |
23199 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
23200 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
23201 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
23202 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
23203 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
23204 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
23205 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
23206 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
23207 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
23208 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
23209 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
23210 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
23211 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
23212 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
23213 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
23214 | #define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
23215 | //OTG2_OTG_V_TOTAL_INT_STATUS |
23216 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
23217 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
23218 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
23219 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
23220 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
23221 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
23222 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
23223 | #define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
23224 | //OTG2_OTG_VSYNC_NOM_INT_STATUS |
23225 | #define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
23226 | #define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
23227 | #define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
23228 | #define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
23229 | //OTG2_OTG_V_BLANK_START_END |
23230 | #define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
23231 | #define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
23232 | #define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
23233 | #define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
23234 | //OTG2_OTG_V_SYNC_A |
23235 | #define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
23236 | #define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
23237 | #define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
23238 | #define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
23239 | //OTG2_OTG_V_SYNC_A_CNTL |
23240 | #define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
23241 | #define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
23242 | //OTG2_OTG_TRIGA_CNTL |
23243 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
23244 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
23245 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
23246 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
23247 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
23248 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
23249 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
23250 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
23251 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
23252 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
23253 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
23254 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
23255 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
23256 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
23257 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
23258 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
23259 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
23260 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
23261 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
23262 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
23263 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
23264 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
23265 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
23266 | #define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
23267 | //OTG2_OTG_TRIGA_MANUAL_TRIG |
23268 | #define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
23269 | #define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
23270 | //OTG2_OTG_TRIGB_CNTL |
23271 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
23272 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
23273 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
23274 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
23275 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
23276 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
23277 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
23278 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
23279 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
23280 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
23281 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
23282 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
23283 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
23284 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
23285 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
23286 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
23287 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
23288 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
23289 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
23290 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
23291 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
23292 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
23293 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
23294 | #define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
23295 | //OTG2_OTG_TRIGB_MANUAL_TRIG |
23296 | #define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
23297 | #define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
23298 | //OTG2_OTG_FORCE_COUNT_NOW_CNTL |
23299 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
23300 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
23301 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
23302 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
23303 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
23304 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
23305 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
23306 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
23307 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
23308 | #define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
23309 | //OTG2_OTG_FLOW_CONTROL |
23310 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
23311 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
23312 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
23313 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
23314 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
23315 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
23316 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
23317 | #define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
23318 | //OTG2_OTG_STEREO_FORCE_NEXT_EYE |
23319 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
23320 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
23321 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
23322 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
23323 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
23324 | #define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
23325 | //OTG2_OTG_AVSYNC_COUNTER |
23326 | #define OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
23327 | #define OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
23328 | //OTG2_OTG_CONTROL |
23329 | #define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
23330 | #define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
23331 | #define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
23332 | #define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
23333 | #define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
23334 | #define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
23335 | #define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
23336 | #define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
23337 | #define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
23338 | #define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
23339 | #define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
23340 | #define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
23341 | //OTG2_OTG_BLANK_CONTROL |
23342 | #define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
23343 | #define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
23344 | #define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
23345 | #define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
23346 | #define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
23347 | #define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
23348 | //OTG2_OTG_PIPE_ABORT_CONTROL |
23349 | #define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
23350 | #define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
23351 | #define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
23352 | #define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
23353 | //OTG2_OTG_INTERLACE_CONTROL |
23354 | #define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
23355 | #define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
23356 | #define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
23357 | #define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
23358 | //OTG2_OTG_INTERLACE_STATUS |
23359 | #define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
23360 | #define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
23361 | #define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
23362 | #define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
23363 | //OTG2_OTG_FIELD_INDICATION_CONTROL |
23364 | #define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
23365 | #define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
23366 | #define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
23367 | #define OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
23368 | //OTG2_OTG_PIXEL_DATA_READBACK0 |
23369 | #define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
23370 | #define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
23371 | #define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
23372 | #define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
23373 | //OTG2_OTG_PIXEL_DATA_READBACK1 |
23374 | #define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
23375 | #define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
23376 | //OTG2_OTG_STATUS |
23377 | #define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
23378 | #define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
23379 | #define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
23380 | #define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
23381 | #define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
23382 | #define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
23383 | #define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
23384 | #define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
23385 | #define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
23386 | #define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
23387 | #define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
23388 | #define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
23389 | #define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
23390 | #define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
23391 | #define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
23392 | #define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
23393 | //OTG2_OTG_STATUS_POSITION |
23394 | #define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
23395 | #define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
23396 | #define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
23397 | #define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
23398 | //OTG2_OTG_NOM_VERT_POSITION |
23399 | #define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
23400 | #define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
23401 | //OTG2_OTG_STATUS_FRAME_COUNT |
23402 | #define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
23403 | #define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
23404 | //OTG2_OTG_STATUS_VF_COUNT |
23405 | #define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
23406 | #define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
23407 | //OTG2_OTG_STATUS_HV_COUNT |
23408 | #define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
23409 | #define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
23410 | //OTG2_OTG_COUNT_CONTROL |
23411 | #define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
23412 | #define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
23413 | #define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
23414 | #define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
23415 | //OTG2_OTG_COUNT_RESET |
23416 | #define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
23417 | #define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
23418 | //OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
23419 | #define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
23420 | #define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
23421 | //OTG2_OTG_VERT_SYNC_CONTROL |
23422 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
23423 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
23424 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
23425 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
23426 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
23427 | #define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
23428 | //OTG2_OTG_STEREO_STATUS |
23429 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
23430 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
23431 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
23432 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
23433 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
23434 | #define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
23435 | #define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
23436 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
23437 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
23438 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
23439 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
23440 | #define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
23441 | #define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
23442 | #define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
23443 | //OTG2_OTG_STEREO_CONTROL |
23444 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
23445 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
23446 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
23447 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
23448 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
23449 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
23450 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
23451 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
23452 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
23453 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
23454 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
23455 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
23456 | #define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
23457 | #define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
23458 | //OTG2_OTG_SNAPSHOT_STATUS |
23459 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
23460 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
23461 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
23462 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
23463 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
23464 | #define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
23465 | //OTG2_OTG_SNAPSHOT_CONTROL |
23466 | #define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
23467 | #define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
23468 | //OTG2_OTG_SNAPSHOT_POSITION |
23469 | #define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
23470 | #define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
23471 | #define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
23472 | #define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
23473 | //OTG2_OTG_SNAPSHOT_FRAME |
23474 | #define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
23475 | #define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
23476 | //OTG2_OTG_INTERRUPT_CONTROL |
23477 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
23478 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
23479 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
23480 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
23481 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
23482 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
23483 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
23484 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
23485 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
23486 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
23487 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
23488 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
23489 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
23490 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
23491 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
23492 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
23493 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
23494 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
23495 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
23496 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
23497 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
23498 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
23499 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
23500 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
23501 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
23502 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
23503 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
23504 | #define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
23505 | //OTG2_OTG_UPDATE_LOCK |
23506 | #define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
23507 | #define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
23508 | //OTG2_OTG_DOUBLE_BUFFER_CONTROL |
23509 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
23510 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
23511 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
23512 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
23513 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
23514 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
23515 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
23516 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
23517 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
23518 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
23519 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
23520 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
23521 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
23522 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
23523 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
23524 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
23525 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
23526 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
23527 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
23528 | #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
23529 | //OTG2_OTG_TEST_PATTERN_CONTROL |
23530 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
23531 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
23532 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
23533 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
23534 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
23535 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
23536 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
23537 | #define OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
23538 | //OTG2_OTG_TEST_PATTERN_PARAMETERS |
23539 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
23540 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
23541 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
23542 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
23543 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
23544 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
23545 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
23546 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
23547 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
23548 | #define OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
23549 | //OTG2_OTG_TEST_PATTERN_COLOR |
23550 | #define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
23551 | #define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
23552 | #define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
23553 | #define OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
23554 | //OTG2_OTG_MASTER_EN |
23555 | #define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
23556 | #define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
23557 | //OTG2_OTG_BLANK_DATA_COLOR |
23558 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
23559 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
23560 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
23561 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
23562 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
23563 | #define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
23564 | //OTG2_OTG_BLANK_DATA_COLOR_EXT |
23565 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
23566 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
23567 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
23568 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
23569 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
23570 | #define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
23571 | //OTG2_OTG_BLACK_COLOR |
23572 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
23573 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
23574 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
23575 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
23576 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
23577 | #define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
23578 | //OTG2_OTG_BLACK_COLOR_EXT |
23579 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
23580 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
23581 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
23582 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
23583 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
23584 | #define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
23585 | //OTG2_OTG_VERTICAL_INTERRUPT0_POSITION |
23586 | #define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
23587 | #define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
23588 | #define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
23589 | #define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
23590 | //OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL |
23591 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
23592 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
23593 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
23594 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
23595 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
23596 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
23597 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
23598 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
23599 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
23600 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
23601 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
23602 | #define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
23603 | //OTG2_OTG_VERTICAL_INTERRUPT1_POSITION |
23604 | #define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
23605 | #define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
23606 | //OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL |
23607 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
23608 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
23609 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
23610 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
23611 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
23612 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
23613 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
23614 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
23615 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
23616 | #define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
23617 | //OTG2_OTG_VERTICAL_INTERRUPT2_POSITION |
23618 | #define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
23619 | #define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
23620 | //OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL |
23621 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
23622 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
23623 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
23624 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
23625 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
23626 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
23627 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
23628 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
23629 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
23630 | #define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
23631 | //OTG2_OTG_CRC_CNTL |
23632 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
23633 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
23634 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
23635 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
23636 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
23637 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
23638 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
23639 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
23640 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
23641 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
23642 | #define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
23643 | #define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
23644 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
23645 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
23646 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
23647 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
23648 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
23649 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
23650 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
23651 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
23652 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
23653 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
23654 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
23655 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
23656 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
23657 | #define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
23658 | #define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
23659 | #define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
23660 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
23661 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
23662 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
23663 | #define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
23664 | //OTG2_OTG_CRC0_WINDOWA_X_CONTROL |
23665 | #define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
23666 | #define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
23667 | #define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
23668 | #define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
23669 | //OTG2_OTG_CRC0_WINDOWA_Y_CONTROL |
23670 | #define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
23671 | #define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
23672 | #define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
23673 | #define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
23674 | //OTG2_OTG_CRC0_WINDOWB_X_CONTROL |
23675 | #define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
23676 | #define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
23677 | #define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
23678 | #define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
23679 | //OTG2_OTG_CRC0_WINDOWB_Y_CONTROL |
23680 | #define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
23681 | #define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
23682 | #define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
23683 | #define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
23684 | //OTG2_OTG_CRC0_DATA_RG |
23685 | #define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
23686 | #define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
23687 | #define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
23688 | #define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
23689 | //OTG2_OTG_CRC0_DATA_B |
23690 | #define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
23691 | #define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
23692 | #define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
23693 | #define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
23694 | //OTG2_OTG_CRC1_WINDOWA_X_CONTROL |
23695 | #define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
23696 | #define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
23697 | #define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
23698 | #define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
23699 | //OTG2_OTG_CRC1_WINDOWA_Y_CONTROL |
23700 | #define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
23701 | #define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
23702 | #define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
23703 | #define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
23704 | //OTG2_OTG_CRC1_WINDOWB_X_CONTROL |
23705 | #define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
23706 | #define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
23707 | #define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
23708 | #define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
23709 | //OTG2_OTG_CRC1_WINDOWB_Y_CONTROL |
23710 | #define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
23711 | #define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
23712 | #define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
23713 | #define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
23714 | //OTG2_OTG_CRC1_DATA_RG |
23715 | #define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
23716 | #define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
23717 | #define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
23718 | #define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
23719 | //OTG2_OTG_CRC1_DATA_B |
23720 | #define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
23721 | #define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
23722 | #define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
23723 | #define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
23724 | //OTG2_OTG_CRC2_DATA_RG |
23725 | #define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
23726 | #define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
23727 | #define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
23728 | #define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
23729 | //OTG2_OTG_CRC2_DATA_B |
23730 | #define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
23731 | #define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
23732 | #define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
23733 | #define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
23734 | //OTG2_OTG_CRC3_DATA_RG |
23735 | #define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
23736 | #define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
23737 | #define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
23738 | #define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
23739 | //OTG2_OTG_CRC3_DATA_B |
23740 | #define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
23741 | #define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
23742 | #define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
23743 | #define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
23744 | //OTG2_OTG_CRC_SIG_RED_GREEN_MASK |
23745 | #define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
23746 | #define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
23747 | #define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
23748 | #define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
23749 | //OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK |
23750 | #define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
23751 | #define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
23752 | #define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
23753 | #define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
23754 | //OTG2_OTG_STATIC_SCREEN_CONTROL |
23755 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
23756 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
23757 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
23758 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
23759 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
23760 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
23761 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
23762 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
23763 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
23764 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
23765 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
23766 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
23767 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
23768 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
23769 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
23770 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
23771 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
23772 | #define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
23773 | //OTG2_OTG_3D_STRUCTURE_CONTROL |
23774 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
23775 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
23776 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
23777 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
23778 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
23779 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
23780 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
23781 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
23782 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
23783 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
23784 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
23785 | #define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
23786 | //OTG2_OTG_GSL_VSYNC_GAP |
23787 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
23788 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
23789 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
23790 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
23791 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
23792 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
23793 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
23794 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
23795 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
23796 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
23797 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
23798 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
23799 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
23800 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
23801 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
23802 | #define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
23803 | //OTG2_OTG_MASTER_UPDATE_MODE |
23804 | #define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
23805 | #define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
23806 | //OTG2_OTG_CLOCK_CONTROL |
23807 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
23808 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
23809 | #define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
23810 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
23811 | #define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
23812 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
23813 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
23814 | #define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
23815 | #define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
23816 | #define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
23817 | //OTG2_OTG_VSTARTUP_PARAM |
23818 | #define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
23819 | #define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
23820 | //OTG2_OTG_VUPDATE_PARAM |
23821 | #define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
23822 | #define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
23823 | #define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
23824 | #define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
23825 | //OTG2_OTG_VREADY_PARAM |
23826 | #define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
23827 | #define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
23828 | //OTG2_OTG_GLOBAL_SYNC_STATUS |
23829 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
23830 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
23831 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
23832 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
23833 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
23834 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
23835 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
23836 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
23837 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
23838 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
23839 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
23840 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
23841 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
23842 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
23843 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
23844 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
23845 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
23846 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
23847 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
23848 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
23849 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
23850 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
23851 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
23852 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
23853 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
23854 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
23855 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
23856 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
23857 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
23858 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
23859 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
23860 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
23861 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
23862 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
23863 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
23864 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
23865 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
23866 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
23867 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
23868 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
23869 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
23870 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
23871 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
23872 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
23873 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
23874 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
23875 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
23876 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
23877 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
23878 | #define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
23879 | //OTG2_OTG_MASTER_UPDATE_LOCK |
23880 | #define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
23881 | #define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
23882 | #define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
23883 | #define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
23884 | //OTG2_OTG_GSL_CONTROL |
23885 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
23886 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
23887 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
23888 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
23889 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
23890 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
23891 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
23892 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
23893 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
23894 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
23895 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
23896 | #define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
23897 | //OTG2_OTG_GSL_WINDOW_X |
23898 | #define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
23899 | #define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
23900 | #define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
23901 | #define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
23902 | //OTG2_OTG_GSL_WINDOW_Y |
23903 | #define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
23904 | #define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
23905 | #define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
23906 | #define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
23907 | //OTG2_OTG_VUPDATE_KEEPOUT |
23908 | #define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
23909 | #define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
23910 | #define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
23911 | #define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
23912 | #define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
23913 | #define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
23914 | //OTG2_OTG_GLOBAL_CONTROL0 |
23915 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
23916 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
23917 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
23918 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
23919 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
23920 | #define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
23921 | //OTG2_OTG_GLOBAL_CONTROL1 |
23922 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
23923 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
23924 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
23925 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
23926 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
23927 | #define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
23928 | //OTG2_OTG_GLOBAL_CONTROL2 |
23929 | #define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
23930 | #define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
23931 | #define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
23932 | #define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
23933 | #define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
23934 | #define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
23935 | #define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
23936 | #define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
23937 | //OTG2_OTG_GLOBAL_CONTROL3 |
23938 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
23939 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
23940 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
23941 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
23942 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
23943 | #define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
23944 | //OTG2_OTG_TRIG_MANUAL_CONTROL |
23945 | #define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
23946 | #define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
23947 | //OTG2_OTG_MANUAL_FLOW_CONTROL |
23948 | #define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
23949 | #define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
23950 | //OTG2_OTG_RANGE_TIMING_INT_STATUS |
23951 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
23952 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
23953 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
23954 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
23955 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
23956 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
23957 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
23958 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
23959 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
23960 | #define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
23961 | //OTG2_OTG_DRR_CONTROL |
23962 | #define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
23963 | #define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
23964 | #define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
23965 | #define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
23966 | //OTG2_OTG_REQUEST_CONTROL |
23967 | #define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
23968 | #define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
23969 | //OTG2_OTG_SPARE_REGISTER |
23970 | #define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
23971 | #define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
23972 | |
23973 | |
23974 | // addressBlock: dce_dc_optc_otg3_dispdec |
23975 | //OTG3_OTG_H_TOTAL |
23976 | #define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
23977 | #define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
23978 | //OTG3_OTG_H_BLANK_START_END |
23979 | #define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
23980 | #define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
23981 | #define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
23982 | #define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
23983 | //OTG3_OTG_H_SYNC_A |
23984 | #define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
23985 | #define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
23986 | #define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
23987 | #define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
23988 | //OTG3_OTG_H_SYNC_A_CNTL |
23989 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
23990 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
23991 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
23992 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
23993 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
23994 | #define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
23995 | //OTG3_OTG_H_TIMING_CNTL |
23996 | #define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
23997 | #define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
23998 | #define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
23999 | #define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
24000 | //OTG3_OTG_V_TOTAL |
24001 | #define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
24002 | #define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
24003 | //OTG3_OTG_V_TOTAL_MIN |
24004 | #define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
24005 | #define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
24006 | //OTG3_OTG_V_TOTAL_MAX |
24007 | #define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
24008 | #define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
24009 | //OTG3_OTG_V_TOTAL_MID |
24010 | #define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
24011 | #define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
24012 | //OTG3_OTG_V_TOTAL_CONTROL |
24013 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
24014 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
24015 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
24016 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
24017 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
24018 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
24019 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
24020 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
24021 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
24022 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
24023 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
24024 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
24025 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
24026 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
24027 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
24028 | #define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
24029 | //OTG3_OTG_V_TOTAL_INT_STATUS |
24030 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
24031 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
24032 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
24033 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
24034 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
24035 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
24036 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
24037 | #define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
24038 | //OTG3_OTG_VSYNC_NOM_INT_STATUS |
24039 | #define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
24040 | #define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
24041 | #define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
24042 | #define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
24043 | //OTG3_OTG_V_BLANK_START_END |
24044 | #define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
24045 | #define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
24046 | #define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
24047 | #define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
24048 | //OTG3_OTG_V_SYNC_A |
24049 | #define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
24050 | #define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
24051 | #define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
24052 | #define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
24053 | //OTG3_OTG_V_SYNC_A_CNTL |
24054 | #define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
24055 | #define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
24056 | //OTG3_OTG_TRIGA_CNTL |
24057 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
24058 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
24059 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
24060 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
24061 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
24062 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
24063 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
24064 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
24065 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
24066 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
24067 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
24068 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
24069 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
24070 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
24071 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
24072 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
24073 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
24074 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
24075 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
24076 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
24077 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
24078 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
24079 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
24080 | #define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
24081 | //OTG3_OTG_TRIGA_MANUAL_TRIG |
24082 | #define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
24083 | #define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
24084 | //OTG3_OTG_TRIGB_CNTL |
24085 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
24086 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
24087 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
24088 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
24089 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
24090 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
24091 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
24092 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
24093 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
24094 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
24095 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
24096 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
24097 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
24098 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
24099 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
24100 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
24101 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
24102 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
24103 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
24104 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
24105 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
24106 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
24107 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
24108 | #define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
24109 | //OTG3_OTG_TRIGB_MANUAL_TRIG |
24110 | #define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
24111 | #define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
24112 | //OTG3_OTG_FORCE_COUNT_NOW_CNTL |
24113 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
24114 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
24115 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
24116 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
24117 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
24118 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
24119 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
24120 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
24121 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
24122 | #define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
24123 | //OTG3_OTG_FLOW_CONTROL |
24124 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
24125 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
24126 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
24127 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
24128 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
24129 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
24130 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
24131 | #define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
24132 | //OTG3_OTG_STEREO_FORCE_NEXT_EYE |
24133 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
24134 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
24135 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
24136 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
24137 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
24138 | #define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
24139 | //OTG3_OTG_AVSYNC_COUNTER |
24140 | #define OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
24141 | #define OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
24142 | //OTG3_OTG_CONTROL |
24143 | #define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
24144 | #define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
24145 | #define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
24146 | #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
24147 | #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
24148 | #define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
24149 | #define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
24150 | #define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
24151 | #define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
24152 | #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
24153 | #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
24154 | #define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
24155 | //OTG3_OTG_BLANK_CONTROL |
24156 | #define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
24157 | #define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
24158 | #define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
24159 | #define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
24160 | #define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
24161 | #define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
24162 | //OTG3_OTG_PIPE_ABORT_CONTROL |
24163 | #define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
24164 | #define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
24165 | #define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
24166 | #define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
24167 | //OTG3_OTG_INTERLACE_CONTROL |
24168 | #define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
24169 | #define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
24170 | #define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
24171 | #define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
24172 | //OTG3_OTG_INTERLACE_STATUS |
24173 | #define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
24174 | #define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
24175 | #define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
24176 | #define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
24177 | //OTG3_OTG_FIELD_INDICATION_CONTROL |
24178 | #define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
24179 | #define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
24180 | #define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
24181 | #define OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
24182 | //OTG3_OTG_PIXEL_DATA_READBACK0 |
24183 | #define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
24184 | #define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
24185 | #define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
24186 | #define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
24187 | //OTG3_OTG_PIXEL_DATA_READBACK1 |
24188 | #define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
24189 | #define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
24190 | //OTG3_OTG_STATUS |
24191 | #define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
24192 | #define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
24193 | #define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
24194 | #define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
24195 | #define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
24196 | #define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
24197 | #define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
24198 | #define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
24199 | #define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
24200 | #define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
24201 | #define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
24202 | #define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
24203 | #define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
24204 | #define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
24205 | #define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
24206 | #define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
24207 | //OTG3_OTG_STATUS_POSITION |
24208 | #define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
24209 | #define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
24210 | #define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
24211 | #define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
24212 | //OTG3_OTG_NOM_VERT_POSITION |
24213 | #define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
24214 | #define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
24215 | //OTG3_OTG_STATUS_FRAME_COUNT |
24216 | #define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
24217 | #define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
24218 | //OTG3_OTG_STATUS_VF_COUNT |
24219 | #define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
24220 | #define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
24221 | //OTG3_OTG_STATUS_HV_COUNT |
24222 | #define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
24223 | #define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
24224 | //OTG3_OTG_COUNT_CONTROL |
24225 | #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
24226 | #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
24227 | #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
24228 | #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
24229 | //OTG3_OTG_COUNT_RESET |
24230 | #define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
24231 | #define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
24232 | //OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
24233 | #define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
24234 | #define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
24235 | //OTG3_OTG_VERT_SYNC_CONTROL |
24236 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
24237 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
24238 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
24239 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
24240 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
24241 | #define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
24242 | //OTG3_OTG_STEREO_STATUS |
24243 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
24244 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
24245 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
24246 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
24247 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
24248 | #define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
24249 | #define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
24250 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
24251 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
24252 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
24253 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
24254 | #define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
24255 | #define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
24256 | #define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
24257 | //OTG3_OTG_STEREO_CONTROL |
24258 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
24259 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
24260 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
24261 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
24262 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
24263 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
24264 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
24265 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
24266 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
24267 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
24268 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
24269 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
24270 | #define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
24271 | #define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
24272 | //OTG3_OTG_SNAPSHOT_STATUS |
24273 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
24274 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
24275 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
24276 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
24277 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
24278 | #define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
24279 | //OTG3_OTG_SNAPSHOT_CONTROL |
24280 | #define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
24281 | #define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
24282 | //OTG3_OTG_SNAPSHOT_POSITION |
24283 | #define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
24284 | #define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
24285 | #define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
24286 | #define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
24287 | //OTG3_OTG_SNAPSHOT_FRAME |
24288 | #define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
24289 | #define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
24290 | //OTG3_OTG_INTERRUPT_CONTROL |
24291 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
24292 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
24293 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
24294 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
24295 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
24296 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
24297 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
24298 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
24299 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
24300 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
24301 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
24302 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
24303 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
24304 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
24305 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
24306 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
24307 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
24308 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
24309 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
24310 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
24311 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
24312 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
24313 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
24314 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
24315 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
24316 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
24317 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
24318 | #define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
24319 | //OTG3_OTG_UPDATE_LOCK |
24320 | #define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
24321 | #define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
24322 | //OTG3_OTG_DOUBLE_BUFFER_CONTROL |
24323 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
24324 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
24325 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
24326 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
24327 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
24328 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
24329 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
24330 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
24331 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
24332 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
24333 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
24334 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
24335 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
24336 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
24337 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
24338 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
24339 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
24340 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
24341 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
24342 | #define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
24343 | //OTG3_OTG_TEST_PATTERN_CONTROL |
24344 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
24345 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
24346 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
24347 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
24348 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
24349 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
24350 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
24351 | #define OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
24352 | //OTG3_OTG_TEST_PATTERN_PARAMETERS |
24353 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
24354 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
24355 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
24356 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
24357 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
24358 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
24359 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
24360 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
24361 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
24362 | #define OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
24363 | //OTG3_OTG_TEST_PATTERN_COLOR |
24364 | #define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
24365 | #define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
24366 | #define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
24367 | #define OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
24368 | //OTG3_OTG_MASTER_EN |
24369 | #define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
24370 | #define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
24371 | //OTG3_OTG_BLANK_DATA_COLOR |
24372 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
24373 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
24374 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
24375 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
24376 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
24377 | #define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
24378 | //OTG3_OTG_BLANK_DATA_COLOR_EXT |
24379 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
24380 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
24381 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
24382 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
24383 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
24384 | #define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
24385 | //OTG3_OTG_BLACK_COLOR |
24386 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
24387 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
24388 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
24389 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
24390 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
24391 | #define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
24392 | //OTG3_OTG_BLACK_COLOR_EXT |
24393 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
24394 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
24395 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
24396 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
24397 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
24398 | #define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
24399 | //OTG3_OTG_VERTICAL_INTERRUPT0_POSITION |
24400 | #define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
24401 | #define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
24402 | #define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
24403 | #define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
24404 | //OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL |
24405 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
24406 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
24407 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
24408 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
24409 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
24410 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
24411 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
24412 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
24413 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
24414 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
24415 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
24416 | #define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
24417 | //OTG3_OTG_VERTICAL_INTERRUPT1_POSITION |
24418 | #define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
24419 | #define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
24420 | //OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL |
24421 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
24422 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
24423 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
24424 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
24425 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
24426 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
24427 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
24428 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
24429 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
24430 | #define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
24431 | //OTG3_OTG_VERTICAL_INTERRUPT2_POSITION |
24432 | #define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
24433 | #define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
24434 | //OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL |
24435 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
24436 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
24437 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
24438 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
24439 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
24440 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
24441 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
24442 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
24443 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
24444 | #define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
24445 | //OTG3_OTG_CRC_CNTL |
24446 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
24447 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
24448 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
24449 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
24450 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
24451 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
24452 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
24453 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
24454 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
24455 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
24456 | #define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
24457 | #define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
24458 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
24459 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
24460 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
24461 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
24462 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
24463 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
24464 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
24465 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
24466 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
24467 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
24468 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
24469 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
24470 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
24471 | #define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
24472 | #define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
24473 | #define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
24474 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
24475 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
24476 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
24477 | #define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
24478 | //OTG3_OTG_CRC0_WINDOWA_X_CONTROL |
24479 | #define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
24480 | #define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
24481 | #define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
24482 | #define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
24483 | //OTG3_OTG_CRC0_WINDOWA_Y_CONTROL |
24484 | #define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
24485 | #define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
24486 | #define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
24487 | #define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
24488 | //OTG3_OTG_CRC0_WINDOWB_X_CONTROL |
24489 | #define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
24490 | #define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
24491 | #define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
24492 | #define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
24493 | //OTG3_OTG_CRC0_WINDOWB_Y_CONTROL |
24494 | #define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
24495 | #define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
24496 | #define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
24497 | #define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
24498 | //OTG3_OTG_CRC0_DATA_RG |
24499 | #define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
24500 | #define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
24501 | #define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
24502 | #define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
24503 | //OTG3_OTG_CRC0_DATA_B |
24504 | #define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
24505 | #define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
24506 | #define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
24507 | #define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
24508 | //OTG3_OTG_CRC1_WINDOWA_X_CONTROL |
24509 | #define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
24510 | #define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
24511 | #define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
24512 | #define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
24513 | //OTG3_OTG_CRC1_WINDOWA_Y_CONTROL |
24514 | #define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
24515 | #define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
24516 | #define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
24517 | #define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
24518 | //OTG3_OTG_CRC1_WINDOWB_X_CONTROL |
24519 | #define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
24520 | #define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
24521 | #define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
24522 | #define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
24523 | //OTG3_OTG_CRC1_WINDOWB_Y_CONTROL |
24524 | #define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
24525 | #define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
24526 | #define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
24527 | #define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
24528 | //OTG3_OTG_CRC1_DATA_RG |
24529 | #define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
24530 | #define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
24531 | #define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
24532 | #define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
24533 | //OTG3_OTG_CRC1_DATA_B |
24534 | #define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
24535 | #define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
24536 | #define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
24537 | #define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
24538 | //OTG3_OTG_CRC2_DATA_RG |
24539 | #define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
24540 | #define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
24541 | #define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
24542 | #define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
24543 | //OTG3_OTG_CRC2_DATA_B |
24544 | #define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
24545 | #define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
24546 | #define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
24547 | #define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
24548 | //OTG3_OTG_CRC3_DATA_RG |
24549 | #define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
24550 | #define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
24551 | #define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
24552 | #define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
24553 | //OTG3_OTG_CRC3_DATA_B |
24554 | #define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
24555 | #define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
24556 | #define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
24557 | #define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
24558 | //OTG3_OTG_CRC_SIG_RED_GREEN_MASK |
24559 | #define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
24560 | #define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
24561 | #define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
24562 | #define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
24563 | //OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK |
24564 | #define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
24565 | #define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
24566 | #define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
24567 | #define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
24568 | //OTG3_OTG_STATIC_SCREEN_CONTROL |
24569 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
24570 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
24571 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
24572 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
24573 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
24574 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
24575 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
24576 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
24577 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
24578 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
24579 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
24580 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
24581 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
24582 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
24583 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
24584 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
24585 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
24586 | #define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
24587 | //OTG3_OTG_3D_STRUCTURE_CONTROL |
24588 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
24589 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
24590 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
24591 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
24592 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
24593 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
24594 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
24595 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
24596 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
24597 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
24598 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
24599 | #define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
24600 | //OTG3_OTG_GSL_VSYNC_GAP |
24601 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
24602 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
24603 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
24604 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
24605 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
24606 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
24607 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
24608 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
24609 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
24610 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
24611 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
24612 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
24613 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
24614 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
24615 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
24616 | #define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
24617 | //OTG3_OTG_MASTER_UPDATE_MODE |
24618 | #define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
24619 | #define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
24620 | //OTG3_OTG_CLOCK_CONTROL |
24621 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
24622 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
24623 | #define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
24624 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
24625 | #define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
24626 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
24627 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
24628 | #define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
24629 | #define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
24630 | #define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
24631 | //OTG3_OTG_VSTARTUP_PARAM |
24632 | #define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
24633 | #define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
24634 | //OTG3_OTG_VUPDATE_PARAM |
24635 | #define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
24636 | #define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
24637 | #define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
24638 | #define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
24639 | //OTG3_OTG_VREADY_PARAM |
24640 | #define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
24641 | #define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
24642 | //OTG3_OTG_GLOBAL_SYNC_STATUS |
24643 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
24644 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
24645 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
24646 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
24647 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
24648 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
24649 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
24650 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
24651 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
24652 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
24653 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
24654 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
24655 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
24656 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
24657 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
24658 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
24659 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
24660 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
24661 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
24662 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
24663 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
24664 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
24665 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
24666 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
24667 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
24668 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
24669 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
24670 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
24671 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
24672 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
24673 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
24674 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
24675 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
24676 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
24677 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
24678 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
24679 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
24680 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
24681 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
24682 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
24683 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
24684 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
24685 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
24686 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
24687 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
24688 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
24689 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
24690 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
24691 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
24692 | #define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
24693 | //OTG3_OTG_MASTER_UPDATE_LOCK |
24694 | #define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
24695 | #define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
24696 | #define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
24697 | #define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
24698 | //OTG3_OTG_GSL_CONTROL |
24699 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
24700 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
24701 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
24702 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
24703 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
24704 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
24705 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
24706 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
24707 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
24708 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
24709 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
24710 | #define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
24711 | //OTG3_OTG_GSL_WINDOW_X |
24712 | #define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
24713 | #define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
24714 | #define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
24715 | #define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
24716 | //OTG3_OTG_GSL_WINDOW_Y |
24717 | #define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
24718 | #define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
24719 | #define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
24720 | #define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
24721 | //OTG3_OTG_VUPDATE_KEEPOUT |
24722 | #define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
24723 | #define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
24724 | #define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
24725 | #define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
24726 | #define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
24727 | #define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
24728 | //OTG3_OTG_GLOBAL_CONTROL0 |
24729 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
24730 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
24731 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
24732 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
24733 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
24734 | #define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
24735 | //OTG3_OTG_GLOBAL_CONTROL1 |
24736 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
24737 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
24738 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
24739 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
24740 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
24741 | #define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
24742 | //OTG3_OTG_GLOBAL_CONTROL2 |
24743 | #define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
24744 | #define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
24745 | #define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
24746 | #define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
24747 | #define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
24748 | #define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
24749 | #define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
24750 | #define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
24751 | //OTG3_OTG_GLOBAL_CONTROL3 |
24752 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
24753 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
24754 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
24755 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
24756 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
24757 | #define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
24758 | //OTG3_OTG_TRIG_MANUAL_CONTROL |
24759 | #define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
24760 | #define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
24761 | //OTG3_OTG_MANUAL_FLOW_CONTROL |
24762 | #define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
24763 | #define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
24764 | //OTG3_OTG_RANGE_TIMING_INT_STATUS |
24765 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
24766 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
24767 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
24768 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
24769 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
24770 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
24771 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
24772 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
24773 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
24774 | #define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
24775 | //OTG3_OTG_DRR_CONTROL |
24776 | #define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
24777 | #define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
24778 | #define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
24779 | #define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
24780 | //OTG3_OTG_REQUEST_CONTROL |
24781 | #define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
24782 | #define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
24783 | //OTG3_OTG_SPARE_REGISTER |
24784 | #define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
24785 | #define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
24786 | |
24787 | |
24788 | // addressBlock: dce_dc_optc_otg4_dispdec |
24789 | //OTG4_OTG_H_TOTAL |
24790 | #define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
24791 | #define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
24792 | //OTG4_OTG_H_BLANK_START_END |
24793 | #define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
24794 | #define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
24795 | #define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
24796 | #define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
24797 | //OTG4_OTG_H_SYNC_A |
24798 | #define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
24799 | #define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
24800 | #define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
24801 | #define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
24802 | //OTG4_OTG_H_SYNC_A_CNTL |
24803 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
24804 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
24805 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
24806 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
24807 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
24808 | #define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
24809 | //OTG4_OTG_H_TIMING_CNTL |
24810 | #define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
24811 | #define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
24812 | #define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
24813 | #define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
24814 | //OTG4_OTG_V_TOTAL |
24815 | #define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
24816 | #define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
24817 | //OTG4_OTG_V_TOTAL_MIN |
24818 | #define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
24819 | #define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
24820 | //OTG4_OTG_V_TOTAL_MAX |
24821 | #define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
24822 | #define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
24823 | //OTG4_OTG_V_TOTAL_MID |
24824 | #define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
24825 | #define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
24826 | //OTG4_OTG_V_TOTAL_CONTROL |
24827 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
24828 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
24829 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
24830 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
24831 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
24832 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
24833 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
24834 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
24835 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
24836 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
24837 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
24838 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
24839 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
24840 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
24841 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
24842 | #define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
24843 | //OTG4_OTG_V_TOTAL_INT_STATUS |
24844 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
24845 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
24846 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
24847 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
24848 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
24849 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
24850 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
24851 | #define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
24852 | //OTG4_OTG_VSYNC_NOM_INT_STATUS |
24853 | #define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
24854 | #define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
24855 | #define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
24856 | #define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
24857 | //OTG4_OTG_V_BLANK_START_END |
24858 | #define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
24859 | #define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
24860 | #define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
24861 | #define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
24862 | //OTG4_OTG_V_SYNC_A |
24863 | #define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
24864 | #define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
24865 | #define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
24866 | #define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
24867 | //OTG4_OTG_V_SYNC_A_CNTL |
24868 | #define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
24869 | #define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
24870 | //OTG4_OTG_TRIGA_CNTL |
24871 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
24872 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
24873 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
24874 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
24875 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
24876 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
24877 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
24878 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
24879 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
24880 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
24881 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
24882 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
24883 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
24884 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
24885 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
24886 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
24887 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
24888 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
24889 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
24890 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
24891 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
24892 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
24893 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
24894 | #define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
24895 | //OTG4_OTG_TRIGA_MANUAL_TRIG |
24896 | #define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
24897 | #define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
24898 | //OTG4_OTG_TRIGB_CNTL |
24899 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
24900 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
24901 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
24902 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
24903 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
24904 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
24905 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
24906 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
24907 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
24908 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
24909 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
24910 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
24911 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
24912 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
24913 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
24914 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
24915 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
24916 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
24917 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
24918 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
24919 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
24920 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
24921 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
24922 | #define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
24923 | //OTG4_OTG_TRIGB_MANUAL_TRIG |
24924 | #define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
24925 | #define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
24926 | //OTG4_OTG_FORCE_COUNT_NOW_CNTL |
24927 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
24928 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
24929 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
24930 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
24931 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
24932 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
24933 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
24934 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
24935 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
24936 | #define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
24937 | //OTG4_OTG_FLOW_CONTROL |
24938 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
24939 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
24940 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
24941 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
24942 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
24943 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
24944 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
24945 | #define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
24946 | //OTG4_OTG_STEREO_FORCE_NEXT_EYE |
24947 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
24948 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
24949 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
24950 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
24951 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
24952 | #define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
24953 | //OTG4_OTG_AVSYNC_COUNTER |
24954 | #define OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
24955 | #define OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
24956 | //OTG4_OTG_CONTROL |
24957 | #define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
24958 | #define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
24959 | #define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
24960 | #define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
24961 | #define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
24962 | #define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
24963 | #define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
24964 | #define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
24965 | #define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
24966 | #define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
24967 | #define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
24968 | #define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
24969 | //OTG4_OTG_BLANK_CONTROL |
24970 | #define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
24971 | #define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
24972 | #define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
24973 | #define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
24974 | #define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
24975 | #define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
24976 | //OTG4_OTG_PIPE_ABORT_CONTROL |
24977 | #define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
24978 | #define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
24979 | #define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
24980 | #define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
24981 | //OTG4_OTG_INTERLACE_CONTROL |
24982 | #define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
24983 | #define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
24984 | #define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
24985 | #define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
24986 | //OTG4_OTG_INTERLACE_STATUS |
24987 | #define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
24988 | #define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
24989 | #define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
24990 | #define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
24991 | //OTG4_OTG_FIELD_INDICATION_CONTROL |
24992 | #define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
24993 | #define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
24994 | #define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
24995 | #define OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
24996 | //OTG4_OTG_PIXEL_DATA_READBACK0 |
24997 | #define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
24998 | #define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
24999 | #define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
25000 | #define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
25001 | //OTG4_OTG_PIXEL_DATA_READBACK1 |
25002 | #define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
25003 | #define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
25004 | //OTG4_OTG_STATUS |
25005 | #define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
25006 | #define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
25007 | #define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
25008 | #define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
25009 | #define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
25010 | #define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
25011 | #define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
25012 | #define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
25013 | #define OTG4_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
25014 | #define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
25015 | #define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
25016 | #define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
25017 | #define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
25018 | #define OTG4_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
25019 | #define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
25020 | #define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
25021 | //OTG4_OTG_STATUS_POSITION |
25022 | #define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
25023 | #define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
25024 | #define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
25025 | #define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
25026 | //OTG4_OTG_NOM_VERT_POSITION |
25027 | #define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
25028 | #define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
25029 | //OTG4_OTG_STATUS_FRAME_COUNT |
25030 | #define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
25031 | #define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
25032 | //OTG4_OTG_STATUS_VF_COUNT |
25033 | #define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
25034 | #define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
25035 | //OTG4_OTG_STATUS_HV_COUNT |
25036 | #define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
25037 | #define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
25038 | //OTG4_OTG_COUNT_CONTROL |
25039 | #define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
25040 | #define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
25041 | #define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
25042 | #define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
25043 | //OTG4_OTG_COUNT_RESET |
25044 | #define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
25045 | #define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
25046 | //OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
25047 | #define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
25048 | #define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
25049 | //OTG4_OTG_VERT_SYNC_CONTROL |
25050 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
25051 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
25052 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
25053 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
25054 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
25055 | #define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
25056 | //OTG4_OTG_STEREO_STATUS |
25057 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
25058 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
25059 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
25060 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
25061 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
25062 | #define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
25063 | #define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
25064 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
25065 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
25066 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
25067 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
25068 | #define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
25069 | #define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
25070 | #define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
25071 | //OTG4_OTG_STEREO_CONTROL |
25072 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
25073 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
25074 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
25075 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
25076 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
25077 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
25078 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
25079 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
25080 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
25081 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
25082 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
25083 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
25084 | #define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
25085 | #define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
25086 | //OTG4_OTG_SNAPSHOT_STATUS |
25087 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
25088 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
25089 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
25090 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
25091 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
25092 | #define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
25093 | //OTG4_OTG_SNAPSHOT_CONTROL |
25094 | #define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
25095 | #define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
25096 | //OTG4_OTG_SNAPSHOT_POSITION |
25097 | #define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
25098 | #define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
25099 | #define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
25100 | #define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
25101 | //OTG4_OTG_SNAPSHOT_FRAME |
25102 | #define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
25103 | #define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
25104 | //OTG4_OTG_INTERRUPT_CONTROL |
25105 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
25106 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
25107 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
25108 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
25109 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
25110 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
25111 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
25112 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
25113 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
25114 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
25115 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
25116 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
25117 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
25118 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
25119 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
25120 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
25121 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
25122 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
25123 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
25124 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
25125 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
25126 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
25127 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
25128 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
25129 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
25130 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
25131 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
25132 | #define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
25133 | //OTG4_OTG_UPDATE_LOCK |
25134 | #define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
25135 | #define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
25136 | //OTG4_OTG_DOUBLE_BUFFER_CONTROL |
25137 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
25138 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
25139 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
25140 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
25141 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
25142 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
25143 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
25144 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
25145 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
25146 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
25147 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
25148 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
25149 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
25150 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
25151 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
25152 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
25153 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
25154 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
25155 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
25156 | #define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
25157 | //OTG4_OTG_TEST_PATTERN_CONTROL |
25158 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
25159 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
25160 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
25161 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
25162 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
25163 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
25164 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
25165 | #define OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
25166 | //OTG4_OTG_TEST_PATTERN_PARAMETERS |
25167 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
25168 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
25169 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
25170 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
25171 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
25172 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
25173 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
25174 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
25175 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
25176 | #define OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
25177 | //OTG4_OTG_TEST_PATTERN_COLOR |
25178 | #define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
25179 | #define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
25180 | #define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
25181 | #define OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
25182 | //OTG4_OTG_MASTER_EN |
25183 | #define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
25184 | #define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
25185 | //OTG4_OTG_BLANK_DATA_COLOR |
25186 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
25187 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
25188 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
25189 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
25190 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
25191 | #define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
25192 | //OTG4_OTG_BLANK_DATA_COLOR_EXT |
25193 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
25194 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
25195 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
25196 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
25197 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
25198 | #define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
25199 | //OTG4_OTG_BLACK_COLOR |
25200 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
25201 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
25202 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
25203 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
25204 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
25205 | #define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
25206 | //OTG4_OTG_BLACK_COLOR_EXT |
25207 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
25208 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
25209 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
25210 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
25211 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
25212 | #define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
25213 | //OTG4_OTG_VERTICAL_INTERRUPT0_POSITION |
25214 | #define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
25215 | #define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
25216 | #define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
25217 | #define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
25218 | //OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL |
25219 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
25220 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
25221 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
25222 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
25223 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
25224 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
25225 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
25226 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
25227 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
25228 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
25229 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
25230 | #define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
25231 | //OTG4_OTG_VERTICAL_INTERRUPT1_POSITION |
25232 | #define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
25233 | #define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
25234 | //OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL |
25235 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
25236 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
25237 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
25238 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
25239 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
25240 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
25241 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
25242 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
25243 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
25244 | #define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
25245 | //OTG4_OTG_VERTICAL_INTERRUPT2_POSITION |
25246 | #define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
25247 | #define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
25248 | //OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL |
25249 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
25250 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
25251 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
25252 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
25253 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
25254 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
25255 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
25256 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
25257 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
25258 | #define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
25259 | //OTG4_OTG_CRC_CNTL |
25260 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
25261 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
25262 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
25263 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
25264 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
25265 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
25266 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
25267 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
25268 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
25269 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
25270 | #define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
25271 | #define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
25272 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
25273 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
25274 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
25275 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
25276 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
25277 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
25278 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
25279 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
25280 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
25281 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
25282 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
25283 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
25284 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
25285 | #define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
25286 | #define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
25287 | #define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
25288 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
25289 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
25290 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
25291 | #define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
25292 | //OTG4_OTG_CRC0_WINDOWA_X_CONTROL |
25293 | #define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
25294 | #define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
25295 | #define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
25296 | #define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
25297 | //OTG4_OTG_CRC0_WINDOWA_Y_CONTROL |
25298 | #define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
25299 | #define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
25300 | #define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
25301 | #define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
25302 | //OTG4_OTG_CRC0_WINDOWB_X_CONTROL |
25303 | #define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
25304 | #define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
25305 | #define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
25306 | #define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
25307 | //OTG4_OTG_CRC0_WINDOWB_Y_CONTROL |
25308 | #define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
25309 | #define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
25310 | #define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
25311 | #define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
25312 | //OTG4_OTG_CRC0_DATA_RG |
25313 | #define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
25314 | #define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
25315 | #define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
25316 | #define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
25317 | //OTG4_OTG_CRC0_DATA_B |
25318 | #define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
25319 | #define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
25320 | #define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
25321 | #define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
25322 | //OTG4_OTG_CRC1_WINDOWA_X_CONTROL |
25323 | #define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
25324 | #define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
25325 | #define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
25326 | #define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
25327 | //OTG4_OTG_CRC1_WINDOWA_Y_CONTROL |
25328 | #define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
25329 | #define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
25330 | #define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
25331 | #define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
25332 | //OTG4_OTG_CRC1_WINDOWB_X_CONTROL |
25333 | #define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
25334 | #define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
25335 | #define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
25336 | #define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
25337 | //OTG4_OTG_CRC1_WINDOWB_Y_CONTROL |
25338 | #define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
25339 | #define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
25340 | #define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
25341 | #define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
25342 | //OTG4_OTG_CRC1_DATA_RG |
25343 | #define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
25344 | #define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
25345 | #define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
25346 | #define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
25347 | //OTG4_OTG_CRC1_DATA_B |
25348 | #define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
25349 | #define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
25350 | #define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
25351 | #define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
25352 | //OTG4_OTG_CRC2_DATA_RG |
25353 | #define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
25354 | #define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
25355 | #define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
25356 | #define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
25357 | //OTG4_OTG_CRC2_DATA_B |
25358 | #define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
25359 | #define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
25360 | #define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
25361 | #define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
25362 | //OTG4_OTG_CRC3_DATA_RG |
25363 | #define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
25364 | #define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
25365 | #define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
25366 | #define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
25367 | //OTG4_OTG_CRC3_DATA_B |
25368 | #define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
25369 | #define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
25370 | #define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
25371 | #define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
25372 | //OTG4_OTG_CRC_SIG_RED_GREEN_MASK |
25373 | #define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
25374 | #define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
25375 | #define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
25376 | #define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
25377 | //OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK |
25378 | #define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
25379 | #define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
25380 | #define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
25381 | #define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
25382 | //OTG4_OTG_STATIC_SCREEN_CONTROL |
25383 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
25384 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
25385 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
25386 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
25387 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
25388 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
25389 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
25390 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
25391 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
25392 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
25393 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
25394 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
25395 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
25396 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
25397 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
25398 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
25399 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
25400 | #define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
25401 | //OTG4_OTG_3D_STRUCTURE_CONTROL |
25402 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
25403 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
25404 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
25405 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
25406 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
25407 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
25408 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
25409 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
25410 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
25411 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
25412 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
25413 | #define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
25414 | //OTG4_OTG_GSL_VSYNC_GAP |
25415 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
25416 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
25417 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
25418 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
25419 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
25420 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
25421 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
25422 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
25423 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
25424 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
25425 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
25426 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
25427 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
25428 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
25429 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
25430 | #define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
25431 | //OTG4_OTG_MASTER_UPDATE_MODE |
25432 | #define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
25433 | #define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
25434 | //OTG4_OTG_CLOCK_CONTROL |
25435 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
25436 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
25437 | #define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
25438 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
25439 | #define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
25440 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
25441 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
25442 | #define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
25443 | #define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
25444 | #define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
25445 | //OTG4_OTG_VSTARTUP_PARAM |
25446 | #define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
25447 | #define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
25448 | //OTG4_OTG_VUPDATE_PARAM |
25449 | #define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
25450 | #define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
25451 | #define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
25452 | #define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
25453 | //OTG4_OTG_VREADY_PARAM |
25454 | #define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
25455 | #define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
25456 | //OTG4_OTG_GLOBAL_SYNC_STATUS |
25457 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
25458 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
25459 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
25460 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
25461 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
25462 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
25463 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
25464 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
25465 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
25466 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
25467 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
25468 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
25469 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
25470 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
25471 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
25472 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
25473 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
25474 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
25475 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
25476 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
25477 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
25478 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
25479 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
25480 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
25481 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
25482 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
25483 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
25484 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
25485 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
25486 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
25487 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
25488 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
25489 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
25490 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
25491 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
25492 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
25493 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
25494 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
25495 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
25496 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
25497 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
25498 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
25499 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
25500 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
25501 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
25502 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
25503 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
25504 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
25505 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
25506 | #define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
25507 | //OTG4_OTG_MASTER_UPDATE_LOCK |
25508 | #define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
25509 | #define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
25510 | #define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
25511 | #define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
25512 | //OTG4_OTG_GSL_CONTROL |
25513 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
25514 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
25515 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
25516 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
25517 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
25518 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
25519 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
25520 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
25521 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
25522 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
25523 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
25524 | #define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
25525 | //OTG4_OTG_GSL_WINDOW_X |
25526 | #define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
25527 | #define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
25528 | #define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
25529 | #define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
25530 | //OTG4_OTG_GSL_WINDOW_Y |
25531 | #define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
25532 | #define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
25533 | #define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
25534 | #define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
25535 | //OTG4_OTG_VUPDATE_KEEPOUT |
25536 | #define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
25537 | #define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
25538 | #define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
25539 | #define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
25540 | #define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
25541 | #define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
25542 | //OTG4_OTG_GLOBAL_CONTROL0 |
25543 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
25544 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
25545 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
25546 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
25547 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
25548 | #define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
25549 | //OTG4_OTG_GLOBAL_CONTROL1 |
25550 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
25551 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
25552 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
25553 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
25554 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
25555 | #define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
25556 | //OTG4_OTG_GLOBAL_CONTROL2 |
25557 | #define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
25558 | #define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
25559 | #define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
25560 | #define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
25561 | #define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
25562 | #define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
25563 | #define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
25564 | #define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
25565 | //OTG4_OTG_GLOBAL_CONTROL3 |
25566 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
25567 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
25568 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
25569 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
25570 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
25571 | #define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
25572 | //OTG4_OTG_TRIG_MANUAL_CONTROL |
25573 | #define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
25574 | #define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
25575 | //OTG4_OTG_MANUAL_FLOW_CONTROL |
25576 | #define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
25577 | #define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
25578 | //OTG4_OTG_RANGE_TIMING_INT_STATUS |
25579 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
25580 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
25581 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
25582 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
25583 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
25584 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
25585 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
25586 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
25587 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
25588 | #define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
25589 | //OTG4_OTG_DRR_CONTROL |
25590 | #define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
25591 | #define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
25592 | #define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
25593 | #define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
25594 | //OTG4_OTG_REQUEST_CONTROL |
25595 | #define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
25596 | #define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
25597 | //OTG4_OTG_SPARE_REGISTER |
25598 | #define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
25599 | #define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
25600 | |
25601 | |
25602 | // addressBlock: dce_dc_optc_otg5_dispdec |
25603 | //OTG5_OTG_H_TOTAL |
25604 | #define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 |
25605 | #define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL |
25606 | //OTG5_OTG_H_BLANK_START_END |
25607 | #define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 |
25608 | #define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 |
25609 | #define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL |
25610 | #define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L |
25611 | //OTG5_OTG_H_SYNC_A |
25612 | #define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 |
25613 | #define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 |
25614 | #define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL |
25615 | #define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L |
25616 | //OTG5_OTG_H_SYNC_A_CNTL |
25617 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 |
25618 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 |
25619 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 |
25620 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L |
25621 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L |
25622 | #define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L |
25623 | //OTG5_OTG_H_TIMING_CNTL |
25624 | #define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 |
25625 | #define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 |
25626 | #define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L |
25627 | #define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L |
25628 | //OTG5_OTG_V_TOTAL |
25629 | #define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 |
25630 | #define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL |
25631 | //OTG5_OTG_V_TOTAL_MIN |
25632 | #define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 |
25633 | #define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL |
25634 | //OTG5_OTG_V_TOTAL_MAX |
25635 | #define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 |
25636 | #define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL |
25637 | //OTG5_OTG_V_TOTAL_MID |
25638 | #define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 |
25639 | #define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL |
25640 | //OTG5_OTG_V_TOTAL_CONTROL |
25641 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 |
25642 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 |
25643 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 |
25644 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 |
25645 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 |
25646 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 |
25647 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 |
25648 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
25649 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L |
25650 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L |
25651 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L |
25652 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L |
25653 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L |
25654 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L |
25655 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L |
25656 | #define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L |
25657 | //OTG5_OTG_V_TOTAL_INT_STATUS |
25658 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
25659 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
25660 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
25661 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
25662 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L |
25663 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L |
25664 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L |
25665 | #define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L |
25666 | //OTG5_OTG_VSYNC_NOM_INT_STATUS |
25667 | #define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 |
25668 | #define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
25669 | #define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L |
25670 | #define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L |
25671 | //OTG5_OTG_V_BLANK_START_END |
25672 | #define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 |
25673 | #define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 |
25674 | #define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL |
25675 | #define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L |
25676 | //OTG5_OTG_V_SYNC_A |
25677 | #define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 |
25678 | #define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 |
25679 | #define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL |
25680 | #define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L |
25681 | //OTG5_OTG_V_SYNC_A_CNTL |
25682 | #define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 |
25683 | #define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L |
25684 | //OTG5_OTG_TRIGA_CNTL |
25685 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
25686 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 |
25687 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 |
25688 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb |
25689 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc |
25690 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd |
25691 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe |
25692 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
25693 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
25694 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
25695 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 |
25696 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f |
25697 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL |
25698 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
25699 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L |
25700 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L |
25701 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L |
25702 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L |
25703 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L |
25704 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
25705 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
25706 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L |
25707 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L |
25708 | #define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L |
25709 | //OTG5_OTG_TRIGA_MANUAL_TRIG |
25710 | #define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
25711 | #define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L |
25712 | //OTG5_OTG_TRIGB_CNTL |
25713 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
25714 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 |
25715 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 |
25716 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb |
25717 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc |
25718 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd |
25719 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe |
25720 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 |
25721 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 |
25722 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
25723 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 |
25724 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f |
25725 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL |
25726 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L |
25727 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L |
25728 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L |
25729 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L |
25730 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L |
25731 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L |
25732 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L |
25733 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L |
25734 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L |
25735 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L |
25736 | #define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L |
25737 | //OTG5_OTG_TRIGB_MANUAL_TRIG |
25738 | #define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
25739 | #define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L |
25740 | //OTG5_OTG_FORCE_COUNT_NOW_CNTL |
25741 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
25742 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
25743 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
25744 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
25745 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
25746 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L |
25747 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L |
25748 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L |
25749 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L |
25750 | #define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L |
25751 | //OTG5_OTG_FLOW_CONTROL |
25752 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
25753 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
25754 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
25755 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
25756 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL |
25757 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L |
25758 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L |
25759 | #define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L |
25760 | //OTG5_OTG_STEREO_FORCE_NEXT_EYE |
25761 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
25762 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 |
25763 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 |
25764 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L |
25765 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L |
25766 | #define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L |
25767 | //OTG5_OTG_AVSYNC_COUNTER |
25768 | #define OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT 0x0 |
25769 | #define OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK 0xFFFFFFFFL |
25770 | //OTG5_OTG_CONTROL |
25771 | #define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 |
25772 | #define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 |
25773 | #define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc |
25774 | #define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd |
25775 | #define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe |
25776 | #define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
25777 | #define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L |
25778 | #define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L |
25779 | #define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L |
25780 | #define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L |
25781 | #define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L |
25782 | #define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L |
25783 | //OTG5_OTG_BLANK_CONTROL |
25784 | #define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 |
25785 | #define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 |
25786 | #define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 |
25787 | #define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L |
25788 | #define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L |
25789 | #define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L |
25790 | //OTG5_OTG_PIPE_ABORT_CONTROL |
25791 | #define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 |
25792 | #define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 |
25793 | #define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L |
25794 | #define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L |
25795 | //OTG5_OTG_INTERLACE_CONTROL |
25796 | #define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 |
25797 | #define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
25798 | #define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L |
25799 | #define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L |
25800 | //OTG5_OTG_INTERLACE_STATUS |
25801 | #define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
25802 | #define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
25803 | #define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L |
25804 | #define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L |
25805 | //OTG5_OTG_FIELD_INDICATION_CONTROL |
25806 | #define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
25807 | #define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT 0x1 |
25808 | #define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x00000001L |
25809 | #define OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK 0x00000002L |
25810 | //OTG5_OTG_PIXEL_DATA_READBACK0 |
25811 | #define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
25812 | #define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
25813 | #define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL |
25814 | #define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L |
25815 | //OTG5_OTG_PIXEL_DATA_READBACK1 |
25816 | #define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 |
25817 | #define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL |
25818 | //OTG5_OTG_STATUS |
25819 | #define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 |
25820 | #define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 |
25821 | #define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 |
25822 | #define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 |
25823 | #define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
25824 | #define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 |
25825 | #define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 |
25826 | #define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 |
25827 | #define OTG5_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L |
25828 | #define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L |
25829 | #define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L |
25830 | #define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L |
25831 | #define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L |
25832 | #define OTG5_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L |
25833 | #define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L |
25834 | #define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L |
25835 | //OTG5_OTG_STATUS_POSITION |
25836 | #define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 |
25837 | #define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 |
25838 | #define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL |
25839 | #define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L |
25840 | //OTG5_OTG_NOM_VERT_POSITION |
25841 | #define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 |
25842 | #define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL |
25843 | //OTG5_OTG_STATUS_FRAME_COUNT |
25844 | #define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 |
25845 | #define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL |
25846 | //OTG5_OTG_STATUS_VF_COUNT |
25847 | #define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 |
25848 | #define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL |
25849 | //OTG5_OTG_STATUS_HV_COUNT |
25850 | #define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 |
25851 | #define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL |
25852 | //OTG5_OTG_COUNT_CONTROL |
25853 | #define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
25854 | #define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 |
25855 | #define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L |
25856 | #define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL |
25857 | //OTG5_OTG_COUNT_RESET |
25858 | #define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 |
25859 | #define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L |
25860 | //OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE |
25861 | #define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
25862 | #define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L |
25863 | //OTG5_OTG_VERT_SYNC_CONTROL |
25864 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
25865 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
25866 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
25867 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L |
25868 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L |
25869 | #define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L |
25870 | //OTG5_OTG_STEREO_STATUS |
25871 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 |
25872 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
25873 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 |
25874 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 |
25875 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
25876 | #define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e |
25877 | #define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f |
25878 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L |
25879 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L |
25880 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L |
25881 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L |
25882 | #define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L |
25883 | #define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L |
25884 | #define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L |
25885 | //OTG5_OTG_STEREO_CONTROL |
25886 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
25887 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
25888 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 |
25889 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 |
25890 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 |
25891 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 |
25892 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 |
25893 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL |
25894 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L |
25895 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L |
25896 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L |
25897 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L |
25898 | #define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L |
25899 | #define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L |
25900 | //OTG5_OTG_SNAPSHOT_STATUS |
25901 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 |
25902 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 |
25903 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
25904 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L |
25905 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L |
25906 | #define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L |
25907 | //OTG5_OTG_SNAPSHOT_CONTROL |
25908 | #define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
25909 | #define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L |
25910 | //OTG5_OTG_SNAPSHOT_POSITION |
25911 | #define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
25912 | #define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
25913 | #define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL |
25914 | #define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L |
25915 | //OTG5_OTG_SNAPSHOT_FRAME |
25916 | #define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
25917 | #define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL |
25918 | //OTG5_OTG_INTERRUPT_CONTROL |
25919 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 |
25920 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
25921 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
25922 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
25923 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
25924 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
25925 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 |
25926 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 |
25927 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a |
25928 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b |
25929 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
25930 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
25931 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
25932 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
25933 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L |
25934 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L |
25935 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L |
25936 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L |
25937 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L |
25938 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L |
25939 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L |
25940 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L |
25941 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L |
25942 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L |
25943 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L |
25944 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L |
25945 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L |
25946 | #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L |
25947 | //OTG5_OTG_UPDATE_LOCK |
25948 | #define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 |
25949 | #define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L |
25950 | //OTG5_OTG_DOUBLE_BUFFER_CONTROL |
25951 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 |
25952 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 |
25953 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 |
25954 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 |
25955 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 |
25956 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 |
25957 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 |
25958 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 |
25959 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
25960 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 |
25961 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L |
25962 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L |
25963 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L |
25964 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L |
25965 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L |
25966 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L |
25967 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L |
25968 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L |
25969 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L |
25970 | #define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L |
25971 | //OTG5_OTG_TEST_PATTERN_CONTROL |
25972 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT 0x0 |
25973 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT 0x8 |
25974 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
25975 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
25976 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK 0x00000001L |
25977 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK 0x00000700L |
25978 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L |
25979 | #define OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK 0xFF000000L |
25980 | //OTG5_OTG_TEST_PATTERN_PARAMETERS |
25981 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT 0x0 |
25982 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT 0x4 |
25983 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT 0x8 |
25984 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT 0xc |
25985 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
25986 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK 0x0000000FL |
25987 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK 0x000000F0L |
25988 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK 0x00000F00L |
25989 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK 0x0000F000L |
25990 | #define OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK 0xFFFF0000L |
25991 | //OTG5_OTG_TEST_PATTERN_COLOR |
25992 | #define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT 0x0 |
25993 | #define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT 0x10 |
25994 | #define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK 0x0000FFFFL |
25995 | #define OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK 0x003F0000L |
25996 | //OTG5_OTG_MASTER_EN |
25997 | #define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 |
25998 | #define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L |
25999 | //OTG5_OTG_BLANK_DATA_COLOR |
26000 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
26001 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
26002 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
26003 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL |
26004 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L |
26005 | #define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L |
26006 | //OTG5_OTG_BLANK_DATA_COLOR_EXT |
26007 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
26008 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
26009 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
26010 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL |
26011 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L |
26012 | #define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L |
26013 | //OTG5_OTG_BLACK_COLOR |
26014 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 |
26015 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa |
26016 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 |
26017 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL |
26018 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L |
26019 | #define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L |
26020 | //OTG5_OTG_BLACK_COLOR_EXT |
26021 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
26022 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
26023 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
26024 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL |
26025 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L |
26026 | #define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L |
26027 | //OTG5_OTG_VERTICAL_INTERRUPT0_POSITION |
26028 | #define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
26029 | #define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
26030 | #define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL |
26031 | #define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L |
26032 | //OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL |
26033 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
26034 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
26035 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
26036 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
26037 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
26038 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
26039 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L |
26040 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L |
26041 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L |
26042 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L |
26043 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L |
26044 | #define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L |
26045 | //OTG5_OTG_VERTICAL_INTERRUPT1_POSITION |
26046 | #define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
26047 | #define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL |
26048 | //OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL |
26049 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
26050 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
26051 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
26052 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
26053 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
26054 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L |
26055 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L |
26056 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L |
26057 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L |
26058 | #define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L |
26059 | //OTG5_OTG_VERTICAL_INTERRUPT2_POSITION |
26060 | #define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
26061 | #define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL |
26062 | //OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL |
26063 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
26064 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
26065 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
26066 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
26067 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
26068 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L |
26069 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L |
26070 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L |
26071 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L |
26072 | #define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L |
26073 | //OTG5_OTG_CRC_CNTL |
26074 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 |
26075 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 |
26076 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 |
26077 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 |
26078 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 |
26079 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 |
26080 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 |
26081 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc |
26082 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT 0x10 |
26083 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 |
26084 | #define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 |
26085 | #define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 |
26086 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c |
26087 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d |
26088 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e |
26089 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f |
26090 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L |
26091 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L |
26092 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L |
26093 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L |
26094 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L |
26095 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L |
26096 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L |
26097 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L |
26098 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK 0x00070000L |
26099 | #define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L |
26100 | #define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L |
26101 | #define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L |
26102 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L |
26103 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L |
26104 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L |
26105 | #define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L |
26106 | //OTG5_OTG_CRC0_WINDOWA_X_CONTROL |
26107 | #define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 |
26108 | #define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 |
26109 | #define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL |
26110 | #define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L |
26111 | //OTG5_OTG_CRC0_WINDOWA_Y_CONTROL |
26112 | #define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
26113 | #define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
26114 | #define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL |
26115 | #define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L |
26116 | //OTG5_OTG_CRC0_WINDOWB_X_CONTROL |
26117 | #define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 |
26118 | #define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 |
26119 | #define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL |
26120 | #define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L |
26121 | //OTG5_OTG_CRC0_WINDOWB_Y_CONTROL |
26122 | #define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
26123 | #define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
26124 | #define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL |
26125 | #define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L |
26126 | //OTG5_OTG_CRC0_DATA_RG |
26127 | #define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
26128 | #define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
26129 | #define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL |
26130 | #define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L |
26131 | //OTG5_OTG_CRC0_DATA_B |
26132 | #define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
26133 | #define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 |
26134 | #define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL |
26135 | #define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L |
26136 | //OTG5_OTG_CRC1_WINDOWA_X_CONTROL |
26137 | #define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 |
26138 | #define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 |
26139 | #define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL |
26140 | #define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L |
26141 | //OTG5_OTG_CRC1_WINDOWA_Y_CONTROL |
26142 | #define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
26143 | #define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
26144 | #define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL |
26145 | #define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L |
26146 | //OTG5_OTG_CRC1_WINDOWB_X_CONTROL |
26147 | #define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 |
26148 | #define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 |
26149 | #define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL |
26150 | #define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L |
26151 | //OTG5_OTG_CRC1_WINDOWB_Y_CONTROL |
26152 | #define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
26153 | #define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
26154 | #define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL |
26155 | #define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L |
26156 | //OTG5_OTG_CRC1_DATA_RG |
26157 | #define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
26158 | #define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
26159 | #define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL |
26160 | #define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L |
26161 | //OTG5_OTG_CRC1_DATA_B |
26162 | #define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
26163 | #define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 |
26164 | #define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL |
26165 | #define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L |
26166 | //OTG5_OTG_CRC2_DATA_RG |
26167 | #define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 |
26168 | #define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 |
26169 | #define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL |
26170 | #define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L |
26171 | //OTG5_OTG_CRC2_DATA_B |
26172 | #define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 |
26173 | #define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 |
26174 | #define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL |
26175 | #define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L |
26176 | //OTG5_OTG_CRC3_DATA_RG |
26177 | #define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 |
26178 | #define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 |
26179 | #define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL |
26180 | #define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L |
26181 | //OTG5_OTG_CRC3_DATA_B |
26182 | #define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 |
26183 | #define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 |
26184 | #define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL |
26185 | #define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L |
26186 | //OTG5_OTG_CRC_SIG_RED_GREEN_MASK |
26187 | #define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 |
26188 | #define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
26189 | #define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL |
26190 | #define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L |
26191 | //OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK |
26192 | #define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
26193 | #define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
26194 | #define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL |
26195 | #define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L |
26196 | //OTG5_OTG_STATIC_SCREEN_CONTROL |
26197 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
26198 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
26199 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 |
26200 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 |
26201 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a |
26202 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b |
26203 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c |
26204 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e |
26205 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f |
26206 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL |
26207 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L |
26208 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L |
26209 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L |
26210 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L |
26211 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L |
26212 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L |
26213 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L |
26214 | #define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L |
26215 | //OTG5_OTG_3D_STRUCTURE_CONTROL |
26216 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 |
26217 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
26218 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
26219 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
26220 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
26221 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
26222 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L |
26223 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L |
26224 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L |
26225 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L |
26226 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L |
26227 | #define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L |
26228 | //OTG5_OTG_GSL_VSYNC_GAP |
26229 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
26230 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
26231 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
26232 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
26233 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
26234 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
26235 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
26236 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 |
26237 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL |
26238 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L |
26239 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L |
26240 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L |
26241 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L |
26242 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L |
26243 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L |
26244 | #define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L |
26245 | //OTG5_OTG_MASTER_UPDATE_MODE |
26246 | #define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 |
26247 | #define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L |
26248 | //OTG5_OTG_CLOCK_CONTROL |
26249 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 |
26250 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 |
26251 | #define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 |
26252 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 |
26253 | #define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 |
26254 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L |
26255 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L |
26256 | #define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L |
26257 | #define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L |
26258 | #define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L |
26259 | //OTG5_OTG_VSTARTUP_PARAM |
26260 | #define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 |
26261 | #define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL |
26262 | //OTG5_OTG_VUPDATE_PARAM |
26263 | #define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 |
26264 | #define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 |
26265 | #define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL |
26266 | #define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L |
26267 | //OTG5_OTG_VREADY_PARAM |
26268 | #define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 |
26269 | #define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL |
26270 | //OTG5_OTG_GLOBAL_SYNC_STATUS |
26271 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 |
26272 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 |
26273 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 |
26274 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 |
26275 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 |
26276 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 |
26277 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 |
26278 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 |
26279 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 |
26280 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 |
26281 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa |
26282 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb |
26283 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc |
26284 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd |
26285 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe |
26286 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf |
26287 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 |
26288 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 |
26289 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 |
26290 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 |
26291 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 |
26292 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 |
26293 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 |
26294 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 |
26295 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 |
26296 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L |
26297 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L |
26298 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L |
26299 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L |
26300 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L |
26301 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L |
26302 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L |
26303 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L |
26304 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L |
26305 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L |
26306 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L |
26307 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L |
26308 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L |
26309 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L |
26310 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L |
26311 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L |
26312 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L |
26313 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L |
26314 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L |
26315 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L |
26316 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L |
26317 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L |
26318 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L |
26319 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L |
26320 | #define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L |
26321 | //OTG5_OTG_MASTER_UPDATE_LOCK |
26322 | #define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 |
26323 | #define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 |
26324 | #define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L |
26325 | #define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L |
26326 | //OTG5_OTG_GSL_CONTROL |
26327 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 |
26328 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 |
26329 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 |
26330 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 |
26331 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 |
26332 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
26333 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L |
26334 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L |
26335 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L |
26336 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L |
26337 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L |
26338 | #define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L |
26339 | //OTG5_OTG_GSL_WINDOW_X |
26340 | #define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 |
26341 | #define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 |
26342 | #define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL |
26343 | #define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L |
26344 | //OTG5_OTG_GSL_WINDOW_Y |
26345 | #define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 |
26346 | #define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 |
26347 | #define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL |
26348 | #define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L |
26349 | //OTG5_OTG_VUPDATE_KEEPOUT |
26350 | #define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 |
26351 | #define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 |
26352 | #define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f |
26353 | #define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL |
26354 | #define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L |
26355 | #define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L |
26356 | //OTG5_OTG_GLOBAL_CONTROL0 |
26357 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 |
26358 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 |
26359 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 |
26360 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL |
26361 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L |
26362 | #define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L |
26363 | //OTG5_OTG_GLOBAL_CONTROL1 |
26364 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 |
26365 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 |
26366 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f |
26367 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL |
26368 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L |
26369 | #define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L |
26370 | //OTG5_OTG_GLOBAL_CONTROL2 |
26371 | #define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 |
26372 | #define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa |
26373 | #define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 |
26374 | #define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f |
26375 | #define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL |
26376 | #define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L |
26377 | #define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L |
26378 | #define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L |
26379 | //OTG5_OTG_GLOBAL_CONTROL3 |
26380 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 |
26381 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 |
26382 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 |
26383 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L |
26384 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L |
26385 | #define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L |
26386 | //OTG5_OTG_TRIG_MANUAL_CONTROL |
26387 | #define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 |
26388 | #define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L |
26389 | //OTG5_OTG_MANUAL_FLOW_CONTROL |
26390 | #define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 |
26391 | #define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L |
26392 | //OTG5_OTG_RANGE_TIMING_INT_STATUS |
26393 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 |
26394 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 |
26395 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 |
26396 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc |
26397 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 |
26398 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L |
26399 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L |
26400 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L |
26401 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L |
26402 | #define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L |
26403 | //OTG5_OTG_DRR_CONTROL |
26404 | #define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 |
26405 | #define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 |
26406 | #define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L |
26407 | #define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L |
26408 | //OTG5_OTG_REQUEST_CONTROL |
26409 | #define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 |
26410 | #define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L |
26411 | //OTG5_OTG_SPARE_REGISTER |
26412 | #define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 |
26413 | #define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL |
26414 | |
26415 | |
26416 | // addressBlock: dce_dc_optc_optc_misc_dispdec |
26417 | //DWB_SOURCE_SELECT |
26418 | #define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 |
26419 | #define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 |
26420 | #define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L |
26421 | #define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L |
26422 | //GSL_SOURCE_SELECT |
26423 | #define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 |
26424 | #define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 |
26425 | #define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 |
26426 | #define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
26427 | #define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L |
26428 | #define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L |
26429 | #define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L |
26430 | #define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L |
26431 | //OPTC_CLOCK_CONTROL |
26432 | #define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 |
26433 | #define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 |
26434 | #define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 |
26435 | #define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L |
26436 | #define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L |
26437 | #define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L |
26438 | //OPTC_MISC_SPARE_REGISTER |
26439 | #define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 |
26440 | #define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL |
26441 | |
26442 | |
26443 | // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec |
26444 | //DC_PERFMON18_PERFCOUNTER_CNTL |
26445 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
26446 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
26447 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
26448 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
26449 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
26450 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
26451 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
26452 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
26453 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
26454 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
26455 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
26456 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
26457 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
26458 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
26459 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
26460 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
26461 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
26462 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
26463 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
26464 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
26465 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
26466 | #define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
26467 | //DC_PERFMON18_PERFCOUNTER_CNTL2 |
26468 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
26469 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
26470 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
26471 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
26472 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
26473 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
26474 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
26475 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
26476 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
26477 | #define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
26478 | //DC_PERFMON18_PERFCOUNTER_STATE |
26479 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
26480 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
26481 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
26482 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
26483 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
26484 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
26485 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
26486 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
26487 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
26488 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
26489 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
26490 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
26491 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
26492 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
26493 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
26494 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
26495 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
26496 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
26497 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
26498 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
26499 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
26500 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
26501 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
26502 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
26503 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
26504 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
26505 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
26506 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
26507 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
26508 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
26509 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
26510 | #define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
26511 | //DC_PERFMON18_PERFMON_CNTL |
26512 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
26513 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
26514 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
26515 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
26516 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
26517 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
26518 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
26519 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
26520 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
26521 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
26522 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
26523 | #define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
26524 | //DC_PERFMON18_PERFMON_CNTL2 |
26525 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
26526 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
26527 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
26528 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
26529 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
26530 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
26531 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
26532 | #define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
26533 | //DC_PERFMON18_PERFMON_CVALUE_INT_MISC |
26534 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
26535 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
26536 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
26537 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
26538 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
26539 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
26540 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
26541 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
26542 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
26543 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
26544 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
26545 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
26546 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
26547 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
26548 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
26549 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
26550 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
26551 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
26552 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
26553 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
26554 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
26555 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
26556 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
26557 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
26558 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
26559 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
26560 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
26561 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
26562 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
26563 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
26564 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
26565 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
26566 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
26567 | #define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
26568 | //DC_PERFMON18_PERFMON_CVALUE_LOW |
26569 | #define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
26570 | #define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
26571 | //DC_PERFMON18_PERFMON_HI |
26572 | #define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
26573 | #define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
26574 | #define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
26575 | #define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
26576 | //DC_PERFMON18_PERFMON_LOW |
26577 | #define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
26578 | #define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
26579 | |
26580 | |
26581 | // addressBlock: dce_dc_dio_dac_dispdec |
26582 | //DAC_ENABLE |
26583 | #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 |
26584 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 |
26585 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 |
26586 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 |
26587 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 |
26588 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 |
26589 | #define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L |
26590 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L |
26591 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000CL |
26592 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L |
26593 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L |
26594 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L |
26595 | //DAC_SOURCE_SELECT |
26596 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 |
26597 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 |
26598 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L |
26599 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L |
26600 | //DAC_CRC_EN |
26601 | #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 |
26602 | #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 |
26603 | #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L |
26604 | #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L |
26605 | //DAC_CRC_CONTROL |
26606 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 |
26607 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 |
26608 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L |
26609 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x00000100L |
26610 | //DAC_CRC_SIG_RGB_MASK |
26611 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
26612 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa |
26613 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 |
26614 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003FFL |
26615 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000FFC00L |
26616 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3FF00000L |
26617 | //DAC_CRC_SIG_CONTROL_MASK |
26618 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 |
26619 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003FL |
26620 | //DAC_CRC_SIG_RGB |
26621 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 |
26622 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa |
26623 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 |
26624 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003FFL |
26625 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000FFC00L |
26626 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3FF00000L |
26627 | //DAC_CRC_SIG_CONTROL |
26628 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 |
26629 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003FL |
26630 | //DAC_SYNC_TRISTATE_CONTROL |
26631 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 |
26632 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 |
26633 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 |
26634 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L |
26635 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L |
26636 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L |
26637 | //DAC_STEREOSYNC_SELECT |
26638 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 |
26639 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L |
26640 | //DAC_AUTODETECT_CONTROL |
26641 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 |
26642 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 |
26643 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 |
26644 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L |
26645 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000FF00L |
26646 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L |
26647 | //DAC_AUTODETECT_CONTROL2 |
26648 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 |
26649 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 |
26650 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000FFL |
26651 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L |
26652 | //DAC_AUTODETECT_CONTROL3 |
26653 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 |
26654 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 |
26655 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000FFL |
26656 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000FF00L |
26657 | //DAC_AUTODETECT_STATUS |
26658 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 |
26659 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 |
26660 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 |
26661 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 |
26662 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 |
26663 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L |
26664 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L |
26665 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L |
26666 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L |
26667 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L |
26668 | //DAC_AUTODETECT_INT_CONTROL |
26669 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 |
26670 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 |
26671 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L |
26672 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L |
26673 | //DAC_FORCE_OUTPUT_CNTL |
26674 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 |
26675 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 |
26676 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 |
26677 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L |
26678 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L |
26679 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x01000000L |
26680 | //DAC_FORCE_DATA |
26681 | #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 |
26682 | #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003FFL |
26683 | //DAC_POWERDOWN |
26684 | #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 |
26685 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 |
26686 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 |
26687 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 |
26688 | #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L |
26689 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L |
26690 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L |
26691 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L |
26692 | //DAC_CONTROL |
26693 | #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 |
26694 | #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 |
26695 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 |
26696 | #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L |
26697 | #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L |
26698 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L |
26699 | //DAC_COMPARATOR_ENABLE |
26700 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 |
26701 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 |
26702 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 |
26703 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 |
26704 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 |
26705 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L |
26706 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L |
26707 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L |
26708 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L |
26709 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L |
26710 | //DAC_COMPARATOR_OUTPUT |
26711 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 |
26712 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 |
26713 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 |
26714 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 |
26715 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L |
26716 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L |
26717 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L |
26718 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L |
26719 | //DAC_PWR_CNTL |
26720 | #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 |
26721 | #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 |
26722 | #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L |
26723 | #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L |
26724 | //DAC_DFT_CONFIG |
26725 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 |
26726 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xFFFFFFFFL |
26727 | //DAC_FIFO_STATUS |
26728 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
26729 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
26730 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
26731 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
26732 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
26733 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d |
26734 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
26735 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
26736 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
26737 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
26738 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
26739 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000F0000L |
26740 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
26741 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L |
26742 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
26743 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
26744 | |
26745 | |
26746 | // addressBlock: dce_dc_dio_dout_i2c_dispdec |
26747 | //DC_I2C_CONTROL |
26748 | #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 |
26749 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 |
26750 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 |
26751 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 |
26752 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 |
26753 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 |
26754 | #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L |
26755 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L |
26756 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L |
26757 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L |
26758 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L |
26759 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L |
26760 | //DC_I2C_ARBITRATION |
26761 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 |
26762 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 |
26763 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 |
26764 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 |
26765 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc |
26766 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 |
26767 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 |
26768 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 |
26769 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 |
26770 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L |
26771 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
26772 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L |
26773 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L |
26774 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L |
26775 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L |
26776 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L |
26777 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L |
26778 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L |
26779 | //DC_I2C_INTERRUPT_CONTROL |
26780 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 |
26781 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 |
26782 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 |
26783 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 |
26784 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 |
26785 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 |
26786 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 |
26787 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 |
26788 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa |
26789 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc |
26790 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd |
26791 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe |
26792 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 |
26793 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 |
26794 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 |
26795 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 |
26796 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 |
26797 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 |
26798 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 |
26799 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 |
26800 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a |
26801 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b |
26802 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c |
26803 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d |
26804 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L |
26805 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L |
26806 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L |
26807 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L |
26808 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L |
26809 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L |
26810 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L |
26811 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L |
26812 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L |
26813 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L |
26814 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L |
26815 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L |
26816 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L |
26817 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L |
26818 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L |
26819 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L |
26820 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L |
26821 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L |
26822 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L |
26823 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L |
26824 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L |
26825 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L |
26826 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L |
26827 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L |
26828 | //DC_I2C_SW_STATUS |
26829 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 |
26830 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 |
26831 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 |
26832 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 |
26833 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 |
26834 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 |
26835 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 |
26836 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc |
26837 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd |
26838 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe |
26839 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf |
26840 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 |
26841 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L |
26842 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L |
26843 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L |
26844 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L |
26845 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L |
26846 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L |
26847 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L |
26848 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L |
26849 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L |
26850 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L |
26851 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L |
26852 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L |
26853 | //DC_I2C_DDC1_HW_STATUS |
26854 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 |
26855 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 |
26856 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 |
26857 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 |
26858 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 |
26859 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26860 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c |
26861 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L |
26862 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L |
26863 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L |
26864 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L |
26865 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L |
26866 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26867 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L |
26868 | //DC_I2C_DDC2_HW_STATUS |
26869 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 |
26870 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 |
26871 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 |
26872 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 |
26873 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 |
26874 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26875 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c |
26876 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L |
26877 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L |
26878 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L |
26879 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L |
26880 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L |
26881 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26882 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L |
26883 | //DC_I2C_DDC3_HW_STATUS |
26884 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 |
26885 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 |
26886 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 |
26887 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 |
26888 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 |
26889 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26890 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c |
26891 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L |
26892 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L |
26893 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L |
26894 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L |
26895 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L |
26896 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26897 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L |
26898 | //DC_I2C_DDC4_HW_STATUS |
26899 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 |
26900 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 |
26901 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 |
26902 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 |
26903 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 |
26904 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26905 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c |
26906 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L |
26907 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L |
26908 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L |
26909 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L |
26910 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L |
26911 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26912 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L |
26913 | //DC_I2C_DDC5_HW_STATUS |
26914 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 |
26915 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 |
26916 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 |
26917 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 |
26918 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 |
26919 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26920 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c |
26921 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L |
26922 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L |
26923 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L |
26924 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L |
26925 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L |
26926 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26927 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L |
26928 | //DC_I2C_DDC6_HW_STATUS |
26929 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 |
26930 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 |
26931 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 |
26932 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 |
26933 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 |
26934 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
26935 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c |
26936 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L |
26937 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L |
26938 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L |
26939 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L |
26940 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L |
26941 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
26942 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L |
26943 | //DC_I2C_DDC1_SPEED |
26944 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 |
26945 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
26946 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 |
26947 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 |
26948 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L |
26949 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
26950 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L |
26951 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L |
26952 | //DC_I2C_DDC1_SETUP |
26953 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 |
26954 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 |
26955 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 |
26956 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 |
26957 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 |
26958 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 |
26959 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 |
26960 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
26961 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 |
26962 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L |
26963 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L |
26964 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L |
26965 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L |
26966 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L |
26967 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L |
26968 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
26969 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
26970 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L |
26971 | //DC_I2C_DDC2_SPEED |
26972 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 |
26973 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
26974 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 |
26975 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 |
26976 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L |
26977 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
26978 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L |
26979 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L |
26980 | //DC_I2C_DDC2_SETUP |
26981 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 |
26982 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 |
26983 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 |
26984 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 |
26985 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 |
26986 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 |
26987 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 |
26988 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
26989 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 |
26990 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L |
26991 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L |
26992 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L |
26993 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L |
26994 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L |
26995 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L |
26996 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
26997 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
26998 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L |
26999 | //DC_I2C_DDC3_SPEED |
27000 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 |
27001 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27002 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27003 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 |
27004 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L |
27005 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27006 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27007 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L |
27008 | //DC_I2C_DDC3_SETUP |
27009 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 |
27010 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 |
27011 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 |
27012 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 |
27013 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 |
27014 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 |
27015 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 |
27016 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
27017 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 |
27018 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L |
27019 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L |
27020 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L |
27021 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L |
27022 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L |
27023 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L |
27024 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27025 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
27026 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L |
27027 | //DC_I2C_DDC4_SPEED |
27028 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 |
27029 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27030 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27031 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 |
27032 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L |
27033 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27034 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27035 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L |
27036 | //DC_I2C_DDC4_SETUP |
27037 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 |
27038 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 |
27039 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 |
27040 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 |
27041 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 |
27042 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 |
27043 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 |
27044 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
27045 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 |
27046 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L |
27047 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L |
27048 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L |
27049 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L |
27050 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L |
27051 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L |
27052 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27053 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
27054 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L |
27055 | //DC_I2C_DDC5_SPEED |
27056 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 |
27057 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27058 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27059 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 |
27060 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L |
27061 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27062 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27063 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L |
27064 | //DC_I2C_DDC5_SETUP |
27065 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 |
27066 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 |
27067 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 |
27068 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 |
27069 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 |
27070 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 |
27071 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 |
27072 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
27073 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 |
27074 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L |
27075 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L |
27076 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L |
27077 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L |
27078 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L |
27079 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L |
27080 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27081 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
27082 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L |
27083 | //DC_I2C_DDC6_SPEED |
27084 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 |
27085 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27086 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27087 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 |
27088 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L |
27089 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27090 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27091 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xFFFF0000L |
27092 | //DC_I2C_DDC6_SETUP |
27093 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 |
27094 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 |
27095 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 |
27096 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 |
27097 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 |
27098 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 |
27099 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 |
27100 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
27101 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 |
27102 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L |
27103 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L |
27104 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L |
27105 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L |
27106 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L |
27107 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L |
27108 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27109 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
27110 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xFF000000L |
27111 | //DC_I2C_TRANSACTION0 |
27112 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 |
27113 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 |
27114 | #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc |
27115 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd |
27116 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 |
27117 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L |
27118 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L |
27119 | #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L |
27120 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L |
27121 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L |
27122 | //DC_I2C_TRANSACTION1 |
27123 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 |
27124 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 |
27125 | #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc |
27126 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd |
27127 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 |
27128 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L |
27129 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L |
27130 | #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L |
27131 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L |
27132 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L |
27133 | //DC_I2C_TRANSACTION2 |
27134 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 |
27135 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 |
27136 | #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc |
27137 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd |
27138 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 |
27139 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L |
27140 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L |
27141 | #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L |
27142 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L |
27143 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L |
27144 | //DC_I2C_TRANSACTION3 |
27145 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 |
27146 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 |
27147 | #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc |
27148 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd |
27149 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 |
27150 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L |
27151 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L |
27152 | #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L |
27153 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L |
27154 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L |
27155 | //DC_I2C_DATA |
27156 | #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 |
27157 | #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 |
27158 | #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 |
27159 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f |
27160 | #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L |
27161 | #define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L |
27162 | #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L |
27163 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L |
27164 | //DC_I2C_DDCVGA_HW_STATUS |
27165 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 |
27166 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 |
27167 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 |
27168 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 |
27169 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 |
27170 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
27171 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c |
27172 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L |
27173 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L |
27174 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L |
27175 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L |
27176 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L |
27177 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L |
27178 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L |
27179 | //DC_I2C_DDCVGA_SPEED |
27180 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 |
27181 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27182 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27183 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 |
27184 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L |
27185 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27186 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27187 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xFFFF0000L |
27188 | //DC_I2C_DDCVGA_SETUP |
27189 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 |
27190 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 |
27191 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 |
27192 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 |
27193 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 |
27194 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 |
27195 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 |
27196 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
27197 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 |
27198 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L |
27199 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L |
27200 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L |
27201 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L |
27202 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L |
27203 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L |
27204 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27205 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L |
27206 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xFF000000L |
27207 | //DC_I2C_EDID_DETECT_CTRL |
27208 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 |
27209 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 |
27210 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c |
27211 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL |
27212 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L |
27213 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L |
27214 | //DC_I2C_READ_REQUEST_INTERRUPT |
27215 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 |
27216 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 |
27217 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 |
27218 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 |
27219 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 |
27220 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 |
27221 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 |
27222 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 |
27223 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 |
27224 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 |
27225 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa |
27226 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb |
27227 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc |
27228 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd |
27229 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe |
27230 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf |
27231 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 |
27232 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 |
27233 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 |
27234 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 |
27235 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 |
27236 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 |
27237 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 |
27238 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 |
27239 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 |
27240 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 |
27241 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a |
27242 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b |
27243 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e |
27244 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f |
27245 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L |
27246 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L |
27247 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L |
27248 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L |
27249 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L |
27250 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L |
27251 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L |
27252 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L |
27253 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L |
27254 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L |
27255 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L |
27256 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L |
27257 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L |
27258 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L |
27259 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L |
27260 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L |
27261 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L |
27262 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L |
27263 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L |
27264 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L |
27265 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L |
27266 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L |
27267 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L |
27268 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L |
27269 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L |
27270 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L |
27271 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L |
27272 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L |
27273 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L |
27274 | #define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L |
27275 | |
27276 | |
27277 | // addressBlock: dce_dc_dio_generic_i2c_dispdec |
27278 | //GENERIC_I2C_CONTROL |
27279 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 |
27280 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 |
27281 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 |
27282 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 |
27283 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L |
27284 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L |
27285 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L |
27286 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L |
27287 | //GENERIC_I2C_INTERRUPT_CONTROL |
27288 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 |
27289 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 |
27290 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 |
27291 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L |
27292 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L |
27293 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L |
27294 | //GENERIC_I2C_STATUS |
27295 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 |
27296 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 |
27297 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 |
27298 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 |
27299 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 |
27300 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa |
27301 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000FL |
27302 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L |
27303 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L |
27304 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L |
27305 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L |
27306 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L |
27307 | //GENERIC_I2C_SPEED |
27308 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 |
27309 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
27310 | #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 |
27311 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 |
27312 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L |
27313 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L |
27314 | #define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x00000300L |
27315 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xFFFF0000L |
27316 | //GENERIC_I2C_SETUP |
27317 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 |
27318 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 |
27319 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 |
27320 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 |
27321 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 |
27322 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L |
27323 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L |
27324 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L |
27325 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000FF00L |
27326 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xFF000000L |
27327 | //GENERIC_I2C_TRANSACTION |
27328 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 |
27329 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 |
27330 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 |
27331 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc |
27332 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd |
27333 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 |
27334 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L |
27335 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L |
27336 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L |
27337 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L |
27338 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L |
27339 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000F0000L |
27340 | //GENERIC_I2C_DATA |
27341 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 |
27342 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 |
27343 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 |
27344 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f |
27345 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L |
27346 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000FF00L |
27347 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000F0000L |
27348 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L |
27349 | //GENERIC_I2C_PIN_SELECTION |
27350 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 |
27351 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 |
27352 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007FL |
27353 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007F00L |
27354 | |
27355 | |
27356 | // addressBlock: dce_dc_dio_dio_misc_dispdec |
27357 | //DIO_SCRATCH0 |
27358 | #define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 |
27359 | #define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL |
27360 | //DIO_SCRATCH1 |
27361 | #define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 |
27362 | #define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL |
27363 | //DIO_SCRATCH2 |
27364 | #define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 |
27365 | #define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL |
27366 | //DIO_SCRATCH3 |
27367 | #define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 |
27368 | #define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL |
27369 | //DIO_SCRATCH4 |
27370 | #define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 |
27371 | #define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL |
27372 | //DIO_SCRATCH5 |
27373 | #define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 |
27374 | #define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL |
27375 | //DIO_SCRATCH6 |
27376 | #define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 |
27377 | #define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL |
27378 | //DIO_SCRATCH7 |
27379 | #define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 |
27380 | #define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL |
27381 | //DCE_VCE_CONTROL |
27382 | #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 |
27383 | #define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L |
27384 | //DIO_MEM_PWR_STATUS |
27385 | #define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 |
27386 | #define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 |
27387 | #define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 |
27388 | #define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 |
27389 | #define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 |
27390 | #define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 |
27391 | #define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 |
27392 | #define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 |
27393 | #define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa |
27394 | #define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc |
27395 | #define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe |
27396 | #define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 |
27397 | #define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 |
27398 | #define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 |
27399 | #define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 |
27400 | #define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L |
27401 | #define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L |
27402 | #define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L |
27403 | #define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L |
27404 | #define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L |
27405 | #define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L |
27406 | #define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L |
27407 | #define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L |
27408 | #define DIO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0x00000C00L |
27409 | #define DIO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x00003000L |
27410 | #define DIO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0x0000C000L |
27411 | #define DIO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x00030000L |
27412 | #define DIO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0x000C0000L |
27413 | #define DIO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x00300000L |
27414 | #define DIO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0x00C00000L |
27415 | //DIO_MEM_PWR_CTRL |
27416 | #define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 |
27417 | #define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 |
27418 | #define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 |
27419 | #define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 |
27420 | #define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 |
27421 | #define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 |
27422 | #define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 |
27423 | #define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 |
27424 | #define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa |
27425 | #define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb |
27426 | #define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd |
27427 | #define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe |
27428 | #define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 |
27429 | #define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 |
27430 | #define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 |
27431 | #define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 |
27432 | #define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 |
27433 | #define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 |
27434 | #define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 |
27435 | #define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a |
27436 | #define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c |
27437 | #define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d |
27438 | #define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f |
27439 | #define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L |
27440 | #define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L |
27441 | #define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L |
27442 | #define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L |
27443 | #define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L |
27444 | #define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L |
27445 | #define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L |
27446 | #define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L |
27447 | #define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L |
27448 | #define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x00001800L |
27449 | #define DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x00002000L |
27450 | #define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0x0000C000L |
27451 | #define DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x00010000L |
27452 | #define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x00060000L |
27453 | #define DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x00080000L |
27454 | #define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x00300000L |
27455 | #define DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x00400000L |
27456 | #define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x01800000L |
27457 | #define DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x02000000L |
27458 | #define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0x0C000000L |
27459 | #define DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000L |
27460 | #define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000L |
27461 | #define DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000L |
27462 | //DIO_MEM_PWR_CTRL2 |
27463 | #define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 |
27464 | #define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS__SHIFT 0x4 |
27465 | #define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE__SHIFT 0x5 |
27466 | #define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS__SHIFT 0x6 |
27467 | #define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE__SHIFT 0x7 |
27468 | #define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS__SHIFT 0x8 |
27469 | #define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE__SHIFT 0x9 |
27470 | #define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS__SHIFT 0xa |
27471 | #define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE__SHIFT 0xb |
27472 | #define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS__SHIFT 0xc |
27473 | #define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE__SHIFT 0xd |
27474 | #define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS__SHIFT 0xe |
27475 | #define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE__SHIFT 0xf |
27476 | #define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 |
27477 | #define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 |
27478 | #define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a |
27479 | #define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b |
27480 | #define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c |
27481 | #define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d |
27482 | #define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e |
27483 | #define DIO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x00000003L |
27484 | #define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_DIS_MASK 0x00000010L |
27485 | #define DIO_MEM_PWR_CTRL2__AFMT0_LIGHT_SLEEP_FORCE_MASK 0x00000020L |
27486 | #define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_DIS_MASK 0x00000040L |
27487 | #define DIO_MEM_PWR_CTRL2__AFMT1_LIGHT_SLEEP_FORCE_MASK 0x00000080L |
27488 | #define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_DIS_MASK 0x00000100L |
27489 | #define DIO_MEM_PWR_CTRL2__AFMT2_LIGHT_SLEEP_FORCE_MASK 0x00000200L |
27490 | #define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_DIS_MASK 0x00000400L |
27491 | #define DIO_MEM_PWR_CTRL2__AFMT3_LIGHT_SLEEP_FORCE_MASK 0x00000800L |
27492 | #define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_DIS_MASK 0x00001000L |
27493 | #define DIO_MEM_PWR_CTRL2__AFMT4_LIGHT_SLEEP_FORCE_MASK 0x00002000L |
27494 | #define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_DIS_MASK 0x00004000L |
27495 | #define DIO_MEM_PWR_CTRL2__AFMT5_LIGHT_SLEEP_FORCE_MASK 0x00008000L |
27496 | #define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L |
27497 | #define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L |
27498 | #define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L |
27499 | #define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L |
27500 | #define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L |
27501 | #define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L |
27502 | #define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L |
27503 | //DIO_CLK_CNTL |
27504 | #define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT 0x5 |
27505 | #define DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 |
27506 | #define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 |
27507 | #define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT 0xa |
27508 | #define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 |
27509 | #define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 |
27510 | #define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a |
27511 | #define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b |
27512 | #define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c |
27513 | #define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d |
27514 | #define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e |
27515 | #define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK 0x00000020L |
27516 | #define DIO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L |
27517 | #define DIO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L |
27518 | #define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK 0x00000400L |
27519 | #define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L |
27520 | #define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L |
27521 | #define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L |
27522 | #define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L |
27523 | #define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L |
27524 | #define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L |
27525 | #define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000L |
27526 | //DIO_POWER_MANAGEMENT_CNTL |
27527 | #define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 |
27528 | #define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 |
27529 | #define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L |
27530 | #define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L |
27531 | //DIO_STEREOSYNC_SEL |
27532 | #define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 |
27533 | #define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 |
27534 | #define DIO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L |
27535 | #define DIO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L |
27536 | //DIO_SOFT_RESET |
27537 | #define DIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 |
27538 | #define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 |
27539 | #define DIO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 |
27540 | #define DIO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 |
27541 | #define DIO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc |
27542 | #define DIO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b |
27543 | #define DIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L |
27544 | #define DIO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x00000010L |
27545 | #define DIO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x00000020L |
27546 | #define DIO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x00000040L |
27547 | #define DIO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x00001000L |
27548 | #define DIO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L |
27549 | //DIG_SOFT_RESET |
27550 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 |
27551 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 |
27552 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 |
27553 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 |
27554 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 |
27555 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 |
27556 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc |
27557 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd |
27558 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 |
27559 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 |
27560 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 |
27561 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 |
27562 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 |
27563 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 |
27564 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L |
27565 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L |
27566 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L |
27567 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L |
27568 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L |
27569 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L |
27570 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L |
27571 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L |
27572 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L |
27573 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L |
27574 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L |
27575 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L |
27576 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L |
27577 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L |
27578 | //DIO_MEM_PWR_STATUS1 |
27579 | #define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT 0x0 |
27580 | #define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT 0x2 |
27581 | #define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT 0x4 |
27582 | #define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT 0x6 |
27583 | #define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT 0x8 |
27584 | #define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT 0xa |
27585 | #define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK 0x00000001L |
27586 | #define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK 0x00000004L |
27587 | #define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK 0x00000010L |
27588 | #define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK 0x00000040L |
27589 | #define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK 0x00000100L |
27590 | #define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK 0x00000400L |
27591 | //DIO_CLK_CNTL2 |
27592 | #define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 |
27593 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 |
27594 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 |
27595 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 |
27596 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa |
27597 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb |
27598 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc |
27599 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd |
27600 | #define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 |
27601 | #define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 |
27602 | #define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 |
27603 | #define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 |
27604 | #define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 |
27605 | #define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 |
27606 | #define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 |
27607 | #define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL |
27608 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L |
27609 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L |
27610 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L |
27611 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L |
27612 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L |
27613 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L |
27614 | #define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L |
27615 | #define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L |
27616 | #define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L |
27617 | #define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L |
27618 | #define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L |
27619 | #define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L |
27620 | #define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L |
27621 | #define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L |
27622 | //DIO_CLK_CNTL3 |
27623 | #define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 |
27624 | #define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 |
27625 | #define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 |
27626 | #define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 |
27627 | #define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 |
27628 | #define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 |
27629 | #define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 |
27630 | #define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa |
27631 | #define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb |
27632 | #define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc |
27633 | #define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd |
27634 | #define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe |
27635 | #define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf |
27636 | #define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 |
27637 | #define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L |
27638 | #define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L |
27639 | #define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L |
27640 | #define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L |
27641 | #define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L |
27642 | #define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L |
27643 | #define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L |
27644 | #define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L |
27645 | #define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L |
27646 | #define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L |
27647 | #define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L |
27648 | #define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L |
27649 | #define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L |
27650 | #define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L |
27651 | //DIO_HDMI_RXSTATUS_TIMER_CONTROL |
27652 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 |
27653 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 |
27654 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 |
27655 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc |
27656 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 |
27657 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L |
27658 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L |
27659 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L |
27660 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L |
27661 | #define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L |
27662 | //DIO_PSP_INTERRUPT_STATUS |
27663 | #define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 |
27664 | #define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 |
27665 | #define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L |
27666 | #define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL |
27667 | //DIO_PSP_INTERRUPT_CLEAR |
27668 | #define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 |
27669 | #define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L |
27670 | //DIO_GENERIC_INTERRUPT_MESSAGE |
27671 | #define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 |
27672 | #define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 |
27673 | #define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L |
27674 | #define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL |
27675 | //DIO_GENERIC_INTERRUPT_CLEAR |
27676 | #define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 |
27677 | #define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L |
27678 | |
27679 | |
27680 | // addressBlock: dce_dc_dio_hpd0_dispdec |
27681 | //HPD0_DC_HPD_INT_STATUS |
27682 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27683 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27684 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27685 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27686 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27687 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27688 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27689 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27690 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27691 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27692 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27693 | #define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27694 | //HPD0_DC_HPD_INT_CONTROL |
27695 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27696 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27697 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27698 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27699 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27700 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27701 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27702 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27703 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27704 | #define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27705 | //HPD0_DC_HPD_CONTROL |
27706 | #define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27707 | #define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27708 | #define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27709 | #define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27710 | #define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27711 | #define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27712 | //HPD0_DC_HPD_FAST_TRAIN_CNTL |
27713 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27714 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27715 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27716 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27717 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27718 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27719 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27720 | #define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27721 | //HPD0_DC_HPD_TOGGLE_FILT_CNTL |
27722 | #define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27723 | #define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27724 | #define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27725 | #define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27726 | |
27727 | |
27728 | // addressBlock: dce_dc_dio_hpd1_dispdec |
27729 | //HPD1_DC_HPD_INT_STATUS |
27730 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27731 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27732 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27733 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27734 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27735 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27736 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27737 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27738 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27739 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27740 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27741 | #define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27742 | //HPD1_DC_HPD_INT_CONTROL |
27743 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27744 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27745 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27746 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27747 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27748 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27749 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27750 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27751 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27752 | #define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27753 | //HPD1_DC_HPD_CONTROL |
27754 | #define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27755 | #define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27756 | #define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27757 | #define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27758 | #define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27759 | #define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27760 | //HPD1_DC_HPD_FAST_TRAIN_CNTL |
27761 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27762 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27763 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27764 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27765 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27766 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27767 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27768 | #define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27769 | //HPD1_DC_HPD_TOGGLE_FILT_CNTL |
27770 | #define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27771 | #define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27772 | #define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27773 | #define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27774 | |
27775 | |
27776 | // addressBlock: dce_dc_dio_hpd2_dispdec |
27777 | //HPD2_DC_HPD_INT_STATUS |
27778 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27779 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27780 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27781 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27782 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27783 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27784 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27785 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27786 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27787 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27788 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27789 | #define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27790 | //HPD2_DC_HPD_INT_CONTROL |
27791 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27792 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27793 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27794 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27795 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27796 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27797 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27798 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27799 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27800 | #define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27801 | //HPD2_DC_HPD_CONTROL |
27802 | #define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27803 | #define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27804 | #define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27805 | #define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27806 | #define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27807 | #define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27808 | //HPD2_DC_HPD_FAST_TRAIN_CNTL |
27809 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27810 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27811 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27812 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27813 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27814 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27815 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27816 | #define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27817 | //HPD2_DC_HPD_TOGGLE_FILT_CNTL |
27818 | #define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27819 | #define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27820 | #define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27821 | #define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27822 | |
27823 | |
27824 | // addressBlock: dce_dc_dio_hpd3_dispdec |
27825 | //HPD3_DC_HPD_INT_STATUS |
27826 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27827 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27828 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27829 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27830 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27831 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27832 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27833 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27834 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27835 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27836 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27837 | #define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27838 | //HPD3_DC_HPD_INT_CONTROL |
27839 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27840 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27841 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27842 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27843 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27844 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27845 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27846 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27847 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27848 | #define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27849 | //HPD3_DC_HPD_CONTROL |
27850 | #define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27851 | #define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27852 | #define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27853 | #define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27854 | #define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27855 | #define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27856 | //HPD3_DC_HPD_FAST_TRAIN_CNTL |
27857 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27858 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27859 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27860 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27861 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27862 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27863 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27864 | #define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27865 | //HPD3_DC_HPD_TOGGLE_FILT_CNTL |
27866 | #define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27867 | #define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27868 | #define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27869 | #define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27870 | |
27871 | |
27872 | // addressBlock: dce_dc_dio_hpd4_dispdec |
27873 | //HPD4_DC_HPD_INT_STATUS |
27874 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27875 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27876 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27877 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27878 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27879 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27880 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27881 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27882 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27883 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27884 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27885 | #define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27886 | //HPD4_DC_HPD_INT_CONTROL |
27887 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27888 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27889 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27890 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27891 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27892 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27893 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27894 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27895 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27896 | #define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27897 | //HPD4_DC_HPD_CONTROL |
27898 | #define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27899 | #define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27900 | #define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27901 | #define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27902 | #define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27903 | #define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27904 | //HPD4_DC_HPD_FAST_TRAIN_CNTL |
27905 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27906 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27907 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27908 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27909 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27910 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27911 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27912 | #define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27913 | //HPD4_DC_HPD_TOGGLE_FILT_CNTL |
27914 | #define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27915 | #define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27916 | #define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27917 | #define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27918 | |
27919 | |
27920 | // addressBlock: dce_dc_dio_hpd5_dispdec |
27921 | //HPD5_DC_HPD_INT_STATUS |
27922 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 |
27923 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 |
27924 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 |
27925 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 |
27926 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
27927 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
27928 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L |
27929 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L |
27930 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L |
27931 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L |
27932 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L |
27933 | #define HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L |
27934 | //HPD5_DC_HPD_INT_CONTROL |
27935 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 |
27936 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 |
27937 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 |
27938 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 |
27939 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 |
27940 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L |
27941 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L |
27942 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L |
27943 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L |
27944 | #define HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L |
27945 | //HPD5_DC_HPD_CONTROL |
27946 | #define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 |
27947 | #define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 |
27948 | #define HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c |
27949 | #define HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL |
27950 | #define HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L |
27951 | #define HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L |
27952 | //HPD5_DC_HPD_FAST_TRAIN_CNTL |
27953 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
27954 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
27955 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 |
27956 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
27957 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL |
27958 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L |
27959 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L |
27960 | #define HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L |
27961 | //HPD5_DC_HPD_TOGGLE_FILT_CNTL |
27962 | #define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 |
27963 | #define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 |
27964 | #define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL |
27965 | #define HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L |
27966 | |
27967 | |
27968 | // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec |
27969 | //DC_PERFMON19_PERFCOUNTER_CNTL |
27970 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
27971 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 |
27972 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
27973 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf |
27974 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 |
27975 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 |
27976 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 |
27977 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 |
27978 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 |
27979 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a |
27980 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
27981 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL |
27982 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L |
27983 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L |
27984 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L |
27985 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L |
27986 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L |
27987 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L |
27988 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L |
27989 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L |
27990 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L |
27991 | #define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L |
27992 | //DC_PERFMON19_PERFCOUNTER_CNTL2 |
27993 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 |
27994 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 |
27995 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 |
27996 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 |
27997 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d |
27998 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L |
27999 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L |
28000 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L |
28001 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L |
28002 | #define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L |
28003 | //DC_PERFMON19_PERFCOUNTER_STATE |
28004 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
28005 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
28006 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
28007 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
28008 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
28009 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
28010 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
28011 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
28012 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
28013 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
28014 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
28015 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
28016 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
28017 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
28018 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
28019 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
28020 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L |
28021 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L |
28022 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L |
28023 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L |
28024 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L |
28025 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L |
28026 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L |
28027 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L |
28028 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L |
28029 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L |
28030 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L |
28031 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L |
28032 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L |
28033 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L |
28034 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L |
28035 | #define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L |
28036 | //DC_PERFMON19_PERFMON_CNTL |
28037 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
28038 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
28039 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
28040 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
28041 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
28042 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
28043 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L |
28044 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L |
28045 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L |
28046 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L |
28047 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L |
28048 | #define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L |
28049 | //DC_PERFMON19_PERFMON_CNTL2 |
28050 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 |
28051 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 |
28052 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 |
28053 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa |
28054 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L |
28055 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L |
28056 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL |
28057 | #define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L |
28058 | //DC_PERFMON19_PERFMON_CVALUE_INT_MISC |
28059 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
28060 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
28061 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
28062 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
28063 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
28064 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
28065 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
28066 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
28067 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
28068 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
28069 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
28070 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
28071 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
28072 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
28073 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
28074 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
28075 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
28076 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L |
28077 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L |
28078 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L |
28079 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L |
28080 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L |
28081 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L |
28082 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L |
28083 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L |
28084 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L |
28085 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L |
28086 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L |
28087 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L |
28088 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L |
28089 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L |
28090 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L |
28091 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L |
28092 | #define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L |
28093 | //DC_PERFMON19_PERFMON_CVALUE_LOW |
28094 | #define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
28095 | #define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL |
28096 | //DC_PERFMON19_PERFMON_HI |
28097 | #define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
28098 | #define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
28099 | #define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL |
28100 | #define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L |
28101 | //DC_PERFMON19_PERFMON_LOW |
28102 | #define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
28103 | #define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL |
28104 | |
28105 | |
28106 | // addressBlock: dce_dc_dio_dp_aux0_dispdec |
28107 | //DP_AUX0_AUX_CONTROL |
28108 | #define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
28109 | #define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
28110 | #define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
28111 | #define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
28112 | #define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
28113 | #define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
28114 | #define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
28115 | #define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
28116 | #define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
28117 | #define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
28118 | #define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
28119 | #define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
28120 | #define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
28121 | #define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
28122 | #define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
28123 | #define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
28124 | #define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
28125 | #define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
28126 | #define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
28127 | #define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
28128 | #define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
28129 | #define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
28130 | #define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
28131 | #define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
28132 | #define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
28133 | #define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
28134 | //DP_AUX0_AUX_SW_CONTROL |
28135 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
28136 | #define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
28137 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
28138 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
28139 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
28140 | #define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
28141 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
28142 | #define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
28143 | //DP_AUX0_AUX_ARB_CONTROL |
28144 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
28145 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
28146 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
28147 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
28148 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
28149 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
28150 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
28151 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
28152 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
28153 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
28154 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
28155 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
28156 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
28157 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
28158 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
28159 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
28160 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
28161 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
28162 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
28163 | #define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
28164 | //DP_AUX0_AUX_INTERRUPT_CONTROL |
28165 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
28166 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
28167 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
28168 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
28169 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
28170 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
28171 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
28172 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
28173 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
28174 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
28175 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
28176 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
28177 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
28178 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
28179 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
28180 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
28181 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
28182 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
28183 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
28184 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
28185 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
28186 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
28187 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
28188 | #define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
28189 | //DP_AUX0_AUX_SW_STATUS |
28190 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
28191 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
28192 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
28193 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
28194 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
28195 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
28196 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
28197 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
28198 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28199 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
28200 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
28201 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
28202 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
28203 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
28204 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
28205 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
28206 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
28207 | #define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
28208 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
28209 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
28210 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
28211 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
28212 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
28213 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
28214 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
28215 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
28216 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28217 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
28218 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
28219 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
28220 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
28221 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
28222 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
28223 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
28224 | #define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28225 | #define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
28226 | //DP_AUX0_AUX_LS_STATUS |
28227 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
28228 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
28229 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
28230 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
28231 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
28232 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
28233 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
28234 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
28235 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28236 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
28237 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
28238 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
28239 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
28240 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
28241 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
28242 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
28243 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
28244 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
28245 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
28246 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
28247 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
28248 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
28249 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
28250 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
28251 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
28252 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
28253 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
28254 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
28255 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28256 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
28257 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
28258 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
28259 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
28260 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
28261 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
28262 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
28263 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28264 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
28265 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
28266 | #define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
28267 | //DP_AUX0_AUX_SW_DATA |
28268 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
28269 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
28270 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
28271 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
28272 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
28273 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
28274 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
28275 | #define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
28276 | //DP_AUX0_AUX_LS_DATA |
28277 | #define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
28278 | #define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
28279 | #define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
28280 | #define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
28281 | //DP_AUX0_AUX_DPHY_TX_REF_CONTROL |
28282 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
28283 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
28284 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
28285 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
28286 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
28287 | #define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
28288 | //DP_AUX0_AUX_DPHY_TX_CONTROL |
28289 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
28290 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
28291 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
28292 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
28293 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
28294 | #define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
28295 | //DP_AUX0_AUX_DPHY_RX_CONTROL0 |
28296 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
28297 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
28298 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
28299 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
28300 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
28301 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
28302 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
28303 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
28304 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
28305 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
28306 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
28307 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
28308 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
28309 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
28310 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
28311 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
28312 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
28313 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
28314 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
28315 | #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
28316 | //DP_AUX0_AUX_DPHY_RX_CONTROL1 |
28317 | #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
28318 | #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
28319 | //DP_AUX0_AUX_DPHY_TX_STATUS |
28320 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
28321 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
28322 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
28323 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
28324 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
28325 | #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
28326 | //DP_AUX0_AUX_DPHY_RX_STATUS |
28327 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
28328 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
28329 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
28330 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
28331 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
28332 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
28333 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
28334 | #define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
28335 | //DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL |
28336 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
28337 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
28338 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
28339 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
28340 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
28341 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
28342 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
28343 | #define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
28344 | //DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS |
28345 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
28346 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
28347 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
28348 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
28349 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
28350 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
28351 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
28352 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
28353 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
28354 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
28355 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
28356 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
28357 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
28358 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
28359 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
28360 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
28361 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
28362 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
28363 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
28364 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
28365 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
28366 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
28367 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
28368 | #define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
28369 | //DP_AUX0_AUX_GTC_SYNC_STATUS |
28370 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
28371 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
28372 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
28373 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
28374 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
28375 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
28376 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
28377 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
28378 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28379 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
28380 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
28381 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
28382 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
28383 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
28384 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
28385 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
28386 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
28387 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
28388 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
28389 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
28390 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
28391 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
28392 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
28393 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
28394 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
28395 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
28396 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
28397 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28398 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
28399 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
28400 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
28401 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
28402 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
28403 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
28404 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
28405 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28406 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
28407 | #define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
28408 | |
28409 | |
28410 | // addressBlock: dce_dc_dio_dp_aux1_dispdec |
28411 | //DP_AUX1_AUX_CONTROL |
28412 | #define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
28413 | #define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
28414 | #define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
28415 | #define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
28416 | #define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
28417 | #define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
28418 | #define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
28419 | #define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
28420 | #define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
28421 | #define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
28422 | #define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
28423 | #define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
28424 | #define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
28425 | #define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
28426 | #define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
28427 | #define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
28428 | #define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
28429 | #define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
28430 | #define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
28431 | #define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
28432 | #define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
28433 | #define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
28434 | #define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
28435 | #define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
28436 | #define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
28437 | #define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
28438 | //DP_AUX1_AUX_SW_CONTROL |
28439 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
28440 | #define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
28441 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
28442 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
28443 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
28444 | #define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
28445 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
28446 | #define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
28447 | //DP_AUX1_AUX_ARB_CONTROL |
28448 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
28449 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
28450 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
28451 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
28452 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
28453 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
28454 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
28455 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
28456 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
28457 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
28458 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
28459 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
28460 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
28461 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
28462 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
28463 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
28464 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
28465 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
28466 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
28467 | #define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
28468 | //DP_AUX1_AUX_INTERRUPT_CONTROL |
28469 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
28470 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
28471 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
28472 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
28473 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
28474 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
28475 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
28476 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
28477 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
28478 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
28479 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
28480 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
28481 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
28482 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
28483 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
28484 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
28485 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
28486 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
28487 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
28488 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
28489 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
28490 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
28491 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
28492 | #define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
28493 | //DP_AUX1_AUX_SW_STATUS |
28494 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
28495 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
28496 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
28497 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
28498 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
28499 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
28500 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
28501 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
28502 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28503 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
28504 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
28505 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
28506 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
28507 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
28508 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
28509 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
28510 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
28511 | #define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
28512 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
28513 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
28514 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
28515 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
28516 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
28517 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
28518 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
28519 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
28520 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28521 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
28522 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
28523 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
28524 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
28525 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
28526 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
28527 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
28528 | #define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28529 | #define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
28530 | //DP_AUX1_AUX_LS_STATUS |
28531 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
28532 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
28533 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
28534 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
28535 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
28536 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
28537 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
28538 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
28539 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28540 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
28541 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
28542 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
28543 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
28544 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
28545 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
28546 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
28547 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
28548 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
28549 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
28550 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
28551 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
28552 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
28553 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
28554 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
28555 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
28556 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
28557 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
28558 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
28559 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28560 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
28561 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
28562 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
28563 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
28564 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
28565 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
28566 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
28567 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28568 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
28569 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
28570 | #define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
28571 | //DP_AUX1_AUX_SW_DATA |
28572 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
28573 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
28574 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
28575 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
28576 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
28577 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
28578 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
28579 | #define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
28580 | //DP_AUX1_AUX_LS_DATA |
28581 | #define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
28582 | #define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
28583 | #define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
28584 | #define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
28585 | //DP_AUX1_AUX_DPHY_TX_REF_CONTROL |
28586 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
28587 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
28588 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
28589 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
28590 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
28591 | #define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
28592 | //DP_AUX1_AUX_DPHY_TX_CONTROL |
28593 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
28594 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
28595 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
28596 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
28597 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
28598 | #define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
28599 | //DP_AUX1_AUX_DPHY_RX_CONTROL0 |
28600 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
28601 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
28602 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
28603 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
28604 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
28605 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
28606 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
28607 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
28608 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
28609 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
28610 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
28611 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
28612 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
28613 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
28614 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
28615 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
28616 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
28617 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
28618 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
28619 | #define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
28620 | //DP_AUX1_AUX_DPHY_RX_CONTROL1 |
28621 | #define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
28622 | #define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
28623 | //DP_AUX1_AUX_DPHY_TX_STATUS |
28624 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
28625 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
28626 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
28627 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
28628 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
28629 | #define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
28630 | //DP_AUX1_AUX_DPHY_RX_STATUS |
28631 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
28632 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
28633 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
28634 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
28635 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
28636 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
28637 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
28638 | #define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
28639 | //DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL |
28640 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
28641 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
28642 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
28643 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
28644 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
28645 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
28646 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
28647 | #define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
28648 | //DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS |
28649 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
28650 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
28651 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
28652 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
28653 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
28654 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
28655 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
28656 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
28657 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
28658 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
28659 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
28660 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
28661 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
28662 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
28663 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
28664 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
28665 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
28666 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
28667 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
28668 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
28669 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
28670 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
28671 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
28672 | #define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
28673 | //DP_AUX1_AUX_GTC_SYNC_STATUS |
28674 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
28675 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
28676 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
28677 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
28678 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
28679 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
28680 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
28681 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
28682 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28683 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
28684 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
28685 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
28686 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
28687 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
28688 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
28689 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
28690 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
28691 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
28692 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
28693 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
28694 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
28695 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
28696 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
28697 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
28698 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
28699 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
28700 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
28701 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28702 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
28703 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
28704 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
28705 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
28706 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
28707 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
28708 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
28709 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28710 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
28711 | #define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
28712 | |
28713 | |
28714 | // addressBlock: dce_dc_dio_dp_aux2_dispdec |
28715 | //DP_AUX2_AUX_CONTROL |
28716 | #define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
28717 | #define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
28718 | #define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
28719 | #define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
28720 | #define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
28721 | #define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
28722 | #define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
28723 | #define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
28724 | #define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
28725 | #define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
28726 | #define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
28727 | #define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
28728 | #define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
28729 | #define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
28730 | #define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
28731 | #define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
28732 | #define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
28733 | #define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
28734 | #define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
28735 | #define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
28736 | #define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
28737 | #define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
28738 | #define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
28739 | #define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
28740 | #define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
28741 | #define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
28742 | //DP_AUX2_AUX_SW_CONTROL |
28743 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
28744 | #define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
28745 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
28746 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
28747 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
28748 | #define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
28749 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
28750 | #define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
28751 | //DP_AUX2_AUX_ARB_CONTROL |
28752 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
28753 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
28754 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
28755 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
28756 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
28757 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
28758 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
28759 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
28760 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
28761 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
28762 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
28763 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
28764 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
28765 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
28766 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
28767 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
28768 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
28769 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
28770 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
28771 | #define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
28772 | //DP_AUX2_AUX_INTERRUPT_CONTROL |
28773 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
28774 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
28775 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
28776 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
28777 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
28778 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
28779 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
28780 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
28781 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
28782 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
28783 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
28784 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
28785 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
28786 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
28787 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
28788 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
28789 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
28790 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
28791 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
28792 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
28793 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
28794 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
28795 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
28796 | #define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
28797 | //DP_AUX2_AUX_SW_STATUS |
28798 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
28799 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
28800 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
28801 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
28802 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
28803 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
28804 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
28805 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
28806 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28807 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
28808 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
28809 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
28810 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
28811 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
28812 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
28813 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
28814 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
28815 | #define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
28816 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
28817 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
28818 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
28819 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
28820 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
28821 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
28822 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
28823 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
28824 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28825 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
28826 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
28827 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
28828 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
28829 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
28830 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
28831 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
28832 | #define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28833 | #define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
28834 | //DP_AUX2_AUX_LS_STATUS |
28835 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
28836 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
28837 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
28838 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
28839 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
28840 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
28841 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
28842 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
28843 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28844 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
28845 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
28846 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
28847 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
28848 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
28849 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
28850 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
28851 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
28852 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
28853 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
28854 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
28855 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
28856 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
28857 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
28858 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
28859 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
28860 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
28861 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
28862 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
28863 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
28864 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
28865 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
28866 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
28867 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
28868 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
28869 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
28870 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
28871 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
28872 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
28873 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
28874 | #define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
28875 | //DP_AUX2_AUX_SW_DATA |
28876 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
28877 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
28878 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
28879 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
28880 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
28881 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
28882 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
28883 | #define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
28884 | //DP_AUX2_AUX_LS_DATA |
28885 | #define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
28886 | #define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
28887 | #define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
28888 | #define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
28889 | //DP_AUX2_AUX_DPHY_TX_REF_CONTROL |
28890 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
28891 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
28892 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
28893 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
28894 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
28895 | #define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
28896 | //DP_AUX2_AUX_DPHY_TX_CONTROL |
28897 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
28898 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
28899 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
28900 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
28901 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
28902 | #define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
28903 | //DP_AUX2_AUX_DPHY_RX_CONTROL0 |
28904 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
28905 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
28906 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
28907 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
28908 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
28909 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
28910 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
28911 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
28912 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
28913 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
28914 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
28915 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
28916 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
28917 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
28918 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
28919 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
28920 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
28921 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
28922 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
28923 | #define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
28924 | //DP_AUX2_AUX_DPHY_RX_CONTROL1 |
28925 | #define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
28926 | #define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
28927 | //DP_AUX2_AUX_DPHY_TX_STATUS |
28928 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
28929 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
28930 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
28931 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
28932 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
28933 | #define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
28934 | //DP_AUX2_AUX_DPHY_RX_STATUS |
28935 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
28936 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
28937 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
28938 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
28939 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
28940 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
28941 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
28942 | #define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
28943 | //DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL |
28944 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
28945 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
28946 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
28947 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
28948 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
28949 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
28950 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
28951 | #define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
28952 | //DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS |
28953 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
28954 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
28955 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
28956 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
28957 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
28958 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
28959 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
28960 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
28961 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
28962 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
28963 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
28964 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
28965 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
28966 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
28967 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
28968 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
28969 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
28970 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
28971 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
28972 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
28973 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
28974 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
28975 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
28976 | #define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
28977 | //DP_AUX2_AUX_GTC_SYNC_STATUS |
28978 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
28979 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
28980 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
28981 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
28982 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
28983 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
28984 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
28985 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
28986 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
28987 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
28988 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
28989 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
28990 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
28991 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
28992 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
28993 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
28994 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
28995 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
28996 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
28997 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
28998 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
28999 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
29000 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
29001 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
29002 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
29003 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
29004 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
29005 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29006 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
29007 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
29008 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
29009 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
29010 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
29011 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
29012 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
29013 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29014 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
29015 | #define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
29016 | |
29017 | |
29018 | // addressBlock: dce_dc_dio_dp_aux3_dispdec |
29019 | //DP_AUX3_AUX_CONTROL |
29020 | #define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
29021 | #define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
29022 | #define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
29023 | #define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
29024 | #define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
29025 | #define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
29026 | #define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
29027 | #define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
29028 | #define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
29029 | #define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
29030 | #define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
29031 | #define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
29032 | #define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
29033 | #define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
29034 | #define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
29035 | #define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
29036 | #define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
29037 | #define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
29038 | #define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
29039 | #define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
29040 | #define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
29041 | #define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
29042 | #define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
29043 | #define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
29044 | #define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
29045 | #define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
29046 | //DP_AUX3_AUX_SW_CONTROL |
29047 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
29048 | #define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
29049 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
29050 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
29051 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
29052 | #define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
29053 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
29054 | #define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
29055 | //DP_AUX3_AUX_ARB_CONTROL |
29056 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
29057 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
29058 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
29059 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
29060 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
29061 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
29062 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
29063 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
29064 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
29065 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
29066 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
29067 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
29068 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
29069 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
29070 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
29071 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
29072 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
29073 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
29074 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
29075 | #define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
29076 | //DP_AUX3_AUX_INTERRUPT_CONTROL |
29077 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
29078 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
29079 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
29080 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
29081 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
29082 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
29083 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
29084 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
29085 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
29086 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
29087 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
29088 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
29089 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
29090 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
29091 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
29092 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
29093 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
29094 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
29095 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
29096 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
29097 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
29098 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
29099 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
29100 | #define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
29101 | //DP_AUX3_AUX_SW_STATUS |
29102 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
29103 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
29104 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
29105 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
29106 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
29107 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
29108 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
29109 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
29110 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29111 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
29112 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
29113 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
29114 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
29115 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
29116 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
29117 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
29118 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
29119 | #define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
29120 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
29121 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
29122 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
29123 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
29124 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
29125 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
29126 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
29127 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
29128 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29129 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
29130 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
29131 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
29132 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
29133 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
29134 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
29135 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
29136 | #define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29137 | #define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
29138 | //DP_AUX3_AUX_LS_STATUS |
29139 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
29140 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
29141 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
29142 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
29143 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
29144 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
29145 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
29146 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
29147 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29148 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
29149 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
29150 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
29151 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
29152 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
29153 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
29154 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
29155 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
29156 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
29157 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
29158 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
29159 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
29160 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
29161 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
29162 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
29163 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
29164 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
29165 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
29166 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
29167 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29168 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
29169 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
29170 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
29171 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
29172 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
29173 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
29174 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
29175 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29176 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
29177 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
29178 | #define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
29179 | //DP_AUX3_AUX_SW_DATA |
29180 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
29181 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
29182 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
29183 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
29184 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
29185 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
29186 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
29187 | #define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
29188 | //DP_AUX3_AUX_LS_DATA |
29189 | #define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
29190 | #define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
29191 | #define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
29192 | #define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
29193 | //DP_AUX3_AUX_DPHY_TX_REF_CONTROL |
29194 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
29195 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
29196 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
29197 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
29198 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
29199 | #define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
29200 | //DP_AUX3_AUX_DPHY_TX_CONTROL |
29201 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
29202 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
29203 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
29204 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
29205 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
29206 | #define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
29207 | //DP_AUX3_AUX_DPHY_RX_CONTROL0 |
29208 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
29209 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
29210 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
29211 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
29212 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
29213 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
29214 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
29215 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
29216 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
29217 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
29218 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
29219 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
29220 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
29221 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
29222 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
29223 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
29224 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
29225 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
29226 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
29227 | #define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
29228 | //DP_AUX3_AUX_DPHY_RX_CONTROL1 |
29229 | #define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
29230 | #define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
29231 | //DP_AUX3_AUX_DPHY_TX_STATUS |
29232 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
29233 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
29234 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
29235 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
29236 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
29237 | #define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
29238 | //DP_AUX3_AUX_DPHY_RX_STATUS |
29239 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
29240 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
29241 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
29242 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
29243 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
29244 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
29245 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
29246 | #define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
29247 | //DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL |
29248 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
29249 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
29250 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
29251 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
29252 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
29253 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
29254 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
29255 | #define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
29256 | //DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS |
29257 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
29258 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
29259 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
29260 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
29261 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
29262 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
29263 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
29264 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
29265 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
29266 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
29267 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
29268 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
29269 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
29270 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
29271 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
29272 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
29273 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
29274 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
29275 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
29276 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
29277 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
29278 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
29279 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
29280 | #define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
29281 | //DP_AUX3_AUX_GTC_SYNC_STATUS |
29282 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
29283 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
29284 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
29285 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
29286 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
29287 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
29288 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
29289 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
29290 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29291 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
29292 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
29293 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
29294 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
29295 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
29296 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
29297 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
29298 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
29299 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
29300 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
29301 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
29302 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
29303 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
29304 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
29305 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
29306 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
29307 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
29308 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
29309 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29310 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
29311 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
29312 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
29313 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
29314 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
29315 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
29316 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
29317 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29318 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
29319 | #define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
29320 | |
29321 | |
29322 | // addressBlock: dce_dc_dio_dp_aux4_dispdec |
29323 | //DP_AUX4_AUX_CONTROL |
29324 | #define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
29325 | #define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
29326 | #define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
29327 | #define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
29328 | #define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
29329 | #define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
29330 | #define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
29331 | #define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
29332 | #define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
29333 | #define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
29334 | #define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
29335 | #define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
29336 | #define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
29337 | #define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
29338 | #define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
29339 | #define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
29340 | #define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
29341 | #define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
29342 | #define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
29343 | #define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
29344 | #define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
29345 | #define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
29346 | #define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
29347 | #define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
29348 | #define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
29349 | #define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
29350 | //DP_AUX4_AUX_SW_CONTROL |
29351 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
29352 | #define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
29353 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
29354 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
29355 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
29356 | #define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
29357 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
29358 | #define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
29359 | //DP_AUX4_AUX_ARB_CONTROL |
29360 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
29361 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
29362 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
29363 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
29364 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
29365 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
29366 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
29367 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
29368 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
29369 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
29370 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
29371 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
29372 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
29373 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
29374 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
29375 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
29376 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
29377 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
29378 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
29379 | #define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
29380 | //DP_AUX4_AUX_INTERRUPT_CONTROL |
29381 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
29382 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
29383 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
29384 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
29385 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
29386 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
29387 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
29388 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
29389 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
29390 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
29391 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
29392 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
29393 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
29394 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
29395 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
29396 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
29397 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
29398 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
29399 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
29400 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
29401 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
29402 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
29403 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
29404 | #define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
29405 | //DP_AUX4_AUX_SW_STATUS |
29406 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
29407 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
29408 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
29409 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
29410 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
29411 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
29412 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
29413 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
29414 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29415 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
29416 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
29417 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
29418 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
29419 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
29420 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
29421 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
29422 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
29423 | #define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
29424 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
29425 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
29426 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
29427 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
29428 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
29429 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
29430 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
29431 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
29432 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29433 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
29434 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
29435 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
29436 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
29437 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
29438 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
29439 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
29440 | #define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29441 | #define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
29442 | //DP_AUX4_AUX_LS_STATUS |
29443 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
29444 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
29445 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
29446 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
29447 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
29448 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
29449 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
29450 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
29451 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29452 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
29453 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
29454 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
29455 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
29456 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
29457 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
29458 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
29459 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
29460 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
29461 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
29462 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
29463 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
29464 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
29465 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
29466 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
29467 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
29468 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
29469 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
29470 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
29471 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29472 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
29473 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
29474 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
29475 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
29476 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
29477 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
29478 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
29479 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29480 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
29481 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
29482 | #define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
29483 | //DP_AUX4_AUX_SW_DATA |
29484 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
29485 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
29486 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
29487 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
29488 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
29489 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
29490 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
29491 | #define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
29492 | //DP_AUX4_AUX_LS_DATA |
29493 | #define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
29494 | #define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
29495 | #define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
29496 | #define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
29497 | //DP_AUX4_AUX_DPHY_TX_REF_CONTROL |
29498 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
29499 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
29500 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
29501 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
29502 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
29503 | #define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
29504 | //DP_AUX4_AUX_DPHY_TX_CONTROL |
29505 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
29506 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
29507 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
29508 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
29509 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
29510 | #define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
29511 | //DP_AUX4_AUX_DPHY_RX_CONTROL0 |
29512 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
29513 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
29514 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
29515 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
29516 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
29517 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
29518 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
29519 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
29520 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
29521 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
29522 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
29523 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
29524 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
29525 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
29526 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
29527 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
29528 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
29529 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
29530 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
29531 | #define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
29532 | //DP_AUX4_AUX_DPHY_RX_CONTROL1 |
29533 | #define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
29534 | #define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
29535 | //DP_AUX4_AUX_DPHY_TX_STATUS |
29536 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
29537 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
29538 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
29539 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
29540 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
29541 | #define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
29542 | //DP_AUX4_AUX_DPHY_RX_STATUS |
29543 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
29544 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
29545 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
29546 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
29547 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
29548 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
29549 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
29550 | #define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
29551 | //DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL |
29552 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
29553 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
29554 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
29555 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
29556 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
29557 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
29558 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
29559 | #define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
29560 | //DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS |
29561 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
29562 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
29563 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
29564 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
29565 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
29566 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
29567 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
29568 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
29569 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
29570 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
29571 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
29572 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
29573 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
29574 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
29575 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
29576 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
29577 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
29578 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
29579 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
29580 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
29581 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
29582 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
29583 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
29584 | #define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
29585 | //DP_AUX4_AUX_GTC_SYNC_STATUS |
29586 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
29587 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
29588 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
29589 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
29590 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
29591 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
29592 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
29593 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
29594 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29595 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
29596 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
29597 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
29598 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
29599 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
29600 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
29601 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
29602 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
29603 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
29604 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
29605 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
29606 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
29607 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
29608 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
29609 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
29610 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
29611 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
29612 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
29613 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29614 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
29615 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
29616 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
29617 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
29618 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
29619 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
29620 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
29621 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29622 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
29623 | #define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
29624 | |
29625 | |
29626 | // addressBlock: dce_dc_dio_dp_aux5_dispdec |
29627 | //DP_AUX5_AUX_CONTROL |
29628 | #define DP_AUX5_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
29629 | #define DP_AUX5_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
29630 | #define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
29631 | #define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
29632 | #define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
29633 | #define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
29634 | #define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
29635 | #define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
29636 | #define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
29637 | #define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
29638 | #define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
29639 | #define DP_AUX5_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
29640 | #define DP_AUX5_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
29641 | #define DP_AUX5_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
29642 | #define DP_AUX5_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
29643 | #define DP_AUX5_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
29644 | #define DP_AUX5_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
29645 | #define DP_AUX5_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
29646 | #define DP_AUX5_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
29647 | #define DP_AUX5_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
29648 | #define DP_AUX5_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
29649 | #define DP_AUX5_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
29650 | #define DP_AUX5_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
29651 | #define DP_AUX5_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
29652 | #define DP_AUX5_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
29653 | #define DP_AUX5_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
29654 | //DP_AUX5_AUX_SW_CONTROL |
29655 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
29656 | #define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
29657 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
29658 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
29659 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
29660 | #define DP_AUX5_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
29661 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
29662 | #define DP_AUX5_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
29663 | //DP_AUX5_AUX_ARB_CONTROL |
29664 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
29665 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
29666 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
29667 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
29668 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
29669 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
29670 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
29671 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
29672 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
29673 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
29674 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
29675 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
29676 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
29677 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
29678 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
29679 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
29680 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
29681 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
29682 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
29683 | #define DP_AUX5_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
29684 | //DP_AUX5_AUX_INTERRUPT_CONTROL |
29685 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
29686 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
29687 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
29688 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
29689 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
29690 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
29691 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
29692 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
29693 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
29694 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
29695 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
29696 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
29697 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
29698 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
29699 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
29700 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
29701 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
29702 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
29703 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
29704 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
29705 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
29706 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
29707 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
29708 | #define DP_AUX5_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
29709 | //DP_AUX5_AUX_SW_STATUS |
29710 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
29711 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
29712 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
29713 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
29714 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
29715 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
29716 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
29717 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
29718 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29719 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
29720 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
29721 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
29722 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
29723 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
29724 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
29725 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
29726 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
29727 | #define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
29728 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
29729 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
29730 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
29731 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
29732 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
29733 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
29734 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
29735 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
29736 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29737 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
29738 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
29739 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
29740 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
29741 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
29742 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
29743 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
29744 | #define DP_AUX5_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29745 | #define DP_AUX5_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
29746 | //DP_AUX5_AUX_LS_STATUS |
29747 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
29748 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
29749 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
29750 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
29751 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
29752 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
29753 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
29754 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
29755 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29756 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
29757 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
29758 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
29759 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
29760 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
29761 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
29762 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
29763 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
29764 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
29765 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
29766 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
29767 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
29768 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
29769 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
29770 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
29771 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
29772 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
29773 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
29774 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
29775 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29776 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
29777 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
29778 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
29779 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
29780 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
29781 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
29782 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
29783 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29784 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
29785 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
29786 | #define DP_AUX5_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
29787 | //DP_AUX5_AUX_SW_DATA |
29788 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
29789 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
29790 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
29791 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
29792 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
29793 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
29794 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
29795 | #define DP_AUX5_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
29796 | //DP_AUX5_AUX_LS_DATA |
29797 | #define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
29798 | #define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
29799 | #define DP_AUX5_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
29800 | #define DP_AUX5_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
29801 | //DP_AUX5_AUX_DPHY_TX_REF_CONTROL |
29802 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
29803 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
29804 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
29805 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
29806 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
29807 | #define DP_AUX5_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
29808 | //DP_AUX5_AUX_DPHY_TX_CONTROL |
29809 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
29810 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
29811 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
29812 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
29813 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
29814 | #define DP_AUX5_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
29815 | //DP_AUX5_AUX_DPHY_RX_CONTROL0 |
29816 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
29817 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
29818 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
29819 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
29820 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
29821 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
29822 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
29823 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
29824 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
29825 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
29826 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
29827 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
29828 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
29829 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
29830 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
29831 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
29832 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
29833 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
29834 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
29835 | #define DP_AUX5_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
29836 | //DP_AUX5_AUX_DPHY_RX_CONTROL1 |
29837 | #define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
29838 | #define DP_AUX5_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
29839 | //DP_AUX5_AUX_DPHY_TX_STATUS |
29840 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
29841 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
29842 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
29843 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
29844 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
29845 | #define DP_AUX5_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
29846 | //DP_AUX5_AUX_DPHY_RX_STATUS |
29847 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
29848 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
29849 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
29850 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
29851 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
29852 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
29853 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
29854 | #define DP_AUX5_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
29855 | //DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL |
29856 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
29857 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
29858 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
29859 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
29860 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
29861 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
29862 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
29863 | #define DP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
29864 | //DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS |
29865 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
29866 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
29867 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
29868 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
29869 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
29870 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
29871 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
29872 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
29873 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
29874 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
29875 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
29876 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
29877 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
29878 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
29879 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
29880 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
29881 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
29882 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
29883 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
29884 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
29885 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
29886 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
29887 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
29888 | #define DP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
29889 | //DP_AUX5_AUX_GTC_SYNC_STATUS |
29890 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
29891 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
29892 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
29893 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
29894 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
29895 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
29896 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
29897 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
29898 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
29899 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
29900 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
29901 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
29902 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
29903 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
29904 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
29905 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
29906 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
29907 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
29908 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
29909 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
29910 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
29911 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
29912 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
29913 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
29914 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
29915 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
29916 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
29917 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
29918 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
29919 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
29920 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
29921 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
29922 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
29923 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
29924 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
29925 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
29926 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
29927 | #define DP_AUX5_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
29928 | |
29929 | |
29930 | // addressBlock: dce_dc_dio_dp_aux6_dispdec |
29931 | //DP_AUX6_AUX_CONTROL |
29932 | #define DP_AUX6_AUX_CONTROL__AUX_EN__SHIFT 0x0 |
29933 | #define DP_AUX6_AUX_CONTROL__AUX_RESET__SHIFT 0x4 |
29934 | #define DP_AUX6_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 |
29935 | #define DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
29936 | #define DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
29937 | #define DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
29938 | #define DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
29939 | #define DP_AUX6_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
29940 | #define DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
29941 | #define DP_AUX6_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
29942 | #define DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
29943 | #define DP_AUX6_AUX_CONTROL__SPARE_0__SHIFT 0x1e |
29944 | #define DP_AUX6_AUX_CONTROL__SPARE_1__SHIFT 0x1f |
29945 | #define DP_AUX6_AUX_CONTROL__AUX_EN_MASK 0x00000001L |
29946 | #define DP_AUX6_AUX_CONTROL__AUX_RESET_MASK 0x00000010L |
29947 | #define DP_AUX6_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L |
29948 | #define DP_AUX6_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L |
29949 | #define DP_AUX6_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L |
29950 | #define DP_AUX6_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L |
29951 | #define DP_AUX6_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L |
29952 | #define DP_AUX6_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L |
29953 | #define DP_AUX6_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L |
29954 | #define DP_AUX6_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L |
29955 | #define DP_AUX6_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L |
29956 | #define DP_AUX6_AUX_CONTROL__SPARE_0_MASK 0x40000000L |
29957 | #define DP_AUX6_AUX_CONTROL__SPARE_1_MASK 0x80000000L |
29958 | //DP_AUX6_AUX_SW_CONTROL |
29959 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
29960 | #define DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
29961 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
29962 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
29963 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L |
29964 | #define DP_AUX6_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L |
29965 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L |
29966 | #define DP_AUX6_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L |
29967 | //DP_AUX6_AUX_ARB_CONTROL |
29968 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
29969 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
29970 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
29971 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
29972 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
29973 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
29974 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
29975 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
29976 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
29977 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
29978 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L |
29979 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL |
29980 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L |
29981 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L |
29982 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L |
29983 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L |
29984 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L |
29985 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L |
29986 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L |
29987 | #define DP_AUX6_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L |
29988 | //DP_AUX6_AUX_INTERRUPT_CONTROL |
29989 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
29990 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
29991 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
29992 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
29993 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
29994 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
29995 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
29996 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
29997 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
29998 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
29999 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
30000 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
30001 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L |
30002 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L |
30003 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L |
30004 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L |
30005 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L |
30006 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L |
30007 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L |
30008 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L |
30009 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L |
30010 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L |
30011 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L |
30012 | #define DP_AUX6_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L |
30013 | //DP_AUX6_AUX_SW_STATUS |
30014 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
30015 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
30016 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
30017 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
30018 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
30019 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
30020 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
30021 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
30022 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
30023 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
30024 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
30025 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
30026 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
30027 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
30028 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
30029 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
30030 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
30031 | #define DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
30032 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L |
30033 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L |
30034 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L |
30035 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L |
30036 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L |
30037 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L |
30038 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L |
30039 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L |
30040 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
30041 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L |
30042 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L |
30043 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L |
30044 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L |
30045 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L |
30046 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L |
30047 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L |
30048 | #define DP_AUX6_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L |
30049 | #define DP_AUX6_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xC0000000L |
30050 | //DP_AUX6_AUX_LS_STATUS |
30051 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
30052 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
30053 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
30054 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
30055 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
30056 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
30057 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
30058 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
30059 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
30060 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
30061 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
30062 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
30063 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
30064 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
30065 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
30066 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
30067 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
30068 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
30069 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
30070 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
30071 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L |
30072 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L |
30073 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L |
30074 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L |
30075 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L |
30076 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L |
30077 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L |
30078 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L |
30079 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
30080 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L |
30081 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L |
30082 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L |
30083 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L |
30084 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L |
30085 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L |
30086 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L |
30087 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L |
30088 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L |
30089 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L |
30090 | #define DP_AUX6_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L |
30091 | //DP_AUX6_AUX_SW_DATA |
30092 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
30093 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
30094 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
30095 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
30096 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L |
30097 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L |
30098 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L |
30099 | #define DP_AUX6_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L |
30100 | //DP_AUX6_AUX_LS_DATA |
30101 | #define DP_AUX6_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
30102 | #define DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
30103 | #define DP_AUX6_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L |
30104 | #define DP_AUX6_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L |
30105 | //DP_AUX6_AUX_DPHY_TX_REF_CONTROL |
30106 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
30107 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
30108 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
30109 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L |
30110 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L |
30111 | #define DP_AUX6_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L |
30112 | //DP_AUX6_AUX_DPHY_TX_CONTROL |
30113 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
30114 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
30115 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
30116 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L |
30117 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L |
30118 | #define DP_AUX6_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L |
30119 | //DP_AUX6_AUX_DPHY_RX_CONTROL0 |
30120 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
30121 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
30122 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
30123 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
30124 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
30125 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
30126 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
30127 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
30128 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
30129 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
30130 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L |
30131 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L |
30132 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L |
30133 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L |
30134 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L |
30135 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L |
30136 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L |
30137 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L |
30138 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L |
30139 | #define DP_AUX6_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L |
30140 | //DP_AUX6_AUX_DPHY_RX_CONTROL1 |
30141 | #define DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
30142 | #define DP_AUX6_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL |
30143 | //DP_AUX6_AUX_DPHY_TX_STATUS |
30144 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
30145 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
30146 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
30147 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L |
30148 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L |
30149 | #define DP_AUX6_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L |
30150 | //DP_AUX6_AUX_DPHY_RX_STATUS |
30151 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
30152 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
30153 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
30154 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
30155 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L |
30156 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L |
30157 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L |
30158 | #define DP_AUX6_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L |
30159 | //DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL |
30160 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
30161 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
30162 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
30163 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
30164 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL |
30165 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L |
30166 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L |
30167 | #define DP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L |
30168 | //DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS |
30169 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
30170 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
30171 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
30172 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
30173 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
30174 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
30175 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
30176 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
30177 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
30178 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
30179 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
30180 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
30181 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L |
30182 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L |
30183 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L |
30184 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L |
30185 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L |
30186 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L |
30187 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L |
30188 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L |
30189 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L |
30190 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L |
30191 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L |
30192 | #define DP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L |
30193 | //DP_AUX6_AUX_GTC_SYNC_STATUS |
30194 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
30195 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
30196 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
30197 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
30198 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
30199 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
30200 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
30201 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
30202 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
30203 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
30204 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
30205 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
30206 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
30207 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
30208 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
30209 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
30210 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
30211 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
30212 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
30213 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L |
30214 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L |
30215 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L |
30216 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L |
30217 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L |
30218 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L |
30219 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L |
30220 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L |
30221 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L |
30222 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L |
30223 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L |
30224 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L |
30225 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L |
30226 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L |
30227 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L |
30228 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L |
30229 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L |
30230 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L |
30231 | #define DP_AUX6_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L |
30232 | |
30233 | |
30234 | // addressBlock: dce_dc_dio_dig0_dispdec |
30235 | //DIG0_DIG_FE_CNTL |
30236 | #define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
30237 | #define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
30238 | #define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
30239 | #define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
30240 | #define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
30241 | #define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
30242 | #define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
30243 | #define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
30244 | #define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
30245 | #define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
30246 | #define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
30247 | #define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
30248 | #define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
30249 | #define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
30250 | #define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
30251 | #define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
30252 | //DIG0_DIG_OUTPUT_CRC_CNTL |
30253 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
30254 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
30255 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
30256 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
30257 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
30258 | #define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
30259 | //DIG0_DIG_OUTPUT_CRC_RESULT |
30260 | #define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
30261 | #define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
30262 | //DIG0_DIG_CLOCK_PATTERN |
30263 | #define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
30264 | #define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
30265 | //DIG0_DIG_TEST_PATTERN |
30266 | #define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
30267 | #define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
30268 | #define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
30269 | #define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
30270 | #define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
30271 | #define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
30272 | #define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
30273 | #define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
30274 | #define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
30275 | #define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
30276 | #define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
30277 | #define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
30278 | //DIG0_DIG_RANDOM_PATTERN_SEED |
30279 | #define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
30280 | #define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
30281 | #define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
30282 | #define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
30283 | //DIG0_DIG_FIFO_STATUS |
30284 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
30285 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
30286 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
30287 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
30288 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
30289 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
30290 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
30291 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
30292 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
30293 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
30294 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
30295 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
30296 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
30297 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
30298 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
30299 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
30300 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
30301 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
30302 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
30303 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
30304 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
30305 | #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
30306 | //DIG0_HDMI_CONTROL |
30307 | #define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
30308 | #define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
30309 | #define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
30310 | #define 0x3 |
30311 | #define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
30312 | #define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
30313 | #define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
30314 | #define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
30315 | #define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
30316 | #define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
30317 | #define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
30318 | #define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
30319 | #define 0x00000008L |
30320 | #define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
30321 | #define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
30322 | #define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
30323 | #define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
30324 | #define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
30325 | //DIG0_HDMI_STATUS |
30326 | #define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
30327 | #define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
30328 | #define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
30329 | #define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
30330 | #define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
30331 | #define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
30332 | #define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
30333 | #define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
30334 | //DIG0_HDMI_AUDIO_PACKET_CONTROL |
30335 | #define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
30336 | #define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
30337 | #define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
30338 | #define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
30339 | //DIG0_HDMI_ACR_PACKET_CONTROL |
30340 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
30341 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
30342 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
30343 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
30344 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
30345 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
30346 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
30347 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
30348 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
30349 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
30350 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
30351 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
30352 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
30353 | #define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
30354 | //DIG0_HDMI_VBI_PACKET_CONTROL |
30355 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
30356 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
30357 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
30358 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
30359 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
30360 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc |
30361 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
30362 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
30363 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
30364 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
30365 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
30366 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
30367 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L |
30368 | #define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
30369 | //DIG0_HDMI_INFOFRAME_CONTROL0 |
30370 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
30371 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
30372 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
30373 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
30374 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
30375 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
30376 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
30377 | #define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
30378 | //DIG0_HDMI_INFOFRAME_CONTROL1 |
30379 | #define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
30380 | #define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
30381 | #define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
30382 | #define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
30383 | //DIG0_HDMI_GENERIC_PACKET_CONTROL0 |
30384 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
30385 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
30386 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
30387 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
30388 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
30389 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
30390 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
30391 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
30392 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
30393 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
30394 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
30395 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
30396 | //DIG0_AFMT_INTERRUPT_STATUS |
30397 | //DIG0_HDMI_GC |
30398 | #define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
30399 | #define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
30400 | #define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
30401 | #define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
30402 | #define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
30403 | #define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
30404 | #define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
30405 | #define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
30406 | #define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
30407 | #define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
30408 | //DIG0_AFMT_AUDIO_PACKET_CONTROL2 |
30409 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
30410 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
30411 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
30412 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
30413 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
30414 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
30415 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
30416 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
30417 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
30418 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
30419 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
30420 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
30421 | //DIG0_AFMT_ISRC1_0 |
30422 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
30423 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
30424 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
30425 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
30426 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
30427 | #define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
30428 | //DIG0_AFMT_ISRC1_1 |
30429 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
30430 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
30431 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
30432 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
30433 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
30434 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
30435 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
30436 | #define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
30437 | //DIG0_AFMT_ISRC1_2 |
30438 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
30439 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
30440 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
30441 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
30442 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
30443 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
30444 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
30445 | #define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
30446 | //DIG0_AFMT_ISRC1_3 |
30447 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
30448 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
30449 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
30450 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
30451 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
30452 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
30453 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
30454 | #define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
30455 | //DIG0_AFMT_ISRC1_4 |
30456 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
30457 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
30458 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
30459 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
30460 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
30461 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
30462 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
30463 | #define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
30464 | //DIG0_AFMT_ISRC2_0 |
30465 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
30466 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
30467 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
30468 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
30469 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
30470 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
30471 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
30472 | #define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
30473 | //DIG0_AFMT_ISRC2_1 |
30474 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
30475 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
30476 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
30477 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
30478 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
30479 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
30480 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
30481 | #define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
30482 | //DIG0_AFMT_ISRC2_2 |
30483 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
30484 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
30485 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
30486 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
30487 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
30488 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
30489 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
30490 | #define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
30491 | //DIG0_AFMT_ISRC2_3 |
30492 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
30493 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
30494 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
30495 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
30496 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
30497 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
30498 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
30499 | #define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
30500 | //DIG0_HDMI_GENERIC_PACKET_CONTROL2 |
30501 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
30502 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
30503 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
30504 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
30505 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
30506 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
30507 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
30508 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
30509 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
30510 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
30511 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
30512 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
30513 | //DIG0_HDMI_GENERIC_PACKET_CONTROL3 |
30514 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
30515 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
30516 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
30517 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
30518 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
30519 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
30520 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
30521 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
30522 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
30523 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
30524 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
30525 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
30526 | //DIG0_HDMI_DB_CONTROL |
30527 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
30528 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
30529 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
30530 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
30531 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
30532 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
30533 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
30534 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
30535 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
30536 | #define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
30537 | //DIG0_AFMT_MPEG_INFO0 |
30538 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
30539 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
30540 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
30541 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
30542 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
30543 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
30544 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
30545 | #define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
30546 | //DIG0_AFMT_MPEG_INFO1 |
30547 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
30548 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
30549 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
30550 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
30551 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
30552 | #define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
30553 | //DIG0_AFMT_GENERIC_HDR |
30554 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
30555 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
30556 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
30557 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
30558 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
30559 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
30560 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
30561 | #define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
30562 | //DIG0_AFMT_GENERIC_0 |
30563 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
30564 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
30565 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
30566 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
30567 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
30568 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
30569 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
30570 | #define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
30571 | //DIG0_AFMT_GENERIC_1 |
30572 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
30573 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
30574 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
30575 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
30576 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
30577 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
30578 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
30579 | #define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
30580 | //DIG0_AFMT_GENERIC_2 |
30581 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
30582 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
30583 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
30584 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
30585 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
30586 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
30587 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
30588 | #define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
30589 | //DIG0_AFMT_GENERIC_3 |
30590 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
30591 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
30592 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
30593 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
30594 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
30595 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
30596 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
30597 | #define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
30598 | //DIG0_AFMT_GENERIC_4 |
30599 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
30600 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
30601 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
30602 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
30603 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
30604 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
30605 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
30606 | #define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
30607 | //DIG0_AFMT_GENERIC_5 |
30608 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
30609 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
30610 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
30611 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
30612 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
30613 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
30614 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
30615 | #define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
30616 | //DIG0_AFMT_GENERIC_6 |
30617 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
30618 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
30619 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
30620 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
30621 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
30622 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
30623 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
30624 | #define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
30625 | //DIG0_AFMT_GENERIC_7 |
30626 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
30627 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
30628 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
30629 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
30630 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
30631 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
30632 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
30633 | #define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
30634 | //DIG0_HDMI_GENERIC_PACKET_CONTROL1 |
30635 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
30636 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
30637 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
30638 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
30639 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
30640 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
30641 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
30642 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
30643 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
30644 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
30645 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
30646 | #define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
30647 | //DIG0_HDMI_ACR_32_0 |
30648 | #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
30649 | #define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
30650 | //DIG0_HDMI_ACR_32_1 |
30651 | #define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
30652 | #define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
30653 | //DIG0_HDMI_ACR_44_0 |
30654 | #define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
30655 | #define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
30656 | //DIG0_HDMI_ACR_44_1 |
30657 | #define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
30658 | #define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
30659 | //DIG0_HDMI_ACR_48_0 |
30660 | #define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
30661 | #define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
30662 | //DIG0_HDMI_ACR_48_1 |
30663 | #define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
30664 | #define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
30665 | //DIG0_HDMI_ACR_STATUS_0 |
30666 | #define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
30667 | #define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
30668 | //DIG0_HDMI_ACR_STATUS_1 |
30669 | #define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
30670 | #define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
30671 | //DIG0_AFMT_AUDIO_INFO0 |
30672 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
30673 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
30674 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
30675 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
30676 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
30677 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
30678 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
30679 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
30680 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
30681 | #define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
30682 | //DIG0_AFMT_AUDIO_INFO1 |
30683 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
30684 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
30685 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
30686 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
30687 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
30688 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
30689 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
30690 | #define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
30691 | //DIG0_AFMT_60958_0 |
30692 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
30693 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
30694 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
30695 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
30696 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
30697 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
30698 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
30699 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
30700 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
30701 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
30702 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
30703 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
30704 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
30705 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
30706 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
30707 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
30708 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
30709 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
30710 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
30711 | #define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
30712 | //DIG0_AFMT_60958_1 |
30713 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
30714 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
30715 | #define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
30716 | #define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
30717 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
30718 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
30719 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
30720 | #define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
30721 | #define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
30722 | #define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
30723 | //DIG0_AFMT_AUDIO_CRC_CONTROL |
30724 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
30725 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
30726 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
30727 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
30728 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
30729 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
30730 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
30731 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
30732 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
30733 | #define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
30734 | //DIG0_AFMT_RAMP_CONTROL0 |
30735 | #define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
30736 | #define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
30737 | #define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
30738 | #define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
30739 | //DIG0_AFMT_RAMP_CONTROL1 |
30740 | #define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
30741 | #define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
30742 | #define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
30743 | #define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
30744 | //DIG0_AFMT_RAMP_CONTROL2 |
30745 | #define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
30746 | #define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
30747 | //DIG0_AFMT_RAMP_CONTROL3 |
30748 | #define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
30749 | #define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
30750 | //DIG0_AFMT_60958_2 |
30751 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
30752 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
30753 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
30754 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
30755 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
30756 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
30757 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
30758 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
30759 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
30760 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
30761 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
30762 | #define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
30763 | //DIG0_AFMT_AUDIO_CRC_RESULT |
30764 | #define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
30765 | #define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
30766 | #define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
30767 | #define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
30768 | //DIG0_AFMT_STATUS |
30769 | #define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
30770 | #define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
30771 | #define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
30772 | #define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
30773 | #define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
30774 | #define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
30775 | #define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
30776 | #define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
30777 | //DIG0_AFMT_AUDIO_PACKET_CONTROL |
30778 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
30779 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
30780 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
30781 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
30782 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
30783 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
30784 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
30785 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
30786 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
30787 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
30788 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
30789 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
30790 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
30791 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
30792 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
30793 | #define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
30794 | //DIG0_AFMT_VBI_PACKET_CONTROL |
30795 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
30796 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
30797 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
30798 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
30799 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
30800 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
30801 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
30802 | #define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
30803 | //DIG0_AFMT_INFOFRAME_CONTROL0 |
30804 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
30805 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
30806 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
30807 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
30808 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
30809 | #define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
30810 | //DIG0_AFMT_AUDIO_SRC_CONTROL |
30811 | #define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
30812 | #define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
30813 | //DIG0_DIG_BE_CNTL |
30814 | #define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
30815 | #define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
30816 | #define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
30817 | #define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
30818 | #define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
30819 | #define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
30820 | #define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
30821 | #define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
30822 | #define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
30823 | #define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
30824 | //DIG0_DIG_BE_EN_CNTL |
30825 | #define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
30826 | #define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
30827 | #define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
30828 | #define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
30829 | //DIG0_TMDS_CNTL |
30830 | #define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
30831 | #define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
30832 | //DIG0_TMDS_CONTROL_CHAR |
30833 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
30834 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
30835 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
30836 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
30837 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
30838 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
30839 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
30840 | #define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
30841 | //DIG0_TMDS_CONTROL0_FEEDBACK |
30842 | #define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
30843 | #define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
30844 | #define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
30845 | #define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
30846 | //DIG0_TMDS_STEREOSYNC_CTL_SEL |
30847 | #define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
30848 | #define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
30849 | //DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 |
30850 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
30851 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
30852 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
30853 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
30854 | //DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 |
30855 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
30856 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
30857 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
30858 | #define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
30859 | //DIG0_TMDS_CTL_BITS |
30860 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
30861 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
30862 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
30863 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
30864 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
30865 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
30866 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
30867 | #define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
30868 | //DIG0_TMDS_DCBALANCER_CONTROL |
30869 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
30870 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
30871 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
30872 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
30873 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
30874 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
30875 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
30876 | #define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
30877 | //DIG0_TMDS_CTL0_1_GEN_CNTL |
30878 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
30879 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
30880 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
30881 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
30882 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
30883 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
30884 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
30885 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
30886 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
30887 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
30888 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
30889 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
30890 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
30891 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
30892 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
30893 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
30894 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
30895 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
30896 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
30897 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
30898 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
30899 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
30900 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
30901 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
30902 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
30903 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
30904 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
30905 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
30906 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
30907 | #define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
30908 | //DIG0_TMDS_CTL2_3_GEN_CNTL |
30909 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
30910 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
30911 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
30912 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
30913 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
30914 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
30915 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
30916 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
30917 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
30918 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
30919 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
30920 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
30921 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
30922 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
30923 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
30924 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
30925 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
30926 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
30927 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
30928 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
30929 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
30930 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
30931 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
30932 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
30933 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
30934 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
30935 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
30936 | #define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
30937 | //DIG0_DIG_VERSION |
30938 | #define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
30939 | #define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
30940 | //DIG0_DIG_LANE_ENABLE |
30941 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
30942 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
30943 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
30944 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
30945 | #define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
30946 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
30947 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
30948 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
30949 | #define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
30950 | #define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
30951 | //DIG0_AFMT_CNTL |
30952 | #define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
30953 | #define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
30954 | #define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
30955 | #define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
30956 | //DIG0_AFMT_VBI_PACKET_CONTROL1 |
30957 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
30958 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
30959 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
30960 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
30961 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
30962 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
30963 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
30964 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
30965 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
30966 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
30967 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
30968 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
30969 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
30970 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
30971 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
30972 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
30973 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
30974 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
30975 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
30976 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
30977 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
30978 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
30979 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
30980 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
30981 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
30982 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
30983 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
30984 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
30985 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
30986 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
30987 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
30988 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
30989 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
30990 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
30991 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
30992 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
30993 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
30994 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
30995 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
30996 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
30997 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
30998 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
30999 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
31000 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
31001 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
31002 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
31003 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
31004 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
31005 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
31006 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
31007 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
31008 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
31009 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
31010 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
31011 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
31012 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
31013 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
31014 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
31015 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
31016 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
31017 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
31018 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
31019 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
31020 | #define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
31021 | |
31022 | |
31023 | // addressBlock: dce_dc_dio_dp0_dispdec |
31024 | //DP0_DP_LINK_CNTL |
31025 | #define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
31026 | #define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
31027 | #define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
31028 | #define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
31029 | #define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
31030 | #define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
31031 | //DP0_DP_PIXEL_FORMAT |
31032 | #define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
31033 | #define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
31034 | #define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
31035 | #define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
31036 | #define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
31037 | #define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
31038 | //DP0_DP_MSA_COLORIMETRY |
31039 | #define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
31040 | #define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
31041 | //DP0_DP_CONFIG |
31042 | #define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
31043 | #define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
31044 | //DP0_DP_VID_STREAM_CNTL |
31045 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
31046 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
31047 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
31048 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
31049 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
31050 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
31051 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
31052 | #define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
31053 | //DP0_DP_STEER_FIFO |
31054 | #define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
31055 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
31056 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
31057 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
31058 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
31059 | #define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
31060 | #define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
31061 | #define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
31062 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
31063 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
31064 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
31065 | #define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
31066 | #define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
31067 | #define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
31068 | //DP0_DP_MSA_MISC |
31069 | #define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
31070 | #define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
31071 | #define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
31072 | #define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
31073 | #define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
31074 | #define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
31075 | #define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
31076 | #define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
31077 | //DP0_DP_VID_TIMING |
31078 | #define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
31079 | #define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
31080 | #define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
31081 | #define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
31082 | #define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
31083 | #define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
31084 | #define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
31085 | #define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
31086 | #define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
31087 | #define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
31088 | //DP0_DP_VID_N |
31089 | #define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 |
31090 | #define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
31091 | //DP0_DP_VID_M |
31092 | #define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 |
31093 | #define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
31094 | //DP0_DP_LINK_FRAMING_CNTL |
31095 | #define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
31096 | #define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
31097 | #define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
31098 | #define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
31099 | #define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
31100 | #define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
31101 | //DP0_DP_HBR2_EYE_PATTERN |
31102 | #define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
31103 | #define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
31104 | //DP0_DP_VID_MSA_VBID |
31105 | #define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
31106 | #define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
31107 | #define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
31108 | #define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
31109 | //DP0_DP_VID_INTERRUPT_CNTL |
31110 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
31111 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
31112 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
31113 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
31114 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
31115 | #define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
31116 | //DP0_DP_DPHY_CNTL |
31117 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
31118 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
31119 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
31120 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
31121 | #define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
31122 | #define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
31123 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
31124 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
31125 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
31126 | #define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
31127 | #define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
31128 | #define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
31129 | //DP0_DP_DPHY_TRAINING_PATTERN_SEL |
31130 | #define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
31131 | #define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
31132 | //DP0_DP_DPHY_SYM0 |
31133 | #define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
31134 | #define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
31135 | #define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
31136 | #define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
31137 | #define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
31138 | #define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
31139 | //DP0_DP_DPHY_SYM1 |
31140 | #define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
31141 | #define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
31142 | #define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
31143 | #define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
31144 | #define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
31145 | #define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
31146 | //DP0_DP_DPHY_SYM2 |
31147 | #define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
31148 | #define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
31149 | #define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
31150 | #define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
31151 | //DP0_DP_DPHY_8B10B_CNTL |
31152 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
31153 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
31154 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
31155 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
31156 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
31157 | #define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
31158 | //DP0_DP_DPHY_PRBS_CNTL |
31159 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
31160 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
31161 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
31162 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
31163 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
31164 | #define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
31165 | //DP0_DP_DPHY_SCRAM_CNTL |
31166 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
31167 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
31168 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
31169 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
31170 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
31171 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
31172 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
31173 | #define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
31174 | //DP0_DP_DPHY_CRC_EN |
31175 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
31176 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
31177 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
31178 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
31179 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
31180 | #define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
31181 | //DP0_DP_DPHY_CRC_CNTL |
31182 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
31183 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
31184 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
31185 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
31186 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
31187 | #define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
31188 | //DP0_DP_DPHY_CRC_RESULT |
31189 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
31190 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
31191 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
31192 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
31193 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
31194 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
31195 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
31196 | #define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
31197 | //DP0_DP_DPHY_CRC_MST_CNTL |
31198 | #define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
31199 | #define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
31200 | #define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
31201 | #define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
31202 | //DP0_DP_DPHY_CRC_MST_STATUS |
31203 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
31204 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
31205 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
31206 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
31207 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
31208 | #define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
31209 | //DP0_DP_DPHY_FAST_TRAINING |
31210 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
31211 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
31212 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
31213 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
31214 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
31215 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
31216 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
31217 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
31218 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
31219 | #define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
31220 | //DP0_DP_DPHY_FAST_TRAINING_STATUS |
31221 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
31222 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
31223 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
31224 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
31225 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
31226 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
31227 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
31228 | #define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
31229 | //DP0_DP_SEC_CNTL |
31230 | #define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
31231 | #define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
31232 | #define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
31233 | #define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
31234 | #define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
31235 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
31236 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
31237 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
31238 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
31239 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
31240 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
31241 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
31242 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
31243 | #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
31244 | #define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
31245 | #define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
31246 | #define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
31247 | #define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
31248 | #define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
31249 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
31250 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
31251 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
31252 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
31253 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
31254 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
31255 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
31256 | #define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
31257 | #define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
31258 | //DP0_DP_SEC_CNTL1 |
31259 | #define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
31260 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
31261 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
31262 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
31263 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
31264 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
31265 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
31266 | #define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
31267 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
31268 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
31269 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
31270 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
31271 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
31272 | #define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
31273 | //DP0_DP_SEC_FRAMING1 |
31274 | #define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
31275 | #define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
31276 | #define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
31277 | #define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
31278 | //DP0_DP_SEC_FRAMING2 |
31279 | #define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
31280 | #define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
31281 | #define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
31282 | #define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
31283 | //DP0_DP_SEC_FRAMING3 |
31284 | #define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
31285 | #define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
31286 | #define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
31287 | #define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
31288 | //DP0_DP_SEC_FRAMING4 |
31289 | #define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
31290 | #define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
31291 | #define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
31292 | #define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
31293 | #define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
31294 | #define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
31295 | #define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
31296 | #define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
31297 | //DP0_DP_SEC_AUD_N |
31298 | #define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
31299 | #define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
31300 | //DP0_DP_SEC_AUD_N_READBACK |
31301 | #define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
31302 | #define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
31303 | //DP0_DP_SEC_AUD_M |
31304 | #define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
31305 | #define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
31306 | //DP0_DP_SEC_AUD_M_READBACK |
31307 | #define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
31308 | #define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
31309 | //DP0_DP_SEC_TIMESTAMP |
31310 | #define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
31311 | #define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
31312 | //DP0_DP_SEC_PACKET_CNTL |
31313 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
31314 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
31315 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
31316 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
31317 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
31318 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
31319 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
31320 | #define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
31321 | //DP0_DP_MSE_RATE_CNTL |
31322 | #define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
31323 | #define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
31324 | #define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
31325 | #define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
31326 | //DP0_DP_MSE_RATE_UPDATE |
31327 | #define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
31328 | #define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
31329 | //DP0_DP_MSE_SAT0 |
31330 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
31331 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
31332 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
31333 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
31334 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
31335 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
31336 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
31337 | #define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
31338 | //DP0_DP_MSE_SAT1 |
31339 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
31340 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
31341 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
31342 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
31343 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
31344 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
31345 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
31346 | #define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
31347 | //DP0_DP_MSE_SAT2 |
31348 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
31349 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
31350 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
31351 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
31352 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
31353 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
31354 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
31355 | #define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
31356 | //DP0_DP_MSE_SAT_UPDATE |
31357 | #define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
31358 | #define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
31359 | #define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
31360 | #define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
31361 | //DP0_DP_MSE_LINK_TIMING |
31362 | #define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
31363 | #define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
31364 | #define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
31365 | #define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
31366 | //DP0_DP_MSE_MISC_CNTL |
31367 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
31368 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
31369 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
31370 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
31371 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
31372 | #define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
31373 | //DP0_DP_DPHY_BS_SR_SWAP_CNTL |
31374 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
31375 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
31376 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
31377 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
31378 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
31379 | #define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
31380 | //DP0_DP_DPHY_HBR2_PATTERN_CONTROL |
31381 | #define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
31382 | #define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
31383 | //DP0_DP_MSE_SAT0_STATUS |
31384 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
31385 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
31386 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
31387 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
31388 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
31389 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
31390 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
31391 | #define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
31392 | //DP0_DP_MSE_SAT1_STATUS |
31393 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
31394 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
31395 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
31396 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
31397 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
31398 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
31399 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
31400 | #define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
31401 | //DP0_DP_MSE_SAT2_STATUS |
31402 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
31403 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
31404 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
31405 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
31406 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
31407 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
31408 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
31409 | #define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
31410 | //DP0_DP_MSA_TIMING_PARAM1 |
31411 | #define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
31412 | #define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
31413 | #define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
31414 | #define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
31415 | //DP0_DP_MSA_TIMING_PARAM2 |
31416 | #define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
31417 | #define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
31418 | #define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
31419 | #define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
31420 | //DP0_DP_MSA_TIMING_PARAM3 |
31421 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
31422 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
31423 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
31424 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
31425 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
31426 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
31427 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
31428 | #define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
31429 | //DP0_DP_MSA_TIMING_PARAM4 |
31430 | #define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
31431 | #define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
31432 | #define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
31433 | #define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
31434 | //DP0_DP_MSO_CNTL |
31435 | #define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
31436 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
31437 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
31438 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
31439 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
31440 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
31441 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
31442 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
31443 | #define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
31444 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
31445 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
31446 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
31447 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
31448 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
31449 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
31450 | #define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
31451 | //DP0_DP_MSO_CNTL1 |
31452 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
31453 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
31454 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
31455 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
31456 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
31457 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
31458 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
31459 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
31460 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
31461 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
31462 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
31463 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
31464 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
31465 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
31466 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
31467 | #define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
31468 | //DP0_DP_DSC_CNTL |
31469 | #define DP0_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
31470 | #define DP0_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
31471 | //DP0_DP_SEC_CNTL2 |
31472 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
31473 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
31474 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
31475 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
31476 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
31477 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
31478 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
31479 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
31480 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
31481 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
31482 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
31483 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
31484 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
31485 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
31486 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
31487 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
31488 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
31489 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
31490 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
31491 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
31492 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
31493 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
31494 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
31495 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
31496 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
31497 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
31498 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
31499 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
31500 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
31501 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
31502 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
31503 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
31504 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
31505 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
31506 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
31507 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
31508 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
31509 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
31510 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
31511 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
31512 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
31513 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
31514 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
31515 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
31516 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
31517 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
31518 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
31519 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
31520 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
31521 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
31522 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
31523 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
31524 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
31525 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
31526 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
31527 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
31528 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
31529 | #define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
31530 | //DP0_DP_SEC_CNTL3 |
31531 | #define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
31532 | #define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
31533 | #define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
31534 | #define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
31535 | //DP0_DP_SEC_CNTL4 |
31536 | #define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
31537 | #define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
31538 | #define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
31539 | #define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
31540 | //DP0_DP_SEC_CNTL5 |
31541 | #define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
31542 | #define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
31543 | #define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
31544 | #define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
31545 | //DP0_DP_SEC_CNTL6 |
31546 | #define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
31547 | #define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
31548 | //DP0_DP_SEC_CNTL7 |
31549 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
31550 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
31551 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
31552 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
31553 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
31554 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
31555 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
31556 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
31557 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
31558 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
31559 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
31560 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
31561 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
31562 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
31563 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
31564 | #define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
31565 | //DP0_DP_DB_CNTL |
31566 | #define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
31567 | #define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
31568 | #define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
31569 | #define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
31570 | #define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
31571 | #define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
31572 | #define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
31573 | #define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
31574 | #define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
31575 | #define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
31576 | //DP0_DP_MSA_VBID_MISC |
31577 | #define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
31578 | #define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
31579 | #define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
31580 | #define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
31581 | #define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
31582 | #define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
31583 | #define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
31584 | #define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
31585 | #define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
31586 | #define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
31587 | #define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
31588 | #define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
31589 | |
31590 | |
31591 | // addressBlock: dce_dc_dio_dig1_dispdec |
31592 | //DIG1_DIG_FE_CNTL |
31593 | #define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
31594 | #define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
31595 | #define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
31596 | #define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
31597 | #define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
31598 | #define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
31599 | #define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
31600 | #define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
31601 | #define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
31602 | #define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
31603 | #define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
31604 | #define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
31605 | #define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
31606 | #define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
31607 | #define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
31608 | #define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
31609 | //DIG1_DIG_OUTPUT_CRC_CNTL |
31610 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
31611 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
31612 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
31613 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
31614 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
31615 | #define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
31616 | //DIG1_DIG_OUTPUT_CRC_RESULT |
31617 | #define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
31618 | #define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
31619 | //DIG1_DIG_CLOCK_PATTERN |
31620 | #define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
31621 | #define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
31622 | //DIG1_DIG_TEST_PATTERN |
31623 | #define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
31624 | #define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
31625 | #define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
31626 | #define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
31627 | #define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
31628 | #define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
31629 | #define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
31630 | #define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
31631 | #define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
31632 | #define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
31633 | #define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
31634 | #define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
31635 | //DIG1_DIG_RANDOM_PATTERN_SEED |
31636 | #define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
31637 | #define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
31638 | #define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
31639 | #define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
31640 | //DIG1_DIG_FIFO_STATUS |
31641 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
31642 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
31643 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
31644 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
31645 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
31646 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
31647 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
31648 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
31649 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
31650 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
31651 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
31652 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
31653 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
31654 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
31655 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
31656 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
31657 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
31658 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
31659 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
31660 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
31661 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
31662 | #define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
31663 | //DIG1_HDMI_CONTROL |
31664 | #define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
31665 | #define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
31666 | #define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
31667 | #define 0x3 |
31668 | #define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
31669 | #define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
31670 | #define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
31671 | #define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
31672 | #define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
31673 | #define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
31674 | #define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
31675 | #define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
31676 | #define 0x00000008L |
31677 | #define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
31678 | #define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
31679 | #define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
31680 | #define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
31681 | #define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
31682 | //DIG1_HDMI_STATUS |
31683 | #define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
31684 | #define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
31685 | #define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
31686 | #define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
31687 | #define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
31688 | #define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
31689 | #define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
31690 | #define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
31691 | //DIG1_HDMI_AUDIO_PACKET_CONTROL |
31692 | #define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
31693 | #define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
31694 | #define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
31695 | #define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
31696 | //DIG1_HDMI_ACR_PACKET_CONTROL |
31697 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
31698 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
31699 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
31700 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
31701 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
31702 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
31703 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
31704 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
31705 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
31706 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
31707 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
31708 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
31709 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
31710 | #define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
31711 | //DIG1_HDMI_VBI_PACKET_CONTROL |
31712 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
31713 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
31714 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
31715 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
31716 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
31717 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
31718 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
31719 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
31720 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
31721 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
31722 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
31723 | #define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
31724 | //DIG1_HDMI_INFOFRAME_CONTROL0 |
31725 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
31726 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
31727 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
31728 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
31729 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
31730 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
31731 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
31732 | #define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
31733 | //DIG1_HDMI_INFOFRAME_CONTROL1 |
31734 | #define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
31735 | #define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
31736 | #define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
31737 | #define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
31738 | //DIG1_HDMI_GENERIC_PACKET_CONTROL0 |
31739 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
31740 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
31741 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
31742 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
31743 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
31744 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
31745 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
31746 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
31747 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
31748 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
31749 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
31750 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
31751 | //DIG1_AFMT_INTERRUPT_STATUS |
31752 | //DIG1_HDMI_GC |
31753 | #define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
31754 | #define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
31755 | #define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
31756 | #define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
31757 | #define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
31758 | #define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
31759 | #define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
31760 | #define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
31761 | #define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
31762 | #define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
31763 | //DIG1_AFMT_AUDIO_PACKET_CONTROL2 |
31764 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
31765 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
31766 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
31767 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
31768 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
31769 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
31770 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
31771 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
31772 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
31773 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
31774 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
31775 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
31776 | //DIG1_AFMT_ISRC1_0 |
31777 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
31778 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
31779 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
31780 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
31781 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
31782 | #define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
31783 | //DIG1_AFMT_ISRC1_1 |
31784 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
31785 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
31786 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
31787 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
31788 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
31789 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
31790 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
31791 | #define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
31792 | //DIG1_AFMT_ISRC1_2 |
31793 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
31794 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
31795 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
31796 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
31797 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
31798 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
31799 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
31800 | #define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
31801 | //DIG1_AFMT_ISRC1_3 |
31802 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
31803 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
31804 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
31805 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
31806 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
31807 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
31808 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
31809 | #define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
31810 | //DIG1_AFMT_ISRC1_4 |
31811 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
31812 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
31813 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
31814 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
31815 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
31816 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
31817 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
31818 | #define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
31819 | //DIG1_AFMT_ISRC2_0 |
31820 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
31821 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
31822 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
31823 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
31824 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
31825 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
31826 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
31827 | #define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
31828 | //DIG1_AFMT_ISRC2_1 |
31829 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
31830 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
31831 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
31832 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
31833 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
31834 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
31835 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
31836 | #define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
31837 | //DIG1_AFMT_ISRC2_2 |
31838 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
31839 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
31840 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
31841 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
31842 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
31843 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
31844 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
31845 | #define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
31846 | //DIG1_AFMT_ISRC2_3 |
31847 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
31848 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
31849 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
31850 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
31851 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
31852 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
31853 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
31854 | #define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
31855 | //DIG1_HDMI_GENERIC_PACKET_CONTROL2 |
31856 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
31857 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
31858 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
31859 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
31860 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
31861 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
31862 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
31863 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
31864 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
31865 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
31866 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
31867 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
31868 | //DIG1_HDMI_GENERIC_PACKET_CONTROL3 |
31869 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
31870 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
31871 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
31872 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
31873 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
31874 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
31875 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
31876 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
31877 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
31878 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
31879 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
31880 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
31881 | //DIG1_HDMI_DB_CONTROL |
31882 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
31883 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
31884 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
31885 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
31886 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
31887 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
31888 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
31889 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
31890 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
31891 | #define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
31892 | //DIG1_AFMT_MPEG_INFO0 |
31893 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
31894 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
31895 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
31896 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
31897 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
31898 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
31899 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
31900 | #define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
31901 | //DIG1_AFMT_MPEG_INFO1 |
31902 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
31903 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
31904 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
31905 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
31906 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
31907 | #define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
31908 | //DIG1_AFMT_GENERIC_HDR |
31909 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
31910 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
31911 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
31912 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
31913 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
31914 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
31915 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
31916 | #define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
31917 | //DIG1_AFMT_GENERIC_0 |
31918 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
31919 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
31920 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
31921 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
31922 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
31923 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
31924 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
31925 | #define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
31926 | //DIG1_AFMT_GENERIC_1 |
31927 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
31928 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
31929 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
31930 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
31931 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
31932 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
31933 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
31934 | #define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
31935 | //DIG1_AFMT_GENERIC_2 |
31936 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
31937 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
31938 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
31939 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
31940 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
31941 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
31942 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
31943 | #define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
31944 | //DIG1_AFMT_GENERIC_3 |
31945 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
31946 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
31947 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
31948 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
31949 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
31950 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
31951 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
31952 | #define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
31953 | //DIG1_AFMT_GENERIC_4 |
31954 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
31955 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
31956 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
31957 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
31958 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
31959 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
31960 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
31961 | #define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
31962 | //DIG1_AFMT_GENERIC_5 |
31963 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
31964 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
31965 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
31966 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
31967 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
31968 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
31969 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
31970 | #define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
31971 | //DIG1_AFMT_GENERIC_6 |
31972 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
31973 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
31974 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
31975 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
31976 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
31977 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
31978 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
31979 | #define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
31980 | //DIG1_AFMT_GENERIC_7 |
31981 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
31982 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
31983 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
31984 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
31985 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
31986 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
31987 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
31988 | #define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
31989 | //DIG1_HDMI_GENERIC_PACKET_CONTROL1 |
31990 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
31991 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
31992 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
31993 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
31994 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
31995 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
31996 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
31997 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
31998 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
31999 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
32000 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
32001 | #define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
32002 | //DIG1_HDMI_ACR_32_0 |
32003 | #define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
32004 | #define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
32005 | //DIG1_HDMI_ACR_32_1 |
32006 | #define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
32007 | #define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
32008 | //DIG1_HDMI_ACR_44_0 |
32009 | #define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
32010 | #define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
32011 | //DIG1_HDMI_ACR_44_1 |
32012 | #define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
32013 | #define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
32014 | //DIG1_HDMI_ACR_48_0 |
32015 | #define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
32016 | #define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
32017 | //DIG1_HDMI_ACR_48_1 |
32018 | #define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
32019 | #define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
32020 | //DIG1_HDMI_ACR_STATUS_0 |
32021 | #define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
32022 | #define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
32023 | //DIG1_HDMI_ACR_STATUS_1 |
32024 | #define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
32025 | #define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
32026 | //DIG1_AFMT_AUDIO_INFO0 |
32027 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
32028 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
32029 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
32030 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
32031 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
32032 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
32033 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
32034 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
32035 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
32036 | #define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
32037 | //DIG1_AFMT_AUDIO_INFO1 |
32038 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
32039 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
32040 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
32041 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
32042 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
32043 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
32044 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
32045 | #define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
32046 | //DIG1_AFMT_60958_0 |
32047 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
32048 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
32049 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
32050 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
32051 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
32052 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
32053 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
32054 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
32055 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
32056 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
32057 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
32058 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
32059 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
32060 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
32061 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
32062 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
32063 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
32064 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
32065 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
32066 | #define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
32067 | //DIG1_AFMT_60958_1 |
32068 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
32069 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
32070 | #define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
32071 | #define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
32072 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
32073 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
32074 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
32075 | #define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
32076 | #define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
32077 | #define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
32078 | //DIG1_AFMT_AUDIO_CRC_CONTROL |
32079 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
32080 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
32081 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
32082 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
32083 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
32084 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
32085 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
32086 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
32087 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
32088 | #define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
32089 | //DIG1_AFMT_RAMP_CONTROL0 |
32090 | #define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
32091 | #define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
32092 | #define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
32093 | #define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
32094 | //DIG1_AFMT_RAMP_CONTROL1 |
32095 | #define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
32096 | #define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
32097 | #define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
32098 | #define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
32099 | //DIG1_AFMT_RAMP_CONTROL2 |
32100 | #define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
32101 | #define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
32102 | //DIG1_AFMT_RAMP_CONTROL3 |
32103 | #define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
32104 | #define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
32105 | //DIG1_AFMT_60958_2 |
32106 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
32107 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
32108 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
32109 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
32110 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
32111 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
32112 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
32113 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
32114 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
32115 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
32116 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
32117 | #define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
32118 | //DIG1_AFMT_AUDIO_CRC_RESULT |
32119 | #define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
32120 | #define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
32121 | #define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
32122 | #define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
32123 | //DIG1_AFMT_STATUS |
32124 | #define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
32125 | #define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
32126 | #define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
32127 | #define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
32128 | #define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
32129 | #define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
32130 | #define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
32131 | #define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
32132 | //DIG1_AFMT_AUDIO_PACKET_CONTROL |
32133 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
32134 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
32135 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
32136 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
32137 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
32138 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
32139 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
32140 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
32141 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
32142 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
32143 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
32144 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
32145 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
32146 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
32147 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
32148 | #define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
32149 | //DIG1_AFMT_VBI_PACKET_CONTROL |
32150 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
32151 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
32152 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
32153 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
32154 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
32155 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
32156 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
32157 | #define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
32158 | //DIG1_AFMT_INFOFRAME_CONTROL0 |
32159 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
32160 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
32161 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
32162 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
32163 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
32164 | #define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
32165 | //DIG1_AFMT_AUDIO_SRC_CONTROL |
32166 | #define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
32167 | #define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
32168 | //DIG1_DIG_BE_CNTL |
32169 | #define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
32170 | #define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
32171 | #define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
32172 | #define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
32173 | #define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
32174 | #define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
32175 | #define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
32176 | #define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
32177 | #define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
32178 | #define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
32179 | //DIG1_DIG_BE_EN_CNTL |
32180 | #define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
32181 | #define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
32182 | #define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
32183 | #define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
32184 | //DIG1_TMDS_CNTL |
32185 | #define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
32186 | #define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
32187 | //DIG1_TMDS_CONTROL_CHAR |
32188 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
32189 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
32190 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
32191 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
32192 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
32193 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
32194 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
32195 | #define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
32196 | //DIG1_TMDS_CONTROL0_FEEDBACK |
32197 | #define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
32198 | #define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
32199 | #define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
32200 | #define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
32201 | //DIG1_TMDS_STEREOSYNC_CTL_SEL |
32202 | #define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
32203 | #define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
32204 | //DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 |
32205 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
32206 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
32207 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
32208 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
32209 | //DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 |
32210 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
32211 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
32212 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
32213 | #define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
32214 | //DIG1_TMDS_CTL_BITS |
32215 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
32216 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
32217 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
32218 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
32219 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
32220 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
32221 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
32222 | #define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
32223 | //DIG1_TMDS_DCBALANCER_CONTROL |
32224 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
32225 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
32226 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
32227 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
32228 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
32229 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
32230 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
32231 | #define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
32232 | //DIG1_TMDS_CTL0_1_GEN_CNTL |
32233 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
32234 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
32235 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
32236 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
32237 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
32238 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
32239 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
32240 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
32241 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
32242 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
32243 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
32244 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
32245 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
32246 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
32247 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
32248 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
32249 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
32250 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
32251 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
32252 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
32253 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
32254 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
32255 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
32256 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
32257 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
32258 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
32259 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
32260 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
32261 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
32262 | #define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
32263 | //DIG1_TMDS_CTL2_3_GEN_CNTL |
32264 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
32265 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
32266 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
32267 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
32268 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
32269 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
32270 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
32271 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
32272 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
32273 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
32274 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
32275 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
32276 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
32277 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
32278 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
32279 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
32280 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
32281 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
32282 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
32283 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
32284 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
32285 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
32286 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
32287 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
32288 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
32289 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
32290 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
32291 | #define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
32292 | //DIG1_DIG_VERSION |
32293 | #define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
32294 | #define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
32295 | //DIG1_DIG_LANE_ENABLE |
32296 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
32297 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
32298 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
32299 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
32300 | #define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
32301 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
32302 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
32303 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
32304 | #define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
32305 | #define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
32306 | //DIG1_AFMT_CNTL |
32307 | #define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
32308 | #define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
32309 | #define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
32310 | #define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
32311 | //DIG1_AFMT_VBI_PACKET_CONTROL1 |
32312 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
32313 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
32314 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
32315 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
32316 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
32317 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
32318 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
32319 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
32320 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
32321 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
32322 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
32323 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
32324 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
32325 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
32326 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
32327 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
32328 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
32329 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
32330 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
32331 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
32332 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
32333 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
32334 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
32335 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
32336 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
32337 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
32338 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
32339 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
32340 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
32341 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
32342 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
32343 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
32344 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
32345 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
32346 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
32347 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
32348 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
32349 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
32350 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
32351 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
32352 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
32353 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
32354 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
32355 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
32356 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
32357 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
32358 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
32359 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
32360 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
32361 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
32362 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
32363 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
32364 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
32365 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
32366 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
32367 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
32368 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
32369 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
32370 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
32371 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
32372 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
32373 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
32374 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
32375 | #define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
32376 | |
32377 | |
32378 | // addressBlock: dce_dc_dio_dp1_dispdec |
32379 | //DP1_DP_LINK_CNTL |
32380 | #define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
32381 | #define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
32382 | #define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
32383 | #define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
32384 | #define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
32385 | #define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
32386 | //DP1_DP_PIXEL_FORMAT |
32387 | #define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
32388 | #define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
32389 | #define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
32390 | #define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
32391 | #define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
32392 | #define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
32393 | //DP1_DP_MSA_COLORIMETRY |
32394 | #define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
32395 | #define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
32396 | //DP1_DP_CONFIG |
32397 | #define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
32398 | #define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
32399 | //DP1_DP_VID_STREAM_CNTL |
32400 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
32401 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
32402 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
32403 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
32404 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
32405 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
32406 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
32407 | #define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
32408 | //DP1_DP_STEER_FIFO |
32409 | #define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
32410 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
32411 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
32412 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
32413 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
32414 | #define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
32415 | #define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
32416 | #define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
32417 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
32418 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
32419 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
32420 | #define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
32421 | #define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
32422 | #define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
32423 | //DP1_DP_MSA_MISC |
32424 | #define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
32425 | #define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
32426 | #define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
32427 | #define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
32428 | #define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
32429 | #define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
32430 | #define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
32431 | #define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
32432 | //DP1_DP_VID_TIMING |
32433 | #define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
32434 | #define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
32435 | #define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
32436 | #define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
32437 | #define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
32438 | #define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
32439 | #define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
32440 | #define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
32441 | #define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
32442 | #define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
32443 | //DP1_DP_VID_N |
32444 | #define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 |
32445 | #define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
32446 | //DP1_DP_VID_M |
32447 | #define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 |
32448 | #define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
32449 | //DP1_DP_LINK_FRAMING_CNTL |
32450 | #define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
32451 | #define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
32452 | #define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
32453 | #define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
32454 | #define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
32455 | #define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
32456 | //DP1_DP_HBR2_EYE_PATTERN |
32457 | #define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
32458 | #define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
32459 | //DP1_DP_VID_MSA_VBID |
32460 | #define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
32461 | #define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
32462 | #define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
32463 | #define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
32464 | //DP1_DP_VID_INTERRUPT_CNTL |
32465 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
32466 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
32467 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
32468 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
32469 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
32470 | #define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
32471 | //DP1_DP_DPHY_CNTL |
32472 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
32473 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
32474 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
32475 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
32476 | #define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
32477 | #define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
32478 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
32479 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
32480 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
32481 | #define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
32482 | #define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
32483 | #define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
32484 | //DP1_DP_DPHY_TRAINING_PATTERN_SEL |
32485 | #define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
32486 | #define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
32487 | //DP1_DP_DPHY_SYM0 |
32488 | #define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
32489 | #define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
32490 | #define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
32491 | #define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
32492 | #define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
32493 | #define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
32494 | //DP1_DP_DPHY_SYM1 |
32495 | #define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
32496 | #define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
32497 | #define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
32498 | #define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
32499 | #define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
32500 | #define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
32501 | //DP1_DP_DPHY_SYM2 |
32502 | #define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
32503 | #define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
32504 | #define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
32505 | #define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
32506 | //DP1_DP_DPHY_8B10B_CNTL |
32507 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
32508 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
32509 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
32510 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
32511 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
32512 | #define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
32513 | //DP1_DP_DPHY_PRBS_CNTL |
32514 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
32515 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
32516 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
32517 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
32518 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
32519 | #define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
32520 | //DP1_DP_DPHY_SCRAM_CNTL |
32521 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
32522 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
32523 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
32524 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
32525 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
32526 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
32527 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
32528 | #define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
32529 | //DP1_DP_DPHY_CRC_EN |
32530 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
32531 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
32532 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
32533 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
32534 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
32535 | #define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
32536 | //DP1_DP_DPHY_CRC_CNTL |
32537 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
32538 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
32539 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
32540 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
32541 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
32542 | #define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
32543 | //DP1_DP_DPHY_CRC_RESULT |
32544 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
32545 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
32546 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
32547 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
32548 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
32549 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
32550 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
32551 | #define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
32552 | //DP1_DP_DPHY_CRC_MST_CNTL |
32553 | #define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
32554 | #define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
32555 | #define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
32556 | #define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
32557 | //DP1_DP_DPHY_CRC_MST_STATUS |
32558 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
32559 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
32560 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
32561 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
32562 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
32563 | #define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
32564 | //DP1_DP_DPHY_FAST_TRAINING |
32565 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
32566 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
32567 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
32568 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
32569 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
32570 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
32571 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
32572 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
32573 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
32574 | #define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
32575 | //DP1_DP_DPHY_FAST_TRAINING_STATUS |
32576 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
32577 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
32578 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
32579 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
32580 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
32581 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
32582 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
32583 | #define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
32584 | //DP1_DP_SEC_CNTL |
32585 | #define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
32586 | #define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
32587 | #define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
32588 | #define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
32589 | #define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
32590 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
32591 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
32592 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
32593 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
32594 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
32595 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
32596 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
32597 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
32598 | #define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
32599 | #define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
32600 | #define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
32601 | #define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
32602 | #define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
32603 | #define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
32604 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
32605 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
32606 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
32607 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
32608 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
32609 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
32610 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
32611 | #define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
32612 | #define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
32613 | //DP1_DP_SEC_CNTL1 |
32614 | #define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
32615 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
32616 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
32617 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
32618 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
32619 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
32620 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
32621 | #define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
32622 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
32623 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
32624 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
32625 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
32626 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
32627 | #define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
32628 | //DP1_DP_SEC_FRAMING1 |
32629 | #define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
32630 | #define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
32631 | #define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
32632 | #define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
32633 | //DP1_DP_SEC_FRAMING2 |
32634 | #define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
32635 | #define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
32636 | #define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
32637 | #define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
32638 | //DP1_DP_SEC_FRAMING3 |
32639 | #define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
32640 | #define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
32641 | #define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
32642 | #define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
32643 | //DP1_DP_SEC_FRAMING4 |
32644 | #define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
32645 | #define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
32646 | #define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
32647 | #define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
32648 | #define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
32649 | #define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
32650 | #define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
32651 | #define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
32652 | //DP1_DP_SEC_AUD_N |
32653 | #define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
32654 | #define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
32655 | //DP1_DP_SEC_AUD_N_READBACK |
32656 | #define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
32657 | #define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
32658 | //DP1_DP_SEC_AUD_M |
32659 | #define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
32660 | #define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
32661 | //DP1_DP_SEC_AUD_M_READBACK |
32662 | #define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
32663 | #define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
32664 | //DP1_DP_SEC_TIMESTAMP |
32665 | #define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
32666 | #define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
32667 | //DP1_DP_SEC_PACKET_CNTL |
32668 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
32669 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
32670 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
32671 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
32672 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
32673 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
32674 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
32675 | #define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
32676 | //DP1_DP_MSE_RATE_CNTL |
32677 | #define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
32678 | #define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
32679 | #define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
32680 | #define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
32681 | //DP1_DP_MSE_RATE_UPDATE |
32682 | #define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
32683 | #define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
32684 | //DP1_DP_MSE_SAT0 |
32685 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
32686 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
32687 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
32688 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
32689 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
32690 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
32691 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
32692 | #define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
32693 | //DP1_DP_MSE_SAT1 |
32694 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
32695 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
32696 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
32697 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
32698 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
32699 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
32700 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
32701 | #define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
32702 | //DP1_DP_MSE_SAT2 |
32703 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
32704 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
32705 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
32706 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
32707 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
32708 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
32709 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
32710 | #define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
32711 | //DP1_DP_MSE_SAT_UPDATE |
32712 | #define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
32713 | #define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
32714 | #define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
32715 | #define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
32716 | //DP1_DP_MSE_LINK_TIMING |
32717 | #define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
32718 | #define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
32719 | #define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
32720 | #define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
32721 | //DP1_DP_MSE_MISC_CNTL |
32722 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
32723 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
32724 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
32725 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
32726 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
32727 | #define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
32728 | //DP1_DP_DPHY_BS_SR_SWAP_CNTL |
32729 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
32730 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
32731 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
32732 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
32733 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
32734 | #define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
32735 | //DP1_DP_DPHY_HBR2_PATTERN_CONTROL |
32736 | #define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
32737 | #define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
32738 | //DP1_DP_MSE_SAT0_STATUS |
32739 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
32740 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
32741 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
32742 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
32743 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
32744 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
32745 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
32746 | #define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
32747 | //DP1_DP_MSE_SAT1_STATUS |
32748 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
32749 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
32750 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
32751 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
32752 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
32753 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
32754 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
32755 | #define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
32756 | //DP1_DP_MSE_SAT2_STATUS |
32757 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
32758 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
32759 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
32760 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
32761 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
32762 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
32763 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
32764 | #define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
32765 | //DP1_DP_MSA_TIMING_PARAM1 |
32766 | #define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
32767 | #define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
32768 | #define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
32769 | #define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
32770 | //DP1_DP_MSA_TIMING_PARAM2 |
32771 | #define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
32772 | #define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
32773 | #define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
32774 | #define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
32775 | //DP1_DP_MSA_TIMING_PARAM3 |
32776 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
32777 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
32778 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
32779 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
32780 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
32781 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
32782 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
32783 | #define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
32784 | //DP1_DP_MSA_TIMING_PARAM4 |
32785 | #define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
32786 | #define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
32787 | #define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
32788 | #define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
32789 | //DP1_DP_MSO_CNTL |
32790 | #define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
32791 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
32792 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
32793 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
32794 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
32795 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
32796 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
32797 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
32798 | #define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
32799 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
32800 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
32801 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
32802 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
32803 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
32804 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
32805 | #define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
32806 | //DP1_DP_MSO_CNTL1 |
32807 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
32808 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
32809 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
32810 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
32811 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
32812 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
32813 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
32814 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
32815 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
32816 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
32817 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
32818 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
32819 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
32820 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
32821 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
32822 | #define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
32823 | //DP1_DP_DSC_CNTL |
32824 | #define DP1_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
32825 | #define DP1_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
32826 | //DP1_DP_SEC_CNTL2 |
32827 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
32828 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
32829 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
32830 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
32831 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
32832 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
32833 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
32834 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
32835 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
32836 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
32837 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
32838 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
32839 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
32840 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
32841 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
32842 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
32843 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
32844 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
32845 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
32846 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
32847 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
32848 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
32849 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
32850 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
32851 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
32852 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
32853 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
32854 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
32855 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
32856 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
32857 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
32858 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
32859 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
32860 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
32861 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
32862 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
32863 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
32864 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
32865 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
32866 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
32867 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
32868 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
32869 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
32870 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
32871 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
32872 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
32873 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
32874 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
32875 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
32876 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
32877 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
32878 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
32879 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
32880 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
32881 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
32882 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
32883 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
32884 | #define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
32885 | //DP1_DP_SEC_CNTL3 |
32886 | #define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
32887 | #define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
32888 | #define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
32889 | #define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
32890 | //DP1_DP_SEC_CNTL4 |
32891 | #define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
32892 | #define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
32893 | #define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
32894 | #define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
32895 | //DP1_DP_SEC_CNTL5 |
32896 | #define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
32897 | #define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
32898 | #define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
32899 | #define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
32900 | //DP1_DP_SEC_CNTL6 |
32901 | #define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
32902 | #define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
32903 | //DP1_DP_SEC_CNTL7 |
32904 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
32905 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
32906 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
32907 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
32908 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
32909 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
32910 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
32911 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
32912 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
32913 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
32914 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
32915 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
32916 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
32917 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
32918 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
32919 | #define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
32920 | //DP1_DP_DB_CNTL |
32921 | #define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
32922 | #define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
32923 | #define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
32924 | #define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
32925 | #define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
32926 | #define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
32927 | #define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
32928 | #define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
32929 | #define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
32930 | #define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
32931 | //DP1_DP_MSA_VBID_MISC |
32932 | #define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
32933 | #define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
32934 | #define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
32935 | #define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
32936 | #define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
32937 | #define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
32938 | #define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
32939 | #define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
32940 | #define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
32941 | #define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
32942 | #define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
32943 | #define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
32944 | |
32945 | |
32946 | // addressBlock: dce_dc_dio_dig2_dispdec |
32947 | //DIG2_DIG_FE_CNTL |
32948 | #define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
32949 | #define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
32950 | #define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
32951 | #define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
32952 | #define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
32953 | #define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
32954 | #define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
32955 | #define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
32956 | #define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
32957 | #define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
32958 | #define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
32959 | #define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
32960 | #define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
32961 | #define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
32962 | #define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
32963 | #define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
32964 | //DIG2_DIG_OUTPUT_CRC_CNTL |
32965 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
32966 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
32967 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
32968 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
32969 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
32970 | #define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
32971 | //DIG2_DIG_OUTPUT_CRC_RESULT |
32972 | #define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
32973 | #define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
32974 | //DIG2_DIG_CLOCK_PATTERN |
32975 | #define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
32976 | #define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
32977 | //DIG2_DIG_TEST_PATTERN |
32978 | #define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
32979 | #define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
32980 | #define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
32981 | #define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
32982 | #define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
32983 | #define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
32984 | #define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
32985 | #define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
32986 | #define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
32987 | #define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
32988 | #define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
32989 | #define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
32990 | //DIG2_DIG_RANDOM_PATTERN_SEED |
32991 | #define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
32992 | #define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
32993 | #define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
32994 | #define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
32995 | //DIG2_DIG_FIFO_STATUS |
32996 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
32997 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
32998 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
32999 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
33000 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
33001 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
33002 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
33003 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
33004 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
33005 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
33006 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
33007 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
33008 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
33009 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
33010 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
33011 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
33012 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
33013 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
33014 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
33015 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
33016 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
33017 | #define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
33018 | //DIG2_HDMI_CONTROL |
33019 | #define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
33020 | #define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
33021 | #define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
33022 | #define 0x3 |
33023 | #define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
33024 | #define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
33025 | #define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
33026 | #define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
33027 | #define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
33028 | #define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
33029 | #define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
33030 | #define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
33031 | #define 0x00000008L |
33032 | #define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
33033 | #define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
33034 | #define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
33035 | #define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
33036 | #define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
33037 | //DIG2_HDMI_STATUS |
33038 | #define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
33039 | #define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
33040 | #define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
33041 | #define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
33042 | #define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
33043 | #define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
33044 | #define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
33045 | #define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
33046 | //DIG2_HDMI_AUDIO_PACKET_CONTROL |
33047 | #define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
33048 | #define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
33049 | #define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
33050 | #define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
33051 | //DIG2_HDMI_ACR_PACKET_CONTROL |
33052 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
33053 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
33054 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
33055 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
33056 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
33057 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
33058 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
33059 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
33060 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
33061 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
33062 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
33063 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
33064 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
33065 | #define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
33066 | //DIG2_HDMI_VBI_PACKET_CONTROL |
33067 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
33068 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
33069 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
33070 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
33071 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
33072 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
33073 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
33074 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
33075 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
33076 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
33077 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
33078 | #define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
33079 | //DIG2_HDMI_INFOFRAME_CONTROL0 |
33080 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
33081 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
33082 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
33083 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
33084 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
33085 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
33086 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
33087 | #define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
33088 | //DIG2_HDMI_INFOFRAME_CONTROL1 |
33089 | #define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
33090 | #define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
33091 | #define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
33092 | #define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
33093 | //DIG2_HDMI_GENERIC_PACKET_CONTROL0 |
33094 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
33095 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
33096 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
33097 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
33098 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
33099 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
33100 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
33101 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
33102 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
33103 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
33104 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
33105 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
33106 | //DIG2_AFMT_INTERRUPT_STATUS |
33107 | //DIG2_HDMI_GC |
33108 | #define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
33109 | #define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
33110 | #define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
33111 | #define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
33112 | #define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
33113 | #define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
33114 | #define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
33115 | #define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
33116 | #define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
33117 | #define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
33118 | //DIG2_AFMT_AUDIO_PACKET_CONTROL2 |
33119 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
33120 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
33121 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
33122 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
33123 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
33124 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
33125 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
33126 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
33127 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
33128 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
33129 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
33130 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
33131 | //DIG2_AFMT_ISRC1_0 |
33132 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
33133 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
33134 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
33135 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
33136 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
33137 | #define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
33138 | //DIG2_AFMT_ISRC1_1 |
33139 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
33140 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
33141 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
33142 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
33143 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
33144 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
33145 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
33146 | #define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
33147 | //DIG2_AFMT_ISRC1_2 |
33148 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
33149 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
33150 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
33151 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
33152 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
33153 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
33154 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
33155 | #define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
33156 | //DIG2_AFMT_ISRC1_3 |
33157 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
33158 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
33159 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
33160 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
33161 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
33162 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
33163 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
33164 | #define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
33165 | //DIG2_AFMT_ISRC1_4 |
33166 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
33167 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
33168 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
33169 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
33170 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
33171 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
33172 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
33173 | #define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
33174 | //DIG2_AFMT_ISRC2_0 |
33175 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
33176 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
33177 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
33178 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
33179 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
33180 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
33181 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
33182 | #define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
33183 | //DIG2_AFMT_ISRC2_1 |
33184 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
33185 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
33186 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
33187 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
33188 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
33189 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
33190 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
33191 | #define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
33192 | //DIG2_AFMT_ISRC2_2 |
33193 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
33194 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
33195 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
33196 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
33197 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
33198 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
33199 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
33200 | #define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
33201 | //DIG2_AFMT_ISRC2_3 |
33202 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
33203 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
33204 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
33205 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
33206 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
33207 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
33208 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
33209 | #define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
33210 | //DIG2_HDMI_GENERIC_PACKET_CONTROL2 |
33211 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
33212 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
33213 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
33214 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
33215 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
33216 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
33217 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
33218 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
33219 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
33220 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
33221 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
33222 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
33223 | //DIG2_HDMI_GENERIC_PACKET_CONTROL3 |
33224 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
33225 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
33226 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
33227 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
33228 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
33229 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
33230 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
33231 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
33232 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
33233 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
33234 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
33235 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
33236 | //DIG2_HDMI_DB_CONTROL |
33237 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
33238 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
33239 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
33240 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
33241 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
33242 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
33243 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
33244 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
33245 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
33246 | #define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
33247 | //DIG2_AFMT_MPEG_INFO0 |
33248 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
33249 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
33250 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
33251 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
33252 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
33253 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
33254 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
33255 | #define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
33256 | //DIG2_AFMT_MPEG_INFO1 |
33257 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
33258 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
33259 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
33260 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
33261 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
33262 | #define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
33263 | //DIG2_AFMT_GENERIC_HDR |
33264 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
33265 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
33266 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
33267 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
33268 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
33269 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
33270 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
33271 | #define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
33272 | //DIG2_AFMT_GENERIC_0 |
33273 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
33274 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
33275 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
33276 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
33277 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
33278 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
33279 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
33280 | #define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
33281 | //DIG2_AFMT_GENERIC_1 |
33282 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
33283 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
33284 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
33285 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
33286 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
33287 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
33288 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
33289 | #define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
33290 | //DIG2_AFMT_GENERIC_2 |
33291 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
33292 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
33293 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
33294 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
33295 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
33296 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
33297 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
33298 | #define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
33299 | //DIG2_AFMT_GENERIC_3 |
33300 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
33301 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
33302 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
33303 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
33304 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
33305 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
33306 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
33307 | #define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
33308 | //DIG2_AFMT_GENERIC_4 |
33309 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
33310 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
33311 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
33312 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
33313 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
33314 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
33315 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
33316 | #define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
33317 | //DIG2_AFMT_GENERIC_5 |
33318 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
33319 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
33320 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
33321 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
33322 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
33323 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
33324 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
33325 | #define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
33326 | //DIG2_AFMT_GENERIC_6 |
33327 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
33328 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
33329 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
33330 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
33331 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
33332 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
33333 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
33334 | #define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
33335 | //DIG2_AFMT_GENERIC_7 |
33336 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
33337 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
33338 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
33339 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
33340 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
33341 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
33342 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
33343 | #define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
33344 | //DIG2_HDMI_GENERIC_PACKET_CONTROL1 |
33345 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
33346 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
33347 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
33348 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
33349 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
33350 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
33351 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
33352 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
33353 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
33354 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
33355 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
33356 | #define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
33357 | //DIG2_HDMI_ACR_32_0 |
33358 | #define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
33359 | #define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
33360 | //DIG2_HDMI_ACR_32_1 |
33361 | #define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
33362 | #define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
33363 | //DIG2_HDMI_ACR_44_0 |
33364 | #define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
33365 | #define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
33366 | //DIG2_HDMI_ACR_44_1 |
33367 | #define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
33368 | #define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
33369 | //DIG2_HDMI_ACR_48_0 |
33370 | #define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
33371 | #define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
33372 | //DIG2_HDMI_ACR_48_1 |
33373 | #define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
33374 | #define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
33375 | //DIG2_HDMI_ACR_STATUS_0 |
33376 | #define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
33377 | #define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
33378 | //DIG2_HDMI_ACR_STATUS_1 |
33379 | #define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
33380 | #define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
33381 | //DIG2_AFMT_AUDIO_INFO0 |
33382 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
33383 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
33384 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
33385 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
33386 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
33387 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
33388 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
33389 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
33390 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
33391 | #define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
33392 | //DIG2_AFMT_AUDIO_INFO1 |
33393 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
33394 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
33395 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
33396 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
33397 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
33398 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
33399 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
33400 | #define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
33401 | //DIG2_AFMT_60958_0 |
33402 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
33403 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
33404 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
33405 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
33406 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
33407 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
33408 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
33409 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
33410 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
33411 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
33412 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
33413 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
33414 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
33415 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
33416 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
33417 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
33418 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
33419 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
33420 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
33421 | #define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
33422 | //DIG2_AFMT_60958_1 |
33423 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
33424 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
33425 | #define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
33426 | #define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
33427 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
33428 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
33429 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
33430 | #define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
33431 | #define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
33432 | #define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
33433 | //DIG2_AFMT_AUDIO_CRC_CONTROL |
33434 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
33435 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
33436 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
33437 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
33438 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
33439 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
33440 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
33441 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
33442 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
33443 | #define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
33444 | //DIG2_AFMT_RAMP_CONTROL0 |
33445 | #define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
33446 | #define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
33447 | #define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
33448 | #define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
33449 | //DIG2_AFMT_RAMP_CONTROL1 |
33450 | #define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
33451 | #define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
33452 | #define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
33453 | #define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
33454 | //DIG2_AFMT_RAMP_CONTROL2 |
33455 | #define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
33456 | #define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
33457 | //DIG2_AFMT_RAMP_CONTROL3 |
33458 | #define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
33459 | #define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
33460 | //DIG2_AFMT_60958_2 |
33461 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
33462 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
33463 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
33464 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
33465 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
33466 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
33467 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
33468 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
33469 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
33470 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
33471 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
33472 | #define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
33473 | //DIG2_AFMT_AUDIO_CRC_RESULT |
33474 | #define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
33475 | #define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
33476 | #define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
33477 | #define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
33478 | //DIG2_AFMT_STATUS |
33479 | #define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
33480 | #define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
33481 | #define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
33482 | #define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
33483 | #define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
33484 | #define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
33485 | #define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
33486 | #define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
33487 | //DIG2_AFMT_AUDIO_PACKET_CONTROL |
33488 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
33489 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
33490 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
33491 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
33492 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
33493 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
33494 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
33495 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
33496 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
33497 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
33498 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
33499 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
33500 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
33501 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
33502 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
33503 | #define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
33504 | //DIG2_AFMT_VBI_PACKET_CONTROL |
33505 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
33506 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
33507 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
33508 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
33509 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
33510 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
33511 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
33512 | #define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
33513 | //DIG2_AFMT_INFOFRAME_CONTROL0 |
33514 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
33515 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
33516 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
33517 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
33518 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
33519 | #define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
33520 | //DIG2_AFMT_AUDIO_SRC_CONTROL |
33521 | #define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
33522 | #define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
33523 | //DIG2_DIG_BE_CNTL |
33524 | #define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
33525 | #define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
33526 | #define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
33527 | #define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
33528 | #define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
33529 | #define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
33530 | #define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
33531 | #define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
33532 | #define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
33533 | #define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
33534 | //DIG2_DIG_BE_EN_CNTL |
33535 | #define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
33536 | #define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
33537 | #define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
33538 | #define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
33539 | //DIG2_TMDS_CNTL |
33540 | #define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
33541 | #define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
33542 | //DIG2_TMDS_CONTROL_CHAR |
33543 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
33544 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
33545 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
33546 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
33547 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
33548 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
33549 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
33550 | #define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
33551 | //DIG2_TMDS_CONTROL0_FEEDBACK |
33552 | #define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
33553 | #define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
33554 | #define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
33555 | #define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
33556 | //DIG2_TMDS_STEREOSYNC_CTL_SEL |
33557 | #define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
33558 | #define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
33559 | //DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 |
33560 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
33561 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
33562 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
33563 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
33564 | //DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 |
33565 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
33566 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
33567 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
33568 | #define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
33569 | //DIG2_TMDS_CTL_BITS |
33570 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
33571 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
33572 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
33573 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
33574 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
33575 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
33576 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
33577 | #define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
33578 | //DIG2_TMDS_DCBALANCER_CONTROL |
33579 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
33580 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
33581 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
33582 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
33583 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
33584 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
33585 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
33586 | #define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
33587 | //DIG2_TMDS_CTL0_1_GEN_CNTL |
33588 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
33589 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
33590 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
33591 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
33592 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
33593 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
33594 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
33595 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
33596 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
33597 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
33598 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
33599 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
33600 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
33601 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
33602 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
33603 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
33604 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
33605 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
33606 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
33607 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
33608 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
33609 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
33610 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
33611 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
33612 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
33613 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
33614 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
33615 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
33616 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
33617 | #define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
33618 | //DIG2_TMDS_CTL2_3_GEN_CNTL |
33619 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
33620 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
33621 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
33622 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
33623 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
33624 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
33625 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
33626 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
33627 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
33628 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
33629 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
33630 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
33631 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
33632 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
33633 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
33634 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
33635 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
33636 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
33637 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
33638 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
33639 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
33640 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
33641 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
33642 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
33643 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
33644 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
33645 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
33646 | #define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
33647 | //DIG2_DIG_VERSION |
33648 | #define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
33649 | #define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
33650 | //DIG2_DIG_LANE_ENABLE |
33651 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
33652 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
33653 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
33654 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
33655 | #define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
33656 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
33657 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
33658 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
33659 | #define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
33660 | #define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
33661 | //DIG2_AFMT_CNTL |
33662 | #define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
33663 | #define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
33664 | #define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
33665 | #define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
33666 | //DIG2_AFMT_VBI_PACKET_CONTROL1 |
33667 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
33668 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
33669 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
33670 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
33671 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
33672 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
33673 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
33674 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
33675 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
33676 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
33677 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
33678 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
33679 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
33680 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
33681 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
33682 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
33683 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
33684 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
33685 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
33686 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
33687 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
33688 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
33689 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
33690 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
33691 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
33692 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
33693 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
33694 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
33695 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
33696 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
33697 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
33698 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
33699 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
33700 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
33701 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
33702 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
33703 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
33704 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
33705 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
33706 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
33707 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
33708 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
33709 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
33710 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
33711 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
33712 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
33713 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
33714 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
33715 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
33716 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
33717 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
33718 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
33719 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
33720 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
33721 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
33722 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
33723 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
33724 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
33725 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
33726 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
33727 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
33728 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
33729 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
33730 | #define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
33731 | |
33732 | |
33733 | // addressBlock: dce_dc_dio_dp2_dispdec |
33734 | //DP2_DP_LINK_CNTL |
33735 | #define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
33736 | #define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
33737 | #define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
33738 | #define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
33739 | #define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
33740 | #define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
33741 | //DP2_DP_PIXEL_FORMAT |
33742 | #define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
33743 | #define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
33744 | #define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
33745 | #define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
33746 | #define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
33747 | #define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
33748 | //DP2_DP_MSA_COLORIMETRY |
33749 | #define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
33750 | #define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
33751 | //DP2_DP_CONFIG |
33752 | #define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
33753 | #define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
33754 | //DP2_DP_VID_STREAM_CNTL |
33755 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
33756 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
33757 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
33758 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
33759 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
33760 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
33761 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
33762 | #define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
33763 | //DP2_DP_STEER_FIFO |
33764 | #define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
33765 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
33766 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
33767 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
33768 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
33769 | #define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
33770 | #define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
33771 | #define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
33772 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
33773 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
33774 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
33775 | #define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
33776 | #define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
33777 | #define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
33778 | //DP2_DP_MSA_MISC |
33779 | #define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
33780 | #define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
33781 | #define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
33782 | #define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
33783 | #define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
33784 | #define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
33785 | #define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
33786 | #define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
33787 | //DP2_DP_VID_TIMING |
33788 | #define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
33789 | #define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
33790 | #define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
33791 | #define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
33792 | #define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
33793 | #define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
33794 | #define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
33795 | #define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
33796 | #define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
33797 | #define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
33798 | //DP2_DP_VID_N |
33799 | #define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 |
33800 | #define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
33801 | //DP2_DP_VID_M |
33802 | #define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 |
33803 | #define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
33804 | //DP2_DP_LINK_FRAMING_CNTL |
33805 | #define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
33806 | #define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
33807 | #define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
33808 | #define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
33809 | #define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
33810 | #define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
33811 | //DP2_DP_HBR2_EYE_PATTERN |
33812 | #define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
33813 | #define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
33814 | //DP2_DP_VID_MSA_VBID |
33815 | #define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
33816 | #define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
33817 | #define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
33818 | #define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
33819 | //DP2_DP_VID_INTERRUPT_CNTL |
33820 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
33821 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
33822 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
33823 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
33824 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
33825 | #define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
33826 | //DP2_DP_DPHY_CNTL |
33827 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
33828 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
33829 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
33830 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
33831 | #define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
33832 | #define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
33833 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
33834 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
33835 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
33836 | #define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
33837 | #define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
33838 | #define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
33839 | //DP2_DP_DPHY_TRAINING_PATTERN_SEL |
33840 | #define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
33841 | #define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
33842 | //DP2_DP_DPHY_SYM0 |
33843 | #define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
33844 | #define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
33845 | #define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
33846 | #define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
33847 | #define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
33848 | #define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
33849 | //DP2_DP_DPHY_SYM1 |
33850 | #define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
33851 | #define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
33852 | #define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
33853 | #define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
33854 | #define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
33855 | #define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
33856 | //DP2_DP_DPHY_SYM2 |
33857 | #define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
33858 | #define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
33859 | #define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
33860 | #define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
33861 | //DP2_DP_DPHY_8B10B_CNTL |
33862 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
33863 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
33864 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
33865 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
33866 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
33867 | #define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
33868 | //DP2_DP_DPHY_PRBS_CNTL |
33869 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
33870 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
33871 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
33872 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
33873 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
33874 | #define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
33875 | //DP2_DP_DPHY_SCRAM_CNTL |
33876 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
33877 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
33878 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
33879 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
33880 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
33881 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
33882 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
33883 | #define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
33884 | //DP2_DP_DPHY_CRC_EN |
33885 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
33886 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
33887 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
33888 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
33889 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
33890 | #define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
33891 | //DP2_DP_DPHY_CRC_CNTL |
33892 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
33893 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
33894 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
33895 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
33896 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
33897 | #define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
33898 | //DP2_DP_DPHY_CRC_RESULT |
33899 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
33900 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
33901 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
33902 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
33903 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
33904 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
33905 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
33906 | #define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
33907 | //DP2_DP_DPHY_CRC_MST_CNTL |
33908 | #define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
33909 | #define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
33910 | #define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
33911 | #define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
33912 | //DP2_DP_DPHY_CRC_MST_STATUS |
33913 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
33914 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
33915 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
33916 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
33917 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
33918 | #define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
33919 | //DP2_DP_DPHY_FAST_TRAINING |
33920 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
33921 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
33922 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
33923 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
33924 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
33925 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
33926 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
33927 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
33928 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
33929 | #define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
33930 | //DP2_DP_DPHY_FAST_TRAINING_STATUS |
33931 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
33932 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
33933 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
33934 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
33935 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
33936 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
33937 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
33938 | #define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
33939 | //DP2_DP_SEC_CNTL |
33940 | #define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
33941 | #define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
33942 | #define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
33943 | #define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
33944 | #define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
33945 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
33946 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
33947 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
33948 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
33949 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
33950 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
33951 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
33952 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
33953 | #define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
33954 | #define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
33955 | #define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
33956 | #define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
33957 | #define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
33958 | #define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
33959 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
33960 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
33961 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
33962 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
33963 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
33964 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
33965 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
33966 | #define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
33967 | #define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
33968 | //DP2_DP_SEC_CNTL1 |
33969 | #define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
33970 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
33971 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
33972 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
33973 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
33974 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
33975 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
33976 | #define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
33977 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
33978 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
33979 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
33980 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
33981 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
33982 | #define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
33983 | //DP2_DP_SEC_FRAMING1 |
33984 | #define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
33985 | #define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
33986 | #define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
33987 | #define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
33988 | //DP2_DP_SEC_FRAMING2 |
33989 | #define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
33990 | #define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
33991 | #define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
33992 | #define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
33993 | //DP2_DP_SEC_FRAMING3 |
33994 | #define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
33995 | #define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
33996 | #define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
33997 | #define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
33998 | //DP2_DP_SEC_FRAMING4 |
33999 | #define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
34000 | #define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
34001 | #define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
34002 | #define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
34003 | #define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
34004 | #define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
34005 | #define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
34006 | #define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
34007 | //DP2_DP_SEC_AUD_N |
34008 | #define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
34009 | #define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
34010 | //DP2_DP_SEC_AUD_N_READBACK |
34011 | #define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
34012 | #define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
34013 | //DP2_DP_SEC_AUD_M |
34014 | #define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
34015 | #define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
34016 | //DP2_DP_SEC_AUD_M_READBACK |
34017 | #define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
34018 | #define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
34019 | //DP2_DP_SEC_TIMESTAMP |
34020 | #define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
34021 | #define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
34022 | //DP2_DP_SEC_PACKET_CNTL |
34023 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
34024 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
34025 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
34026 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
34027 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
34028 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
34029 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
34030 | #define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
34031 | //DP2_DP_MSE_RATE_CNTL |
34032 | #define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
34033 | #define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
34034 | #define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
34035 | #define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
34036 | //DP2_DP_MSE_RATE_UPDATE |
34037 | #define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
34038 | #define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
34039 | //DP2_DP_MSE_SAT0 |
34040 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
34041 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
34042 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
34043 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
34044 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
34045 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
34046 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
34047 | #define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
34048 | //DP2_DP_MSE_SAT1 |
34049 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
34050 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
34051 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
34052 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
34053 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
34054 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
34055 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
34056 | #define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
34057 | //DP2_DP_MSE_SAT2 |
34058 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
34059 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
34060 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
34061 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
34062 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
34063 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
34064 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
34065 | #define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
34066 | //DP2_DP_MSE_SAT_UPDATE |
34067 | #define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
34068 | #define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
34069 | #define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
34070 | #define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
34071 | //DP2_DP_MSE_LINK_TIMING |
34072 | #define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
34073 | #define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
34074 | #define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
34075 | #define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
34076 | //DP2_DP_MSE_MISC_CNTL |
34077 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
34078 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
34079 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
34080 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
34081 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
34082 | #define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
34083 | //DP2_DP_DPHY_BS_SR_SWAP_CNTL |
34084 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
34085 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
34086 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
34087 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
34088 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
34089 | #define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
34090 | //DP2_DP_DPHY_HBR2_PATTERN_CONTROL |
34091 | #define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
34092 | #define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
34093 | //DP2_DP_MSE_SAT0_STATUS |
34094 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
34095 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
34096 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
34097 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
34098 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
34099 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
34100 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
34101 | #define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
34102 | //DP2_DP_MSE_SAT1_STATUS |
34103 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
34104 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
34105 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
34106 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
34107 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
34108 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
34109 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
34110 | #define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
34111 | //DP2_DP_MSE_SAT2_STATUS |
34112 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
34113 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
34114 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
34115 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
34116 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
34117 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
34118 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
34119 | #define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
34120 | //DP2_DP_MSA_TIMING_PARAM1 |
34121 | #define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
34122 | #define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
34123 | #define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
34124 | #define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
34125 | //DP2_DP_MSA_TIMING_PARAM2 |
34126 | #define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
34127 | #define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
34128 | #define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
34129 | #define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
34130 | //DP2_DP_MSA_TIMING_PARAM3 |
34131 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
34132 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
34133 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
34134 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
34135 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
34136 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
34137 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
34138 | #define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
34139 | //DP2_DP_MSA_TIMING_PARAM4 |
34140 | #define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
34141 | #define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
34142 | #define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
34143 | #define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
34144 | //DP2_DP_MSO_CNTL |
34145 | #define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
34146 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
34147 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
34148 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
34149 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
34150 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
34151 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
34152 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
34153 | #define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
34154 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
34155 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
34156 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
34157 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
34158 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
34159 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
34160 | #define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
34161 | //DP2_DP_MSO_CNTL1 |
34162 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
34163 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
34164 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
34165 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
34166 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
34167 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
34168 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
34169 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
34170 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
34171 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
34172 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
34173 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
34174 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
34175 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
34176 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
34177 | #define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
34178 | //DP2_DP_DSC_CNTL |
34179 | #define DP2_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
34180 | #define DP2_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
34181 | //DP2_DP_SEC_CNTL2 |
34182 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
34183 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
34184 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
34185 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
34186 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
34187 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
34188 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
34189 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
34190 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
34191 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
34192 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
34193 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
34194 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
34195 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
34196 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
34197 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
34198 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
34199 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
34200 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
34201 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
34202 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
34203 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
34204 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
34205 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
34206 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
34207 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
34208 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
34209 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
34210 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
34211 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
34212 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
34213 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
34214 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
34215 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
34216 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
34217 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
34218 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
34219 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
34220 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
34221 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
34222 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
34223 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
34224 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
34225 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
34226 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
34227 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
34228 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
34229 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
34230 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
34231 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
34232 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
34233 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
34234 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
34235 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
34236 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
34237 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
34238 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
34239 | #define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
34240 | //DP2_DP_SEC_CNTL3 |
34241 | #define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
34242 | #define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
34243 | #define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
34244 | #define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
34245 | //DP2_DP_SEC_CNTL4 |
34246 | #define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
34247 | #define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
34248 | #define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
34249 | #define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
34250 | //DP2_DP_SEC_CNTL5 |
34251 | #define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
34252 | #define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
34253 | #define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
34254 | #define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
34255 | //DP2_DP_SEC_CNTL6 |
34256 | #define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
34257 | #define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
34258 | //DP2_DP_SEC_CNTL7 |
34259 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
34260 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
34261 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
34262 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
34263 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
34264 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
34265 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
34266 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
34267 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
34268 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
34269 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
34270 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
34271 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
34272 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
34273 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
34274 | #define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
34275 | //DP2_DP_DB_CNTL |
34276 | #define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
34277 | #define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
34278 | #define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
34279 | #define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
34280 | #define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
34281 | #define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
34282 | #define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
34283 | #define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
34284 | #define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
34285 | #define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
34286 | //DP2_DP_MSA_VBID_MISC |
34287 | #define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
34288 | #define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
34289 | #define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
34290 | #define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
34291 | #define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
34292 | #define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
34293 | #define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
34294 | #define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
34295 | #define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
34296 | #define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
34297 | #define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
34298 | #define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
34299 | |
34300 | |
34301 | // addressBlock: dce_dc_dio_dig3_dispdec |
34302 | //DIG3_DIG_FE_CNTL |
34303 | #define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
34304 | #define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
34305 | #define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
34306 | #define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
34307 | #define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
34308 | #define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
34309 | #define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
34310 | #define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
34311 | #define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
34312 | #define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
34313 | #define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
34314 | #define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
34315 | #define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
34316 | #define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
34317 | #define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
34318 | #define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
34319 | //DIG3_DIG_OUTPUT_CRC_CNTL |
34320 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
34321 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
34322 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
34323 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
34324 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
34325 | #define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
34326 | //DIG3_DIG_OUTPUT_CRC_RESULT |
34327 | #define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
34328 | #define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
34329 | //DIG3_DIG_CLOCK_PATTERN |
34330 | #define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
34331 | #define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
34332 | //DIG3_DIG_TEST_PATTERN |
34333 | #define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
34334 | #define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
34335 | #define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
34336 | #define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
34337 | #define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
34338 | #define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
34339 | #define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
34340 | #define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
34341 | #define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
34342 | #define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
34343 | #define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
34344 | #define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
34345 | //DIG3_DIG_RANDOM_PATTERN_SEED |
34346 | #define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
34347 | #define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
34348 | #define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
34349 | #define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
34350 | //DIG3_DIG_FIFO_STATUS |
34351 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
34352 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
34353 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
34354 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
34355 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
34356 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
34357 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
34358 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
34359 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
34360 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
34361 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
34362 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
34363 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
34364 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
34365 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
34366 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
34367 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
34368 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
34369 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
34370 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
34371 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
34372 | #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
34373 | //DIG3_HDMI_CONTROL |
34374 | #define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
34375 | #define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
34376 | #define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
34377 | #define 0x3 |
34378 | #define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
34379 | #define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
34380 | #define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
34381 | #define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
34382 | #define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
34383 | #define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
34384 | #define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
34385 | #define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
34386 | #define 0x00000008L |
34387 | #define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
34388 | #define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
34389 | #define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
34390 | #define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
34391 | #define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
34392 | //DIG3_HDMI_STATUS |
34393 | #define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
34394 | #define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
34395 | #define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
34396 | #define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
34397 | #define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
34398 | #define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
34399 | #define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
34400 | #define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
34401 | //DIG3_HDMI_AUDIO_PACKET_CONTROL |
34402 | #define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
34403 | #define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
34404 | #define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
34405 | #define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
34406 | //DIG3_HDMI_ACR_PACKET_CONTROL |
34407 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
34408 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
34409 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
34410 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
34411 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
34412 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
34413 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
34414 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
34415 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
34416 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
34417 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
34418 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
34419 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
34420 | #define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
34421 | //DIG3_HDMI_VBI_PACKET_CONTROL |
34422 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
34423 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
34424 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
34425 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
34426 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
34427 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
34428 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
34429 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
34430 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
34431 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
34432 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
34433 | #define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
34434 | //DIG3_HDMI_INFOFRAME_CONTROL0 |
34435 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
34436 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
34437 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
34438 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
34439 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
34440 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
34441 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
34442 | #define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
34443 | //DIG3_HDMI_INFOFRAME_CONTROL1 |
34444 | #define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
34445 | #define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
34446 | #define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
34447 | #define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
34448 | //DIG3_HDMI_GENERIC_PACKET_CONTROL0 |
34449 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
34450 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
34451 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
34452 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
34453 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
34454 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
34455 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
34456 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
34457 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
34458 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
34459 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
34460 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
34461 | //DIG3_AFMT_INTERRUPT_STATUS |
34462 | //DIG3_HDMI_GC |
34463 | #define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
34464 | #define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
34465 | #define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
34466 | #define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
34467 | #define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
34468 | #define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
34469 | #define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
34470 | #define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
34471 | #define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
34472 | #define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
34473 | //DIG3_AFMT_AUDIO_PACKET_CONTROL2 |
34474 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
34475 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
34476 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
34477 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
34478 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
34479 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
34480 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
34481 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
34482 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
34483 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
34484 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
34485 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
34486 | //DIG3_AFMT_ISRC1_0 |
34487 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
34488 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
34489 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
34490 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
34491 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
34492 | #define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
34493 | //DIG3_AFMT_ISRC1_1 |
34494 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
34495 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
34496 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
34497 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
34498 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
34499 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
34500 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
34501 | #define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
34502 | //DIG3_AFMT_ISRC1_2 |
34503 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
34504 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
34505 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
34506 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
34507 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
34508 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
34509 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
34510 | #define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
34511 | //DIG3_AFMT_ISRC1_3 |
34512 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
34513 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
34514 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
34515 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
34516 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
34517 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
34518 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
34519 | #define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
34520 | //DIG3_AFMT_ISRC1_4 |
34521 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
34522 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
34523 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
34524 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
34525 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
34526 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
34527 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
34528 | #define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
34529 | //DIG3_AFMT_ISRC2_0 |
34530 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
34531 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
34532 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
34533 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
34534 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
34535 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
34536 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
34537 | #define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
34538 | //DIG3_AFMT_ISRC2_1 |
34539 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
34540 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
34541 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
34542 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
34543 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
34544 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
34545 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
34546 | #define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
34547 | //DIG3_AFMT_ISRC2_2 |
34548 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
34549 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
34550 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
34551 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
34552 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
34553 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
34554 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
34555 | #define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
34556 | //DIG3_AFMT_ISRC2_3 |
34557 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
34558 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
34559 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
34560 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
34561 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
34562 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
34563 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
34564 | #define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
34565 | //DIG3_HDMI_GENERIC_PACKET_CONTROL2 |
34566 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
34567 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
34568 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
34569 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
34570 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
34571 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
34572 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
34573 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
34574 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
34575 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
34576 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
34577 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
34578 | //DIG3_HDMI_GENERIC_PACKET_CONTROL3 |
34579 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
34580 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
34581 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
34582 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
34583 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
34584 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
34585 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
34586 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
34587 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
34588 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
34589 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
34590 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
34591 | //DIG3_HDMI_DB_CONTROL |
34592 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
34593 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
34594 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
34595 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
34596 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
34597 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
34598 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
34599 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
34600 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
34601 | #define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
34602 | //DIG3_AFMT_MPEG_INFO0 |
34603 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
34604 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
34605 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
34606 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
34607 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
34608 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
34609 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
34610 | #define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
34611 | //DIG3_AFMT_MPEG_INFO1 |
34612 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
34613 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
34614 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
34615 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
34616 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
34617 | #define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
34618 | //DIG3_AFMT_GENERIC_HDR |
34619 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
34620 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
34621 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
34622 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
34623 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
34624 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
34625 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
34626 | #define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
34627 | //DIG3_AFMT_GENERIC_0 |
34628 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
34629 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
34630 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
34631 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
34632 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
34633 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
34634 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
34635 | #define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
34636 | //DIG3_AFMT_GENERIC_1 |
34637 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
34638 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
34639 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
34640 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
34641 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
34642 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
34643 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
34644 | #define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
34645 | //DIG3_AFMT_GENERIC_2 |
34646 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
34647 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
34648 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
34649 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
34650 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
34651 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
34652 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
34653 | #define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
34654 | //DIG3_AFMT_GENERIC_3 |
34655 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
34656 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
34657 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
34658 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
34659 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
34660 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
34661 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
34662 | #define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
34663 | //DIG3_AFMT_GENERIC_4 |
34664 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
34665 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
34666 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
34667 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
34668 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
34669 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
34670 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
34671 | #define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
34672 | //DIG3_AFMT_GENERIC_5 |
34673 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
34674 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
34675 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
34676 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
34677 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
34678 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
34679 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
34680 | #define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
34681 | //DIG3_AFMT_GENERIC_6 |
34682 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
34683 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
34684 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
34685 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
34686 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
34687 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
34688 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
34689 | #define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
34690 | //DIG3_AFMT_GENERIC_7 |
34691 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
34692 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
34693 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
34694 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
34695 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
34696 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
34697 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
34698 | #define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
34699 | //DIG3_HDMI_GENERIC_PACKET_CONTROL1 |
34700 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
34701 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
34702 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
34703 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
34704 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
34705 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
34706 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
34707 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
34708 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
34709 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
34710 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
34711 | #define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
34712 | //DIG3_HDMI_ACR_32_0 |
34713 | #define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
34714 | #define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
34715 | //DIG3_HDMI_ACR_32_1 |
34716 | #define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
34717 | #define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
34718 | //DIG3_HDMI_ACR_44_0 |
34719 | #define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
34720 | #define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
34721 | //DIG3_HDMI_ACR_44_1 |
34722 | #define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
34723 | #define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
34724 | //DIG3_HDMI_ACR_48_0 |
34725 | #define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
34726 | #define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
34727 | //DIG3_HDMI_ACR_48_1 |
34728 | #define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
34729 | #define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
34730 | //DIG3_HDMI_ACR_STATUS_0 |
34731 | #define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
34732 | #define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
34733 | //DIG3_HDMI_ACR_STATUS_1 |
34734 | #define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
34735 | #define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
34736 | //DIG3_AFMT_AUDIO_INFO0 |
34737 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
34738 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
34739 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
34740 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
34741 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
34742 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
34743 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
34744 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
34745 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
34746 | #define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
34747 | //DIG3_AFMT_AUDIO_INFO1 |
34748 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
34749 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
34750 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
34751 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
34752 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
34753 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
34754 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
34755 | #define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
34756 | //DIG3_AFMT_60958_0 |
34757 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
34758 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
34759 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
34760 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
34761 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
34762 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
34763 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
34764 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
34765 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
34766 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
34767 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
34768 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
34769 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
34770 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
34771 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
34772 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
34773 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
34774 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
34775 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
34776 | #define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
34777 | //DIG3_AFMT_60958_1 |
34778 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
34779 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
34780 | #define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
34781 | #define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
34782 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
34783 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
34784 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
34785 | #define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
34786 | #define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
34787 | #define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
34788 | //DIG3_AFMT_AUDIO_CRC_CONTROL |
34789 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
34790 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
34791 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
34792 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
34793 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
34794 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
34795 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
34796 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
34797 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
34798 | #define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
34799 | //DIG3_AFMT_RAMP_CONTROL0 |
34800 | #define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
34801 | #define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
34802 | #define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
34803 | #define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
34804 | //DIG3_AFMT_RAMP_CONTROL1 |
34805 | #define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
34806 | #define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
34807 | #define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
34808 | #define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
34809 | //DIG3_AFMT_RAMP_CONTROL2 |
34810 | #define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
34811 | #define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
34812 | //DIG3_AFMT_RAMP_CONTROL3 |
34813 | #define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
34814 | #define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
34815 | //DIG3_AFMT_60958_2 |
34816 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
34817 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
34818 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
34819 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
34820 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
34821 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
34822 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
34823 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
34824 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
34825 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
34826 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
34827 | #define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
34828 | //DIG3_AFMT_AUDIO_CRC_RESULT |
34829 | #define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
34830 | #define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
34831 | #define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
34832 | #define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
34833 | //DIG3_AFMT_STATUS |
34834 | #define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
34835 | #define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
34836 | #define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
34837 | #define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
34838 | #define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
34839 | #define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
34840 | #define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
34841 | #define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
34842 | //DIG3_AFMT_AUDIO_PACKET_CONTROL |
34843 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
34844 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
34845 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
34846 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
34847 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
34848 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
34849 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
34850 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
34851 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
34852 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
34853 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
34854 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
34855 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
34856 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
34857 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
34858 | #define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
34859 | //DIG3_AFMT_VBI_PACKET_CONTROL |
34860 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
34861 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
34862 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
34863 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
34864 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
34865 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
34866 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
34867 | #define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
34868 | //DIG3_AFMT_INFOFRAME_CONTROL0 |
34869 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
34870 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
34871 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
34872 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
34873 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
34874 | #define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
34875 | //DIG3_AFMT_AUDIO_SRC_CONTROL |
34876 | #define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
34877 | #define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
34878 | //DIG3_DIG_BE_CNTL |
34879 | #define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
34880 | #define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
34881 | #define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
34882 | #define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
34883 | #define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
34884 | #define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
34885 | #define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
34886 | #define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
34887 | #define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
34888 | #define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
34889 | //DIG3_DIG_BE_EN_CNTL |
34890 | #define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
34891 | #define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
34892 | #define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
34893 | #define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
34894 | //DIG3_TMDS_CNTL |
34895 | #define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
34896 | #define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
34897 | //DIG3_TMDS_CONTROL_CHAR |
34898 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
34899 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
34900 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
34901 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
34902 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
34903 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
34904 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
34905 | #define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
34906 | //DIG3_TMDS_CONTROL0_FEEDBACK |
34907 | #define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
34908 | #define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
34909 | #define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
34910 | #define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
34911 | //DIG3_TMDS_STEREOSYNC_CTL_SEL |
34912 | #define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
34913 | #define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
34914 | //DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 |
34915 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
34916 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
34917 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
34918 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
34919 | //DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 |
34920 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
34921 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
34922 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
34923 | #define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
34924 | //DIG3_TMDS_CTL_BITS |
34925 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
34926 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
34927 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
34928 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
34929 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
34930 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
34931 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
34932 | #define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
34933 | //DIG3_TMDS_DCBALANCER_CONTROL |
34934 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
34935 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
34936 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
34937 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
34938 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
34939 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
34940 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
34941 | #define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
34942 | //DIG3_TMDS_CTL0_1_GEN_CNTL |
34943 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
34944 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
34945 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
34946 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
34947 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
34948 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
34949 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
34950 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
34951 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
34952 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
34953 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
34954 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
34955 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
34956 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
34957 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
34958 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
34959 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
34960 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
34961 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
34962 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
34963 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
34964 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
34965 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
34966 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
34967 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
34968 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
34969 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
34970 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
34971 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
34972 | #define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
34973 | //DIG3_TMDS_CTL2_3_GEN_CNTL |
34974 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
34975 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
34976 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
34977 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
34978 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
34979 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
34980 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
34981 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
34982 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
34983 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
34984 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
34985 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
34986 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
34987 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
34988 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
34989 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
34990 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
34991 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
34992 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
34993 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
34994 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
34995 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
34996 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
34997 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
34998 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
34999 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
35000 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
35001 | #define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
35002 | //DIG3_DIG_VERSION |
35003 | #define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
35004 | #define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
35005 | //DIG3_DIG_LANE_ENABLE |
35006 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
35007 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
35008 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
35009 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
35010 | #define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
35011 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
35012 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
35013 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
35014 | #define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
35015 | #define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
35016 | //DIG3_AFMT_CNTL |
35017 | #define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
35018 | #define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
35019 | #define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
35020 | #define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
35021 | //DIG3_AFMT_VBI_PACKET_CONTROL1 |
35022 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
35023 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
35024 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
35025 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
35026 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
35027 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
35028 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
35029 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
35030 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
35031 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
35032 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
35033 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
35034 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
35035 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
35036 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
35037 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
35038 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
35039 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
35040 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
35041 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
35042 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
35043 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
35044 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
35045 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
35046 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
35047 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
35048 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
35049 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
35050 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
35051 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
35052 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
35053 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
35054 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
35055 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
35056 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
35057 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
35058 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
35059 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
35060 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
35061 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
35062 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
35063 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
35064 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
35065 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
35066 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
35067 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
35068 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
35069 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
35070 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
35071 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
35072 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
35073 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
35074 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
35075 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
35076 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
35077 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
35078 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
35079 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
35080 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
35081 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
35082 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
35083 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
35084 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
35085 | #define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
35086 | |
35087 | |
35088 | // addressBlock: dce_dc_dio_dp3_dispdec |
35089 | //DP3_DP_LINK_CNTL |
35090 | #define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
35091 | #define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
35092 | #define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
35093 | #define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
35094 | #define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
35095 | #define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
35096 | //DP3_DP_PIXEL_FORMAT |
35097 | #define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
35098 | #define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
35099 | #define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
35100 | #define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
35101 | #define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
35102 | #define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
35103 | //DP3_DP_MSA_COLORIMETRY |
35104 | #define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
35105 | #define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
35106 | //DP3_DP_CONFIG |
35107 | #define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
35108 | #define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
35109 | //DP3_DP_VID_STREAM_CNTL |
35110 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
35111 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
35112 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
35113 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
35114 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
35115 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
35116 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
35117 | #define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
35118 | //DP3_DP_STEER_FIFO |
35119 | #define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
35120 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
35121 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
35122 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
35123 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
35124 | #define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
35125 | #define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
35126 | #define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
35127 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
35128 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
35129 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
35130 | #define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
35131 | #define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
35132 | #define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
35133 | //DP3_DP_MSA_MISC |
35134 | #define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
35135 | #define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
35136 | #define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
35137 | #define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
35138 | #define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
35139 | #define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
35140 | #define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
35141 | #define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
35142 | //DP3_DP_VID_TIMING |
35143 | #define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
35144 | #define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
35145 | #define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
35146 | #define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
35147 | #define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
35148 | #define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
35149 | #define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
35150 | #define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
35151 | #define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
35152 | #define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
35153 | //DP3_DP_VID_N |
35154 | #define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 |
35155 | #define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
35156 | //DP3_DP_VID_M |
35157 | #define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 |
35158 | #define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
35159 | //DP3_DP_LINK_FRAMING_CNTL |
35160 | #define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
35161 | #define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
35162 | #define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
35163 | #define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
35164 | #define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
35165 | #define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
35166 | //DP3_DP_HBR2_EYE_PATTERN |
35167 | #define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
35168 | #define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
35169 | //DP3_DP_VID_MSA_VBID |
35170 | #define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
35171 | #define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
35172 | #define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
35173 | #define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
35174 | //DP3_DP_VID_INTERRUPT_CNTL |
35175 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
35176 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
35177 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
35178 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
35179 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
35180 | #define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
35181 | //DP3_DP_DPHY_CNTL |
35182 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
35183 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
35184 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
35185 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
35186 | #define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
35187 | #define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
35188 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
35189 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
35190 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
35191 | #define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
35192 | #define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
35193 | #define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
35194 | //DP3_DP_DPHY_TRAINING_PATTERN_SEL |
35195 | #define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
35196 | #define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
35197 | //DP3_DP_DPHY_SYM0 |
35198 | #define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
35199 | #define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
35200 | #define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
35201 | #define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
35202 | #define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
35203 | #define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
35204 | //DP3_DP_DPHY_SYM1 |
35205 | #define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
35206 | #define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
35207 | #define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
35208 | #define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
35209 | #define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
35210 | #define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
35211 | //DP3_DP_DPHY_SYM2 |
35212 | #define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
35213 | #define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
35214 | #define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
35215 | #define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
35216 | //DP3_DP_DPHY_8B10B_CNTL |
35217 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
35218 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
35219 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
35220 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
35221 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
35222 | #define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
35223 | //DP3_DP_DPHY_PRBS_CNTL |
35224 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
35225 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
35226 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
35227 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
35228 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
35229 | #define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
35230 | //DP3_DP_DPHY_SCRAM_CNTL |
35231 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
35232 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
35233 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
35234 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
35235 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
35236 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
35237 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
35238 | #define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
35239 | //DP3_DP_DPHY_CRC_EN |
35240 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
35241 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
35242 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
35243 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
35244 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
35245 | #define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
35246 | //DP3_DP_DPHY_CRC_CNTL |
35247 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
35248 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
35249 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
35250 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
35251 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
35252 | #define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
35253 | //DP3_DP_DPHY_CRC_RESULT |
35254 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
35255 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
35256 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
35257 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
35258 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
35259 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
35260 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
35261 | #define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
35262 | //DP3_DP_DPHY_CRC_MST_CNTL |
35263 | #define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
35264 | #define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
35265 | #define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
35266 | #define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
35267 | //DP3_DP_DPHY_CRC_MST_STATUS |
35268 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
35269 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
35270 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
35271 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
35272 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
35273 | #define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
35274 | //DP3_DP_DPHY_FAST_TRAINING |
35275 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
35276 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
35277 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
35278 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
35279 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
35280 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
35281 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
35282 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
35283 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
35284 | #define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
35285 | //DP3_DP_DPHY_FAST_TRAINING_STATUS |
35286 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
35287 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
35288 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
35289 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
35290 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
35291 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
35292 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
35293 | #define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
35294 | //DP3_DP_SEC_CNTL |
35295 | #define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
35296 | #define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
35297 | #define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
35298 | #define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
35299 | #define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
35300 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
35301 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
35302 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
35303 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
35304 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
35305 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
35306 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
35307 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
35308 | #define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
35309 | #define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
35310 | #define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
35311 | #define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
35312 | #define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
35313 | #define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
35314 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
35315 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
35316 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
35317 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
35318 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
35319 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
35320 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
35321 | #define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
35322 | #define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
35323 | //DP3_DP_SEC_CNTL1 |
35324 | #define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
35325 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
35326 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
35327 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
35328 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
35329 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
35330 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
35331 | #define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
35332 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
35333 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
35334 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
35335 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
35336 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
35337 | #define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
35338 | //DP3_DP_SEC_FRAMING1 |
35339 | #define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
35340 | #define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
35341 | #define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
35342 | #define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
35343 | //DP3_DP_SEC_FRAMING2 |
35344 | #define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
35345 | #define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
35346 | #define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
35347 | #define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
35348 | //DP3_DP_SEC_FRAMING3 |
35349 | #define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
35350 | #define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
35351 | #define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
35352 | #define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
35353 | //DP3_DP_SEC_FRAMING4 |
35354 | #define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
35355 | #define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
35356 | #define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
35357 | #define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
35358 | #define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
35359 | #define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
35360 | #define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
35361 | #define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
35362 | //DP3_DP_SEC_AUD_N |
35363 | #define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
35364 | #define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
35365 | //DP3_DP_SEC_AUD_N_READBACK |
35366 | #define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
35367 | #define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
35368 | //DP3_DP_SEC_AUD_M |
35369 | #define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
35370 | #define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
35371 | //DP3_DP_SEC_AUD_M_READBACK |
35372 | #define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
35373 | #define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
35374 | //DP3_DP_SEC_TIMESTAMP |
35375 | #define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
35376 | #define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
35377 | //DP3_DP_SEC_PACKET_CNTL |
35378 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
35379 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
35380 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
35381 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
35382 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
35383 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
35384 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
35385 | #define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
35386 | //DP3_DP_MSE_RATE_CNTL |
35387 | #define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
35388 | #define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
35389 | #define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
35390 | #define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
35391 | //DP3_DP_MSE_RATE_UPDATE |
35392 | #define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
35393 | #define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
35394 | //DP3_DP_MSE_SAT0 |
35395 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
35396 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
35397 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
35398 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
35399 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
35400 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
35401 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
35402 | #define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
35403 | //DP3_DP_MSE_SAT1 |
35404 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
35405 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
35406 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
35407 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
35408 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
35409 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
35410 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
35411 | #define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
35412 | //DP3_DP_MSE_SAT2 |
35413 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
35414 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
35415 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
35416 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
35417 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
35418 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
35419 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
35420 | #define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
35421 | //DP3_DP_MSE_SAT_UPDATE |
35422 | #define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
35423 | #define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
35424 | #define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
35425 | #define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
35426 | //DP3_DP_MSE_LINK_TIMING |
35427 | #define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
35428 | #define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
35429 | #define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
35430 | #define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
35431 | //DP3_DP_MSE_MISC_CNTL |
35432 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
35433 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
35434 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
35435 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
35436 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
35437 | #define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
35438 | //DP3_DP_DPHY_BS_SR_SWAP_CNTL |
35439 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
35440 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
35441 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
35442 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
35443 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
35444 | #define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
35445 | //DP3_DP_DPHY_HBR2_PATTERN_CONTROL |
35446 | #define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
35447 | #define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
35448 | //DP3_DP_MSE_SAT0_STATUS |
35449 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
35450 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
35451 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
35452 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
35453 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
35454 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
35455 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
35456 | #define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
35457 | //DP3_DP_MSE_SAT1_STATUS |
35458 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
35459 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
35460 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
35461 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
35462 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
35463 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
35464 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
35465 | #define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
35466 | //DP3_DP_MSE_SAT2_STATUS |
35467 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
35468 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
35469 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
35470 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
35471 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
35472 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
35473 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
35474 | #define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
35475 | //DP3_DP_MSA_TIMING_PARAM1 |
35476 | #define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
35477 | #define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
35478 | #define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
35479 | #define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
35480 | //DP3_DP_MSA_TIMING_PARAM2 |
35481 | #define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
35482 | #define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
35483 | #define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
35484 | #define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
35485 | //DP3_DP_MSA_TIMING_PARAM3 |
35486 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
35487 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
35488 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
35489 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
35490 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
35491 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
35492 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
35493 | #define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
35494 | //DP3_DP_MSA_TIMING_PARAM4 |
35495 | #define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
35496 | #define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
35497 | #define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
35498 | #define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
35499 | //DP3_DP_MSO_CNTL |
35500 | #define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
35501 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
35502 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
35503 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
35504 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
35505 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
35506 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
35507 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
35508 | #define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
35509 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
35510 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
35511 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
35512 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
35513 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
35514 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
35515 | #define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
35516 | //DP3_DP_MSO_CNTL1 |
35517 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
35518 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
35519 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
35520 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
35521 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
35522 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
35523 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
35524 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
35525 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
35526 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
35527 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
35528 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
35529 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
35530 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
35531 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
35532 | #define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
35533 | //DP3_DP_DSC_CNTL |
35534 | #define DP3_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
35535 | #define DP3_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
35536 | //DP3_DP_SEC_CNTL2 |
35537 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
35538 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
35539 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
35540 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
35541 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
35542 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
35543 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
35544 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
35545 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
35546 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
35547 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
35548 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
35549 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
35550 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
35551 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
35552 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
35553 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
35554 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
35555 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
35556 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
35557 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
35558 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
35559 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
35560 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
35561 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
35562 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
35563 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
35564 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
35565 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
35566 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
35567 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
35568 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
35569 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
35570 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
35571 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
35572 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
35573 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
35574 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
35575 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
35576 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
35577 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
35578 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
35579 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
35580 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
35581 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
35582 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
35583 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
35584 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
35585 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
35586 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
35587 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
35588 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
35589 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
35590 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
35591 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
35592 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
35593 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
35594 | #define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
35595 | //DP3_DP_SEC_CNTL3 |
35596 | #define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
35597 | #define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
35598 | #define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
35599 | #define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
35600 | //DP3_DP_SEC_CNTL4 |
35601 | #define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
35602 | #define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
35603 | #define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
35604 | #define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
35605 | //DP3_DP_SEC_CNTL5 |
35606 | #define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
35607 | #define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
35608 | #define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
35609 | #define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
35610 | //DP3_DP_SEC_CNTL6 |
35611 | #define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
35612 | #define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
35613 | //DP3_DP_SEC_CNTL7 |
35614 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
35615 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
35616 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
35617 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
35618 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
35619 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
35620 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
35621 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
35622 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
35623 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
35624 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
35625 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
35626 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
35627 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
35628 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
35629 | #define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
35630 | //DP3_DP_DB_CNTL |
35631 | #define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
35632 | #define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
35633 | #define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
35634 | #define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
35635 | #define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
35636 | #define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
35637 | #define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
35638 | #define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
35639 | #define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
35640 | #define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
35641 | //DP3_DP_MSA_VBID_MISC |
35642 | #define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
35643 | #define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
35644 | #define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
35645 | #define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
35646 | #define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
35647 | #define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
35648 | #define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
35649 | #define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
35650 | #define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
35651 | #define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
35652 | #define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
35653 | #define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
35654 | |
35655 | |
35656 | // addressBlock: dce_dc_dio_dig4_dispdec |
35657 | //DIG4_DIG_FE_CNTL |
35658 | #define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
35659 | #define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
35660 | #define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
35661 | #define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
35662 | #define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
35663 | #define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
35664 | #define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
35665 | #define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
35666 | #define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
35667 | #define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
35668 | #define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
35669 | #define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
35670 | #define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
35671 | #define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
35672 | #define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
35673 | #define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
35674 | //DIG4_DIG_OUTPUT_CRC_CNTL |
35675 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
35676 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
35677 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
35678 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
35679 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
35680 | #define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
35681 | //DIG4_DIG_OUTPUT_CRC_RESULT |
35682 | #define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
35683 | #define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
35684 | //DIG4_DIG_CLOCK_PATTERN |
35685 | #define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
35686 | #define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
35687 | //DIG4_DIG_TEST_PATTERN |
35688 | #define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
35689 | #define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
35690 | #define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
35691 | #define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
35692 | #define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
35693 | #define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
35694 | #define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
35695 | #define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
35696 | #define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
35697 | #define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
35698 | #define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
35699 | #define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
35700 | //DIG4_DIG_RANDOM_PATTERN_SEED |
35701 | #define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
35702 | #define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
35703 | #define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
35704 | #define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
35705 | //DIG4_DIG_FIFO_STATUS |
35706 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
35707 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
35708 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
35709 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
35710 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
35711 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
35712 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
35713 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
35714 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
35715 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
35716 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
35717 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
35718 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
35719 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
35720 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
35721 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
35722 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
35723 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
35724 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
35725 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
35726 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
35727 | #define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
35728 | //DIG4_HDMI_CONTROL |
35729 | #define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
35730 | #define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
35731 | #define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
35732 | #define 0x3 |
35733 | #define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
35734 | #define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
35735 | #define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
35736 | #define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
35737 | #define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
35738 | #define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
35739 | #define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
35740 | #define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
35741 | #define 0x00000008L |
35742 | #define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
35743 | #define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
35744 | #define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
35745 | #define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
35746 | #define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
35747 | //DIG4_HDMI_STATUS |
35748 | #define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
35749 | #define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
35750 | #define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
35751 | #define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
35752 | #define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
35753 | #define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
35754 | #define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
35755 | #define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
35756 | //DIG4_HDMI_AUDIO_PACKET_CONTROL |
35757 | #define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
35758 | #define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
35759 | #define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
35760 | #define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
35761 | //DIG4_HDMI_ACR_PACKET_CONTROL |
35762 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
35763 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
35764 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
35765 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
35766 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
35767 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
35768 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
35769 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
35770 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
35771 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
35772 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
35773 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
35774 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
35775 | #define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
35776 | //DIG4_HDMI_VBI_PACKET_CONTROL |
35777 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
35778 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
35779 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
35780 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
35781 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
35782 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
35783 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
35784 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
35785 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
35786 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
35787 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
35788 | #define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
35789 | //DIG4_HDMI_INFOFRAME_CONTROL0 |
35790 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
35791 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
35792 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
35793 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
35794 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
35795 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
35796 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
35797 | #define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
35798 | //DIG4_HDMI_INFOFRAME_CONTROL1 |
35799 | #define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
35800 | #define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
35801 | #define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
35802 | #define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
35803 | //DIG4_HDMI_GENERIC_PACKET_CONTROL0 |
35804 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
35805 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
35806 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
35807 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
35808 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
35809 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
35810 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
35811 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
35812 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
35813 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
35814 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
35815 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
35816 | //DIG4_AFMT_INTERRUPT_STATUS |
35817 | //DIG4_HDMI_GC |
35818 | #define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
35819 | #define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
35820 | #define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
35821 | #define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
35822 | #define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
35823 | #define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
35824 | #define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
35825 | #define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
35826 | #define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
35827 | #define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
35828 | //DIG4_AFMT_AUDIO_PACKET_CONTROL2 |
35829 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
35830 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
35831 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
35832 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
35833 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
35834 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
35835 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
35836 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
35837 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
35838 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
35839 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
35840 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
35841 | //DIG4_AFMT_ISRC1_0 |
35842 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
35843 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
35844 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
35845 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
35846 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
35847 | #define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
35848 | //DIG4_AFMT_ISRC1_1 |
35849 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
35850 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
35851 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
35852 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
35853 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
35854 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
35855 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
35856 | #define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
35857 | //DIG4_AFMT_ISRC1_2 |
35858 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
35859 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
35860 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
35861 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
35862 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
35863 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
35864 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
35865 | #define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
35866 | //DIG4_AFMT_ISRC1_3 |
35867 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
35868 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
35869 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
35870 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
35871 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
35872 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
35873 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
35874 | #define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
35875 | //DIG4_AFMT_ISRC1_4 |
35876 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
35877 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
35878 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
35879 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
35880 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
35881 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
35882 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
35883 | #define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
35884 | //DIG4_AFMT_ISRC2_0 |
35885 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
35886 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
35887 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
35888 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
35889 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
35890 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
35891 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
35892 | #define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
35893 | //DIG4_AFMT_ISRC2_1 |
35894 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
35895 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
35896 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
35897 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
35898 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
35899 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
35900 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
35901 | #define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
35902 | //DIG4_AFMT_ISRC2_2 |
35903 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
35904 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
35905 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
35906 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
35907 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
35908 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
35909 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
35910 | #define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
35911 | //DIG4_AFMT_ISRC2_3 |
35912 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
35913 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
35914 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
35915 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
35916 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
35917 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
35918 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
35919 | #define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
35920 | //DIG4_HDMI_GENERIC_PACKET_CONTROL2 |
35921 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
35922 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
35923 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
35924 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
35925 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
35926 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
35927 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
35928 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
35929 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
35930 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
35931 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
35932 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
35933 | //DIG4_HDMI_GENERIC_PACKET_CONTROL3 |
35934 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
35935 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
35936 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
35937 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
35938 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
35939 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
35940 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
35941 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
35942 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
35943 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
35944 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
35945 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
35946 | //DIG4_HDMI_DB_CONTROL |
35947 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
35948 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
35949 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
35950 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
35951 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
35952 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
35953 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
35954 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
35955 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
35956 | #define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
35957 | //DIG4_AFMT_MPEG_INFO0 |
35958 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
35959 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
35960 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
35961 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
35962 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
35963 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
35964 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
35965 | #define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
35966 | //DIG4_AFMT_MPEG_INFO1 |
35967 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
35968 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
35969 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
35970 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
35971 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
35972 | #define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
35973 | //DIG4_AFMT_GENERIC_HDR |
35974 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
35975 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
35976 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
35977 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
35978 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
35979 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
35980 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
35981 | #define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
35982 | //DIG4_AFMT_GENERIC_0 |
35983 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
35984 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
35985 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
35986 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
35987 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
35988 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
35989 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
35990 | #define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
35991 | //DIG4_AFMT_GENERIC_1 |
35992 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
35993 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
35994 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
35995 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
35996 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
35997 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
35998 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
35999 | #define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
36000 | //DIG4_AFMT_GENERIC_2 |
36001 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
36002 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
36003 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
36004 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
36005 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
36006 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
36007 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
36008 | #define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
36009 | //DIG4_AFMT_GENERIC_3 |
36010 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
36011 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
36012 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
36013 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
36014 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
36015 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
36016 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
36017 | #define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
36018 | //DIG4_AFMT_GENERIC_4 |
36019 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
36020 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
36021 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
36022 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
36023 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
36024 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
36025 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
36026 | #define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
36027 | //DIG4_AFMT_GENERIC_5 |
36028 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
36029 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
36030 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
36031 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
36032 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
36033 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
36034 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
36035 | #define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
36036 | //DIG4_AFMT_GENERIC_6 |
36037 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
36038 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
36039 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
36040 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
36041 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
36042 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
36043 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
36044 | #define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
36045 | //DIG4_AFMT_GENERIC_7 |
36046 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
36047 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
36048 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
36049 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
36050 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
36051 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
36052 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
36053 | #define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
36054 | //DIG4_HDMI_GENERIC_PACKET_CONTROL1 |
36055 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
36056 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
36057 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
36058 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
36059 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
36060 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
36061 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
36062 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
36063 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
36064 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
36065 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
36066 | #define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
36067 | //DIG4_HDMI_ACR_32_0 |
36068 | #define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
36069 | #define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
36070 | //DIG4_HDMI_ACR_32_1 |
36071 | #define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
36072 | #define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
36073 | //DIG4_HDMI_ACR_44_0 |
36074 | #define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
36075 | #define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
36076 | //DIG4_HDMI_ACR_44_1 |
36077 | #define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
36078 | #define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
36079 | //DIG4_HDMI_ACR_48_0 |
36080 | #define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
36081 | #define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
36082 | //DIG4_HDMI_ACR_48_1 |
36083 | #define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
36084 | #define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
36085 | //DIG4_HDMI_ACR_STATUS_0 |
36086 | #define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
36087 | #define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
36088 | //DIG4_HDMI_ACR_STATUS_1 |
36089 | #define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
36090 | #define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
36091 | //DIG4_AFMT_AUDIO_INFO0 |
36092 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
36093 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
36094 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
36095 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
36096 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
36097 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
36098 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
36099 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
36100 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
36101 | #define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
36102 | //DIG4_AFMT_AUDIO_INFO1 |
36103 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
36104 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
36105 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
36106 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
36107 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
36108 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
36109 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
36110 | #define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
36111 | //DIG4_AFMT_60958_0 |
36112 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
36113 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
36114 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
36115 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
36116 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
36117 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
36118 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
36119 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
36120 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
36121 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
36122 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
36123 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
36124 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
36125 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
36126 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
36127 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
36128 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
36129 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
36130 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
36131 | #define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
36132 | //DIG4_AFMT_60958_1 |
36133 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
36134 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
36135 | #define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
36136 | #define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
36137 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
36138 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
36139 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
36140 | #define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
36141 | #define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
36142 | #define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
36143 | //DIG4_AFMT_AUDIO_CRC_CONTROL |
36144 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
36145 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
36146 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
36147 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
36148 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
36149 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
36150 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
36151 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
36152 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
36153 | #define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
36154 | //DIG4_AFMT_RAMP_CONTROL0 |
36155 | #define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
36156 | #define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
36157 | #define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
36158 | #define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
36159 | //DIG4_AFMT_RAMP_CONTROL1 |
36160 | #define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
36161 | #define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
36162 | #define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
36163 | #define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
36164 | //DIG4_AFMT_RAMP_CONTROL2 |
36165 | #define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
36166 | #define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
36167 | //DIG4_AFMT_RAMP_CONTROL3 |
36168 | #define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
36169 | #define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
36170 | //DIG4_AFMT_60958_2 |
36171 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
36172 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
36173 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
36174 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
36175 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
36176 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
36177 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
36178 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
36179 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
36180 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
36181 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
36182 | #define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
36183 | //DIG4_AFMT_AUDIO_CRC_RESULT |
36184 | #define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
36185 | #define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
36186 | #define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
36187 | #define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
36188 | //DIG4_AFMT_STATUS |
36189 | #define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
36190 | #define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
36191 | #define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
36192 | #define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
36193 | #define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
36194 | #define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
36195 | #define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
36196 | #define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
36197 | //DIG4_AFMT_AUDIO_PACKET_CONTROL |
36198 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
36199 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
36200 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
36201 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
36202 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
36203 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
36204 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
36205 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
36206 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
36207 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
36208 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
36209 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
36210 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
36211 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
36212 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
36213 | #define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
36214 | //DIG4_AFMT_VBI_PACKET_CONTROL |
36215 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
36216 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
36217 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
36218 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
36219 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
36220 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
36221 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
36222 | #define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
36223 | //DIG4_AFMT_INFOFRAME_CONTROL0 |
36224 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
36225 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
36226 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
36227 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
36228 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
36229 | #define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
36230 | //DIG4_AFMT_AUDIO_SRC_CONTROL |
36231 | #define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
36232 | #define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
36233 | //DIG4_DIG_BE_CNTL |
36234 | #define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
36235 | #define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
36236 | #define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
36237 | #define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
36238 | #define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
36239 | #define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
36240 | #define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
36241 | #define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
36242 | #define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
36243 | #define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
36244 | //DIG4_DIG_BE_EN_CNTL |
36245 | #define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
36246 | #define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
36247 | #define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
36248 | #define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
36249 | //DIG4_TMDS_CNTL |
36250 | #define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
36251 | #define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
36252 | //DIG4_TMDS_CONTROL_CHAR |
36253 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
36254 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
36255 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
36256 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
36257 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
36258 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
36259 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
36260 | #define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
36261 | //DIG4_TMDS_CONTROL0_FEEDBACK |
36262 | #define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
36263 | #define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
36264 | #define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
36265 | #define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
36266 | //DIG4_TMDS_STEREOSYNC_CTL_SEL |
36267 | #define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
36268 | #define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
36269 | //DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 |
36270 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
36271 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
36272 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
36273 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
36274 | //DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 |
36275 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
36276 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
36277 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
36278 | #define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
36279 | //DIG4_TMDS_CTL_BITS |
36280 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
36281 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
36282 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
36283 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
36284 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
36285 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
36286 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
36287 | #define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
36288 | //DIG4_TMDS_DCBALANCER_CONTROL |
36289 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
36290 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
36291 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
36292 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
36293 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
36294 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
36295 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
36296 | #define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
36297 | //DIG4_TMDS_CTL0_1_GEN_CNTL |
36298 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
36299 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
36300 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
36301 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
36302 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
36303 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
36304 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
36305 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
36306 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
36307 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
36308 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
36309 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
36310 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
36311 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
36312 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
36313 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
36314 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
36315 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
36316 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
36317 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
36318 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
36319 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
36320 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
36321 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
36322 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
36323 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
36324 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
36325 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
36326 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
36327 | #define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
36328 | //DIG4_TMDS_CTL2_3_GEN_CNTL |
36329 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
36330 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
36331 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
36332 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
36333 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
36334 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
36335 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
36336 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
36337 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
36338 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
36339 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
36340 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
36341 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
36342 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
36343 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
36344 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
36345 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
36346 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
36347 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
36348 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
36349 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
36350 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
36351 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
36352 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
36353 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
36354 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
36355 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
36356 | #define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
36357 | //DIG4_DIG_VERSION |
36358 | #define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
36359 | #define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
36360 | //DIG4_DIG_LANE_ENABLE |
36361 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
36362 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
36363 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
36364 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
36365 | #define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
36366 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
36367 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
36368 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
36369 | #define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
36370 | #define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
36371 | //DIG4_AFMT_CNTL |
36372 | #define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
36373 | #define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
36374 | #define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
36375 | #define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
36376 | //DIG4_AFMT_VBI_PACKET_CONTROL1 |
36377 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
36378 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
36379 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
36380 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
36381 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
36382 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
36383 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
36384 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
36385 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
36386 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
36387 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
36388 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
36389 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
36390 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
36391 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
36392 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
36393 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
36394 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
36395 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
36396 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
36397 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
36398 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
36399 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
36400 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
36401 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
36402 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
36403 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
36404 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
36405 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
36406 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
36407 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
36408 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
36409 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
36410 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
36411 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
36412 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
36413 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
36414 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
36415 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
36416 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
36417 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
36418 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
36419 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
36420 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
36421 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
36422 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
36423 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
36424 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
36425 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
36426 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
36427 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
36428 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
36429 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
36430 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
36431 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
36432 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
36433 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
36434 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
36435 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
36436 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
36437 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
36438 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
36439 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
36440 | #define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
36441 | |
36442 | |
36443 | // addressBlock: dce_dc_dio_dp4_dispdec |
36444 | //DP4_DP_LINK_CNTL |
36445 | #define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
36446 | #define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
36447 | #define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
36448 | #define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
36449 | #define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
36450 | #define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
36451 | //DP4_DP_PIXEL_FORMAT |
36452 | #define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
36453 | #define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
36454 | #define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
36455 | #define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
36456 | #define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
36457 | #define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
36458 | //DP4_DP_MSA_COLORIMETRY |
36459 | #define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
36460 | #define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
36461 | //DP4_DP_CONFIG |
36462 | #define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
36463 | #define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
36464 | //DP4_DP_VID_STREAM_CNTL |
36465 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
36466 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
36467 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
36468 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
36469 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
36470 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
36471 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
36472 | #define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
36473 | //DP4_DP_STEER_FIFO |
36474 | #define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
36475 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
36476 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
36477 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
36478 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
36479 | #define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
36480 | #define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
36481 | #define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
36482 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
36483 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
36484 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
36485 | #define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
36486 | #define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
36487 | #define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
36488 | //DP4_DP_MSA_MISC |
36489 | #define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
36490 | #define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
36491 | #define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
36492 | #define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
36493 | #define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
36494 | #define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
36495 | #define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
36496 | #define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
36497 | //DP4_DP_VID_TIMING |
36498 | #define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
36499 | #define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
36500 | #define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
36501 | #define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
36502 | #define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
36503 | #define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
36504 | #define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
36505 | #define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
36506 | #define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
36507 | #define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
36508 | //DP4_DP_VID_N |
36509 | #define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 |
36510 | #define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
36511 | //DP4_DP_VID_M |
36512 | #define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 |
36513 | #define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
36514 | //DP4_DP_LINK_FRAMING_CNTL |
36515 | #define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
36516 | #define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
36517 | #define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
36518 | #define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
36519 | #define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
36520 | #define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
36521 | //DP4_DP_HBR2_EYE_PATTERN |
36522 | #define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
36523 | #define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
36524 | //DP4_DP_VID_MSA_VBID |
36525 | #define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
36526 | #define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
36527 | #define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
36528 | #define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
36529 | //DP4_DP_VID_INTERRUPT_CNTL |
36530 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
36531 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
36532 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
36533 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
36534 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
36535 | #define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
36536 | //DP4_DP_DPHY_CNTL |
36537 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
36538 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
36539 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
36540 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
36541 | #define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
36542 | #define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
36543 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
36544 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
36545 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
36546 | #define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
36547 | #define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
36548 | #define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
36549 | //DP4_DP_DPHY_TRAINING_PATTERN_SEL |
36550 | #define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
36551 | #define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
36552 | //DP4_DP_DPHY_SYM0 |
36553 | #define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
36554 | #define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
36555 | #define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
36556 | #define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
36557 | #define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
36558 | #define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
36559 | //DP4_DP_DPHY_SYM1 |
36560 | #define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
36561 | #define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
36562 | #define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
36563 | #define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
36564 | #define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
36565 | #define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
36566 | //DP4_DP_DPHY_SYM2 |
36567 | #define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
36568 | #define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
36569 | #define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
36570 | #define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
36571 | //DP4_DP_DPHY_8B10B_CNTL |
36572 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
36573 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
36574 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
36575 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
36576 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
36577 | #define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
36578 | //DP4_DP_DPHY_PRBS_CNTL |
36579 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
36580 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
36581 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
36582 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
36583 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
36584 | #define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
36585 | //DP4_DP_DPHY_SCRAM_CNTL |
36586 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
36587 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
36588 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
36589 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
36590 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
36591 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
36592 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
36593 | #define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
36594 | //DP4_DP_DPHY_CRC_EN |
36595 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
36596 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
36597 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
36598 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
36599 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
36600 | #define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
36601 | //DP4_DP_DPHY_CRC_CNTL |
36602 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
36603 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
36604 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
36605 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
36606 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
36607 | #define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
36608 | //DP4_DP_DPHY_CRC_RESULT |
36609 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
36610 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
36611 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
36612 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
36613 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
36614 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
36615 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
36616 | #define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
36617 | //DP4_DP_DPHY_CRC_MST_CNTL |
36618 | #define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
36619 | #define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
36620 | #define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
36621 | #define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
36622 | //DP4_DP_DPHY_CRC_MST_STATUS |
36623 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
36624 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
36625 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
36626 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
36627 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
36628 | #define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
36629 | //DP4_DP_DPHY_FAST_TRAINING |
36630 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
36631 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
36632 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
36633 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
36634 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
36635 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
36636 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
36637 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
36638 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
36639 | #define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
36640 | //DP4_DP_DPHY_FAST_TRAINING_STATUS |
36641 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
36642 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
36643 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
36644 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
36645 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
36646 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
36647 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
36648 | #define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
36649 | //DP4_DP_SEC_CNTL |
36650 | #define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
36651 | #define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
36652 | #define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
36653 | #define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
36654 | #define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
36655 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
36656 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
36657 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
36658 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
36659 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
36660 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
36661 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
36662 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
36663 | #define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
36664 | #define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
36665 | #define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
36666 | #define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
36667 | #define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
36668 | #define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
36669 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
36670 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
36671 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
36672 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
36673 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
36674 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
36675 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
36676 | #define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
36677 | #define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
36678 | //DP4_DP_SEC_CNTL1 |
36679 | #define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
36680 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
36681 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
36682 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
36683 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
36684 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
36685 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
36686 | #define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
36687 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
36688 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
36689 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
36690 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
36691 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
36692 | #define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
36693 | //DP4_DP_SEC_FRAMING1 |
36694 | #define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
36695 | #define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
36696 | #define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
36697 | #define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
36698 | //DP4_DP_SEC_FRAMING2 |
36699 | #define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
36700 | #define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
36701 | #define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
36702 | #define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
36703 | //DP4_DP_SEC_FRAMING3 |
36704 | #define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
36705 | #define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
36706 | #define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
36707 | #define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
36708 | //DP4_DP_SEC_FRAMING4 |
36709 | #define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
36710 | #define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
36711 | #define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
36712 | #define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
36713 | #define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
36714 | #define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
36715 | #define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
36716 | #define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
36717 | //DP4_DP_SEC_AUD_N |
36718 | #define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
36719 | #define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
36720 | //DP4_DP_SEC_AUD_N_READBACK |
36721 | #define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
36722 | #define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
36723 | //DP4_DP_SEC_AUD_M |
36724 | #define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
36725 | #define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
36726 | //DP4_DP_SEC_AUD_M_READBACK |
36727 | #define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
36728 | #define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
36729 | //DP4_DP_SEC_TIMESTAMP |
36730 | #define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
36731 | #define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
36732 | //DP4_DP_SEC_PACKET_CNTL |
36733 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
36734 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
36735 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
36736 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
36737 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
36738 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
36739 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
36740 | #define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
36741 | //DP4_DP_MSE_RATE_CNTL |
36742 | #define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
36743 | #define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
36744 | #define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
36745 | #define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
36746 | //DP4_DP_MSE_RATE_UPDATE |
36747 | #define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
36748 | #define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
36749 | //DP4_DP_MSE_SAT0 |
36750 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
36751 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
36752 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
36753 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
36754 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
36755 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
36756 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
36757 | #define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
36758 | //DP4_DP_MSE_SAT1 |
36759 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
36760 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
36761 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
36762 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
36763 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
36764 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
36765 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
36766 | #define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
36767 | //DP4_DP_MSE_SAT2 |
36768 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
36769 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
36770 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
36771 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
36772 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
36773 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
36774 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
36775 | #define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
36776 | //DP4_DP_MSE_SAT_UPDATE |
36777 | #define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
36778 | #define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
36779 | #define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
36780 | #define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
36781 | //DP4_DP_MSE_LINK_TIMING |
36782 | #define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
36783 | #define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
36784 | #define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
36785 | #define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
36786 | //DP4_DP_MSE_MISC_CNTL |
36787 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
36788 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
36789 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
36790 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
36791 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
36792 | #define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
36793 | //DP4_DP_DPHY_BS_SR_SWAP_CNTL |
36794 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
36795 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
36796 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
36797 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
36798 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
36799 | #define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
36800 | //DP4_DP_DPHY_HBR2_PATTERN_CONTROL |
36801 | #define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
36802 | #define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
36803 | //DP4_DP_MSE_SAT0_STATUS |
36804 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
36805 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
36806 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
36807 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
36808 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
36809 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
36810 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
36811 | #define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
36812 | //DP4_DP_MSE_SAT1_STATUS |
36813 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
36814 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
36815 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
36816 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
36817 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
36818 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
36819 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
36820 | #define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
36821 | //DP4_DP_MSE_SAT2_STATUS |
36822 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
36823 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
36824 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
36825 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
36826 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
36827 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
36828 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
36829 | #define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
36830 | //DP4_DP_MSA_TIMING_PARAM1 |
36831 | #define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
36832 | #define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
36833 | #define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
36834 | #define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
36835 | //DP4_DP_MSA_TIMING_PARAM2 |
36836 | #define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
36837 | #define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
36838 | #define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
36839 | #define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
36840 | //DP4_DP_MSA_TIMING_PARAM3 |
36841 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
36842 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
36843 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
36844 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
36845 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
36846 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
36847 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
36848 | #define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
36849 | //DP4_DP_MSA_TIMING_PARAM4 |
36850 | #define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
36851 | #define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
36852 | #define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
36853 | #define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
36854 | //DP4_DP_MSO_CNTL |
36855 | #define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
36856 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
36857 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
36858 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
36859 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
36860 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
36861 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
36862 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
36863 | #define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
36864 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
36865 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
36866 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
36867 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
36868 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
36869 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
36870 | #define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
36871 | //DP4_DP_MSO_CNTL1 |
36872 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
36873 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
36874 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
36875 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
36876 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
36877 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
36878 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
36879 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
36880 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
36881 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
36882 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
36883 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
36884 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
36885 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
36886 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
36887 | #define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
36888 | //DP4_DP_DSC_CNTL |
36889 | #define DP4_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
36890 | #define DP4_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
36891 | //DP4_DP_SEC_CNTL2 |
36892 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
36893 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
36894 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
36895 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
36896 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
36897 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
36898 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
36899 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
36900 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
36901 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
36902 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
36903 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
36904 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
36905 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
36906 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
36907 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
36908 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
36909 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
36910 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
36911 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
36912 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
36913 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
36914 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
36915 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
36916 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
36917 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
36918 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
36919 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
36920 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
36921 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
36922 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
36923 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
36924 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
36925 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
36926 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
36927 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
36928 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
36929 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
36930 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
36931 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
36932 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
36933 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
36934 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
36935 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
36936 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
36937 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
36938 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
36939 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
36940 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
36941 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
36942 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
36943 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
36944 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
36945 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
36946 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
36947 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
36948 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
36949 | #define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
36950 | //DP4_DP_SEC_CNTL3 |
36951 | #define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
36952 | #define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
36953 | #define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
36954 | #define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
36955 | //DP4_DP_SEC_CNTL4 |
36956 | #define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
36957 | #define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
36958 | #define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
36959 | #define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
36960 | //DP4_DP_SEC_CNTL5 |
36961 | #define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
36962 | #define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
36963 | #define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
36964 | #define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
36965 | //DP4_DP_SEC_CNTL6 |
36966 | #define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
36967 | #define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
36968 | //DP4_DP_SEC_CNTL7 |
36969 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
36970 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
36971 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
36972 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
36973 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
36974 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
36975 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
36976 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
36977 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
36978 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
36979 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
36980 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
36981 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
36982 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
36983 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
36984 | #define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
36985 | //DP4_DP_DB_CNTL |
36986 | #define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
36987 | #define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
36988 | #define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
36989 | #define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
36990 | #define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
36991 | #define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
36992 | #define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
36993 | #define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
36994 | #define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
36995 | #define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
36996 | //DP4_DP_MSA_VBID_MISC |
36997 | #define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
36998 | #define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
36999 | #define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
37000 | #define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
37001 | #define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
37002 | #define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
37003 | #define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
37004 | #define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
37005 | #define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
37006 | #define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
37007 | #define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
37008 | #define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
37009 | |
37010 | |
37011 | // addressBlock: dce_dc_dio_dig5_dispdec |
37012 | //DIG5_DIG_FE_CNTL |
37013 | #define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
37014 | #define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
37015 | #define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
37016 | #define DIG5_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
37017 | #define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
37018 | #define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
37019 | #define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
37020 | #define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
37021 | #define DIG5_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
37022 | #define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
37023 | #define DIG5_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
37024 | #define DIG5_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
37025 | #define DIG5_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
37026 | #define DIG5_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
37027 | #define DIG5_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
37028 | #define DIG5_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
37029 | //DIG5_DIG_OUTPUT_CRC_CNTL |
37030 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
37031 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
37032 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
37033 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
37034 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
37035 | #define DIG5_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
37036 | //DIG5_DIG_OUTPUT_CRC_RESULT |
37037 | #define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
37038 | #define DIG5_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
37039 | //DIG5_DIG_CLOCK_PATTERN |
37040 | #define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
37041 | #define DIG5_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
37042 | //DIG5_DIG_TEST_PATTERN |
37043 | #define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
37044 | #define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
37045 | #define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
37046 | #define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
37047 | #define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
37048 | #define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
37049 | #define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
37050 | #define DIG5_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
37051 | #define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
37052 | #define DIG5_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
37053 | #define DIG5_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
37054 | #define DIG5_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
37055 | //DIG5_DIG_RANDOM_PATTERN_SEED |
37056 | #define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
37057 | #define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
37058 | #define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
37059 | #define DIG5_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
37060 | //DIG5_DIG_FIFO_STATUS |
37061 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
37062 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
37063 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
37064 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
37065 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
37066 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
37067 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
37068 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
37069 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
37070 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
37071 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
37072 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
37073 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
37074 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
37075 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
37076 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
37077 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
37078 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
37079 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
37080 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
37081 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
37082 | #define DIG5_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
37083 | //DIG5_HDMI_CONTROL |
37084 | #define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
37085 | #define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
37086 | #define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
37087 | #define 0x3 |
37088 | #define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
37089 | #define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
37090 | #define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
37091 | #define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
37092 | #define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
37093 | #define DIG5_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
37094 | #define DIG5_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
37095 | #define DIG5_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
37096 | #define 0x00000008L |
37097 | #define DIG5_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
37098 | #define DIG5_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
37099 | #define DIG5_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
37100 | #define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
37101 | #define DIG5_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
37102 | //DIG5_HDMI_STATUS |
37103 | #define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
37104 | #define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
37105 | #define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
37106 | #define DIG5_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
37107 | #define DIG5_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
37108 | #define DIG5_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
37109 | #define DIG5_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
37110 | #define DIG5_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
37111 | //DIG5_HDMI_AUDIO_PACKET_CONTROL |
37112 | #define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
37113 | #define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
37114 | #define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
37115 | #define DIG5_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
37116 | //DIG5_HDMI_ACR_PACKET_CONTROL |
37117 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
37118 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
37119 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
37120 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
37121 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
37122 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
37123 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
37124 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
37125 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
37126 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
37127 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
37128 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
37129 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
37130 | #define DIG5_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
37131 | //DIG5_HDMI_VBI_PACKET_CONTROL |
37132 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
37133 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
37134 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
37135 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
37136 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
37137 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
37138 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
37139 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
37140 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
37141 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
37142 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
37143 | #define DIG5_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
37144 | //DIG5_HDMI_INFOFRAME_CONTROL0 |
37145 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
37146 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
37147 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
37148 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
37149 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
37150 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
37151 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
37152 | #define DIG5_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
37153 | //DIG5_HDMI_INFOFRAME_CONTROL1 |
37154 | #define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
37155 | #define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
37156 | #define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
37157 | #define DIG5_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
37158 | //DIG5_HDMI_GENERIC_PACKET_CONTROL0 |
37159 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
37160 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
37161 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
37162 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
37163 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
37164 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
37165 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
37166 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
37167 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
37168 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
37169 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
37170 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
37171 | //DIG5_AFMT_INTERRUPT_STATUS |
37172 | //DIG5_HDMI_GC |
37173 | #define DIG5_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
37174 | #define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
37175 | #define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
37176 | #define DIG5_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
37177 | #define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
37178 | #define DIG5_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
37179 | #define DIG5_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
37180 | #define DIG5_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
37181 | #define DIG5_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
37182 | #define DIG5_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
37183 | //DIG5_AFMT_AUDIO_PACKET_CONTROL2 |
37184 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
37185 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
37186 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
37187 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
37188 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
37189 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
37190 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
37191 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
37192 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
37193 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
37194 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
37195 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
37196 | //DIG5_AFMT_ISRC1_0 |
37197 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
37198 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
37199 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
37200 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
37201 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
37202 | #define DIG5_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
37203 | //DIG5_AFMT_ISRC1_1 |
37204 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
37205 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
37206 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
37207 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
37208 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
37209 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
37210 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
37211 | #define DIG5_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
37212 | //DIG5_AFMT_ISRC1_2 |
37213 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
37214 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
37215 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
37216 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
37217 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
37218 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
37219 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
37220 | #define DIG5_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
37221 | //DIG5_AFMT_ISRC1_3 |
37222 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
37223 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
37224 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
37225 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
37226 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
37227 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
37228 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
37229 | #define DIG5_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
37230 | //DIG5_AFMT_ISRC1_4 |
37231 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
37232 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
37233 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
37234 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
37235 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
37236 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
37237 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
37238 | #define DIG5_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
37239 | //DIG5_AFMT_ISRC2_0 |
37240 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
37241 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
37242 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
37243 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
37244 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
37245 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
37246 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
37247 | #define DIG5_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
37248 | //DIG5_AFMT_ISRC2_1 |
37249 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
37250 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
37251 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
37252 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
37253 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
37254 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
37255 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
37256 | #define DIG5_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
37257 | //DIG5_AFMT_ISRC2_2 |
37258 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
37259 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
37260 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
37261 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
37262 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
37263 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
37264 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
37265 | #define DIG5_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
37266 | //DIG5_AFMT_ISRC2_3 |
37267 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
37268 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
37269 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
37270 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
37271 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
37272 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
37273 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
37274 | #define DIG5_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
37275 | //DIG5_HDMI_GENERIC_PACKET_CONTROL2 |
37276 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
37277 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
37278 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
37279 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
37280 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
37281 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
37282 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
37283 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
37284 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
37285 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
37286 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
37287 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
37288 | //DIG5_HDMI_GENERIC_PACKET_CONTROL3 |
37289 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
37290 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
37291 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
37292 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
37293 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
37294 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
37295 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
37296 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
37297 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
37298 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
37299 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
37300 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
37301 | //DIG5_HDMI_DB_CONTROL |
37302 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
37303 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
37304 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
37305 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
37306 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
37307 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
37308 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
37309 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
37310 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
37311 | #define DIG5_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
37312 | //DIG5_AFMT_MPEG_INFO0 |
37313 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
37314 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
37315 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
37316 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
37317 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
37318 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
37319 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
37320 | #define DIG5_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
37321 | //DIG5_AFMT_MPEG_INFO1 |
37322 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
37323 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
37324 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
37325 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
37326 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
37327 | #define DIG5_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
37328 | //DIG5_AFMT_GENERIC_HDR |
37329 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
37330 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
37331 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
37332 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
37333 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
37334 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
37335 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
37336 | #define DIG5_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
37337 | //DIG5_AFMT_GENERIC_0 |
37338 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
37339 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
37340 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
37341 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
37342 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
37343 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
37344 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
37345 | #define DIG5_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
37346 | //DIG5_AFMT_GENERIC_1 |
37347 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
37348 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
37349 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
37350 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
37351 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
37352 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
37353 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
37354 | #define DIG5_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
37355 | //DIG5_AFMT_GENERIC_2 |
37356 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
37357 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
37358 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
37359 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
37360 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
37361 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
37362 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
37363 | #define DIG5_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
37364 | //DIG5_AFMT_GENERIC_3 |
37365 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
37366 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
37367 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
37368 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
37369 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
37370 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
37371 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
37372 | #define DIG5_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
37373 | //DIG5_AFMT_GENERIC_4 |
37374 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
37375 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
37376 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
37377 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
37378 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
37379 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
37380 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
37381 | #define DIG5_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
37382 | //DIG5_AFMT_GENERIC_5 |
37383 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
37384 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
37385 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
37386 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
37387 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
37388 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
37389 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
37390 | #define DIG5_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
37391 | //DIG5_AFMT_GENERIC_6 |
37392 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
37393 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
37394 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
37395 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
37396 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
37397 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
37398 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
37399 | #define DIG5_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
37400 | //DIG5_AFMT_GENERIC_7 |
37401 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
37402 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
37403 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
37404 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
37405 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
37406 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
37407 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
37408 | #define DIG5_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
37409 | //DIG5_HDMI_GENERIC_PACKET_CONTROL1 |
37410 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
37411 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
37412 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
37413 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
37414 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
37415 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
37416 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
37417 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
37418 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
37419 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
37420 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
37421 | #define DIG5_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
37422 | //DIG5_HDMI_ACR_32_0 |
37423 | #define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
37424 | #define DIG5_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
37425 | //DIG5_HDMI_ACR_32_1 |
37426 | #define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
37427 | #define DIG5_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
37428 | //DIG5_HDMI_ACR_44_0 |
37429 | #define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
37430 | #define DIG5_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
37431 | //DIG5_HDMI_ACR_44_1 |
37432 | #define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
37433 | #define DIG5_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
37434 | //DIG5_HDMI_ACR_48_0 |
37435 | #define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
37436 | #define DIG5_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
37437 | //DIG5_HDMI_ACR_48_1 |
37438 | #define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
37439 | #define DIG5_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
37440 | //DIG5_HDMI_ACR_STATUS_0 |
37441 | #define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
37442 | #define DIG5_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
37443 | //DIG5_HDMI_ACR_STATUS_1 |
37444 | #define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
37445 | #define DIG5_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
37446 | //DIG5_AFMT_AUDIO_INFO0 |
37447 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
37448 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
37449 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
37450 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
37451 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
37452 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
37453 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
37454 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
37455 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
37456 | #define DIG5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
37457 | //DIG5_AFMT_AUDIO_INFO1 |
37458 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
37459 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
37460 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
37461 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
37462 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
37463 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
37464 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
37465 | #define DIG5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
37466 | //DIG5_AFMT_60958_0 |
37467 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
37468 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
37469 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
37470 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
37471 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
37472 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
37473 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
37474 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
37475 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
37476 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
37477 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
37478 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
37479 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
37480 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
37481 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
37482 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
37483 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
37484 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
37485 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
37486 | #define DIG5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
37487 | //DIG5_AFMT_60958_1 |
37488 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
37489 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
37490 | #define DIG5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
37491 | #define DIG5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
37492 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
37493 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
37494 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
37495 | #define DIG5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
37496 | #define DIG5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
37497 | #define DIG5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
37498 | //DIG5_AFMT_AUDIO_CRC_CONTROL |
37499 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
37500 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
37501 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
37502 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
37503 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
37504 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
37505 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
37506 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
37507 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
37508 | #define DIG5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
37509 | //DIG5_AFMT_RAMP_CONTROL0 |
37510 | #define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
37511 | #define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
37512 | #define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
37513 | #define DIG5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
37514 | //DIG5_AFMT_RAMP_CONTROL1 |
37515 | #define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
37516 | #define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
37517 | #define DIG5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
37518 | #define DIG5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
37519 | //DIG5_AFMT_RAMP_CONTROL2 |
37520 | #define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
37521 | #define DIG5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
37522 | //DIG5_AFMT_RAMP_CONTROL3 |
37523 | #define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
37524 | #define DIG5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
37525 | //DIG5_AFMT_60958_2 |
37526 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
37527 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
37528 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
37529 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
37530 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
37531 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
37532 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
37533 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
37534 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
37535 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
37536 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
37537 | #define DIG5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
37538 | //DIG5_AFMT_AUDIO_CRC_RESULT |
37539 | #define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
37540 | #define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
37541 | #define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
37542 | #define DIG5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
37543 | //DIG5_AFMT_STATUS |
37544 | #define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
37545 | #define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
37546 | #define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
37547 | #define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
37548 | #define DIG5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
37549 | #define DIG5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
37550 | #define DIG5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
37551 | #define DIG5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
37552 | //DIG5_AFMT_AUDIO_PACKET_CONTROL |
37553 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
37554 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
37555 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
37556 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
37557 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
37558 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
37559 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
37560 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
37561 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
37562 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
37563 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
37564 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
37565 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
37566 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
37567 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
37568 | #define DIG5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
37569 | //DIG5_AFMT_VBI_PACKET_CONTROL |
37570 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
37571 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
37572 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
37573 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
37574 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
37575 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
37576 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
37577 | #define DIG5_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
37578 | //DIG5_AFMT_INFOFRAME_CONTROL0 |
37579 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
37580 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
37581 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
37582 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
37583 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
37584 | #define DIG5_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
37585 | //DIG5_AFMT_AUDIO_SRC_CONTROL |
37586 | #define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
37587 | #define DIG5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
37588 | //DIG5_DIG_BE_CNTL |
37589 | #define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
37590 | #define DIG5_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
37591 | #define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
37592 | #define DIG5_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
37593 | #define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
37594 | #define DIG5_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
37595 | #define DIG5_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
37596 | #define DIG5_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
37597 | #define DIG5_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
37598 | #define DIG5_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
37599 | //DIG5_DIG_BE_EN_CNTL |
37600 | #define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
37601 | #define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
37602 | #define DIG5_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
37603 | #define DIG5_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
37604 | //DIG5_TMDS_CNTL |
37605 | #define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
37606 | #define DIG5_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
37607 | //DIG5_TMDS_CONTROL_CHAR |
37608 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
37609 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
37610 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
37611 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
37612 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
37613 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
37614 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
37615 | #define DIG5_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
37616 | //DIG5_TMDS_CONTROL0_FEEDBACK |
37617 | #define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
37618 | #define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
37619 | #define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
37620 | #define DIG5_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
37621 | //DIG5_TMDS_STEREOSYNC_CTL_SEL |
37622 | #define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
37623 | #define DIG5_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
37624 | //DIG5_TMDS_SYNC_CHAR_PATTERN_0_1 |
37625 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
37626 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
37627 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
37628 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
37629 | //DIG5_TMDS_SYNC_CHAR_PATTERN_2_3 |
37630 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
37631 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
37632 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
37633 | #define DIG5_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
37634 | //DIG5_TMDS_CTL_BITS |
37635 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
37636 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
37637 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
37638 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
37639 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
37640 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
37641 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
37642 | #define DIG5_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
37643 | //DIG5_TMDS_DCBALANCER_CONTROL |
37644 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
37645 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
37646 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
37647 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
37648 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
37649 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
37650 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
37651 | #define DIG5_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
37652 | //DIG5_TMDS_CTL0_1_GEN_CNTL |
37653 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
37654 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
37655 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
37656 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
37657 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
37658 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
37659 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
37660 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
37661 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
37662 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
37663 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
37664 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
37665 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
37666 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
37667 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
37668 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
37669 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
37670 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
37671 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
37672 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
37673 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
37674 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
37675 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
37676 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
37677 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
37678 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
37679 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
37680 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
37681 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
37682 | #define DIG5_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
37683 | //DIG5_TMDS_CTL2_3_GEN_CNTL |
37684 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
37685 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
37686 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
37687 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
37688 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
37689 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
37690 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
37691 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
37692 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
37693 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
37694 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
37695 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
37696 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
37697 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
37698 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
37699 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
37700 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
37701 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
37702 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
37703 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
37704 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
37705 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
37706 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
37707 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
37708 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
37709 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
37710 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
37711 | #define DIG5_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
37712 | //DIG5_DIG_VERSION |
37713 | #define DIG5_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
37714 | #define DIG5_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
37715 | //DIG5_DIG_LANE_ENABLE |
37716 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
37717 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
37718 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
37719 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
37720 | #define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
37721 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
37722 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
37723 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
37724 | #define DIG5_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
37725 | #define DIG5_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
37726 | //DIG5_AFMT_CNTL |
37727 | #define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
37728 | #define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
37729 | #define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
37730 | #define DIG5_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
37731 | //DIG5_AFMT_VBI_PACKET_CONTROL1 |
37732 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
37733 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
37734 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
37735 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
37736 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
37737 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
37738 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
37739 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
37740 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
37741 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
37742 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
37743 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
37744 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
37745 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
37746 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
37747 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
37748 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
37749 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
37750 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
37751 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
37752 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
37753 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
37754 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
37755 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
37756 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
37757 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
37758 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
37759 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
37760 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
37761 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
37762 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
37763 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
37764 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
37765 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
37766 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
37767 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
37768 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
37769 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
37770 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
37771 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
37772 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
37773 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
37774 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
37775 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
37776 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
37777 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
37778 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
37779 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
37780 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
37781 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
37782 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
37783 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
37784 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
37785 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
37786 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
37787 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
37788 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
37789 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
37790 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
37791 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
37792 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
37793 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
37794 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
37795 | #define DIG5_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
37796 | |
37797 | |
37798 | // addressBlock: dce_dc_dio_dp5_dispdec |
37799 | //DP5_DP_LINK_CNTL |
37800 | #define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
37801 | #define DP5_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
37802 | #define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
37803 | #define DP5_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
37804 | #define DP5_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
37805 | #define DP5_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
37806 | //DP5_DP_PIXEL_FORMAT |
37807 | #define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
37808 | #define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
37809 | #define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
37810 | #define DP5_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
37811 | #define DP5_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
37812 | #define DP5_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
37813 | //DP5_DP_MSA_COLORIMETRY |
37814 | #define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
37815 | #define DP5_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
37816 | //DP5_DP_CONFIG |
37817 | #define DP5_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
37818 | #define DP5_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
37819 | //DP5_DP_VID_STREAM_CNTL |
37820 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
37821 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
37822 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
37823 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
37824 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
37825 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
37826 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
37827 | #define DP5_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
37828 | //DP5_DP_STEER_FIFO |
37829 | #define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
37830 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
37831 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
37832 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
37833 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
37834 | #define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
37835 | #define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
37836 | #define DP5_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
37837 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
37838 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
37839 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
37840 | #define DP5_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
37841 | #define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
37842 | #define DP5_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
37843 | //DP5_DP_MSA_MISC |
37844 | #define DP5_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
37845 | #define DP5_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
37846 | #define DP5_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
37847 | #define DP5_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
37848 | #define DP5_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
37849 | #define DP5_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
37850 | #define DP5_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
37851 | #define DP5_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
37852 | //DP5_DP_VID_TIMING |
37853 | #define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
37854 | #define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
37855 | #define DP5_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
37856 | #define DP5_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
37857 | #define DP5_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
37858 | #define DP5_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
37859 | #define DP5_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
37860 | #define DP5_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
37861 | #define DP5_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
37862 | #define DP5_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
37863 | //DP5_DP_VID_N |
37864 | #define DP5_DP_VID_N__DP_VID_N__SHIFT 0x0 |
37865 | #define DP5_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
37866 | //DP5_DP_VID_M |
37867 | #define DP5_DP_VID_M__DP_VID_M__SHIFT 0x0 |
37868 | #define DP5_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
37869 | //DP5_DP_LINK_FRAMING_CNTL |
37870 | #define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
37871 | #define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
37872 | #define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
37873 | #define DP5_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
37874 | #define DP5_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
37875 | #define DP5_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
37876 | //DP5_DP_HBR2_EYE_PATTERN |
37877 | #define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
37878 | #define DP5_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
37879 | //DP5_DP_VID_MSA_VBID |
37880 | #define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
37881 | #define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
37882 | #define DP5_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
37883 | #define DP5_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
37884 | //DP5_DP_VID_INTERRUPT_CNTL |
37885 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
37886 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
37887 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
37888 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
37889 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
37890 | #define DP5_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
37891 | //DP5_DP_DPHY_CNTL |
37892 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
37893 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
37894 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
37895 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
37896 | #define DP5_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
37897 | #define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
37898 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
37899 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
37900 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
37901 | #define DP5_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
37902 | #define DP5_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
37903 | #define DP5_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
37904 | //DP5_DP_DPHY_TRAINING_PATTERN_SEL |
37905 | #define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
37906 | #define DP5_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
37907 | //DP5_DP_DPHY_SYM0 |
37908 | #define DP5_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
37909 | #define DP5_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
37910 | #define DP5_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
37911 | #define DP5_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
37912 | #define DP5_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
37913 | #define DP5_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
37914 | //DP5_DP_DPHY_SYM1 |
37915 | #define DP5_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
37916 | #define DP5_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
37917 | #define DP5_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
37918 | #define DP5_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
37919 | #define DP5_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
37920 | #define DP5_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
37921 | //DP5_DP_DPHY_SYM2 |
37922 | #define DP5_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
37923 | #define DP5_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
37924 | #define DP5_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
37925 | #define DP5_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
37926 | //DP5_DP_DPHY_8B10B_CNTL |
37927 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
37928 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
37929 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
37930 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
37931 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
37932 | #define DP5_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
37933 | //DP5_DP_DPHY_PRBS_CNTL |
37934 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
37935 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
37936 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
37937 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
37938 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
37939 | #define DP5_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
37940 | //DP5_DP_DPHY_SCRAM_CNTL |
37941 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
37942 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
37943 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
37944 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
37945 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
37946 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
37947 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
37948 | #define DP5_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
37949 | //DP5_DP_DPHY_CRC_EN |
37950 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
37951 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
37952 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
37953 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
37954 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
37955 | #define DP5_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
37956 | //DP5_DP_DPHY_CRC_CNTL |
37957 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
37958 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
37959 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
37960 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
37961 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
37962 | #define DP5_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
37963 | //DP5_DP_DPHY_CRC_RESULT |
37964 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
37965 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
37966 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
37967 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
37968 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
37969 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
37970 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
37971 | #define DP5_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
37972 | //DP5_DP_DPHY_CRC_MST_CNTL |
37973 | #define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
37974 | #define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
37975 | #define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
37976 | #define DP5_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
37977 | //DP5_DP_DPHY_CRC_MST_STATUS |
37978 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
37979 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
37980 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
37981 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
37982 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
37983 | #define DP5_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
37984 | //DP5_DP_DPHY_FAST_TRAINING |
37985 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
37986 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
37987 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
37988 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
37989 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
37990 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
37991 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
37992 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
37993 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
37994 | #define DP5_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
37995 | //DP5_DP_DPHY_FAST_TRAINING_STATUS |
37996 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
37997 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
37998 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
37999 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
38000 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
38001 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
38002 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
38003 | #define DP5_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
38004 | //DP5_DP_SEC_CNTL |
38005 | #define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
38006 | #define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
38007 | #define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
38008 | #define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
38009 | #define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
38010 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
38011 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
38012 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
38013 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
38014 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
38015 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
38016 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
38017 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
38018 | #define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
38019 | #define DP5_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
38020 | #define DP5_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
38021 | #define DP5_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
38022 | #define DP5_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
38023 | #define DP5_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
38024 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
38025 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
38026 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
38027 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
38028 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
38029 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
38030 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
38031 | #define DP5_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
38032 | #define DP5_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
38033 | //DP5_DP_SEC_CNTL1 |
38034 | #define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
38035 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
38036 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
38037 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
38038 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
38039 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
38040 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
38041 | #define DP5_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
38042 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
38043 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
38044 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
38045 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
38046 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
38047 | #define DP5_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
38048 | //DP5_DP_SEC_FRAMING1 |
38049 | #define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
38050 | #define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
38051 | #define DP5_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
38052 | #define DP5_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
38053 | //DP5_DP_SEC_FRAMING2 |
38054 | #define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
38055 | #define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
38056 | #define DP5_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
38057 | #define DP5_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
38058 | //DP5_DP_SEC_FRAMING3 |
38059 | #define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
38060 | #define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
38061 | #define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
38062 | #define DP5_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
38063 | //DP5_DP_SEC_FRAMING4 |
38064 | #define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
38065 | #define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
38066 | #define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
38067 | #define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
38068 | #define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
38069 | #define DP5_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
38070 | #define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
38071 | #define DP5_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
38072 | //DP5_DP_SEC_AUD_N |
38073 | #define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
38074 | #define DP5_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
38075 | //DP5_DP_SEC_AUD_N_READBACK |
38076 | #define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
38077 | #define DP5_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
38078 | //DP5_DP_SEC_AUD_M |
38079 | #define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
38080 | #define DP5_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
38081 | //DP5_DP_SEC_AUD_M_READBACK |
38082 | #define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
38083 | #define DP5_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
38084 | //DP5_DP_SEC_TIMESTAMP |
38085 | #define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
38086 | #define DP5_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
38087 | //DP5_DP_SEC_PACKET_CNTL |
38088 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
38089 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
38090 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
38091 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
38092 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
38093 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
38094 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
38095 | #define DP5_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
38096 | //DP5_DP_MSE_RATE_CNTL |
38097 | #define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
38098 | #define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
38099 | #define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
38100 | #define DP5_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
38101 | //DP5_DP_MSE_RATE_UPDATE |
38102 | #define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
38103 | #define DP5_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
38104 | //DP5_DP_MSE_SAT0 |
38105 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
38106 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
38107 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
38108 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
38109 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
38110 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
38111 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
38112 | #define DP5_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
38113 | //DP5_DP_MSE_SAT1 |
38114 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
38115 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
38116 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
38117 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
38118 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
38119 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
38120 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
38121 | #define DP5_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
38122 | //DP5_DP_MSE_SAT2 |
38123 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
38124 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
38125 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
38126 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
38127 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
38128 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
38129 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
38130 | #define DP5_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
38131 | //DP5_DP_MSE_SAT_UPDATE |
38132 | #define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
38133 | #define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
38134 | #define DP5_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
38135 | #define DP5_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
38136 | //DP5_DP_MSE_LINK_TIMING |
38137 | #define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
38138 | #define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
38139 | #define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
38140 | #define DP5_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
38141 | //DP5_DP_MSE_MISC_CNTL |
38142 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
38143 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
38144 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
38145 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
38146 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
38147 | #define DP5_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
38148 | //DP5_DP_DPHY_BS_SR_SWAP_CNTL |
38149 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
38150 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
38151 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
38152 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
38153 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
38154 | #define DP5_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
38155 | //DP5_DP_DPHY_HBR2_PATTERN_CONTROL |
38156 | #define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
38157 | #define DP5_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
38158 | //DP5_DP_MSE_SAT0_STATUS |
38159 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
38160 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
38161 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
38162 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
38163 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
38164 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
38165 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
38166 | #define DP5_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
38167 | //DP5_DP_MSE_SAT1_STATUS |
38168 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
38169 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
38170 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
38171 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
38172 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
38173 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
38174 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
38175 | #define DP5_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
38176 | //DP5_DP_MSE_SAT2_STATUS |
38177 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
38178 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
38179 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
38180 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
38181 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
38182 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
38183 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
38184 | #define DP5_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
38185 | //DP5_DP_MSA_TIMING_PARAM1 |
38186 | #define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
38187 | #define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
38188 | #define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
38189 | #define DP5_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
38190 | //DP5_DP_MSA_TIMING_PARAM2 |
38191 | #define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
38192 | #define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
38193 | #define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
38194 | #define DP5_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
38195 | //DP5_DP_MSA_TIMING_PARAM3 |
38196 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
38197 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
38198 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
38199 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
38200 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
38201 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
38202 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
38203 | #define DP5_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
38204 | //DP5_DP_MSA_TIMING_PARAM4 |
38205 | #define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
38206 | #define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
38207 | #define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
38208 | #define DP5_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
38209 | //DP5_DP_MSO_CNTL |
38210 | #define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
38211 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
38212 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
38213 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
38214 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
38215 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
38216 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
38217 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
38218 | #define DP5_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
38219 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
38220 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
38221 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
38222 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
38223 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
38224 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
38225 | #define DP5_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
38226 | //DP5_DP_MSO_CNTL1 |
38227 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
38228 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
38229 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
38230 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
38231 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
38232 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
38233 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
38234 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
38235 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
38236 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
38237 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
38238 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
38239 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
38240 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
38241 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
38242 | #define DP5_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
38243 | //DP5_DP_DSC_CNTL |
38244 | #define DP5_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
38245 | #define DP5_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
38246 | //DP5_DP_SEC_CNTL2 |
38247 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
38248 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
38249 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
38250 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
38251 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
38252 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
38253 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
38254 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
38255 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
38256 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
38257 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
38258 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
38259 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
38260 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
38261 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
38262 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
38263 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
38264 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
38265 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
38266 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
38267 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
38268 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
38269 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
38270 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
38271 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
38272 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
38273 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
38274 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
38275 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
38276 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
38277 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
38278 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
38279 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
38280 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
38281 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
38282 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
38283 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
38284 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
38285 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
38286 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
38287 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
38288 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
38289 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
38290 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
38291 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
38292 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
38293 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
38294 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
38295 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
38296 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
38297 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
38298 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
38299 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
38300 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
38301 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
38302 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
38303 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
38304 | #define DP5_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
38305 | //DP5_DP_SEC_CNTL3 |
38306 | #define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
38307 | #define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
38308 | #define DP5_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
38309 | #define DP5_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
38310 | //DP5_DP_SEC_CNTL4 |
38311 | #define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
38312 | #define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
38313 | #define DP5_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
38314 | #define DP5_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
38315 | //DP5_DP_SEC_CNTL5 |
38316 | #define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
38317 | #define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
38318 | #define DP5_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
38319 | #define DP5_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
38320 | //DP5_DP_SEC_CNTL6 |
38321 | #define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
38322 | #define DP5_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
38323 | //DP5_DP_SEC_CNTL7 |
38324 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
38325 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
38326 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
38327 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
38328 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
38329 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
38330 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
38331 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
38332 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
38333 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
38334 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
38335 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
38336 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
38337 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
38338 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
38339 | #define DP5_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
38340 | //DP5_DP_DB_CNTL |
38341 | #define DP5_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
38342 | #define DP5_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
38343 | #define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
38344 | #define DP5_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
38345 | #define DP5_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
38346 | #define DP5_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
38347 | #define DP5_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
38348 | #define DP5_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
38349 | #define DP5_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
38350 | #define DP5_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
38351 | //DP5_DP_MSA_VBID_MISC |
38352 | #define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
38353 | #define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
38354 | #define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
38355 | #define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
38356 | #define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
38357 | #define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
38358 | #define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
38359 | #define DP5_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
38360 | #define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
38361 | #define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
38362 | #define DP5_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
38363 | #define DP5_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
38364 | |
38365 | |
38366 | // addressBlock: dce_dc_dio_dig6_dispdec |
38367 | //DIG6_DIG_FE_CNTL |
38368 | #define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
38369 | #define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
38370 | #define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
38371 | #define DIG6_DIG_FE_CNTL__DIG_START__SHIFT 0xa |
38372 | #define DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc |
38373 | #define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
38374 | #define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c |
38375 | #define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e |
38376 | #define DIG6_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L |
38377 | #define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L |
38378 | #define DIG6_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L |
38379 | #define DIG6_DIG_FE_CNTL__DIG_START_MASK 0x00000400L |
38380 | #define DIG6_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L |
38381 | #define DIG6_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L |
38382 | #define DIG6_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L |
38383 | #define DIG6_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L |
38384 | //DIG6_DIG_OUTPUT_CRC_CNTL |
38385 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
38386 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
38387 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
38388 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L |
38389 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L |
38390 | #define DIG6_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L |
38391 | //DIG6_DIG_OUTPUT_CRC_RESULT |
38392 | #define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
38393 | #define DIG6_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL |
38394 | //DIG6_DIG_CLOCK_PATTERN |
38395 | #define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
38396 | #define DIG6_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL |
38397 | //DIG6_DIG_TEST_PATTERN |
38398 | #define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
38399 | #define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
38400 | #define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
38401 | #define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
38402 | #define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
38403 | #define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
38404 | #define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L |
38405 | #define DIG6_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L |
38406 | #define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L |
38407 | #define DIG6_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L |
38408 | #define DIG6_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L |
38409 | #define DIG6_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L |
38410 | //DIG6_DIG_RANDOM_PATTERN_SEED |
38411 | #define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
38412 | #define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
38413 | #define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL |
38414 | #define DIG6_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L |
38415 | //DIG6_DIG_FIFO_STATUS |
38416 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
38417 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
38418 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
38419 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
38420 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
38421 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
38422 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
38423 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a |
38424 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
38425 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
38426 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
38427 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L |
38428 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L |
38429 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL |
38430 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L |
38431 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L |
38432 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L |
38433 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L |
38434 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L |
38435 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L |
38436 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L |
38437 | #define DIG6_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L |
38438 | //DIG6_HDMI_CONTROL |
38439 | #define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
38440 | #define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 |
38441 | #define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 |
38442 | #define 0x3 |
38443 | #define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
38444 | #define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
38445 | #define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
38446 | #define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
38447 | #define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
38448 | #define DIG6_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L |
38449 | #define DIG6_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L |
38450 | #define DIG6_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L |
38451 | #define 0x00000008L |
38452 | #define DIG6_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L |
38453 | #define DIG6_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L |
38454 | #define DIG6_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L |
38455 | #define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L |
38456 | #define DIG6_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L |
38457 | //DIG6_HDMI_STATUS |
38458 | #define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
38459 | #define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
38460 | #define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
38461 | #define DIG6_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
38462 | #define DIG6_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L |
38463 | #define DIG6_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L |
38464 | #define DIG6_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L |
38465 | #define DIG6_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L |
38466 | //DIG6_HDMI_AUDIO_PACKET_CONTROL |
38467 | #define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
38468 | #define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
38469 | #define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L |
38470 | #define DIG6_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L |
38471 | //DIG6_HDMI_ACR_PACKET_CONTROL |
38472 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
38473 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
38474 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
38475 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
38476 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
38477 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
38478 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
38479 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L |
38480 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L |
38481 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L |
38482 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L |
38483 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L |
38484 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L |
38485 | #define DIG6_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L |
38486 | //DIG6_HDMI_VBI_PACKET_CONTROL |
38487 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
38488 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
38489 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
38490 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
38491 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
38492 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
38493 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L |
38494 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L |
38495 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L |
38496 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L |
38497 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L |
38498 | #define DIG6_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L |
38499 | //DIG6_HDMI_INFOFRAME_CONTROL0 |
38500 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
38501 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
38502 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
38503 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
38504 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L |
38505 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L |
38506 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L |
38507 | #define DIG6_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L |
38508 | //DIG6_HDMI_INFOFRAME_CONTROL1 |
38509 | #define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
38510 | #define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
38511 | #define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L |
38512 | #define DIG6_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L |
38513 | //DIG6_HDMI_GENERIC_PACKET_CONTROL0 |
38514 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
38515 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
38516 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
38517 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
38518 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
38519 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
38520 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L |
38521 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L |
38522 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L |
38523 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L |
38524 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003F0000L |
38525 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3F000000L |
38526 | //DIG6_AFMT_INTERRUPT_STATUS |
38527 | //DIG6_HDMI_GC |
38528 | #define DIG6_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
38529 | #define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
38530 | #define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
38531 | #define DIG6_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
38532 | #define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
38533 | #define DIG6_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L |
38534 | #define DIG6_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L |
38535 | #define DIG6_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L |
38536 | #define DIG6_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L |
38537 | #define DIG6_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L |
38538 | //DIG6_AFMT_AUDIO_PACKET_CONTROL2 |
38539 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
38540 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
38541 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
38542 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
38543 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
38544 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
38545 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L |
38546 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L |
38547 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L |
38548 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L |
38549 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L |
38550 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L |
38551 | //DIG6_AFMT_ISRC1_0 |
38552 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
38553 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
38554 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
38555 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L |
38556 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L |
38557 | #define DIG6_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L |
38558 | //DIG6_AFMT_ISRC1_1 |
38559 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
38560 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
38561 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
38562 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
38563 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL |
38564 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L |
38565 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L |
38566 | #define DIG6_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L |
38567 | //DIG6_AFMT_ISRC1_2 |
38568 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
38569 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
38570 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
38571 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
38572 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL |
38573 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L |
38574 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L |
38575 | #define DIG6_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L |
38576 | //DIG6_AFMT_ISRC1_3 |
38577 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
38578 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
38579 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
38580 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
38581 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL |
38582 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L |
38583 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L |
38584 | #define DIG6_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L |
38585 | //DIG6_AFMT_ISRC1_4 |
38586 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
38587 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
38588 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
38589 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
38590 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL |
38591 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L |
38592 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L |
38593 | #define DIG6_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L |
38594 | //DIG6_AFMT_ISRC2_0 |
38595 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
38596 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
38597 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
38598 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
38599 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL |
38600 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L |
38601 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L |
38602 | #define DIG6_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L |
38603 | //DIG6_AFMT_ISRC2_1 |
38604 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
38605 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
38606 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
38607 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
38608 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL |
38609 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L |
38610 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L |
38611 | #define DIG6_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L |
38612 | //DIG6_AFMT_ISRC2_2 |
38613 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
38614 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
38615 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
38616 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
38617 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL |
38618 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L |
38619 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L |
38620 | #define DIG6_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L |
38621 | //DIG6_AFMT_ISRC2_3 |
38622 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
38623 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
38624 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
38625 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
38626 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL |
38627 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L |
38628 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L |
38629 | #define DIG6_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L |
38630 | //DIG6_HDMI_GENERIC_PACKET_CONTROL2 |
38631 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND__SHIFT 0x0 |
38632 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT__SHIFT 0x1 |
38633 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND__SHIFT 0x4 |
38634 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT__SHIFT 0x5 |
38635 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE__SHIFT 0x10 |
38636 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE__SHIFT 0x18 |
38637 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_SEND_MASK 0x00000001L |
38638 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_CONT_MASK 0x00000002L |
38639 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_SEND_MASK 0x00000010L |
38640 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_CONT_MASK 0x00000020L |
38641 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_LINE_MASK 0x003F0000L |
38642 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_LINE_MASK 0x3F000000L |
38643 | //DIG6_HDMI_GENERIC_PACKET_CONTROL3 |
38644 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND__SHIFT 0x0 |
38645 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT__SHIFT 0x1 |
38646 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND__SHIFT 0x4 |
38647 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT__SHIFT 0x5 |
38648 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE__SHIFT 0x10 |
38649 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE__SHIFT 0x18 |
38650 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_SEND_MASK 0x00000001L |
38651 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_CONT_MASK 0x00000002L |
38652 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_SEND_MASK 0x00000010L |
38653 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_CONT_MASK 0x00000020L |
38654 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC6_LINE_MASK 0x003F0000L |
38655 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC7_LINE_MASK 0x3F000000L |
38656 | //DIG6_HDMI_DB_CONTROL |
38657 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 |
38658 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 |
38659 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 |
38660 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 |
38661 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc |
38662 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L |
38663 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L |
38664 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L |
38665 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L |
38666 | #define DIG6_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L |
38667 | //DIG6_AFMT_MPEG_INFO0 |
38668 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
38669 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
38670 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
38671 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
38672 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL |
38673 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L |
38674 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L |
38675 | #define DIG6_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L |
38676 | //DIG6_AFMT_MPEG_INFO1 |
38677 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
38678 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
38679 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
38680 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL |
38681 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L |
38682 | #define DIG6_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L |
38683 | //DIG6_AFMT_GENERIC_HDR |
38684 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
38685 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
38686 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
38687 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
38688 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL |
38689 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L |
38690 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L |
38691 | #define DIG6_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L |
38692 | //DIG6_AFMT_GENERIC_0 |
38693 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
38694 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
38695 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
38696 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
38697 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL |
38698 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L |
38699 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L |
38700 | #define DIG6_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L |
38701 | //DIG6_AFMT_GENERIC_1 |
38702 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
38703 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
38704 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
38705 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
38706 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL |
38707 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L |
38708 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L |
38709 | #define DIG6_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L |
38710 | //DIG6_AFMT_GENERIC_2 |
38711 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
38712 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
38713 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
38714 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
38715 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL |
38716 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L |
38717 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L |
38718 | #define DIG6_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L |
38719 | //DIG6_AFMT_GENERIC_3 |
38720 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
38721 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
38722 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
38723 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
38724 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL |
38725 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L |
38726 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L |
38727 | #define DIG6_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L |
38728 | //DIG6_AFMT_GENERIC_4 |
38729 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
38730 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
38731 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
38732 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
38733 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL |
38734 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L |
38735 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L |
38736 | #define DIG6_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L |
38737 | //DIG6_AFMT_GENERIC_5 |
38738 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
38739 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
38740 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
38741 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
38742 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL |
38743 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L |
38744 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L |
38745 | #define DIG6_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L |
38746 | //DIG6_AFMT_GENERIC_6 |
38747 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
38748 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
38749 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
38750 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
38751 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL |
38752 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L |
38753 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L |
38754 | #define DIG6_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L |
38755 | //DIG6_AFMT_GENERIC_7 |
38756 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
38757 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
38758 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
38759 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
38760 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL |
38761 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L |
38762 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L |
38763 | #define DIG6_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L |
38764 | //DIG6_HDMI_GENERIC_PACKET_CONTROL1 |
38765 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
38766 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
38767 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
38768 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
38769 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
38770 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
38771 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L |
38772 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L |
38773 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L |
38774 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L |
38775 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003F0000L |
38776 | #define DIG6_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3F000000L |
38777 | //DIG6_HDMI_ACR_32_0 |
38778 | #define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
38779 | #define DIG6_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L |
38780 | //DIG6_HDMI_ACR_32_1 |
38781 | #define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
38782 | #define DIG6_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL |
38783 | //DIG6_HDMI_ACR_44_0 |
38784 | #define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
38785 | #define DIG6_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L |
38786 | //DIG6_HDMI_ACR_44_1 |
38787 | #define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
38788 | #define DIG6_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL |
38789 | //DIG6_HDMI_ACR_48_0 |
38790 | #define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
38791 | #define DIG6_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L |
38792 | //DIG6_HDMI_ACR_48_1 |
38793 | #define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
38794 | #define DIG6_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL |
38795 | //DIG6_HDMI_ACR_STATUS_0 |
38796 | #define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
38797 | #define DIG6_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L |
38798 | //DIG6_HDMI_ACR_STATUS_1 |
38799 | #define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
38800 | #define DIG6_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL |
38801 | //DIG6_AFMT_AUDIO_INFO0 |
38802 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
38803 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
38804 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
38805 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
38806 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
38807 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL |
38808 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L |
38809 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L |
38810 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L |
38811 | #define DIG6_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L |
38812 | //DIG6_AFMT_AUDIO_INFO1 |
38813 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
38814 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
38815 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
38816 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
38817 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL |
38818 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L |
38819 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L |
38820 | #define DIG6_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L |
38821 | //DIG6_AFMT_60958_0 |
38822 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
38823 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
38824 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
38825 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
38826 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
38827 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
38828 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
38829 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
38830 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
38831 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
38832 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L |
38833 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L |
38834 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L |
38835 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L |
38836 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L |
38837 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L |
38838 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L |
38839 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L |
38840 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L |
38841 | #define DIG6_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L |
38842 | //DIG6_AFMT_60958_1 |
38843 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
38844 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
38845 | #define DIG6_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
38846 | #define DIG6_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
38847 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
38848 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL |
38849 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L |
38850 | #define DIG6_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L |
38851 | #define DIG6_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L |
38852 | #define DIG6_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L |
38853 | //DIG6_AFMT_AUDIO_CRC_CONTROL |
38854 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
38855 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
38856 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
38857 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
38858 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
38859 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L |
38860 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L |
38861 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L |
38862 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L |
38863 | #define DIG6_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L |
38864 | //DIG6_AFMT_RAMP_CONTROL0 |
38865 | #define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
38866 | #define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
38867 | #define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL |
38868 | #define DIG6_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L |
38869 | //DIG6_AFMT_RAMP_CONTROL1 |
38870 | #define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
38871 | #define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
38872 | #define DIG6_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL |
38873 | #define DIG6_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L |
38874 | //DIG6_AFMT_RAMP_CONTROL2 |
38875 | #define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
38876 | #define DIG6_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL |
38877 | //DIG6_AFMT_RAMP_CONTROL3 |
38878 | #define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
38879 | #define DIG6_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL |
38880 | //DIG6_AFMT_60958_2 |
38881 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
38882 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
38883 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
38884 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
38885 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
38886 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
38887 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
38888 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
38889 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L |
38890 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L |
38891 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L |
38892 | #define DIG6_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L |
38893 | //DIG6_AFMT_AUDIO_CRC_RESULT |
38894 | #define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
38895 | #define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
38896 | #define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L |
38897 | #define DIG6_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L |
38898 | //DIG6_AFMT_STATUS |
38899 | #define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
38900 | #define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
38901 | #define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
38902 | #define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
38903 | #define DIG6_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L |
38904 | #define DIG6_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L |
38905 | #define DIG6_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L |
38906 | #define DIG6_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L |
38907 | //DIG6_AFMT_AUDIO_PACKET_CONTROL |
38908 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
38909 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
38910 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
38911 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
38912 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
38913 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
38914 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
38915 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
38916 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L |
38917 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L |
38918 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L |
38919 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L |
38920 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L |
38921 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L |
38922 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L |
38923 | #define DIG6_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L |
38924 | //DIG6_AFMT_VBI_PACKET_CONTROL |
38925 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 |
38926 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 |
38927 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 |
38928 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c |
38929 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L |
38930 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L |
38931 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L |
38932 | #define DIG6_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L |
38933 | //DIG6_AFMT_INFOFRAME_CONTROL0 |
38934 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
38935 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
38936 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
38937 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L |
38938 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L |
38939 | #define DIG6_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L |
38940 | //DIG6_AFMT_AUDIO_SRC_CONTROL |
38941 | #define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
38942 | #define DIG6_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L |
38943 | //DIG6_DIG_BE_CNTL |
38944 | #define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 |
38945 | #define DIG6_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 |
38946 | #define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
38947 | #define DIG6_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
38948 | #define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
38949 | #define DIG6_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L |
38950 | #define DIG6_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L |
38951 | #define DIG6_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L |
38952 | #define DIG6_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L |
38953 | #define DIG6_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L |
38954 | //DIG6_DIG_BE_EN_CNTL |
38955 | #define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
38956 | #define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
38957 | #define DIG6_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L |
38958 | #define DIG6_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L |
38959 | //DIG6_TMDS_CNTL |
38960 | #define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
38961 | #define DIG6_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L |
38962 | //DIG6_TMDS_CONTROL_CHAR |
38963 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
38964 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
38965 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
38966 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
38967 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L |
38968 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L |
38969 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L |
38970 | #define DIG6_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L |
38971 | //DIG6_TMDS_CONTROL0_FEEDBACK |
38972 | #define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
38973 | #define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
38974 | #define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L |
38975 | #define DIG6_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L |
38976 | //DIG6_TMDS_STEREOSYNC_CTL_SEL |
38977 | #define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
38978 | #define DIG6_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L |
38979 | //DIG6_TMDS_SYNC_CHAR_PATTERN_0_1 |
38980 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
38981 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
38982 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL |
38983 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L |
38984 | //DIG6_TMDS_SYNC_CHAR_PATTERN_2_3 |
38985 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
38986 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
38987 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL |
38988 | #define DIG6_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L |
38989 | //DIG6_TMDS_CTL_BITS |
38990 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
38991 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
38992 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
38993 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
38994 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L |
38995 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L |
38996 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L |
38997 | #define DIG6_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L |
38998 | //DIG6_TMDS_DCBALANCER_CONTROL |
38999 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
39000 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
39001 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
39002 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
39003 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L |
39004 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L |
39005 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L |
39006 | #define DIG6_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L |
39007 | //DIG6_TMDS_CTL0_1_GEN_CNTL |
39008 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
39009 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
39010 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
39011 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
39012 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
39013 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
39014 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
39015 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
39016 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
39017 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
39018 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
39019 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
39020 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
39021 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
39022 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
39023 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL |
39024 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L |
39025 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L |
39026 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L |
39027 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L |
39028 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L |
39029 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L |
39030 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L |
39031 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L |
39032 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L |
39033 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L |
39034 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L |
39035 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L |
39036 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L |
39037 | #define DIG6_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L |
39038 | //DIG6_TMDS_CTL2_3_GEN_CNTL |
39039 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
39040 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
39041 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
39042 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
39043 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
39044 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
39045 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
39046 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
39047 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
39048 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
39049 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
39050 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
39051 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
39052 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
39053 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL |
39054 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L |
39055 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L |
39056 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L |
39057 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L |
39058 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L |
39059 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L |
39060 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L |
39061 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L |
39062 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L |
39063 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L |
39064 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L |
39065 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L |
39066 | #define DIG6_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L |
39067 | //DIG6_DIG_VERSION |
39068 | #define DIG6_DIG_VERSION__DIG_TYPE__SHIFT 0x0 |
39069 | #define DIG6_DIG_VERSION__DIG_TYPE_MASK 0x00000001L |
39070 | //DIG6_DIG_LANE_ENABLE |
39071 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
39072 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
39073 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
39074 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
39075 | #define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
39076 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L |
39077 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L |
39078 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L |
39079 | #define DIG6_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L |
39080 | #define DIG6_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L |
39081 | //DIG6_AFMT_CNTL |
39082 | #define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 |
39083 | #define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 |
39084 | #define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L |
39085 | #define DIG6_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L |
39086 | //DIG6_AFMT_VBI_PACKET_CONTROL1 |
39087 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 |
39088 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 |
39089 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 |
39090 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 |
39091 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 |
39092 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 |
39093 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 |
39094 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 |
39095 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 |
39096 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 |
39097 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa |
39098 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb |
39099 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc |
39100 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd |
39101 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe |
39102 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf |
39103 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 |
39104 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 |
39105 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 |
39106 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 |
39107 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 |
39108 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 |
39109 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 |
39110 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 |
39111 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 |
39112 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 |
39113 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a |
39114 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b |
39115 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c |
39116 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d |
39117 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e |
39118 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f |
39119 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L |
39120 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L |
39121 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L |
39122 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L |
39123 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L |
39124 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L |
39125 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L |
39126 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L |
39127 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L |
39128 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L |
39129 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L |
39130 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L |
39131 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L |
39132 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L |
39133 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L |
39134 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L |
39135 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L |
39136 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L |
39137 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L |
39138 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L |
39139 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L |
39140 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L |
39141 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L |
39142 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L |
39143 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L |
39144 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L |
39145 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L |
39146 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L |
39147 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L |
39148 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L |
39149 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L |
39150 | #define DIG6_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L |
39151 | |
39152 | |
39153 | // addressBlock: dce_dc_dio_dp6_dispdec |
39154 | //DP6_DP_LINK_CNTL |
39155 | #define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
39156 | #define DP6_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
39157 | #define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
39158 | #define DP6_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L |
39159 | #define DP6_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L |
39160 | #define DP6_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L |
39161 | //DP6_DP_PIXEL_FORMAT |
39162 | #define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
39163 | #define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
39164 | #define DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c |
39165 | #define DP6_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L |
39166 | #define DP6_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L |
39167 | #define DP6_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L |
39168 | //DP6_DP_MSA_COLORIMETRY |
39169 | #define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 |
39170 | #define DP6_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L |
39171 | //DP6_DP_CONFIG |
39172 | #define DP6_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
39173 | #define DP6_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L |
39174 | //DP6_DP_VID_STREAM_CNTL |
39175 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
39176 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
39177 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
39178 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
39179 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L |
39180 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L |
39181 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L |
39182 | #define DP6_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L |
39183 | //DP6_DP_STEER_FIFO |
39184 | #define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
39185 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
39186 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
39187 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
39188 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
39189 | #define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
39190 | #define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
39191 | #define DP6_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L |
39192 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L |
39193 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L |
39194 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L |
39195 | #define DP6_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L |
39196 | #define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L |
39197 | #define DP6_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L |
39198 | //DP6_DP_MSA_MISC |
39199 | #define DP6_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 |
39200 | #define DP6_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
39201 | #define DP6_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
39202 | #define DP6_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
39203 | #define DP6_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL |
39204 | #define DP6_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L |
39205 | #define DP6_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L |
39206 | #define DP6_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L |
39207 | //DP6_DP_VID_TIMING |
39208 | #define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 |
39209 | #define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
39210 | #define DP6_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa |
39211 | #define DP6_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc |
39212 | #define DP6_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
39213 | #define DP6_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L |
39214 | #define DP6_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L |
39215 | #define DP6_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L |
39216 | #define DP6_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L |
39217 | #define DP6_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L |
39218 | //DP6_DP_VID_N |
39219 | #define DP6_DP_VID_N__DP_VID_N__SHIFT 0x0 |
39220 | #define DP6_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL |
39221 | //DP6_DP_VID_M |
39222 | #define DP6_DP_VID_M__DP_VID_M__SHIFT 0x0 |
39223 | #define DP6_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL |
39224 | //DP6_DP_LINK_FRAMING_CNTL |
39225 | #define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
39226 | #define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
39227 | #define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
39228 | #define DP6_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL |
39229 | #define DP6_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L |
39230 | #define DP6_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L |
39231 | //DP6_DP_HBR2_EYE_PATTERN |
39232 | #define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
39233 | #define DP6_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L |
39234 | //DP6_DP_VID_MSA_VBID |
39235 | #define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
39236 | #define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
39237 | #define DP6_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL |
39238 | #define DP6_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L |
39239 | //DP6_DP_VID_INTERRUPT_CNTL |
39240 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
39241 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
39242 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
39243 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L |
39244 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L |
39245 | #define DP6_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L |
39246 | //DP6_DP_DPHY_CNTL |
39247 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
39248 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
39249 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
39250 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
39251 | #define DP6_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
39252 | #define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
39253 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L |
39254 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L |
39255 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L |
39256 | #define DP6_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L |
39257 | #define DP6_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L |
39258 | #define DP6_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L |
39259 | //DP6_DP_DPHY_TRAINING_PATTERN_SEL |
39260 | #define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
39261 | #define DP6_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L |
39262 | //DP6_DP_DPHY_SYM0 |
39263 | #define DP6_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
39264 | #define DP6_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
39265 | #define DP6_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
39266 | #define DP6_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL |
39267 | #define DP6_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L |
39268 | #define DP6_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L |
39269 | //DP6_DP_DPHY_SYM1 |
39270 | #define DP6_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
39271 | #define DP6_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
39272 | #define DP6_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
39273 | #define DP6_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL |
39274 | #define DP6_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L |
39275 | #define DP6_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L |
39276 | //DP6_DP_DPHY_SYM2 |
39277 | #define DP6_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
39278 | #define DP6_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
39279 | #define DP6_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL |
39280 | #define DP6_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L |
39281 | //DP6_DP_DPHY_8B10B_CNTL |
39282 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
39283 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
39284 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
39285 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L |
39286 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L |
39287 | #define DP6_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L |
39288 | //DP6_DP_DPHY_PRBS_CNTL |
39289 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
39290 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
39291 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
39292 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L |
39293 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L |
39294 | #define DP6_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L |
39295 | //DP6_DP_DPHY_SCRAM_CNTL |
39296 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 |
39297 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
39298 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
39299 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 |
39300 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L |
39301 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L |
39302 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L |
39303 | #define DP6_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L |
39304 | //DP6_DP_DPHY_CRC_EN |
39305 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
39306 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
39307 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
39308 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L |
39309 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L |
39310 | #define DP6_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L |
39311 | //DP6_DP_DPHY_CRC_CNTL |
39312 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
39313 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
39314 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
39315 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L |
39316 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L |
39317 | #define DP6_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L |
39318 | //DP6_DP_DPHY_CRC_RESULT |
39319 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
39320 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
39321 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
39322 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
39323 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL |
39324 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L |
39325 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L |
39326 | #define DP6_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L |
39327 | //DP6_DP_DPHY_CRC_MST_CNTL |
39328 | #define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
39329 | #define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
39330 | #define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL |
39331 | #define DP6_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L |
39332 | //DP6_DP_DPHY_CRC_MST_STATUS |
39333 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
39334 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
39335 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
39336 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L |
39337 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L |
39338 | #define DP6_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L |
39339 | //DP6_DP_DPHY_FAST_TRAINING |
39340 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
39341 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
39342 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
39343 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
39344 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
39345 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L |
39346 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L |
39347 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L |
39348 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L |
39349 | #define DP6_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L |
39350 | //DP6_DP_DPHY_FAST_TRAINING_STATUS |
39351 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
39352 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
39353 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
39354 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
39355 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L |
39356 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L |
39357 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L |
39358 | #define DP6_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L |
39359 | //DP6_DP_SEC_CNTL |
39360 | #define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
39361 | #define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
39362 | #define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
39363 | #define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
39364 | #define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
39365 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
39366 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
39367 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
39368 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
39369 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 |
39370 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 |
39371 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a |
39372 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b |
39373 | #define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
39374 | #define DP6_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L |
39375 | #define DP6_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L |
39376 | #define DP6_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L |
39377 | #define DP6_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L |
39378 | #define DP6_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L |
39379 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L |
39380 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L |
39381 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L |
39382 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L |
39383 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L |
39384 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L |
39385 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L |
39386 | #define DP6_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L |
39387 | #define DP6_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L |
39388 | //DP6_DP_SEC_CNTL1 |
39389 | #define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
39390 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 |
39391 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 |
39392 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 |
39393 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 |
39394 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 |
39395 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 |
39396 | #define DP6_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L |
39397 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L |
39398 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L |
39399 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L |
39400 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L |
39401 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L |
39402 | #define DP6_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L |
39403 | //DP6_DP_SEC_FRAMING1 |
39404 | #define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
39405 | #define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
39406 | #define DP6_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL |
39407 | #define DP6_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
39408 | //DP6_DP_SEC_FRAMING2 |
39409 | #define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
39410 | #define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
39411 | #define DP6_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL |
39412 | #define DP6_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
39413 | //DP6_DP_SEC_FRAMING3 |
39414 | #define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
39415 | #define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
39416 | #define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL |
39417 | #define DP6_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L |
39418 | //DP6_DP_SEC_FRAMING4 |
39419 | #define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
39420 | #define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
39421 | #define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
39422 | #define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
39423 | #define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L |
39424 | #define DP6_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L |
39425 | #define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L |
39426 | #define DP6_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L |
39427 | //DP6_DP_SEC_AUD_N |
39428 | #define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
39429 | #define DP6_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL |
39430 | //DP6_DP_SEC_AUD_N_READBACK |
39431 | #define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
39432 | #define DP6_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL |
39433 | //DP6_DP_SEC_AUD_M |
39434 | #define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
39435 | #define DP6_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL |
39436 | //DP6_DP_SEC_AUD_M_READBACK |
39437 | #define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
39438 | #define DP6_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL |
39439 | //DP6_DP_SEC_TIMESTAMP |
39440 | #define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
39441 | #define DP6_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L |
39442 | //DP6_DP_SEC_PACKET_CNTL |
39443 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
39444 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
39445 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
39446 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
39447 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL |
39448 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L |
39449 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L |
39450 | #define DP6_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L |
39451 | //DP6_DP_MSE_RATE_CNTL |
39452 | #define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
39453 | #define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
39454 | #define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL |
39455 | #define DP6_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L |
39456 | //DP6_DP_MSE_RATE_UPDATE |
39457 | #define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
39458 | #define DP6_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L |
39459 | //DP6_DP_MSE_SAT0 |
39460 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
39461 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
39462 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
39463 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
39464 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L |
39465 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L |
39466 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L |
39467 | #define DP6_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L |
39468 | //DP6_DP_MSE_SAT1 |
39469 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
39470 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
39471 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
39472 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
39473 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L |
39474 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L |
39475 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L |
39476 | #define DP6_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L |
39477 | //DP6_DP_MSE_SAT2 |
39478 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
39479 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
39480 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
39481 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
39482 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L |
39483 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L |
39484 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L |
39485 | #define DP6_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L |
39486 | //DP6_DP_MSE_SAT_UPDATE |
39487 | #define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
39488 | #define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
39489 | #define DP6_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L |
39490 | #define DP6_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L |
39491 | //DP6_DP_MSE_LINK_TIMING |
39492 | #define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
39493 | #define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
39494 | #define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL |
39495 | #define DP6_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L |
39496 | //DP6_DP_MSE_MISC_CNTL |
39497 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
39498 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
39499 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
39500 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L |
39501 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L |
39502 | #define DP6_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L |
39503 | //DP6_DP_DPHY_BS_SR_SWAP_CNTL |
39504 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 |
39505 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf |
39506 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 |
39507 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL |
39508 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L |
39509 | #define DP6_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L |
39510 | //DP6_DP_DPHY_HBR2_PATTERN_CONTROL |
39511 | #define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 |
39512 | #define DP6_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L |
39513 | //DP6_DP_MSE_SAT0_STATUS |
39514 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 |
39515 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 |
39516 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 |
39517 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 |
39518 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L |
39519 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L |
39520 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L |
39521 | #define DP6_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L |
39522 | //DP6_DP_MSE_SAT1_STATUS |
39523 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 |
39524 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 |
39525 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 |
39526 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 |
39527 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L |
39528 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L |
39529 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L |
39530 | #define DP6_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L |
39531 | //DP6_DP_MSE_SAT2_STATUS |
39532 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 |
39533 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 |
39534 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 |
39535 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 |
39536 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L |
39537 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L |
39538 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L |
39539 | #define DP6_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L |
39540 | //DP6_DP_MSA_TIMING_PARAM1 |
39541 | #define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 |
39542 | #define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 |
39543 | #define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL |
39544 | #define DP6_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L |
39545 | //DP6_DP_MSA_TIMING_PARAM2 |
39546 | #define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 |
39547 | #define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 |
39548 | #define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL |
39549 | #define DP6_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L |
39550 | //DP6_DP_MSA_TIMING_PARAM3 |
39551 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 |
39552 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf |
39553 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 |
39554 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f |
39555 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL |
39556 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L |
39557 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L |
39558 | #define DP6_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L |
39559 | //DP6_DP_MSA_TIMING_PARAM4 |
39560 | #define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 |
39561 | #define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 |
39562 | #define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL |
39563 | #define DP6_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L |
39564 | //DP6_DP_MSO_CNTL |
39565 | #define DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 |
39566 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 |
39567 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 |
39568 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc |
39569 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 |
39570 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 |
39571 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 |
39572 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c |
39573 | #define DP6_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L |
39574 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L |
39575 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L |
39576 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L |
39577 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L |
39578 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L |
39579 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L |
39580 | #define DP6_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L |
39581 | //DP6_DP_MSO_CNTL1 |
39582 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 |
39583 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 |
39584 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 |
39585 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc |
39586 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 |
39587 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 |
39588 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 |
39589 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c |
39590 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL |
39591 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L |
39592 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L |
39593 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L |
39594 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L |
39595 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L |
39596 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L |
39597 | #define DP6_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L |
39598 | //DP6_DP_DSC_CNTL |
39599 | #define DP6_DP_DSC_CNTL__DP_DSC_EN__SHIFT 0x0 |
39600 | #define DP6_DP_DSC_CNTL__DP_DSC_EN_MASK 0x00000001L |
39601 | //DP6_DP_SEC_CNTL2 |
39602 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 |
39603 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 |
39604 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 |
39605 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 |
39606 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 |
39607 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 |
39608 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 |
39609 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 |
39610 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 |
39611 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 |
39612 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa |
39613 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb |
39614 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc |
39615 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd |
39616 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe |
39617 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf |
39618 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 |
39619 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 |
39620 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 |
39621 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 |
39622 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 |
39623 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 |
39624 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 |
39625 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 |
39626 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 |
39627 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 |
39628 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a |
39629 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b |
39630 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c |
39631 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L |
39632 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L |
39633 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L |
39634 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L |
39635 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L |
39636 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L |
39637 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L |
39638 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L |
39639 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L |
39640 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L |
39641 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L |
39642 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L |
39643 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L |
39644 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L |
39645 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L |
39646 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L |
39647 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L |
39648 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L |
39649 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L |
39650 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L |
39651 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L |
39652 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L |
39653 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L |
39654 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L |
39655 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L |
39656 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L |
39657 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L |
39658 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L |
39659 | #define DP6_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L |
39660 | //DP6_DP_SEC_CNTL3 |
39661 | #define DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 |
39662 | #define DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 |
39663 | #define DP6_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL |
39664 | #define DP6_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L |
39665 | //DP6_DP_SEC_CNTL4 |
39666 | #define DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 |
39667 | #define DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 |
39668 | #define DP6_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL |
39669 | #define DP6_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L |
39670 | //DP6_DP_SEC_CNTL5 |
39671 | #define DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 |
39672 | #define DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 |
39673 | #define DP6_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL |
39674 | #define DP6_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L |
39675 | //DP6_DP_SEC_CNTL6 |
39676 | #define DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 |
39677 | #define DP6_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL |
39678 | //DP6_DP_SEC_CNTL7 |
39679 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 |
39680 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 |
39681 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 |
39682 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc |
39683 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 |
39684 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 |
39685 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 |
39686 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c |
39687 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L |
39688 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L |
39689 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L |
39690 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L |
39691 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L |
39692 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L |
39693 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L |
39694 | #define DP6_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L |
39695 | //DP6_DP_DB_CNTL |
39696 | #define DP6_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 |
39697 | #define DP6_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 |
39698 | #define DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 |
39699 | #define DP6_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 |
39700 | #define DP6_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc |
39701 | #define DP6_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L |
39702 | #define DP6_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L |
39703 | #define DP6_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L |
39704 | #define DP6_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L |
39705 | #define DP6_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L |
39706 | //DP6_DP_MSA_VBID_MISC |
39707 | #define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
39708 | #define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 |
39709 | #define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 |
39710 | #define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 |
39711 | #define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc |
39712 | #define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd |
39713 | #define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L |
39714 | #define DP6_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L |
39715 | #define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L |
39716 | #define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L |
39717 | #define DP6_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L |
39718 | #define DP6_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L |
39719 | |
39720 | |
39721 | // addressBlock: dce_dc_dcio_dcio_dispdec |
39722 | //DC_GENERICA |
39723 | #define DC_GENERICA__GENERICA_EN__SHIFT 0x0 |
39724 | #define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 |
39725 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
39726 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
39727 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
39728 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
39729 | #define DC_GENERICA__GENERICA_EN_MASK 0x00000001L |
39730 | #define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L |
39731 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L |
39732 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L |
39733 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L |
39734 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L |
39735 | //DC_GENERICB |
39736 | #define DC_GENERICB__GENERICB_EN__SHIFT 0x0 |
39737 | #define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 |
39738 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
39739 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
39740 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
39741 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
39742 | #define DC_GENERICB__GENERICB_EN_MASK 0x00000001L |
39743 | #define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L |
39744 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L |
39745 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L |
39746 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L |
39747 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L |
39748 | //DC_REF_CLK_CNTL |
39749 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 |
39750 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 |
39751 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L |
39752 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L |
39753 | //DC_GPIO_DEBUG |
39754 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 |
39755 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 |
39756 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 |
39757 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 |
39758 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f |
39759 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L |
39760 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L |
39761 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L |
39762 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x00020000L |
39763 | #define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000L |
39764 | //UNIPHYA_LINK_CNTL |
39765 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39766 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39767 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39768 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39769 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39770 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39771 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39772 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39773 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39774 | #define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39775 | #define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39776 | #define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39777 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39778 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39779 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39780 | #define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39781 | #define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39782 | #define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39783 | //UNIPHYA_CHANNEL_XBAR_CNTL |
39784 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39785 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39786 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39787 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39788 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39789 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39790 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39791 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39792 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39793 | #define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39794 | //UNIPHYB_LINK_CNTL |
39795 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39796 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39797 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39798 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39799 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39800 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39801 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39802 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39803 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39804 | #define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39805 | #define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39806 | #define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39807 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39808 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39809 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39810 | #define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39811 | #define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39812 | #define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39813 | //UNIPHYB_CHANNEL_XBAR_CNTL |
39814 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39815 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39816 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39817 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39818 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39819 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39820 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39821 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39822 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39823 | #define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39824 | //UNIPHYC_LINK_CNTL |
39825 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39826 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39827 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39828 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39829 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39830 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39831 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39832 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39833 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39834 | #define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39835 | #define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39836 | #define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39837 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39838 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39839 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39840 | #define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39841 | #define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39842 | #define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39843 | //UNIPHYC_CHANNEL_XBAR_CNTL |
39844 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39845 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39846 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39847 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39848 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39849 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39850 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39851 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39852 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39853 | #define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39854 | //UNIPHYD_LINK_CNTL |
39855 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39856 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39857 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39858 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39859 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39860 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39861 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39862 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39863 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39864 | #define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39865 | #define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39866 | #define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39867 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39868 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39869 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39870 | #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39871 | #define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39872 | #define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39873 | //UNIPHYD_CHANNEL_XBAR_CNTL |
39874 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39875 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39876 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39877 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39878 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39879 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39880 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39881 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39882 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39883 | #define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39884 | //UNIPHYE_LINK_CNTL |
39885 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39886 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39887 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39888 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39889 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39890 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39891 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39892 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39893 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39894 | #define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39895 | #define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39896 | #define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39897 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39898 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39899 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39900 | #define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39901 | #define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39902 | #define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39903 | //UNIPHYE_CHANNEL_XBAR_CNTL |
39904 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39905 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39906 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39907 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39908 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39909 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39910 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39911 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39912 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39913 | #define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39914 | //UNIPHYF_LINK_CNTL |
39915 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39916 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39917 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39918 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39919 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39920 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39921 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39922 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39923 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39924 | #define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39925 | #define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39926 | #define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39927 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39928 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39929 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39930 | #define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39931 | #define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39932 | #define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39933 | //UNIPHYF_CHANNEL_XBAR_CNTL |
39934 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39935 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39936 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39937 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39938 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39939 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39940 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39941 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39942 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39943 | #define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39944 | //UNIPHYG_LINK_CNTL |
39945 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
39946 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
39947 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
39948 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
39949 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
39950 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
39951 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
39952 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
39953 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 |
39954 | #define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L |
39955 | #define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L |
39956 | #define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L |
39957 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L |
39958 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L |
39959 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L |
39960 | #define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L |
39961 | #define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L |
39962 | #define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L |
39963 | //UNIPHYG_CHANNEL_XBAR_CNTL |
39964 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
39965 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
39966 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
39967 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
39968 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c |
39969 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L |
39970 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L |
39971 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L |
39972 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L |
39973 | #define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L |
39974 | //DCIO_WRCMD_DELAY |
39975 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 |
39976 | #define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 |
39977 | #define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 |
39978 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc |
39979 | #define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 |
39980 | #define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0x0000000FL |
39981 | #define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L |
39982 | #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L |
39983 | #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L |
39984 | #define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L |
39985 | //DC_PINSTRAPS |
39986 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe |
39987 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L |
39988 | //DC_DVODATA_CONFIG |
39989 | #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 |
39990 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 |
39991 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 |
39992 | #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L |
39993 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L |
39994 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L |
39995 | //LVTMA_PWRSEQ_CNTL |
39996 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 |
39997 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 |
39998 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 |
39999 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 |
40000 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 |
40001 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa |
40002 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 |
40003 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 |
40004 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 |
40005 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 |
40006 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 |
40007 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a |
40008 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L |
40009 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L |
40010 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L |
40011 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L |
40012 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L |
40013 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L |
40014 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L |
40015 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L |
40016 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L |
40017 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L |
40018 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L |
40019 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L |
40020 | //LVTMA_PWRSEQ_STATE |
40021 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 |
40022 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 |
40023 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 |
40024 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 |
40025 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 |
40026 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 |
40027 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L |
40028 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L |
40029 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L |
40030 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L |
40031 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L |
40032 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L |
40033 | //LVTMA_PWRSEQ_REF_DIV |
40034 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 |
40035 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 |
40036 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL |
40037 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L |
40038 | //LVTMA_PWRSEQ_DELAY1 |
40039 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 |
40040 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 |
40041 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 |
40042 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 |
40043 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL |
40044 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L |
40045 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L |
40046 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L |
40047 | //LVTMA_PWRSEQ_DELAY2 |
40048 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 |
40049 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 |
40050 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 |
40051 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 |
40052 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL |
40053 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L |
40054 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L |
40055 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L |
40056 | //BL_PWM_CNTL |
40057 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 |
40058 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e |
40059 | #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f |
40060 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL |
40061 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L |
40062 | #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L |
40063 | //BL_PWM_CNTL2 |
40064 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 |
40065 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e |
40066 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f |
40067 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL |
40068 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L |
40069 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L |
40070 | //BL_PWM_PERIOD_CNTL |
40071 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 |
40072 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 |
40073 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL |
40074 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L |
40075 | //BL_PWM_GRP1_REG_LOCK |
40076 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 |
40077 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 |
40078 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 |
40079 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 |
40080 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
40081 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
40082 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L |
40083 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L |
40084 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L |
40085 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L |
40086 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L |
40087 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L |
40088 | //DCIO_GSL_GENLK_PAD_CNTL |
40089 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 |
40090 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 |
40091 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 |
40092 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 |
40093 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L |
40094 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L |
40095 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L |
40096 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L |
40097 | //DCIO_GSL_SWAPLOCK_PAD_CNTL |
40098 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 |
40099 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 |
40100 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 |
40101 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 |
40102 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L |
40103 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L |
40104 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L |
40105 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L |
40106 | //DCIO_CLOCK_CNTL |
40107 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 |
40108 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 |
40109 | #define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL |
40110 | #define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L |
40111 | //DIO_OTG_EXT_VSYNC_CNTL |
40112 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX__SHIFT 0x0 |
40113 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX__SHIFT 0x4 |
40114 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX__SHIFT 0x8 |
40115 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX__SHIFT 0xc |
40116 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX__SHIFT 0x10 |
40117 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX__SHIFT 0x14 |
40118 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 |
40119 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c |
40120 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG0_EXT_VSYNC_MUX_MASK 0x00000007L |
40121 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG1_EXT_VSYNC_MUX_MASK 0x00000070L |
40122 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG2_EXT_VSYNC_MUX_MASK 0x00000700L |
40123 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG3_EXT_VSYNC_MUX_MASK 0x00007000L |
40124 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG4_EXT_VSYNC_MUX_MASK 0x00070000L |
40125 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_OTG5_EXT_VSYNC_MUX_MASK 0x00700000L |
40126 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x07000000L |
40127 | #define DIO_OTG_EXT_VSYNC_CNTL__DIO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000L |
40128 | //DCIO_SOFT_RESET |
40129 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 |
40130 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 |
40131 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 |
40132 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 |
40133 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 |
40134 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 |
40135 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 |
40136 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 |
40137 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 |
40138 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 |
40139 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa |
40140 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb |
40141 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc |
40142 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd |
40143 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 |
40144 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 |
40145 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 |
40146 | #define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a |
40147 | #define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L |
40148 | #define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L |
40149 | #define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L |
40150 | #define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L |
40151 | #define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L |
40152 | #define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L |
40153 | #define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L |
40154 | #define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L |
40155 | #define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L |
40156 | #define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L |
40157 | #define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L |
40158 | #define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L |
40159 | #define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L |
40160 | #define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L |
40161 | #define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L |
40162 | #define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L |
40163 | #define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L |
40164 | #define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L |
40165 | //DCIO_DPHY_SEL |
40166 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 |
40167 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 |
40168 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 |
40169 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 |
40170 | #define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x00000003L |
40171 | #define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0x0000000CL |
40172 | #define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x00000030L |
40173 | #define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0x000000C0L |
40174 | //UNIPHY_IMPCAL_LINKA |
40175 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 |
40176 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 |
40177 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 |
40178 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa |
40179 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 |
40180 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 |
40181 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 |
40182 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c |
40183 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e |
40184 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L |
40185 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L |
40186 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L |
40187 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L |
40188 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000F0000L |
40189 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00F00000L |
40190 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0F000000L |
40191 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L |
40192 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L |
40193 | //UNIPHY_IMPCAL_LINKB |
40194 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 |
40195 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 |
40196 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 |
40197 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa |
40198 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 |
40199 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 |
40200 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 |
40201 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c |
40202 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e |
40203 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L |
40204 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L |
40205 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L |
40206 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L |
40207 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000F0000L |
40208 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00F00000L |
40209 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0F000000L |
40210 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L |
40211 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L |
40212 | //UNIPHY_IMPCAL_PERIOD |
40213 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 |
40214 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xFFFFFFFFL |
40215 | //AUXP_IMPCAL |
40216 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 |
40217 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 |
40218 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 |
40219 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa |
40220 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 |
40221 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 |
40222 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 |
40223 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
40224 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L |
40225 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L |
40226 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L |
40227 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L |
40228 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000F0000L |
40229 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00F00000L |
40230 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0F000000L |
40231 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L |
40232 | //AUXN_IMPCAL |
40233 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 |
40234 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 |
40235 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 |
40236 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa |
40237 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 |
40238 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 |
40239 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 |
40240 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
40241 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L |
40242 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L |
40243 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L |
40244 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L |
40245 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000F0000L |
40246 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00F00000L |
40247 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0F000000L |
40248 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L |
40249 | //DCIO_IMPCAL_CNTL |
40250 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
40251 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 |
40252 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 |
40253 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc |
40254 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf |
40255 | #define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0x0000000FL |
40256 | #define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x00000020L |
40257 | #define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x00000300L |
40258 | #define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x00007000L |
40259 | #define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x00078000L |
40260 | //UNIPHY_IMPCAL_PSW_AB |
40261 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 |
40262 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 |
40263 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007FFFL |
40264 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7FFF0000L |
40265 | //UNIPHY_IMPCAL_LINKC |
40266 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 |
40267 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 |
40268 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 |
40269 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa |
40270 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 |
40271 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 |
40272 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 |
40273 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c |
40274 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e |
40275 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L |
40276 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L |
40277 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L |
40278 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L |
40279 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000F0000L |
40280 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00F00000L |
40281 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0F000000L |
40282 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L |
40283 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L |
40284 | //UNIPHY_IMPCAL_LINKD |
40285 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 |
40286 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 |
40287 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 |
40288 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa |
40289 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 |
40290 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 |
40291 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 |
40292 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c |
40293 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e |
40294 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L |
40295 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L |
40296 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L |
40297 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L |
40298 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000F0000L |
40299 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00F00000L |
40300 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0F000000L |
40301 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L |
40302 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L |
40303 | //DCIO_IMPCAL_CNTL_CD |
40304 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
40305 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 |
40306 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 |
40307 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc |
40308 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000FL |
40309 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L |
40310 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L |
40311 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L |
40312 | //UNIPHY_IMPCAL_PSW_CD |
40313 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 |
40314 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 |
40315 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007FFFL |
40316 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7FFF0000L |
40317 | //UNIPHY_IMPCAL_LINKE |
40318 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 |
40319 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 |
40320 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 |
40321 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa |
40322 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 |
40323 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 |
40324 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 |
40325 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c |
40326 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e |
40327 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L |
40328 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L |
40329 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L |
40330 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L |
40331 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000F0000L |
40332 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00F00000L |
40333 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0F000000L |
40334 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L |
40335 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L |
40336 | //UNIPHY_IMPCAL_LINKF |
40337 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 |
40338 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 |
40339 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 |
40340 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa |
40341 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 |
40342 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 |
40343 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 |
40344 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c |
40345 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e |
40346 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L |
40347 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L |
40348 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L |
40349 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L |
40350 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000F0000L |
40351 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00F00000L |
40352 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0F000000L |
40353 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L |
40354 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L |
40355 | //DCIO_IMPCAL_CNTL_EF |
40356 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
40357 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 |
40358 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 |
40359 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc |
40360 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000FL |
40361 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L |
40362 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L |
40363 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L |
40364 | //UNIPHY_IMPCAL_PSW_EF |
40365 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 |
40366 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 |
40367 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007FFFL |
40368 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7FFF0000L |
40369 | //DCIO_DPCS_TX_INTERRUPT |
40370 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE__SHIFT 0x0 |
40371 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK__SHIFT 0x1 |
40372 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR__SHIFT 0x2 |
40373 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE__SHIFT 0x3 |
40374 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK__SHIFT 0x4 |
40375 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR__SHIFT 0x5 |
40376 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE__SHIFT 0x6 |
40377 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK__SHIFT 0x7 |
40378 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR__SHIFT 0x8 |
40379 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE__SHIFT 0x9 |
40380 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK__SHIFT 0xa |
40381 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR__SHIFT 0xb |
40382 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE__SHIFT 0xc |
40383 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK__SHIFT 0xd |
40384 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR__SHIFT 0xe |
40385 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE__SHIFT 0xf |
40386 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK__SHIFT 0x10 |
40387 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR__SHIFT 0x11 |
40388 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE__SHIFT 0x12 |
40389 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK__SHIFT 0x13 |
40390 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR__SHIFT 0x14 |
40391 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_TYPE_MASK 0x00000001L |
40392 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_MASK_MASK 0x00000002L |
40393 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXA_INT_OCCUR_MASK 0x00000004L |
40394 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_TYPE_MASK 0x00000008L |
40395 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_MASK_MASK 0x00000010L |
40396 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXB_INT_OCCUR_MASK 0x00000020L |
40397 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_TYPE_MASK 0x00000040L |
40398 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_MASK_MASK 0x00000080L |
40399 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXC_INT_OCCUR_MASK 0x00000100L |
40400 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_TYPE_MASK 0x00000200L |
40401 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_MASK_MASK 0x00000400L |
40402 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXD_INT_OCCUR_MASK 0x00000800L |
40403 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_TYPE_MASK 0x00001000L |
40404 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_MASK_MASK 0x00002000L |
40405 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXE_INT_OCCUR_MASK 0x00004000L |
40406 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_TYPE_MASK 0x00008000L |
40407 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_MASK_MASK 0x00010000L |
40408 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXF_INT_OCCUR_MASK 0x00020000L |
40409 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_TYPE_MASK 0x00040000L |
40410 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_MASK_MASK 0x00080000L |
40411 | #define DCIO_DPCS_TX_INTERRUPT__DCIO_DPCS_TXG_INT_OCCUR_MASK 0x00100000L |
40412 | //DCIO_DPCS_RX_INTERRUPT |
40413 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE__SHIFT 0x0 |
40414 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK__SHIFT 0x1 |
40415 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR__SHIFT 0x2 |
40416 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_TYPE_MASK 0x00000001L |
40417 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_MASK_MASK 0x00000002L |
40418 | #define DCIO_DPCS_RX_INTERRUPT__DCIO_DPCS_RXA_INT_OCCUR_MASK 0x00000004L |
40419 | //DCIO_SEMAPHORE0 |
40420 | #define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ__SHIFT 0x0 |
40421 | #define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT__SHIFT 0x10 |
40422 | #define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_REQ_MASK 0x0000FFFFL |
40423 | #define DCIO_SEMAPHORE0__DCIO_SEMAPHORE0_GNT_MASK 0xFFFF0000L |
40424 | //DCIO_SEMAPHORE1 |
40425 | #define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ__SHIFT 0x0 |
40426 | #define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT__SHIFT 0x10 |
40427 | #define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_REQ_MASK 0x0000FFFFL |
40428 | #define DCIO_SEMAPHORE1__DCIO_SEMAPHORE1_GNT_MASK 0xFFFF0000L |
40429 | //DCIO_SEMAPHORE2 |
40430 | #define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ__SHIFT 0x0 |
40431 | #define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT__SHIFT 0x10 |
40432 | #define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_REQ_MASK 0x0000FFFFL |
40433 | #define DCIO_SEMAPHORE2__DCIO_SEMAPHORE2_GNT_MASK 0xFFFF0000L |
40434 | //DCIO_SEMAPHORE3 |
40435 | #define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ__SHIFT 0x0 |
40436 | #define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT__SHIFT 0x10 |
40437 | #define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_REQ_MASK 0x0000FFFFL |
40438 | #define DCIO_SEMAPHORE3__DCIO_SEMAPHORE3_GNT_MASK 0xFFFF0000L |
40439 | //DCIO_SEMAPHORE4 |
40440 | #define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ__SHIFT 0x0 |
40441 | #define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT__SHIFT 0x10 |
40442 | #define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_REQ_MASK 0x0000FFFFL |
40443 | #define DCIO_SEMAPHORE4__DCIO_SEMAPHORE4_GNT_MASK 0xFFFF0000L |
40444 | //DCIO_SEMAPHORE5 |
40445 | #define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ__SHIFT 0x0 |
40446 | #define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT__SHIFT 0x10 |
40447 | #define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_REQ_MASK 0x0000FFFFL |
40448 | #define DCIO_SEMAPHORE5__DCIO_SEMAPHORE5_GNT_MASK 0xFFFF0000L |
40449 | //DCIO_SEMAPHORE6 |
40450 | #define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ__SHIFT 0x0 |
40451 | #define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT__SHIFT 0x10 |
40452 | #define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_REQ_MASK 0x0000FFFFL |
40453 | #define DCIO_SEMAPHORE6__DCIO_SEMAPHORE6_GNT_MASK 0xFFFF0000L |
40454 | //DCIO_SEMAPHORE7 |
40455 | #define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ__SHIFT 0x0 |
40456 | #define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT__SHIFT 0x10 |
40457 | #define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_REQ_MASK 0x0000FFFFL |
40458 | #define DCIO_SEMAPHORE7__DCIO_SEMAPHORE7_GNT_MASK 0xFFFF0000L |
40459 | //DCIO_USBC_FLIP_EN_SEL |
40460 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL__SHIFT 0x0 |
40461 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL__SHIFT 0x4 |
40462 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL__SHIFT 0x8 |
40463 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL__SHIFT 0xc |
40464 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL__SHIFT 0x10 |
40465 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL__SHIFT 0x14 |
40466 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN__SHIFT 0x18 |
40467 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN__SHIFT 0x19 |
40468 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN__SHIFT 0x1a |
40469 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN__SHIFT 0x1b |
40470 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN__SHIFT 0x1c |
40471 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN__SHIFT 0x1d |
40472 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYA_USBC_FLIP_EN_SEL_MASK 0x00000007L |
40473 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYB_USBC_FLIP_EN_SEL_MASK 0x00000070L |
40474 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYC_USBC_FLIP_EN_SEL_MASK 0x00000700L |
40475 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYD_USBC_FLIP_EN_SEL_MASK 0x00007000L |
40476 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYE_USBC_FLIP_EN_SEL_MASK 0x00070000L |
40477 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_UNIPHYF_USBC_FLIP_EN_SEL_MASK 0x00700000L |
40478 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKA_USBC_DP_FLIP_EN_MASK 0x01000000L |
40479 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKB_USBC_DP_FLIP_EN_MASK 0x02000000L |
40480 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKC_USBC_DP_FLIP_EN_MASK 0x04000000L |
40481 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKD_USBC_DP_FLIP_EN_MASK 0x08000000L |
40482 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKE_USBC_DP_FLIP_EN_MASK 0x10000000L |
40483 | #define DCIO_USBC_FLIP_EN_SEL__DCIO_FCH_DC_LINKF_USBC_DP_FLIP_EN_MASK 0x20000000L |
40484 | |
40485 | |
40486 | // addressBlock: dce_dc_dcio_dcio_chip_dispdec |
40487 | //DC_GPIO_GENERIC_MASK |
40488 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 |
40489 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 |
40490 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 |
40491 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 |
40492 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 |
40493 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 |
40494 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 |
40495 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 |
40496 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa |
40497 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc |
40498 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd |
40499 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe |
40500 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 |
40501 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 |
40502 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 |
40503 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 |
40504 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 |
40505 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 |
40506 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 |
40507 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 |
40508 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a |
40509 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L |
40510 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L |
40511 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL |
40512 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L |
40513 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L |
40514 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L |
40515 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L |
40516 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L |
40517 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L |
40518 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L |
40519 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L |
40520 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L |
40521 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L |
40522 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L |
40523 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L |
40524 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L |
40525 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L |
40526 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L |
40527 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L |
40528 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L |
40529 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L |
40530 | //DC_GPIO_GENERIC_A |
40531 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 |
40532 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 |
40533 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 |
40534 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 |
40535 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 |
40536 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 |
40537 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 |
40538 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L |
40539 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L |
40540 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L |
40541 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L |
40542 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L |
40543 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L |
40544 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L |
40545 | //DC_GPIO_GENERIC_EN |
40546 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 |
40547 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 |
40548 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 |
40549 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 |
40550 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 |
40551 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 |
40552 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 |
40553 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L |
40554 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L |
40555 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L |
40556 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L |
40557 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L |
40558 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L |
40559 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L |
40560 | //DC_GPIO_GENERIC_Y |
40561 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 |
40562 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 |
40563 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 |
40564 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 |
40565 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 |
40566 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 |
40567 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 |
40568 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L |
40569 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L |
40570 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L |
40571 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L |
40572 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L |
40573 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L |
40574 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L |
40575 | //DC_GPIO_DVODATA_MASK |
40576 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 |
40577 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 |
40578 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d |
40579 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00FFFFFFL |
40580 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1F000000L |
40581 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000L |
40582 | //DC_GPIO_DVODATA_A |
40583 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 |
40584 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 |
40585 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d |
40586 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00FFFFFFL |
40587 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1F000000L |
40588 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000L |
40589 | //DC_GPIO_DVODATA_EN |
40590 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 |
40591 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 |
40592 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d |
40593 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00FFFFFFL |
40594 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1F000000L |
40595 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000L |
40596 | //DC_GPIO_DVODATA_Y |
40597 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 |
40598 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 |
40599 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d |
40600 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00FFFFFFL |
40601 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1F000000L |
40602 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000L |
40603 | //DC_GPIO_DDC1_MASK |
40604 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 |
40605 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 |
40606 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 |
40607 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 |
40608 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc |
40609 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe |
40610 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 |
40611 | #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 |
40612 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 |
40613 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 |
40614 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c |
40615 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L |
40616 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L |
40617 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L |
40618 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L |
40619 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L |
40620 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L |
40621 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L |
40622 | #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L |
40623 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L |
40624 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L |
40625 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L |
40626 | //DC_GPIO_DDC1_A |
40627 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 |
40628 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 |
40629 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L |
40630 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L |
40631 | //DC_GPIO_DDC1_EN |
40632 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 |
40633 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 |
40634 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L |
40635 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L |
40636 | //DC_GPIO_DDC1_Y |
40637 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 |
40638 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 |
40639 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L |
40640 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L |
40641 | //DC_GPIO_DDC2_MASK |
40642 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 |
40643 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 |
40644 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 |
40645 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 |
40646 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc |
40647 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe |
40648 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 |
40649 | #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 |
40650 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 |
40651 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 |
40652 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c |
40653 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L |
40654 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L |
40655 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L |
40656 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L |
40657 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L |
40658 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L |
40659 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L |
40660 | #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L |
40661 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L |
40662 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L |
40663 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L |
40664 | //DC_GPIO_DDC2_A |
40665 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 |
40666 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 |
40667 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L |
40668 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L |
40669 | //DC_GPIO_DDC2_EN |
40670 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 |
40671 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 |
40672 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L |
40673 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L |
40674 | //DC_GPIO_DDC2_Y |
40675 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 |
40676 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 |
40677 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L |
40678 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L |
40679 | //DC_GPIO_DDC3_MASK |
40680 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 |
40681 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 |
40682 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 |
40683 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 |
40684 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc |
40685 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe |
40686 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 |
40687 | #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 |
40688 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 |
40689 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 |
40690 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c |
40691 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L |
40692 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L |
40693 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L |
40694 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L |
40695 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L |
40696 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L |
40697 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L |
40698 | #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L |
40699 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L |
40700 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L |
40701 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L |
40702 | //DC_GPIO_DDC3_A |
40703 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 |
40704 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 |
40705 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L |
40706 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L |
40707 | //DC_GPIO_DDC3_EN |
40708 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 |
40709 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 |
40710 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L |
40711 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L |
40712 | //DC_GPIO_DDC3_Y |
40713 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 |
40714 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 |
40715 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L |
40716 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L |
40717 | //DC_GPIO_DDC4_MASK |
40718 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 |
40719 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 |
40720 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 |
40721 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 |
40722 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc |
40723 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe |
40724 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 |
40725 | #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 |
40726 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 |
40727 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 |
40728 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c |
40729 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L |
40730 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L |
40731 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L |
40732 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L |
40733 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L |
40734 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L |
40735 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L |
40736 | #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L |
40737 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L |
40738 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L |
40739 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L |
40740 | //DC_GPIO_DDC4_A |
40741 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 |
40742 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 |
40743 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L |
40744 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L |
40745 | //DC_GPIO_DDC4_EN |
40746 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 |
40747 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 |
40748 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L |
40749 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L |
40750 | //DC_GPIO_DDC4_Y |
40751 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 |
40752 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 |
40753 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L |
40754 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L |
40755 | //DC_GPIO_DDC5_MASK |
40756 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 |
40757 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 |
40758 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 |
40759 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 |
40760 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc |
40761 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe |
40762 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 |
40763 | #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 |
40764 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 |
40765 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 |
40766 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c |
40767 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L |
40768 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L |
40769 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L |
40770 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L |
40771 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L |
40772 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L |
40773 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L |
40774 | #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L |
40775 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L |
40776 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L |
40777 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L |
40778 | //DC_GPIO_DDC5_A |
40779 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 |
40780 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 |
40781 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L |
40782 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L |
40783 | //DC_GPIO_DDC5_EN |
40784 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 |
40785 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 |
40786 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L |
40787 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L |
40788 | //DC_GPIO_DDC5_Y |
40789 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 |
40790 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 |
40791 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L |
40792 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L |
40793 | //DC_GPIO_DDC6_MASK |
40794 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 |
40795 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 |
40796 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 |
40797 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 |
40798 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc |
40799 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe |
40800 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 |
40801 | #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 |
40802 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 |
40803 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 |
40804 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c |
40805 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L |
40806 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L |
40807 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L |
40808 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L |
40809 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L |
40810 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L |
40811 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L |
40812 | #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L |
40813 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L |
40814 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0F000000L |
40815 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xF0000000L |
40816 | //DC_GPIO_DDC6_A |
40817 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 |
40818 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 |
40819 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L |
40820 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L |
40821 | //DC_GPIO_DDC6_EN |
40822 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 |
40823 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 |
40824 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L |
40825 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L |
40826 | //DC_GPIO_DDC6_Y |
40827 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 |
40828 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 |
40829 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L |
40830 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L |
40831 | //DC_GPIO_DDCVGA_MASK |
40832 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 |
40833 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 |
40834 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 |
40835 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc |
40836 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe |
40837 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 |
40838 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 |
40839 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 |
40840 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 |
40841 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c |
40842 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L |
40843 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L |
40844 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L |
40845 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L |
40846 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L |
40847 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L |
40848 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L |
40849 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L |
40850 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L |
40851 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L |
40852 | //DC_GPIO_DDCVGA_A |
40853 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 |
40854 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 |
40855 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L |
40856 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L |
40857 | //DC_GPIO_DDCVGA_EN |
40858 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 |
40859 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 |
40860 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L |
40861 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L |
40862 | //DC_GPIO_DDCVGA_Y |
40863 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 |
40864 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 |
40865 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L |
40866 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L |
40867 | //DC_GPIO_SYNCA_MASK |
40868 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 |
40869 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 |
40870 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 |
40871 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 |
40872 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc |
40873 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe |
40874 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK__SHIFT 0x18 |
40875 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK__SHIFT 0x1c |
40876 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L |
40877 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L |
40878 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x000000C0L |
40879 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L |
40880 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L |
40881 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x0000C000L |
40882 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_OPTC_HSYNC_MASK_MASK 0x07000000L |
40883 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_OPTC_VSYNC_MASK_MASK 0x70000000L |
40884 | //DC_GPIO_SYNCA_A |
40885 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 |
40886 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 |
40887 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L |
40888 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L |
40889 | //DC_GPIO_SYNCA_EN |
40890 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 |
40891 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 |
40892 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L |
40893 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L |
40894 | //DC_GPIO_SYNCA_Y |
40895 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 |
40896 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 |
40897 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L |
40898 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L |
40899 | //DC_GPIO_GENLK_MASK |
40900 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 |
40901 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 |
40902 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 |
40903 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 |
40904 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 |
40905 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 |
40906 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb |
40907 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc |
40908 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 |
40909 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 |
40910 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 |
40911 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 |
40912 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 |
40913 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 |
40914 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b |
40915 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c |
40916 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L |
40917 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L |
40918 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L |
40919 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L |
40920 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L |
40921 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L |
40922 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L |
40923 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L |
40924 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L |
40925 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L |
40926 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L |
40927 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L |
40928 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L |
40929 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L |
40930 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L |
40931 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L |
40932 | //DC_GPIO_GENLK_A |
40933 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 |
40934 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 |
40935 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 |
40936 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 |
40937 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L |
40938 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L |
40939 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L |
40940 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L |
40941 | //DC_GPIO_GENLK_EN |
40942 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 |
40943 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 |
40944 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 |
40945 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 |
40946 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L |
40947 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L |
40948 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L |
40949 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L |
40950 | //DC_GPIO_GENLK_Y |
40951 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 |
40952 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 |
40953 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 |
40954 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 |
40955 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L |
40956 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L |
40957 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L |
40958 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L |
40959 | //DC_GPIO_HPD_MASK |
40960 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 |
40961 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 |
40962 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 |
40963 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 |
40964 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 |
40965 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 |
40966 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 |
40967 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 |
40968 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa |
40969 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 |
40970 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 |
40971 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 |
40972 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 |
40973 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 |
40974 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 |
40975 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 |
40976 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 |
40977 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a |
40978 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c |
40979 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d |
40980 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e |
40981 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L |
40982 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L |
40983 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L |
40984 | #define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L |
40985 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L |
40986 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L |
40987 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L |
40988 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L |
40989 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L |
40990 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L |
40991 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L |
40992 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L |
40993 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L |
40994 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L |
40995 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L |
40996 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L |
40997 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L |
40998 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L |
40999 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L |
41000 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L |
41001 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L |
41002 | //DC_GPIO_HPD_A |
41003 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 |
41004 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 |
41005 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 |
41006 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 |
41007 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a |
41008 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c |
41009 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L |
41010 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L |
41011 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L |
41012 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L |
41013 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L |
41014 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L |
41015 | //DC_GPIO_HPD_EN |
41016 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 |
41017 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 |
41018 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 |
41019 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 |
41020 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 |
41021 | #define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 |
41022 | #define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 |
41023 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 |
41024 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 |
41025 | #define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 |
41026 | #define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa |
41027 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 |
41028 | #define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 |
41029 | #define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 |
41030 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 |
41031 | #define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 |
41032 | #define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 |
41033 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 |
41034 | #define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 |
41035 | #define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a |
41036 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c |
41037 | #define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d |
41038 | #define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e |
41039 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L |
41040 | #define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L |
41041 | #define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L |
41042 | #define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L |
41043 | #define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L |
41044 | #define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L |
41045 | #define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L |
41046 | #define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L |
41047 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L |
41048 | #define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L |
41049 | #define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L |
41050 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L |
41051 | #define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L |
41052 | #define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L |
41053 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L |
41054 | #define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L |
41055 | #define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L |
41056 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L |
41057 | #define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L |
41058 | #define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L |
41059 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L |
41060 | #define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L |
41061 | #define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L |
41062 | //DC_GPIO_HPD_Y |
41063 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 |
41064 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 |
41065 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 |
41066 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 |
41067 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a |
41068 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c |
41069 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L |
41070 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L |
41071 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L |
41072 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L |
41073 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L |
41074 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L |
41075 | //DC_GPIO_PWRSEQ_MASK |
41076 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 |
41077 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 |
41078 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 |
41079 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 |
41080 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc |
41081 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe |
41082 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 |
41083 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 |
41084 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 |
41085 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 |
41086 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 |
41087 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a |
41088 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c |
41089 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d |
41090 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e |
41091 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L |
41092 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L |
41093 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L |
41094 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L |
41095 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L |
41096 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L |
41097 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L |
41098 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L |
41099 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L |
41100 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L |
41101 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L |
41102 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L |
41103 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L |
41104 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L |
41105 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L |
41106 | //DC_GPIO_PWRSEQ_A |
41107 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 |
41108 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 |
41109 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 |
41110 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 |
41111 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f |
41112 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L |
41113 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L |
41114 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L |
41115 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L |
41116 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L |
41117 | //DC_GPIO_PWRSEQ_EN |
41118 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 |
41119 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 |
41120 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 |
41121 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 |
41122 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 |
41123 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f |
41124 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L |
41125 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L |
41126 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L |
41127 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L |
41128 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L |
41129 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L |
41130 | //DC_GPIO_PWRSEQ_Y |
41131 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 |
41132 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 |
41133 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 |
41134 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 |
41135 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f |
41136 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L |
41137 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L |
41138 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L |
41139 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L |
41140 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L |
41141 | //DC_GPIO_PAD_STRENGTH_1 |
41142 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 |
41143 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 |
41144 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 |
41145 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc |
41146 | #define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 |
41147 | #define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 |
41148 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 |
41149 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c |
41150 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL |
41151 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L |
41152 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L |
41153 | #define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L |
41154 | #define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L |
41155 | #define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L |
41156 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L |
41157 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L |
41158 | //DC_GPIO_PAD_STRENGTH_2 |
41159 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 |
41160 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 |
41161 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 |
41162 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc |
41163 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 |
41164 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 |
41165 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e |
41166 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL |
41167 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L |
41168 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L |
41169 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L |
41170 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L |
41171 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L |
41172 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L |
41173 | //PHY_AUX_CNTL |
41174 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 |
41175 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 |
41176 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 |
41177 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 |
41178 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 |
41179 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 |
41180 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 |
41181 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 |
41182 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc |
41183 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd |
41184 | #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe |
41185 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 |
41186 | #define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x14 |
41187 | #define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17 |
41188 | #define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18 |
41189 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L |
41190 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L |
41191 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L |
41192 | #define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L |
41193 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L |
41194 | #define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L |
41195 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L |
41196 | #define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L |
41197 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L |
41198 | #define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00002000L |
41199 | #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L |
41200 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00030000L |
41201 | #define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x00700000L |
41202 | #define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L |
41203 | #define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L |
41204 | //DC_GPIO_I2CPAD_MASK |
41205 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 |
41206 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 |
41207 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 |
41208 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 |
41209 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 |
41210 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 |
41211 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L |
41212 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L |
41213 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L |
41214 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L |
41215 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L |
41216 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L |
41217 | //DC_GPIO_I2CPAD_A |
41218 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 |
41219 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 |
41220 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L |
41221 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L |
41222 | //DC_GPIO_I2CPAD_EN |
41223 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 |
41224 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 |
41225 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L |
41226 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L |
41227 | //DC_GPIO_I2CPAD_Y |
41228 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 |
41229 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 |
41230 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L |
41231 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L |
41232 | //DC_GPIO_I2CPAD_STRENGTH |
41233 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 |
41234 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 |
41235 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000FL |
41236 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000F0L |
41237 | //DVO_STRENGTH_CONTROL |
41238 | #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 |
41239 | #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 |
41240 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 |
41241 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc |
41242 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 |
41243 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 |
41244 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 |
41245 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c |
41246 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d |
41247 | #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000FL |
41248 | #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000F0L |
41249 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000F00L |
41250 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000F000L |
41251 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x00070000L |
41252 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x00700000L |
41253 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x07000000L |
41254 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L |
41255 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L |
41256 | //DVO_VREF_CONTROL |
41257 | #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 |
41258 | #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 |
41259 | #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 |
41260 | #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L |
41261 | #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L |
41262 | #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000F0L |
41263 | //DVO_SKEW_ADJUST |
41264 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 |
41265 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xFFFFFFFFL |
41266 | //DC_GPIO_I2S_SPDIF_MASK |
41267 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 |
41268 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 |
41269 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 |
41270 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 |
41271 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 |
41272 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 |
41273 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 |
41274 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa |
41275 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb |
41276 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc |
41277 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0x0000000FL |
41278 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x00000010L |
41279 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x00000020L |
41280 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x00000040L |
41281 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x00000080L |
41282 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x00000100L |
41283 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x00000200L |
41284 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x00000400L |
41285 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x00000800L |
41286 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x00001000L |
41287 | //DC_GPIO_I2S_SPDIF_A |
41288 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 |
41289 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 |
41290 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 |
41291 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 |
41292 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 |
41293 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 |
41294 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 |
41295 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa |
41296 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb |
41297 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc |
41298 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0x0000000FL |
41299 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x00000010L |
41300 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x00000020L |
41301 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x00000040L |
41302 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x00000080L |
41303 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x00000100L |
41304 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x00000200L |
41305 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x00000400L |
41306 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x00000800L |
41307 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x00001000L |
41308 | //DC_GPIO_I2S_SPDIF_EN |
41309 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 |
41310 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 |
41311 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 |
41312 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 |
41313 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 |
41314 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 |
41315 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 |
41316 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa |
41317 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb |
41318 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc |
41319 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT__SHIFT 0xd |
41320 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU__SHIFT 0xe |
41321 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL__SHIFT 0xf |
41322 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN__SHIFT 0x10 |
41323 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN__SHIFT 0x11 |
41324 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE__SHIFT 0x12 |
41325 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0x0000000FL |
41326 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x00000010L |
41327 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x00000020L |
41328 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x00000040L |
41329 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x00000080L |
41330 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x00000100L |
41331 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x00000200L |
41332 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x00000400L |
41333 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x00000800L |
41334 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x00001000L |
41335 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_APORT_MASK 0x00002000L |
41336 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_PU_MASK 0x00004000L |
41337 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_RXSEL_MASK 0x00008000L |
41338 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SCHMEN_MASK 0x00010000L |
41339 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_SMODE_EN_MASK 0x00020000L |
41340 | #define DC_GPIO_I2S_SPDIF_EN__SPDIF1_IMODE_MASK 0x00040000L |
41341 | //DC_GPIO_I2S_SPDIF_Y |
41342 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 |
41343 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 |
41344 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 |
41345 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 |
41346 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 |
41347 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 |
41348 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 |
41349 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa |
41350 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb |
41351 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc |
41352 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0x0000000FL |
41353 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x00000010L |
41354 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x00000020L |
41355 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x00000040L |
41356 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x00000080L |
41357 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x00000100L |
41358 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x00000200L |
41359 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x00000400L |
41360 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x00000800L |
41361 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x00001000L |
41362 | //DC_GPIO_I2S_SPDIF_STRENGTH |
41363 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 |
41364 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN__SHIFT 0x8 |
41365 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP__SHIFT 0xb |
41366 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 |
41367 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN__SHIFT 0x18 |
41368 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP__SHIFT 0x1b |
41369 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x00000007L |
41370 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SN_MASK 0x00000700L |
41371 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_SP_MASK 0x00003800L |
41372 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x00070000L |
41373 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SN_MASK 0x07000000L |
41374 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_SP_MASK 0x38000000L |
41375 | //DC_GPIO_TX12_EN |
41376 | #define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 |
41377 | #define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 |
41378 | #define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 |
41379 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 |
41380 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 |
41381 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 |
41382 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 |
41383 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 |
41384 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 |
41385 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 |
41386 | #define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L |
41387 | #define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L |
41388 | #define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L |
41389 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L |
41390 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L |
41391 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L |
41392 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L |
41393 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L |
41394 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L |
41395 | #define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L |
41396 | //DC_GPIO_AUX_CTRL_0 |
41397 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 |
41398 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 |
41399 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 |
41400 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 |
41401 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 |
41402 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa |
41403 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc |
41404 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL__SHIFT 0xe |
41405 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 |
41406 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 |
41407 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 |
41408 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 |
41409 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 |
41410 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 |
41411 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 |
41412 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN__SHIFT 0x17 |
41413 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 |
41414 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 |
41415 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a |
41416 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b |
41417 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c |
41418 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d |
41419 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e |
41420 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL__SHIFT 0x1f |
41421 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L |
41422 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL |
41423 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L |
41424 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L |
41425 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L |
41426 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L |
41427 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L |
41428 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_FALLSLEWSEL_MASK 0x0000C000L |
41429 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L |
41430 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L |
41431 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L |
41432 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L |
41433 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L |
41434 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L |
41435 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L |
41436 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCEN_MASK 0x00800000L |
41437 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L |
41438 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L |
41439 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L |
41440 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L |
41441 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L |
41442 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L |
41443 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L |
41444 | #define DC_GPIO_AUX_CTRL_0__DC_GPIO_GENI2C_SPIKERCSEL_MASK 0x80000000L |
41445 | //DC_GPIO_AUX_CTRL_1 |
41446 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 |
41447 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 |
41448 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 |
41449 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 |
41450 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 |
41451 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 |
41452 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 |
41453 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 |
41454 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 |
41455 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 |
41456 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa |
41457 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb |
41458 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc |
41459 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL__SHIFT 0xd |
41460 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe |
41461 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE__SHIFT 0x10 |
41462 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 |
41463 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN__SHIFT 0x13 |
41464 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 |
41465 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL__SHIFT 0x16 |
41466 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN__SHIFT 0x18 |
41467 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 |
41468 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a |
41469 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b |
41470 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c |
41471 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d |
41472 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e |
41473 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L |
41474 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L |
41475 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L |
41476 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L |
41477 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L |
41478 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L |
41479 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L |
41480 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L |
41481 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L |
41482 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L |
41483 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L |
41484 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L |
41485 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L |
41486 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_COMPSEL_MASK 0x00002000L |
41487 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L |
41488 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SPARE_MASK 0x00030000L |
41489 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L |
41490 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_SLEWN_MASK 0x00080000L |
41491 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L |
41492 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_RXSEL_MASK 0x00C00000L |
41493 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_GENI2C_PDEN_MASK 0x01000000L |
41494 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L |
41495 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L |
41496 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L |
41497 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L |
41498 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L |
41499 | #define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L |
41500 | //DC_GPIO_AUX_CTRL_2 |
41501 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 |
41502 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 |
41503 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 |
41504 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 |
41505 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 |
41506 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa |
41507 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc |
41508 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd |
41509 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe |
41510 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 |
41511 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 |
41512 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 |
41513 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 |
41514 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 |
41515 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 |
41516 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 |
41517 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a |
41518 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b |
41519 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c |
41520 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d |
41521 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e |
41522 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L |
41523 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL |
41524 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L |
41525 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L |
41526 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L |
41527 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L |
41528 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L |
41529 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L |
41530 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L |
41531 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L |
41532 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L |
41533 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L |
41534 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L |
41535 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L |
41536 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L |
41537 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L |
41538 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L |
41539 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L |
41540 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L |
41541 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L |
41542 | #define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L |
41543 | //DC_GPIO_RXEN |
41544 | #define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 |
41545 | #define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 |
41546 | #define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 |
41547 | #define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 |
41548 | #define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 |
41549 | #define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 |
41550 | #define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 |
41551 | #define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 |
41552 | #define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 |
41553 | #define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa |
41554 | #define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb |
41555 | #define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc |
41556 | #define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd |
41557 | #define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe |
41558 | #define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf |
41559 | #define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 |
41560 | #define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 |
41561 | #define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 |
41562 | #define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 |
41563 | #define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14 |
41564 | #define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15 |
41565 | #define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16 |
41566 | #define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L |
41567 | #define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L |
41568 | #define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L |
41569 | #define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L |
41570 | #define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L |
41571 | #define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L |
41572 | #define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L |
41573 | #define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L |
41574 | #define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L |
41575 | #define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L |
41576 | #define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L |
41577 | #define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L |
41578 | #define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L |
41579 | #define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L |
41580 | #define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L |
41581 | #define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L |
41582 | #define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L |
41583 | #define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L |
41584 | #define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L |
41585 | #define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L |
41586 | #define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L |
41587 | #define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L |
41588 | //DC_GPIO_PULLUPEN |
41589 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 |
41590 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 |
41591 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 |
41592 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 |
41593 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 |
41594 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 |
41595 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 |
41596 | #define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 |
41597 | #define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 |
41598 | #define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe |
41599 | #define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 |
41600 | #define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 |
41601 | #define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 |
41602 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L |
41603 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L |
41604 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L |
41605 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L |
41606 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L |
41607 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L |
41608 | #define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L |
41609 | #define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L |
41610 | #define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L |
41611 | #define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L |
41612 | #define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L |
41613 | #define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L |
41614 | #define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L |
41615 | |
41616 | |
41617 | // addressBlock: dce_dc_dcio_dcio_dac_dispdec |
41618 | //DAC_MACRO_CNTL_RESERVED0 |
41619 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41620 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41621 | //DAC_MACRO_CNTL_RESERVED1 |
41622 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41623 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41624 | //DAC_MACRO_CNTL_RESERVED2 |
41625 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41626 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41627 | //DAC_MACRO_CNTL_RESERVED3 |
41628 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41629 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41630 | |
41631 | |
41632 | // addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec |
41633 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 |
41634 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41635 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41636 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 |
41637 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41638 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41639 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 |
41640 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41641 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41642 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 |
41643 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41644 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41645 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 |
41646 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41647 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41648 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 |
41649 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41650 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41651 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 |
41652 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41653 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41654 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 |
41655 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41656 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41657 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 |
41658 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41659 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41660 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 |
41661 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41662 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41663 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 |
41664 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41665 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41666 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 |
41667 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41668 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41669 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 |
41670 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41671 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41672 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 |
41673 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41674 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41675 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 |
41676 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41677 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41678 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 |
41679 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41680 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41681 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 |
41682 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41683 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41684 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 |
41685 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41686 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41687 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 |
41688 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41689 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41690 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 |
41691 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41692 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41693 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 |
41694 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41695 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41696 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 |
41697 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41698 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41699 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 |
41700 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41701 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41702 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 |
41703 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41704 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41705 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 |
41706 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41707 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41708 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 |
41709 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41710 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41711 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 |
41712 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41713 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41714 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 |
41715 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41716 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41717 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 |
41718 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41719 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41720 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 |
41721 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41722 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41723 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 |
41724 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41725 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41726 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 |
41727 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41728 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41729 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 |
41730 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41731 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41732 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 |
41733 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41734 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41735 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 |
41736 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41737 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41738 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 |
41739 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41740 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41741 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 |
41742 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41743 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41744 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 |
41745 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41746 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41747 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 |
41748 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41749 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41750 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 |
41751 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41752 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41753 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 |
41754 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41755 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41756 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 |
41757 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41758 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41759 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 |
41760 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41761 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41762 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 |
41763 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41764 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41765 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 |
41766 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41767 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41768 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 |
41769 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41770 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41771 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 |
41772 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41773 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41774 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 |
41775 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41776 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41777 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 |
41778 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41779 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41780 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 |
41781 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41782 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41783 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 |
41784 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41785 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41786 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 |
41787 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41788 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41789 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 |
41790 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41791 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41792 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 |
41793 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41794 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41795 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 |
41796 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41797 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41798 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 |
41799 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41800 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41801 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 |
41802 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41803 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41804 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 |
41805 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41806 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41807 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 |
41808 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41809 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41810 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 |
41811 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41812 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41813 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 |
41814 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41815 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41816 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 |
41817 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41818 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41819 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 |
41820 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41821 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41822 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 |
41823 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41824 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41825 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 |
41826 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41827 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41828 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 |
41829 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41830 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41831 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 |
41832 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41833 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41834 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 |
41835 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41836 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41837 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 |
41838 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41839 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41840 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 |
41841 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41842 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41843 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 |
41844 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41845 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41846 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 |
41847 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41848 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41849 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 |
41850 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41851 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41852 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 |
41853 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41854 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41855 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 |
41856 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41857 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41858 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 |
41859 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41860 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41861 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 |
41862 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41863 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41864 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 |
41865 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41866 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41867 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 |
41868 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41869 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41870 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 |
41871 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41872 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41873 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 |
41874 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41875 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41876 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 |
41877 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41878 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41879 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 |
41880 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41881 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41882 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 |
41883 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41884 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41885 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 |
41886 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41887 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41888 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 |
41889 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41890 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41891 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 |
41892 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41893 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41894 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 |
41895 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41896 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41897 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 |
41898 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41899 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41900 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 |
41901 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41902 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41903 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 |
41904 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41905 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41906 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 |
41907 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41908 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41909 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 |
41910 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41911 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41912 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 |
41913 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41914 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41915 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 |
41916 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41917 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41918 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 |
41919 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41920 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41921 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 |
41922 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41923 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41924 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 |
41925 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41926 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41927 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 |
41928 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41929 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41930 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 |
41931 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41932 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41933 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 |
41934 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41935 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41936 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 |
41937 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41938 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41939 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 |
41940 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41941 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41942 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 |
41943 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41944 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41945 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 |
41946 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41947 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41948 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 |
41949 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41950 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41951 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 |
41952 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41953 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41954 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 |
41955 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41956 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41957 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 |
41958 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41959 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41960 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 |
41961 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41962 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41963 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 |
41964 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41965 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41966 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 |
41967 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41968 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41969 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 |
41970 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41971 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41972 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 |
41973 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41974 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41975 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 |
41976 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41977 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41978 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 |
41979 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41980 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41981 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 |
41982 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41983 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41984 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 |
41985 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41986 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41987 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 |
41988 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41989 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41990 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 |
41991 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41992 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41993 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 |
41994 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41995 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41996 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 |
41997 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
41998 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
41999 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 |
42000 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42001 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42002 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 |
42003 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42004 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42005 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 |
42006 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42007 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42008 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 |
42009 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42010 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42011 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 |
42012 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42013 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42014 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 |
42015 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42016 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42017 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 |
42018 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42019 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42020 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 |
42021 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42022 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42023 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 |
42024 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42025 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42026 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 |
42027 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42028 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42029 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 |
42030 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42031 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42032 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 |
42033 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42034 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42035 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 |
42036 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42037 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42038 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 |
42039 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42040 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42041 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 |
42042 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42043 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42044 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 |
42045 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42046 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42047 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 |
42048 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42049 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42050 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 |
42051 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42052 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42053 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 |
42054 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42055 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42056 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 |
42057 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42058 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42059 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 |
42060 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42061 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42062 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 |
42063 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42064 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42065 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 |
42066 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42067 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42068 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 |
42069 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42070 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42071 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 |
42072 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42073 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42074 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 |
42075 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42076 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42077 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 |
42078 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42079 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42080 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 |
42081 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42082 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42083 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 |
42084 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42085 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42086 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 |
42087 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42088 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42089 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 |
42090 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42091 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42092 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 |
42093 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42094 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42095 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 |
42096 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42097 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42098 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 |
42099 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42100 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42101 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 |
42102 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42103 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42104 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 |
42105 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42106 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42107 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 |
42108 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42109 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42110 | //DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 |
42111 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42112 | #define DCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42113 | |
42114 | |
42115 | // addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec |
42116 | //DC_COMBOPHYCMREGS0_COMMON_FUSE1 |
42117 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 |
42118 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 |
42119 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 |
42120 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 |
42121 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa |
42122 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc |
42123 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd |
42124 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 |
42125 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 |
42126 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 |
42127 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 |
42128 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L |
42129 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L |
42130 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L |
42131 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L |
42132 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L |
42133 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L |
42134 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L |
42135 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L |
42136 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L |
42137 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L |
42138 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L |
42139 | //DC_COMBOPHYCMREGS0_COMMON_FUSE2 |
42140 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 |
42141 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 |
42142 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 |
42143 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare__SHIFT 0xe |
42144 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L |
42145 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL |
42146 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L |
42147 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L |
42148 | //DC_COMBOPHYCMREGS0_COMMON_FUSE3 |
42149 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 |
42150 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 |
42151 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa |
42152 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd |
42153 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 |
42154 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 |
42155 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 |
42156 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 |
42157 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 |
42158 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a |
42159 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d |
42160 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L |
42161 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL |
42162 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L |
42163 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L |
42164 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L |
42165 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L |
42166 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L |
42167 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L |
42168 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L |
42169 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L |
42170 | #define DC_COMBOPHYCMREGS0_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L |
42171 | //DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM |
42172 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 |
42173 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 |
42174 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 |
42175 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 |
42176 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL |
42177 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L |
42178 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L |
42179 | #define DC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L |
42180 | //DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT |
42181 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 |
42182 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 |
42183 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb |
42184 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL |
42185 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L |
42186 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L |
42187 | //DC_COMBOPHYCMREGS0_COMMON_TXCNTRL |
42188 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 |
42189 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 |
42190 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 |
42191 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 |
42192 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc |
42193 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL |
42194 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L |
42195 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L |
42196 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L |
42197 | #define DC_COMBOPHYCMREGS0_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L |
42198 | //DC_COMBOPHYCMREGS0_COMMON_TMDP |
42199 | #define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare__SHIFT 0x0 |
42200 | #define DC_COMBOPHYCMREGS0_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL |
42201 | //DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS |
42202 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 |
42203 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 |
42204 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 |
42205 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 |
42206 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 |
42207 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 |
42208 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 |
42209 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 |
42210 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L |
42211 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L |
42212 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L |
42213 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L |
42214 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L |
42215 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L |
42216 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L |
42217 | #define DC_COMBOPHYCMREGS0_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L |
42218 | //DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL |
42219 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 |
42220 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 |
42221 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 |
42222 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 |
42223 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L |
42224 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL |
42225 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L |
42226 | #define DC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L |
42227 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 |
42228 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 |
42229 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL |
42230 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 |
42231 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 |
42232 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL |
42233 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 |
42234 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 |
42235 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL |
42236 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 |
42237 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 |
42238 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL |
42239 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 |
42240 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 |
42241 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL |
42242 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 |
42243 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 |
42244 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL |
42245 | //DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 |
42246 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 |
42247 | #define DC_COMBOPHYCMREGS0_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL |
42248 | |
42249 | |
42250 | // addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec |
42251 | //DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 |
42252 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 |
42253 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 |
42254 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 |
42255 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L |
42256 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L |
42257 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L |
42258 | //DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 |
42259 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 |
42260 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 |
42261 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 |
42262 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L |
42263 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L |
42264 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L |
42265 | //DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 |
42266 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 |
42267 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 |
42268 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 |
42269 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 |
42270 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa |
42271 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc |
42272 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd |
42273 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe |
42274 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf |
42275 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 |
42276 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 |
42277 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 |
42278 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L |
42279 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L |
42280 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L |
42281 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L |
42282 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L |
42283 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L |
42284 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L |
42285 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L |
42286 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L |
42287 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L |
42288 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L |
42289 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L |
42290 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 |
42291 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 |
42292 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL |
42293 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 |
42294 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 |
42295 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL |
42296 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 |
42297 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 |
42298 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL |
42299 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 |
42300 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 |
42301 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL |
42302 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 |
42303 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 |
42304 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL |
42305 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 |
42306 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 |
42307 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL |
42308 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 |
42309 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 |
42310 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL |
42311 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 |
42312 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 |
42313 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL |
42314 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 |
42315 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 |
42316 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL |
42317 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 |
42318 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 |
42319 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL |
42320 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 |
42321 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 |
42322 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL |
42323 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 |
42324 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 |
42325 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL |
42326 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 |
42327 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 |
42328 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL |
42329 | //DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 |
42330 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 |
42331 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 |
42332 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 |
42333 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L |
42334 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L |
42335 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L |
42336 | //DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 |
42337 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 |
42338 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 |
42339 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 |
42340 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L |
42341 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L |
42342 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L |
42343 | //DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 |
42344 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 |
42345 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 |
42346 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 |
42347 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 |
42348 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa |
42349 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc |
42350 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd |
42351 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe |
42352 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf |
42353 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 |
42354 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 |
42355 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 |
42356 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L |
42357 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L |
42358 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L |
42359 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L |
42360 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L |
42361 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L |
42362 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L |
42363 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L |
42364 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L |
42365 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L |
42366 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L |
42367 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L |
42368 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 |
42369 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 |
42370 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL |
42371 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 |
42372 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 |
42373 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL |
42374 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 |
42375 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 |
42376 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL |
42377 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 |
42378 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 |
42379 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL |
42380 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 |
42381 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 |
42382 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL |
42383 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 |
42384 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 |
42385 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL |
42386 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 |
42387 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 |
42388 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL |
42389 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 |
42390 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 |
42391 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL |
42392 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 |
42393 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 |
42394 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL |
42395 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 |
42396 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 |
42397 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL |
42398 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 |
42399 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 |
42400 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL |
42401 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 |
42402 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 |
42403 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL |
42404 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 |
42405 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 |
42406 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL |
42407 | //DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 |
42408 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 |
42409 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 |
42410 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 |
42411 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L |
42412 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L |
42413 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L |
42414 | //DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 |
42415 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 |
42416 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 |
42417 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 |
42418 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L |
42419 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L |
42420 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L |
42421 | //DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 |
42422 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 |
42423 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 |
42424 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 |
42425 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 |
42426 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa |
42427 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc |
42428 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd |
42429 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe |
42430 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf |
42431 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 |
42432 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 |
42433 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 |
42434 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L |
42435 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L |
42436 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L |
42437 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L |
42438 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L |
42439 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L |
42440 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L |
42441 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L |
42442 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L |
42443 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L |
42444 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L |
42445 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L |
42446 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 |
42447 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 |
42448 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL |
42449 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 |
42450 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 |
42451 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL |
42452 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 |
42453 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 |
42454 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL |
42455 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 |
42456 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 |
42457 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL |
42458 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 |
42459 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 |
42460 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL |
42461 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 |
42462 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 |
42463 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL |
42464 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 |
42465 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 |
42466 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL |
42467 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 |
42468 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 |
42469 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL |
42470 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 |
42471 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 |
42472 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL |
42473 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 |
42474 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 |
42475 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL |
42476 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 |
42477 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 |
42478 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL |
42479 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 |
42480 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 |
42481 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL |
42482 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 |
42483 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 |
42484 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL |
42485 | //DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 |
42486 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 |
42487 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 |
42488 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 |
42489 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L |
42490 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L |
42491 | #define DC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L |
42492 | //DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 |
42493 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 |
42494 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 |
42495 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 |
42496 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L |
42497 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L |
42498 | #define DC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L |
42499 | //DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 |
42500 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 |
42501 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 |
42502 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 |
42503 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 |
42504 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa |
42505 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc |
42506 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd |
42507 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe |
42508 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf |
42509 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 |
42510 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 |
42511 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 |
42512 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L |
42513 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L |
42514 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L |
42515 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L |
42516 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L |
42517 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L |
42518 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L |
42519 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L |
42520 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L |
42521 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L |
42522 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L |
42523 | #define DC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L |
42524 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 |
42525 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 |
42526 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL |
42527 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 |
42528 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 |
42529 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL |
42530 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 |
42531 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 |
42532 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL |
42533 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 |
42534 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 |
42535 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL |
42536 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 |
42537 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 |
42538 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL |
42539 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 |
42540 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 |
42541 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL |
42542 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 |
42543 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 |
42544 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL |
42545 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 |
42546 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 |
42547 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL |
42548 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 |
42549 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 |
42550 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL |
42551 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 |
42552 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 |
42553 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL |
42554 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 |
42555 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 |
42556 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL |
42557 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 |
42558 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 |
42559 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL |
42560 | //DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 |
42561 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 |
42562 | #define DC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL |
42563 | |
42564 | |
42565 | // addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec |
42566 | //DC_COMBOPHYPLLREGS0_FREQ_CTRL0 |
42567 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 |
42568 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int__SHIFT 0x10 |
42569 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL |
42570 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L |
42571 | //DC_COMBOPHYPLLREGS0_FREQ_CTRL1 |
42572 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 |
42573 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int__SHIFT 0x10 |
42574 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL |
42575 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L |
42576 | //DC_COMBOPHYPLLREGS0_FREQ_CTRL2 |
42577 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom__SHIFT 0x0 |
42578 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 |
42579 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL |
42580 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L |
42581 | //DC_COMBOPHYPLLREGS0_FREQ_CTRL3 |
42582 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div__SHIFT 0x0 |
42583 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 |
42584 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en__SHIFT 0x6 |
42585 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en__SHIFT 0x8 |
42586 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel__SHIFT 0xa |
42587 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en__SHIFT 0xc |
42588 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 |
42589 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 |
42590 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__refclk_div_MASK 0x00000003L |
42591 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L |
42592 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fracn_en_MASK 0x00000040L |
42593 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__ssc_en_MASK 0x00000100L |
42594 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__fcw_sel_MASK 0x00000400L |
42595 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L |
42596 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L |
42597 | #define DC_COMBOPHYPLLREGS0_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L |
42598 | //DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE |
42599 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 |
42600 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 |
42601 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 |
42602 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc |
42603 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 |
42604 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 |
42605 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L |
42606 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL |
42607 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L |
42608 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L |
42609 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L |
42610 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L |
42611 | //DC_COMBOPHYPLLREGS0_BW_CTRL_FINE |
42612 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 |
42613 | #define DC_COMBOPHYPLLREGS0_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL |
42614 | //DC_COMBOPHYPLLREGS0_CAL_CTRL |
42615 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 |
42616 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en__SHIFT 0x1 |
42617 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 |
42618 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel__SHIFT 0x9 |
42619 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis__SHIFT 0xb |
42620 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio__SHIFT 0xd |
42621 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 |
42622 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 |
42623 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate__SHIFT 0x18 |
42624 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L |
42625 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_en_MASK 0x00000002L |
42626 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L |
42627 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__meas_win_sel_MASK 0x00000600L |
42628 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L |
42629 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_ratio_MASK 0x001FE000L |
42630 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L |
42631 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L |
42632 | #define DC_COMBOPHYPLLREGS0_CAL_CTRL__refclk_rate_MASK 0xFF000000L |
42633 | //DC_COMBOPHYPLLREGS0_LOOP_CTRL |
42634 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 |
42635 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 |
42636 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 |
42637 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 |
42638 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa |
42639 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc |
42640 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe |
42641 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en__SHIFT 0x10 |
42642 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 |
42643 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset__SHIFT 0x14 |
42644 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L |
42645 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L |
42646 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L |
42647 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L |
42648 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L |
42649 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L |
42650 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L |
42651 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__prbs_en_MASK 0x00010000L |
42652 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L |
42653 | #define DC_COMBOPHYPLLREGS0_LOOP_CTRL__phase_offset_MASK 0x07F00000L |
42654 | //DC_COMBOPHYPLLREGS0_VREG_CFG |
42655 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac__SHIFT 0x0 |
42656 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en__SHIFT 0x1 |
42657 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2__SHIFT 0x2 |
42658 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel__SHIFT 0x3 |
42659 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode__SHIFT 0x5 |
42660 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel__SHIFT 0x7 |
42661 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi__SHIFT 0xb |
42662 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo__SHIFT 0xc |
42663 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver__SHIFT 0xd |
42664 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump__SHIFT 0xf |
42665 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x__SHIFT 0x10 |
42666 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x__SHIFT 0x11 |
42667 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on__SHIFT 0x12 |
42668 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2__SHIFT 0x14 |
42669 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_ac_MASK 0x00000001L |
42670 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__bleeder_en_MASK 0x00000002L |
42671 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__is_1p2_MASK 0x00000004L |
42672 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_obs_sel_MASK 0x00000018L |
42673 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_on_mode_MASK 0x00000060L |
42674 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__rlad_tap_sel_MASK 0x00000780L |
42675 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_hi_MASK 0x00000800L |
42676 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__reg_off_lo_MASK 0x00001000L |
42677 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__scale_driver_MASK 0x00006000L |
42678 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_bump_MASK 0x00008000L |
42679 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__sel_rladder_x_MASK 0x00010000L |
42680 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__short_rc_filt_x_MASK 0x00020000L |
42681 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__vref_pwr_on_MASK 0x00040000L |
42682 | #define DC_COMBOPHYPLLREGS0_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L |
42683 | //DC_COMBOPHYPLLREGS0_OBSERVE0 |
42684 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 |
42685 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock__SHIFT 0x6 |
42686 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis__SHIFT 0x8 |
42687 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg__SHIFT 0xa |
42688 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel__SHIFT 0x15 |
42689 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL |
42690 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__clear_sticky_lock_MASK 0x00000040L |
42691 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__lock_det_dis_MASK 0x00000100L |
42692 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__dco_cfg_MASK 0x0003FC00L |
42693 | #define DC_COMBOPHYPLLREGS0_OBSERVE0__anaobs_sel_MASK 0x00E00000L |
42694 | //DC_COMBOPHYPLLREGS0_OBSERVE1 |
42695 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel__SHIFT 0x0 |
42696 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel__SHIFT 0x5 |
42697 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div__SHIFT 0xa |
42698 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div__SHIFT 0xd |
42699 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer__SHIFT 0x10 |
42700 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_sel_MASK 0x0000000FL |
42701 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L |
42702 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_div_MASK 0x00000C00L |
42703 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__digobs_trig_div_MASK 0x00006000L |
42704 | #define DC_COMBOPHYPLLREGS0_OBSERVE1__lock_timer_MASK 0x3FFF0000L |
42705 | //DC_COMBOPHYPLLREGS0_DFT_OUT |
42706 | #define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data__SHIFT 0x0 |
42707 | #define DC_COMBOPHYPLLREGS0_DFT_OUT__dft_data_MASK 0xFFFFFFFFL |
42708 | //DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 |
42709 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 |
42710 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L |
42711 | //DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL |
42712 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 |
42713 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 |
42714 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 |
42715 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 |
42716 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 |
42717 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa |
42718 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd |
42719 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe |
42720 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf |
42721 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 |
42722 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 |
42723 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L |
42724 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L |
42725 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL |
42726 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L |
42727 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L |
42728 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L |
42729 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L |
42730 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L |
42731 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L |
42732 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L |
42733 | #define DC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L |
42734 | |
42735 | |
42736 | // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec |
42737 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 |
42738 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42739 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42740 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 |
42741 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42742 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42743 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 |
42744 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42745 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42746 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 |
42747 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42748 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42749 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 |
42750 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42751 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42752 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 |
42753 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42754 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42755 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 |
42756 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42757 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42758 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 |
42759 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42760 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42761 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 |
42762 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42763 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42764 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 |
42765 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42766 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42767 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 |
42768 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42769 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42770 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 |
42771 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42772 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42773 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 |
42774 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42775 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42776 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 |
42777 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42778 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42779 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 |
42780 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42781 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42782 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 |
42783 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42784 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42785 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 |
42786 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42787 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42788 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 |
42789 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42790 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42791 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 |
42792 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42793 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42794 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 |
42795 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42796 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42797 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 |
42798 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42799 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42800 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 |
42801 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42802 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42803 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 |
42804 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42805 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42806 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 |
42807 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42808 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42809 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 |
42810 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42811 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42812 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 |
42813 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42814 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42815 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 |
42816 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42817 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42818 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 |
42819 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42820 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42821 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 |
42822 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42823 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42824 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 |
42825 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42826 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42827 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 |
42828 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42829 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42830 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 |
42831 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42832 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42833 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 |
42834 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42835 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42836 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 |
42837 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42838 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42839 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 |
42840 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42841 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42842 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 |
42843 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42844 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42845 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 |
42846 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42847 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42848 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 |
42849 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42850 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42851 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 |
42852 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42853 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42854 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 |
42855 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42856 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42857 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 |
42858 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42859 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42860 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 |
42861 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42862 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42863 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 |
42864 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42865 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42866 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 |
42867 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42868 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42869 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 |
42870 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42871 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42872 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 |
42873 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42874 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42875 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 |
42876 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42877 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42878 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 |
42879 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42880 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42881 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 |
42882 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42883 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42884 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 |
42885 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42886 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42887 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 |
42888 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42889 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42890 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 |
42891 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42892 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42893 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 |
42894 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42895 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42896 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 |
42897 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42898 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42899 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 |
42900 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42901 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42902 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 |
42903 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42904 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42905 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 |
42906 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42907 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42908 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 |
42909 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42910 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42911 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 |
42912 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42913 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42914 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 |
42915 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42916 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42917 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 |
42918 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42919 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42920 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 |
42921 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42922 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42923 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 |
42924 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42925 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42926 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 |
42927 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42928 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42929 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 |
42930 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42931 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42932 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 |
42933 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42934 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42935 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 |
42936 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42937 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42938 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 |
42939 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42940 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42941 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 |
42942 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42943 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42944 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 |
42945 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42946 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42947 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 |
42948 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42949 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42950 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 |
42951 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42952 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42953 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 |
42954 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42955 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42956 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 |
42957 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42958 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42959 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 |
42960 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42961 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42962 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 |
42963 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42964 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42965 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 |
42966 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42967 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42968 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 |
42969 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42970 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42971 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 |
42972 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42973 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42974 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 |
42975 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42976 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42977 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 |
42978 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42979 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42980 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 |
42981 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42982 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42983 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 |
42984 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42985 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42986 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 |
42987 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42988 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42989 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 |
42990 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42991 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42992 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 |
42993 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42994 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42995 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 |
42996 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
42997 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
42998 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 |
42999 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43000 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43001 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 |
43002 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43003 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43004 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 |
43005 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43006 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43007 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 |
43008 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43009 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43010 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 |
43011 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43012 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43013 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 |
43014 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43015 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43016 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 |
43017 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43018 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43019 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 |
43020 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43021 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43022 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 |
43023 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43024 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43025 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 |
43026 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43027 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43028 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 |
43029 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43030 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43031 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 |
43032 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43033 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43034 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 |
43035 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43036 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43037 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 |
43038 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43039 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43040 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 |
43041 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43042 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43043 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 |
43044 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43045 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43046 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 |
43047 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43048 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43049 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 |
43050 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43051 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43052 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 |
43053 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43054 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43055 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 |
43056 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43057 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43058 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 |
43059 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43060 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43061 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 |
43062 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43063 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43064 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 |
43065 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43066 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43067 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 |
43068 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43069 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43070 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 |
43071 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43072 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43073 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 |
43074 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43075 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43076 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 |
43077 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43078 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43079 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 |
43080 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43081 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43082 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 |
43083 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43084 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43085 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 |
43086 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43087 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43088 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 |
43089 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43090 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43091 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 |
43092 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43093 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43094 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 |
43095 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43096 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43097 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 |
43098 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43099 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43100 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 |
43101 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43102 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43103 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 |
43104 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43105 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43106 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 |
43107 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43108 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43109 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 |
43110 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43111 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43112 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 |
43113 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43114 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43115 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 |
43116 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43117 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43118 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 |
43119 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43120 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43121 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 |
43122 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43123 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43124 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 |
43125 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43126 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43127 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 |
43128 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43129 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43130 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 |
43131 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43132 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43133 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 |
43134 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43135 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43136 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 |
43137 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43138 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43139 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 |
43140 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43141 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43142 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 |
43143 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43144 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43145 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 |
43146 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43147 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43148 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 |
43149 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43150 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43151 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 |
43152 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43153 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43154 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 |
43155 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43156 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43157 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 |
43158 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43159 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43160 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 |
43161 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43162 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43163 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 |
43164 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43165 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43166 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 |
43167 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43168 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43169 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 |
43170 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43171 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43172 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 |
43173 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43174 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43175 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 |
43176 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43177 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43178 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 |
43179 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43180 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43181 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 |
43182 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43183 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43184 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 |
43185 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43186 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43187 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 |
43188 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43189 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43190 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 |
43191 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43192 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43193 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 |
43194 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43195 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43196 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 |
43197 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43198 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43199 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 |
43200 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43201 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43202 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 |
43203 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43204 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43205 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 |
43206 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43207 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43208 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 |
43209 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43210 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43211 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 |
43212 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43213 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43214 | //DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 |
43215 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43216 | #define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43217 | |
43218 | |
43219 | // addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec |
43220 | //DC_COMBOPHYCMREGS1_COMMON_FUSE1 |
43221 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 |
43222 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 |
43223 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 |
43224 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 |
43225 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa |
43226 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc |
43227 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd |
43228 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 |
43229 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 |
43230 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 |
43231 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 |
43232 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L |
43233 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L |
43234 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L |
43235 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L |
43236 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L |
43237 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L |
43238 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L |
43239 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L |
43240 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L |
43241 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L |
43242 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L |
43243 | //DC_COMBOPHYCMREGS1_COMMON_FUSE2 |
43244 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 |
43245 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 |
43246 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 |
43247 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare__SHIFT 0xe |
43248 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L |
43249 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL |
43250 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L |
43251 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L |
43252 | //DC_COMBOPHYCMREGS1_COMMON_FUSE3 |
43253 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 |
43254 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 |
43255 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa |
43256 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd |
43257 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 |
43258 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 |
43259 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 |
43260 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 |
43261 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 |
43262 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a |
43263 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d |
43264 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L |
43265 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL |
43266 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L |
43267 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L |
43268 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L |
43269 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L |
43270 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L |
43271 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L |
43272 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L |
43273 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L |
43274 | #define DC_COMBOPHYCMREGS1_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L |
43275 | //DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM |
43276 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 |
43277 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 |
43278 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 |
43279 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 |
43280 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL |
43281 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L |
43282 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L |
43283 | #define DC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L |
43284 | //DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT |
43285 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 |
43286 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 |
43287 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb |
43288 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL |
43289 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L |
43290 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L |
43291 | //DC_COMBOPHYCMREGS1_COMMON_TXCNTRL |
43292 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 |
43293 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 |
43294 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 |
43295 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 |
43296 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc |
43297 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL |
43298 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L |
43299 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L |
43300 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L |
43301 | #define DC_COMBOPHYCMREGS1_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L |
43302 | //DC_COMBOPHYCMREGS1_COMMON_TMDP |
43303 | #define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare__SHIFT 0x0 |
43304 | #define DC_COMBOPHYCMREGS1_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL |
43305 | //DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS |
43306 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 |
43307 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 |
43308 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 |
43309 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 |
43310 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 |
43311 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 |
43312 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 |
43313 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 |
43314 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L |
43315 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L |
43316 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L |
43317 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L |
43318 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L |
43319 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L |
43320 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L |
43321 | #define DC_COMBOPHYCMREGS1_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L |
43322 | //DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL |
43323 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 |
43324 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 |
43325 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 |
43326 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 |
43327 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L |
43328 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL |
43329 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L |
43330 | #define DC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L |
43331 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 |
43332 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 |
43333 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL |
43334 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 |
43335 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 |
43336 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL |
43337 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 |
43338 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 |
43339 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL |
43340 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 |
43341 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 |
43342 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL |
43343 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 |
43344 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 |
43345 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL |
43346 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 |
43347 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 |
43348 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL |
43349 | //DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 |
43350 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 |
43351 | #define DC_COMBOPHYCMREGS1_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL |
43352 | |
43353 | |
43354 | // addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec |
43355 | //DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 |
43356 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 |
43357 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 |
43358 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 |
43359 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L |
43360 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L |
43361 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L |
43362 | //DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 |
43363 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 |
43364 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 |
43365 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 |
43366 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L |
43367 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L |
43368 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L |
43369 | //DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 |
43370 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 |
43371 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 |
43372 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 |
43373 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 |
43374 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa |
43375 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc |
43376 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd |
43377 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe |
43378 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf |
43379 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 |
43380 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 |
43381 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 |
43382 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L |
43383 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L |
43384 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L |
43385 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L |
43386 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L |
43387 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L |
43388 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L |
43389 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L |
43390 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L |
43391 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L |
43392 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L |
43393 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L |
43394 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 |
43395 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 |
43396 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL |
43397 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 |
43398 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 |
43399 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL |
43400 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 |
43401 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 |
43402 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL |
43403 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 |
43404 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 |
43405 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL |
43406 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 |
43407 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 |
43408 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL |
43409 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 |
43410 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 |
43411 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL |
43412 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 |
43413 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 |
43414 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL |
43415 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 |
43416 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 |
43417 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL |
43418 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 |
43419 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 |
43420 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL |
43421 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 |
43422 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 |
43423 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL |
43424 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 |
43425 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 |
43426 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL |
43427 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 |
43428 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 |
43429 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL |
43430 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 |
43431 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 |
43432 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL |
43433 | //DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 |
43434 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 |
43435 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 |
43436 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 |
43437 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L |
43438 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L |
43439 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L |
43440 | //DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 |
43441 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 |
43442 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 |
43443 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 |
43444 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L |
43445 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L |
43446 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L |
43447 | //DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 |
43448 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 |
43449 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 |
43450 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 |
43451 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 |
43452 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa |
43453 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc |
43454 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd |
43455 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe |
43456 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf |
43457 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 |
43458 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 |
43459 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 |
43460 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L |
43461 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L |
43462 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L |
43463 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L |
43464 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L |
43465 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L |
43466 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L |
43467 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L |
43468 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L |
43469 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L |
43470 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L |
43471 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L |
43472 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 |
43473 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 |
43474 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL |
43475 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 |
43476 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 |
43477 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL |
43478 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 |
43479 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 |
43480 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL |
43481 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 |
43482 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 |
43483 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL |
43484 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 |
43485 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 |
43486 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL |
43487 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 |
43488 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 |
43489 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL |
43490 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 |
43491 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 |
43492 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL |
43493 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 |
43494 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 |
43495 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL |
43496 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 |
43497 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 |
43498 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL |
43499 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 |
43500 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 |
43501 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL |
43502 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 |
43503 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 |
43504 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL |
43505 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 |
43506 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 |
43507 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL |
43508 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 |
43509 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 |
43510 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL |
43511 | //DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 |
43512 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 |
43513 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 |
43514 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 |
43515 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L |
43516 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L |
43517 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L |
43518 | //DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 |
43519 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 |
43520 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 |
43521 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 |
43522 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L |
43523 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L |
43524 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L |
43525 | //DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 |
43526 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 |
43527 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 |
43528 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 |
43529 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 |
43530 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa |
43531 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc |
43532 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd |
43533 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe |
43534 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf |
43535 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 |
43536 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 |
43537 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 |
43538 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L |
43539 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L |
43540 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L |
43541 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L |
43542 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L |
43543 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L |
43544 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L |
43545 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L |
43546 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L |
43547 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L |
43548 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L |
43549 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L |
43550 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 |
43551 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 |
43552 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL |
43553 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 |
43554 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 |
43555 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL |
43556 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 |
43557 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 |
43558 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL |
43559 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 |
43560 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 |
43561 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL |
43562 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 |
43563 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 |
43564 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL |
43565 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 |
43566 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 |
43567 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL |
43568 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 |
43569 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 |
43570 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL |
43571 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 |
43572 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 |
43573 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL |
43574 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 |
43575 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 |
43576 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL |
43577 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 |
43578 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 |
43579 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL |
43580 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 |
43581 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 |
43582 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL |
43583 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 |
43584 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 |
43585 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL |
43586 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 |
43587 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 |
43588 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL |
43589 | //DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 |
43590 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 |
43591 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 |
43592 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 |
43593 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L |
43594 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L |
43595 | #define DC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L |
43596 | //DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 |
43597 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 |
43598 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 |
43599 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 |
43600 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L |
43601 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L |
43602 | #define DC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L |
43603 | //DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 |
43604 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 |
43605 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 |
43606 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 |
43607 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 |
43608 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa |
43609 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc |
43610 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd |
43611 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe |
43612 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf |
43613 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 |
43614 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 |
43615 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 |
43616 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L |
43617 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L |
43618 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L |
43619 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L |
43620 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L |
43621 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L |
43622 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L |
43623 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L |
43624 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L |
43625 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L |
43626 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L |
43627 | #define DC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L |
43628 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 |
43629 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 |
43630 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL |
43631 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 |
43632 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 |
43633 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL |
43634 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 |
43635 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 |
43636 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL |
43637 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 |
43638 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 |
43639 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL |
43640 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 |
43641 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 |
43642 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL |
43643 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 |
43644 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 |
43645 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL |
43646 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 |
43647 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 |
43648 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL |
43649 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 |
43650 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 |
43651 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL |
43652 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 |
43653 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 |
43654 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL |
43655 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 |
43656 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 |
43657 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL |
43658 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 |
43659 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 |
43660 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL |
43661 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 |
43662 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 |
43663 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL |
43664 | //DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 |
43665 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 |
43666 | #define DC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL |
43667 | |
43668 | |
43669 | // addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec |
43670 | //DC_COMBOPHYPLLREGS1_FREQ_CTRL0 |
43671 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 |
43672 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int__SHIFT 0x10 |
43673 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL |
43674 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L |
43675 | //DC_COMBOPHYPLLREGS1_FREQ_CTRL1 |
43676 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 |
43677 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int__SHIFT 0x10 |
43678 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL |
43679 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L |
43680 | //DC_COMBOPHYPLLREGS1_FREQ_CTRL2 |
43681 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom__SHIFT 0x0 |
43682 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 |
43683 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL |
43684 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L |
43685 | //DC_COMBOPHYPLLREGS1_FREQ_CTRL3 |
43686 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div__SHIFT 0x0 |
43687 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 |
43688 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en__SHIFT 0x6 |
43689 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en__SHIFT 0x8 |
43690 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel__SHIFT 0xa |
43691 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en__SHIFT 0xc |
43692 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 |
43693 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 |
43694 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__refclk_div_MASK 0x00000003L |
43695 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L |
43696 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fracn_en_MASK 0x00000040L |
43697 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__ssc_en_MASK 0x00000100L |
43698 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__fcw_sel_MASK 0x00000400L |
43699 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L |
43700 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L |
43701 | #define DC_COMBOPHYPLLREGS1_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L |
43702 | //DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE |
43703 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 |
43704 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 |
43705 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 |
43706 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc |
43707 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 |
43708 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 |
43709 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L |
43710 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL |
43711 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L |
43712 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L |
43713 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L |
43714 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L |
43715 | //DC_COMBOPHYPLLREGS1_BW_CTRL_FINE |
43716 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 |
43717 | #define DC_COMBOPHYPLLREGS1_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL |
43718 | //DC_COMBOPHYPLLREGS1_CAL_CTRL |
43719 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 |
43720 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en__SHIFT 0x1 |
43721 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 |
43722 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel__SHIFT 0x9 |
43723 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis__SHIFT 0xb |
43724 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio__SHIFT 0xd |
43725 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 |
43726 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 |
43727 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate__SHIFT 0x18 |
43728 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L |
43729 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_en_MASK 0x00000002L |
43730 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L |
43731 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__meas_win_sel_MASK 0x00000600L |
43732 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L |
43733 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_ratio_MASK 0x001FE000L |
43734 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L |
43735 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L |
43736 | #define DC_COMBOPHYPLLREGS1_CAL_CTRL__refclk_rate_MASK 0xFF000000L |
43737 | //DC_COMBOPHYPLLREGS1_LOOP_CTRL |
43738 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 |
43739 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 |
43740 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 |
43741 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 |
43742 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa |
43743 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc |
43744 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe |
43745 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en__SHIFT 0x10 |
43746 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 |
43747 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset__SHIFT 0x14 |
43748 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L |
43749 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L |
43750 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L |
43751 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L |
43752 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L |
43753 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L |
43754 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L |
43755 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__prbs_en_MASK 0x00010000L |
43756 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L |
43757 | #define DC_COMBOPHYPLLREGS1_LOOP_CTRL__phase_offset_MASK 0x07F00000L |
43758 | //DC_COMBOPHYPLLREGS1_VREG_CFG |
43759 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac__SHIFT 0x0 |
43760 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en__SHIFT 0x1 |
43761 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2__SHIFT 0x2 |
43762 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel__SHIFT 0x3 |
43763 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode__SHIFT 0x5 |
43764 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel__SHIFT 0x7 |
43765 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi__SHIFT 0xb |
43766 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo__SHIFT 0xc |
43767 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver__SHIFT 0xd |
43768 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump__SHIFT 0xf |
43769 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x__SHIFT 0x10 |
43770 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x__SHIFT 0x11 |
43771 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on__SHIFT 0x12 |
43772 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2__SHIFT 0x14 |
43773 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_ac_MASK 0x00000001L |
43774 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__bleeder_en_MASK 0x00000002L |
43775 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__is_1p2_MASK 0x00000004L |
43776 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_obs_sel_MASK 0x00000018L |
43777 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_on_mode_MASK 0x00000060L |
43778 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__rlad_tap_sel_MASK 0x00000780L |
43779 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_hi_MASK 0x00000800L |
43780 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__reg_off_lo_MASK 0x00001000L |
43781 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__scale_driver_MASK 0x00006000L |
43782 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_bump_MASK 0x00008000L |
43783 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__sel_rladder_x_MASK 0x00010000L |
43784 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__short_rc_filt_x_MASK 0x00020000L |
43785 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__vref_pwr_on_MASK 0x00040000L |
43786 | #define DC_COMBOPHYPLLREGS1_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L |
43787 | //DC_COMBOPHYPLLREGS1_OBSERVE0 |
43788 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 |
43789 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock__SHIFT 0x6 |
43790 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis__SHIFT 0x8 |
43791 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg__SHIFT 0xa |
43792 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel__SHIFT 0x15 |
43793 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL |
43794 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__clear_sticky_lock_MASK 0x00000040L |
43795 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__lock_det_dis_MASK 0x00000100L |
43796 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__dco_cfg_MASK 0x0003FC00L |
43797 | #define DC_COMBOPHYPLLREGS1_OBSERVE0__anaobs_sel_MASK 0x00E00000L |
43798 | //DC_COMBOPHYPLLREGS1_OBSERVE1 |
43799 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel__SHIFT 0x0 |
43800 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel__SHIFT 0x5 |
43801 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div__SHIFT 0xa |
43802 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div__SHIFT 0xd |
43803 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer__SHIFT 0x10 |
43804 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_sel_MASK 0x0000000FL |
43805 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L |
43806 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_div_MASK 0x00000C00L |
43807 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__digobs_trig_div_MASK 0x00006000L |
43808 | #define DC_COMBOPHYPLLREGS1_OBSERVE1__lock_timer_MASK 0x3FFF0000L |
43809 | //DC_COMBOPHYPLLREGS1_DFT_OUT |
43810 | #define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data__SHIFT 0x0 |
43811 | #define DC_COMBOPHYPLLREGS1_DFT_OUT__dft_data_MASK 0xFFFFFFFFL |
43812 | //DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 |
43813 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 |
43814 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L |
43815 | //DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL |
43816 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 |
43817 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 |
43818 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 |
43819 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 |
43820 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 |
43821 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa |
43822 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd |
43823 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe |
43824 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf |
43825 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 |
43826 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 |
43827 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L |
43828 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L |
43829 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL |
43830 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L |
43831 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L |
43832 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L |
43833 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L |
43834 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L |
43835 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L |
43836 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L |
43837 | #define DC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L |
43838 | |
43839 | |
43840 | // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec |
43841 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 |
43842 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43843 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43844 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 |
43845 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43846 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43847 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 |
43848 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43849 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43850 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 |
43851 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43852 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43853 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 |
43854 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43855 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43856 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 |
43857 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43858 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43859 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 |
43860 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43861 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43862 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 |
43863 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43864 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43865 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 |
43866 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43867 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43868 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 |
43869 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43870 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43871 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 |
43872 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43873 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43874 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 |
43875 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43876 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43877 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 |
43878 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43879 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43880 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 |
43881 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43882 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43883 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 |
43884 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43885 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43886 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 |
43887 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43888 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43889 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 |
43890 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43891 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43892 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 |
43893 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43894 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43895 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 |
43896 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43897 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43898 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 |
43899 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43900 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43901 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 |
43902 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43903 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43904 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 |
43905 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43906 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43907 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 |
43908 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43909 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43910 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 |
43911 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43912 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43913 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 |
43914 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43915 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43916 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 |
43917 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43918 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43919 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 |
43920 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43921 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43922 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 |
43923 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43924 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43925 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 |
43926 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43927 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43928 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 |
43929 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43930 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43931 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 |
43932 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43933 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43934 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 |
43935 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43936 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43937 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 |
43938 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43939 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43940 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 |
43941 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43942 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43943 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 |
43944 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43945 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43946 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 |
43947 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43948 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43949 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 |
43950 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43951 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43952 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 |
43953 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43954 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43955 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 |
43956 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43957 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43958 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 |
43959 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43960 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43961 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 |
43962 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43963 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43964 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 |
43965 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43966 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43967 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 |
43968 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43969 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43970 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 |
43971 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43972 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43973 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 |
43974 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43975 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43976 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 |
43977 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43978 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43979 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 |
43980 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43981 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43982 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 |
43983 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43984 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43985 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 |
43986 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43987 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43988 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 |
43989 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43990 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43991 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 |
43992 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43993 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43994 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 |
43995 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43996 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
43997 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 |
43998 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
43999 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44000 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 |
44001 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44002 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44003 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 |
44004 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44005 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44006 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 |
44007 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44008 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44009 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 |
44010 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44011 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44012 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 |
44013 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44014 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44015 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 |
44016 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44017 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44018 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 |
44019 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44020 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44021 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 |
44022 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44023 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44024 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 |
44025 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44026 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44027 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 |
44028 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44029 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44030 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 |
44031 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44032 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44033 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 |
44034 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44035 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44036 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 |
44037 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44038 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44039 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 |
44040 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44041 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44042 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 |
44043 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44044 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44045 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 |
44046 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44047 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44048 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 |
44049 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44050 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44051 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 |
44052 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44053 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44054 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 |
44055 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44056 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44057 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 |
44058 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44059 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44060 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 |
44061 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44062 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44063 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 |
44064 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44065 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44066 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 |
44067 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44068 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44069 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 |
44070 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44071 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44072 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 |
44073 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44074 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44075 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 |
44076 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44077 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44078 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 |
44079 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44080 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44081 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 |
44082 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44083 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44084 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 |
44085 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44086 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44087 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 |
44088 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44089 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44090 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 |
44091 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44092 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44093 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 |
44094 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44095 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44096 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 |
44097 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44098 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44099 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 |
44100 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44101 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44102 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 |
44103 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44104 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44105 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 |
44106 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44107 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44108 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 |
44109 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44110 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44111 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 |
44112 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44113 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44114 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 |
44115 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44116 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44117 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 |
44118 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44119 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44120 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 |
44121 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44122 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44123 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 |
44124 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44125 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44126 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 |
44127 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44128 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44129 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 |
44130 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44131 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44132 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 |
44133 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44134 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44135 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 |
44136 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44137 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44138 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 |
44139 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44140 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44141 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 |
44142 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44143 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44144 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 |
44145 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44146 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44147 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 |
44148 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44149 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44150 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 |
44151 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44152 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44153 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 |
44154 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44155 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44156 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 |
44157 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44158 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44159 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 |
44160 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44161 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44162 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 |
44163 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44164 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44165 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 |
44166 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44167 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44168 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 |
44169 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44170 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44171 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 |
44172 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44173 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44174 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 |
44175 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44176 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44177 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 |
44178 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44179 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44180 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 |
44181 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44182 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44183 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 |
44184 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44185 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44186 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 |
44187 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44188 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44189 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 |
44190 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44191 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44192 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 |
44193 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44194 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44195 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 |
44196 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44197 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44198 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 |
44199 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44200 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44201 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 |
44202 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44203 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44204 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 |
44205 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44206 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44207 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 |
44208 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44209 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44210 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 |
44211 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44212 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44213 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 |
44214 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44215 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44216 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 |
44217 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44218 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44219 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 |
44220 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44221 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44222 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 |
44223 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44224 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44225 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 |
44226 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44227 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44228 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 |
44229 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44230 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44231 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 |
44232 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44233 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44234 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 |
44235 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44236 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44237 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 |
44238 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44239 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44240 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 |
44241 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44242 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44243 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 |
44244 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44245 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44246 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 |
44247 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44248 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44249 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 |
44250 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44251 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44252 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 |
44253 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44254 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44255 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 |
44256 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44257 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44258 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 |
44259 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44260 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44261 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 |
44262 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44263 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44264 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 |
44265 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44266 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44267 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 |
44268 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44269 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44270 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 |
44271 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44272 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44273 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 |
44274 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44275 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44276 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 |
44277 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44278 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44279 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 |
44280 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44281 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44282 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 |
44283 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44284 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44285 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 |
44286 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44287 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44288 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 |
44289 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44290 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44291 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 |
44292 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44293 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44294 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 |
44295 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44296 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44297 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 |
44298 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44299 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44300 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 |
44301 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44302 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44303 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 |
44304 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44305 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44306 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 |
44307 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44308 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44309 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 |
44310 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44311 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44312 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 |
44313 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44314 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44315 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 |
44316 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44317 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44318 | //DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 |
44319 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44320 | #define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44321 | |
44322 | |
44323 | // addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec |
44324 | //DC_COMBOPHYCMREGS2_COMMON_FUSE1 |
44325 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 |
44326 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 |
44327 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 |
44328 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 |
44329 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa |
44330 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc |
44331 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd |
44332 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 |
44333 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 |
44334 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 |
44335 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 |
44336 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L |
44337 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L |
44338 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L |
44339 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L |
44340 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L |
44341 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L |
44342 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L |
44343 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L |
44344 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L |
44345 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L |
44346 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L |
44347 | //DC_COMBOPHYCMREGS2_COMMON_FUSE2 |
44348 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 |
44349 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 |
44350 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 |
44351 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare__SHIFT 0xe |
44352 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L |
44353 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL |
44354 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L |
44355 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L |
44356 | //DC_COMBOPHYCMREGS2_COMMON_FUSE3 |
44357 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 |
44358 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 |
44359 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa |
44360 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd |
44361 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 |
44362 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 |
44363 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 |
44364 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 |
44365 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 |
44366 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a |
44367 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d |
44368 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L |
44369 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL |
44370 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L |
44371 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L |
44372 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L |
44373 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L |
44374 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L |
44375 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L |
44376 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L |
44377 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L |
44378 | #define DC_COMBOPHYCMREGS2_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L |
44379 | //DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM |
44380 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 |
44381 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 |
44382 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 |
44383 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 |
44384 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL |
44385 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L |
44386 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L |
44387 | #define DC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L |
44388 | //DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT |
44389 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 |
44390 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 |
44391 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb |
44392 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL |
44393 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L |
44394 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L |
44395 | //DC_COMBOPHYCMREGS2_COMMON_TXCNTRL |
44396 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 |
44397 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 |
44398 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 |
44399 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 |
44400 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc |
44401 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL |
44402 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L |
44403 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L |
44404 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L |
44405 | #define DC_COMBOPHYCMREGS2_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L |
44406 | //DC_COMBOPHYCMREGS2_COMMON_TMDP |
44407 | #define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare__SHIFT 0x0 |
44408 | #define DC_COMBOPHYCMREGS2_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL |
44409 | //DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS |
44410 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 |
44411 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 |
44412 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 |
44413 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 |
44414 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 |
44415 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 |
44416 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 |
44417 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 |
44418 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L |
44419 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L |
44420 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L |
44421 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L |
44422 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L |
44423 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L |
44424 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L |
44425 | #define DC_COMBOPHYCMREGS2_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L |
44426 | //DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL |
44427 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 |
44428 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 |
44429 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 |
44430 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 |
44431 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L |
44432 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL |
44433 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L |
44434 | #define DC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L |
44435 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 |
44436 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 |
44437 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL |
44438 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 |
44439 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 |
44440 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL |
44441 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 |
44442 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 |
44443 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL |
44444 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 |
44445 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 |
44446 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL |
44447 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 |
44448 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 |
44449 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL |
44450 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 |
44451 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 |
44452 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL |
44453 | //DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 |
44454 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 |
44455 | #define DC_COMBOPHYCMREGS2_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL |
44456 | |
44457 | |
44458 | // addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec |
44459 | //DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 |
44460 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 |
44461 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 |
44462 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 |
44463 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L |
44464 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L |
44465 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L |
44466 | //DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 |
44467 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 |
44468 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 |
44469 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 |
44470 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L |
44471 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L |
44472 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L |
44473 | //DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 |
44474 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 |
44475 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 |
44476 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 |
44477 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 |
44478 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa |
44479 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc |
44480 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd |
44481 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe |
44482 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf |
44483 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 |
44484 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 |
44485 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 |
44486 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L |
44487 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L |
44488 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L |
44489 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L |
44490 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L |
44491 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L |
44492 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L |
44493 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L |
44494 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L |
44495 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L |
44496 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L |
44497 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L |
44498 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 |
44499 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 |
44500 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL |
44501 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 |
44502 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 |
44503 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL |
44504 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 |
44505 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 |
44506 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL |
44507 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 |
44508 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 |
44509 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL |
44510 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 |
44511 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 |
44512 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL |
44513 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 |
44514 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 |
44515 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL |
44516 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 |
44517 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 |
44518 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL |
44519 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 |
44520 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 |
44521 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL |
44522 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 |
44523 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 |
44524 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL |
44525 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 |
44526 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 |
44527 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL |
44528 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 |
44529 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 |
44530 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL |
44531 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 |
44532 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 |
44533 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL |
44534 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 |
44535 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 |
44536 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL |
44537 | //DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 |
44538 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 |
44539 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 |
44540 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 |
44541 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L |
44542 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L |
44543 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L |
44544 | //DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 |
44545 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 |
44546 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 |
44547 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 |
44548 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L |
44549 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L |
44550 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L |
44551 | //DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 |
44552 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 |
44553 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 |
44554 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 |
44555 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 |
44556 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa |
44557 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc |
44558 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd |
44559 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe |
44560 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf |
44561 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 |
44562 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 |
44563 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 |
44564 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L |
44565 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L |
44566 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L |
44567 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L |
44568 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L |
44569 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L |
44570 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L |
44571 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L |
44572 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L |
44573 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L |
44574 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L |
44575 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L |
44576 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 |
44577 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 |
44578 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL |
44579 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 |
44580 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 |
44581 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL |
44582 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 |
44583 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 |
44584 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL |
44585 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 |
44586 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 |
44587 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL |
44588 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 |
44589 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 |
44590 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL |
44591 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 |
44592 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 |
44593 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL |
44594 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 |
44595 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 |
44596 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL |
44597 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 |
44598 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 |
44599 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL |
44600 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 |
44601 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 |
44602 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL |
44603 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 |
44604 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 |
44605 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL |
44606 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 |
44607 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 |
44608 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL |
44609 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 |
44610 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 |
44611 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL |
44612 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 |
44613 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 |
44614 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL |
44615 | //DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 |
44616 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 |
44617 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 |
44618 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 |
44619 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L |
44620 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L |
44621 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L |
44622 | //DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 |
44623 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 |
44624 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 |
44625 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 |
44626 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L |
44627 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L |
44628 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L |
44629 | //DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 |
44630 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 |
44631 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 |
44632 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 |
44633 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 |
44634 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa |
44635 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc |
44636 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd |
44637 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe |
44638 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf |
44639 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 |
44640 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 |
44641 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 |
44642 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L |
44643 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L |
44644 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L |
44645 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L |
44646 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L |
44647 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L |
44648 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L |
44649 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L |
44650 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L |
44651 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L |
44652 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L |
44653 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L |
44654 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 |
44655 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 |
44656 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL |
44657 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 |
44658 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 |
44659 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL |
44660 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 |
44661 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 |
44662 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL |
44663 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 |
44664 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 |
44665 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL |
44666 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 |
44667 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 |
44668 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL |
44669 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 |
44670 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 |
44671 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL |
44672 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 |
44673 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 |
44674 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL |
44675 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 |
44676 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 |
44677 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL |
44678 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 |
44679 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 |
44680 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL |
44681 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 |
44682 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 |
44683 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL |
44684 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 |
44685 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 |
44686 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL |
44687 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 |
44688 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 |
44689 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL |
44690 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 |
44691 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 |
44692 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL |
44693 | //DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 |
44694 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 |
44695 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 |
44696 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 |
44697 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L |
44698 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L |
44699 | #define DC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L |
44700 | //DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 |
44701 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 |
44702 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 |
44703 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 |
44704 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L |
44705 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L |
44706 | #define DC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L |
44707 | //DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 |
44708 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 |
44709 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 |
44710 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 |
44711 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 |
44712 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa |
44713 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc |
44714 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd |
44715 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe |
44716 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf |
44717 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 |
44718 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 |
44719 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 |
44720 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L |
44721 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L |
44722 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L |
44723 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L |
44724 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L |
44725 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L |
44726 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L |
44727 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L |
44728 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L |
44729 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L |
44730 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L |
44731 | #define DC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L |
44732 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 |
44733 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 |
44734 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL |
44735 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 |
44736 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 |
44737 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL |
44738 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 |
44739 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 |
44740 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL |
44741 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 |
44742 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 |
44743 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL |
44744 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 |
44745 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 |
44746 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL |
44747 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 |
44748 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 |
44749 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL |
44750 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 |
44751 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 |
44752 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL |
44753 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 |
44754 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 |
44755 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL |
44756 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 |
44757 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 |
44758 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL |
44759 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 |
44760 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 |
44761 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL |
44762 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 |
44763 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 |
44764 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL |
44765 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 |
44766 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 |
44767 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL |
44768 | //DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 |
44769 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 |
44770 | #define DC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL |
44771 | |
44772 | |
44773 | // addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec |
44774 | //DC_COMBOPHYPLLREGS2_FREQ_CTRL0 |
44775 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 |
44776 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int__SHIFT 0x10 |
44777 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL |
44778 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L |
44779 | //DC_COMBOPHYPLLREGS2_FREQ_CTRL1 |
44780 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 |
44781 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int__SHIFT 0x10 |
44782 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL |
44783 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L |
44784 | //DC_COMBOPHYPLLREGS2_FREQ_CTRL2 |
44785 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom__SHIFT 0x0 |
44786 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 |
44787 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL |
44788 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L |
44789 | //DC_COMBOPHYPLLREGS2_FREQ_CTRL3 |
44790 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div__SHIFT 0x0 |
44791 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 |
44792 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en__SHIFT 0x6 |
44793 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en__SHIFT 0x8 |
44794 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel__SHIFT 0xa |
44795 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en__SHIFT 0xc |
44796 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 |
44797 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 |
44798 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__refclk_div_MASK 0x00000003L |
44799 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L |
44800 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fracn_en_MASK 0x00000040L |
44801 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__ssc_en_MASK 0x00000100L |
44802 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__fcw_sel_MASK 0x00000400L |
44803 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L |
44804 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L |
44805 | #define DC_COMBOPHYPLLREGS2_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L |
44806 | //DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE |
44807 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 |
44808 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 |
44809 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 |
44810 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc |
44811 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 |
44812 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 |
44813 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L |
44814 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL |
44815 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L |
44816 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L |
44817 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L |
44818 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L |
44819 | //DC_COMBOPHYPLLREGS2_BW_CTRL_FINE |
44820 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 |
44821 | #define DC_COMBOPHYPLLREGS2_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL |
44822 | //DC_COMBOPHYPLLREGS2_CAL_CTRL |
44823 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 |
44824 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en__SHIFT 0x1 |
44825 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 |
44826 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel__SHIFT 0x9 |
44827 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis__SHIFT 0xb |
44828 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio__SHIFT 0xd |
44829 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 |
44830 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 |
44831 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate__SHIFT 0x18 |
44832 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L |
44833 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_en_MASK 0x00000002L |
44834 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L |
44835 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__meas_win_sel_MASK 0x00000600L |
44836 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L |
44837 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_ratio_MASK 0x001FE000L |
44838 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L |
44839 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L |
44840 | #define DC_COMBOPHYPLLREGS2_CAL_CTRL__refclk_rate_MASK 0xFF000000L |
44841 | //DC_COMBOPHYPLLREGS2_LOOP_CTRL |
44842 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 |
44843 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 |
44844 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 |
44845 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 |
44846 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa |
44847 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc |
44848 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe |
44849 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en__SHIFT 0x10 |
44850 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 |
44851 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset__SHIFT 0x14 |
44852 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L |
44853 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L |
44854 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L |
44855 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L |
44856 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L |
44857 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L |
44858 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L |
44859 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__prbs_en_MASK 0x00010000L |
44860 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L |
44861 | #define DC_COMBOPHYPLLREGS2_LOOP_CTRL__phase_offset_MASK 0x07F00000L |
44862 | //DC_COMBOPHYPLLREGS2_VREG_CFG |
44863 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac__SHIFT 0x0 |
44864 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en__SHIFT 0x1 |
44865 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2__SHIFT 0x2 |
44866 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel__SHIFT 0x3 |
44867 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode__SHIFT 0x5 |
44868 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel__SHIFT 0x7 |
44869 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi__SHIFT 0xb |
44870 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo__SHIFT 0xc |
44871 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver__SHIFT 0xd |
44872 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump__SHIFT 0xf |
44873 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x__SHIFT 0x10 |
44874 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x__SHIFT 0x11 |
44875 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on__SHIFT 0x12 |
44876 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2__SHIFT 0x14 |
44877 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_ac_MASK 0x00000001L |
44878 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__bleeder_en_MASK 0x00000002L |
44879 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__is_1p2_MASK 0x00000004L |
44880 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_obs_sel_MASK 0x00000018L |
44881 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_on_mode_MASK 0x00000060L |
44882 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__rlad_tap_sel_MASK 0x00000780L |
44883 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_hi_MASK 0x00000800L |
44884 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__reg_off_lo_MASK 0x00001000L |
44885 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__scale_driver_MASK 0x00006000L |
44886 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_bump_MASK 0x00008000L |
44887 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__sel_rladder_x_MASK 0x00010000L |
44888 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__short_rc_filt_x_MASK 0x00020000L |
44889 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__vref_pwr_on_MASK 0x00040000L |
44890 | #define DC_COMBOPHYPLLREGS2_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L |
44891 | //DC_COMBOPHYPLLREGS2_OBSERVE0 |
44892 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 |
44893 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock__SHIFT 0x6 |
44894 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis__SHIFT 0x8 |
44895 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg__SHIFT 0xa |
44896 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel__SHIFT 0x15 |
44897 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL |
44898 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__clear_sticky_lock_MASK 0x00000040L |
44899 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__lock_det_dis_MASK 0x00000100L |
44900 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__dco_cfg_MASK 0x0003FC00L |
44901 | #define DC_COMBOPHYPLLREGS2_OBSERVE0__anaobs_sel_MASK 0x00E00000L |
44902 | //DC_COMBOPHYPLLREGS2_OBSERVE1 |
44903 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel__SHIFT 0x0 |
44904 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel__SHIFT 0x5 |
44905 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div__SHIFT 0xa |
44906 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div__SHIFT 0xd |
44907 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer__SHIFT 0x10 |
44908 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_sel_MASK 0x0000000FL |
44909 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L |
44910 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_div_MASK 0x00000C00L |
44911 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__digobs_trig_div_MASK 0x00006000L |
44912 | #define DC_COMBOPHYPLLREGS2_OBSERVE1__lock_timer_MASK 0x3FFF0000L |
44913 | //DC_COMBOPHYPLLREGS2_DFT_OUT |
44914 | #define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data__SHIFT 0x0 |
44915 | #define DC_COMBOPHYPLLREGS2_DFT_OUT__dft_data_MASK 0xFFFFFFFFL |
44916 | //DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 |
44917 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 |
44918 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L |
44919 | //DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL |
44920 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 |
44921 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 |
44922 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 |
44923 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 |
44924 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 |
44925 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa |
44926 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd |
44927 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe |
44928 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf |
44929 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 |
44930 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 |
44931 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L |
44932 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L |
44933 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL |
44934 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L |
44935 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L |
44936 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L |
44937 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L |
44938 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L |
44939 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L |
44940 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L |
44941 | #define DC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L |
44942 | |
44943 | |
44944 | // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec |
44945 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 |
44946 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44947 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44948 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 |
44949 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44950 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44951 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 |
44952 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44953 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44954 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 |
44955 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44956 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44957 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 |
44958 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44959 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44960 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 |
44961 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44962 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44963 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 |
44964 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44965 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44966 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 |
44967 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44968 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44969 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 |
44970 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44971 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44972 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 |
44973 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44974 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44975 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 |
44976 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44977 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44978 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 |
44979 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44980 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44981 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 |
44982 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44983 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44984 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 |
44985 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44986 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44987 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 |
44988 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44989 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44990 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 |
44991 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44992 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44993 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 |
44994 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44995 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44996 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 |
44997 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
44998 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
44999 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 |
45000 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45001 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45002 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 |
45003 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45004 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45005 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 |
45006 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45007 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45008 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 |
45009 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45010 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45011 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 |
45012 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45013 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45014 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 |
45015 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45016 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45017 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 |
45018 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45019 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45020 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 |
45021 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45022 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45023 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 |
45024 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45025 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45026 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 |
45027 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45028 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45029 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 |
45030 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45031 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45032 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 |
45033 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45034 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45035 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 |
45036 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45037 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45038 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 |
45039 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45040 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45041 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 |
45042 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45043 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45044 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 |
45045 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45046 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45047 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 |
45048 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45049 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45050 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 |
45051 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45052 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45053 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 |
45054 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45055 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45056 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 |
45057 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45058 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45059 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 |
45060 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45061 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45062 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 |
45063 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45064 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45065 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 |
45066 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45067 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45068 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 |
45069 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45070 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45071 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 |
45072 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45073 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45074 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 |
45075 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45076 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45077 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 |
45078 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45079 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45080 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 |
45081 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45082 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45083 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 |
45084 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45085 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45086 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 |
45087 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45088 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45089 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 |
45090 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45091 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45092 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 |
45093 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45094 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45095 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 |
45096 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45097 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45098 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 |
45099 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45100 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45101 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 |
45102 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45103 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45104 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 |
45105 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45106 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45107 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 |
45108 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45109 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45110 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 |
45111 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45112 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45113 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 |
45114 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45115 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45116 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 |
45117 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45118 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45119 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 |
45120 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45121 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45122 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 |
45123 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45124 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45125 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 |
45126 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45127 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45128 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 |
45129 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45130 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45131 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 |
45132 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45133 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45134 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 |
45135 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45136 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45137 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 |
45138 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45139 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45140 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 |
45141 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45142 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45143 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 |
45144 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45145 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45146 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 |
45147 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45148 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45149 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 |
45150 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45151 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45152 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 |
45153 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45154 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45155 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 |
45156 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45157 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45158 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 |
45159 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45160 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45161 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 |
45162 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45163 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45164 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 |
45165 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45166 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45167 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 |
45168 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45169 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45170 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 |
45171 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45172 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45173 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 |
45174 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45175 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45176 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 |
45177 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45178 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45179 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 |
45180 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45181 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45182 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 |
45183 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45184 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45185 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 |
45186 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45187 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45188 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 |
45189 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45190 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45191 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 |
45192 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45193 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45194 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 |
45195 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45196 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45197 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 |
45198 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45199 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45200 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 |
45201 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45202 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45203 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 |
45204 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45205 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45206 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 |
45207 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45208 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45209 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 |
45210 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45211 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45212 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 |
45213 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45214 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45215 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 |
45216 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45217 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45218 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 |
45219 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45220 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45221 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 |
45222 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45223 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45224 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 |
45225 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45226 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45227 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 |
45228 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45229 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45230 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 |
45231 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45232 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45233 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 |
45234 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45235 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45236 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 |
45237 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45238 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45239 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 |
45240 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45241 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45242 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 |
45243 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45244 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45245 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 |
45246 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45247 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45248 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 |
45249 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45250 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45251 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 |
45252 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45253 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45254 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 |
45255 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45256 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45257 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 |
45258 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45259 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45260 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 |
45261 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45262 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45263 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 |
45264 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45265 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45266 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 |
45267 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45268 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45269 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 |
45270 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45271 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45272 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 |
45273 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45274 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45275 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 |
45276 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45277 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45278 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 |
45279 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45280 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45281 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 |
45282 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45283 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45284 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 |
45285 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45286 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45287 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 |
45288 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45289 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45290 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 |
45291 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45292 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45293 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 |
45294 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45295 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45296 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 |
45297 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45298 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45299 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 |
45300 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45301 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45302 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 |
45303 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45304 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45305 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 |
45306 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45307 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45308 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 |
45309 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45310 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45311 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 |
45312 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45313 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45314 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 |
45315 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45316 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45317 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 |
45318 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45319 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45320 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 |
45321 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45322 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45323 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 |
45324 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45325 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45326 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 |
45327 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45328 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45329 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 |
45330 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45331 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45332 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 |
45333 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45334 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45335 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 |
45336 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45337 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45338 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 |
45339 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45340 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45341 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 |
45342 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45343 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45344 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 |
45345 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45346 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45347 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 |
45348 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45349 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45350 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 |
45351 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45352 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45353 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 |
45354 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45355 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45356 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 |
45357 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45358 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45359 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 |
45360 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45361 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45362 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 |
45363 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45364 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45365 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 |
45366 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45367 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45368 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 |
45369 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45370 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45371 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 |
45372 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45373 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45374 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 |
45375 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45376 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45377 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 |
45378 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45379 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45380 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 |
45381 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45382 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45383 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 |
45384 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45385 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45386 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 |
45387 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45388 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45389 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 |
45390 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45391 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45392 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 |
45393 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45394 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45395 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 |
45396 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45397 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45398 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 |
45399 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45400 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45401 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 |
45402 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45403 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45404 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 |
45405 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45406 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45407 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 |
45408 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45409 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45410 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 |
45411 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45412 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45413 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 |
45414 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45415 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45416 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 |
45417 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45418 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45419 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 |
45420 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45421 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45422 | //DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 |
45423 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 |
45424 | #define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
45425 | |
45426 | |
45427 | // addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec |
45428 | //DC_COMBOPHYCMREGS3_COMMON_FUSE1 |
45429 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 |
45430 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0__SHIFT 0x1 |
45431 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val__SHIFT 0x3 |
45432 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1__SHIFT 0x9 |
45433 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0xa |
45434 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2__SHIFT 0xc |
45435 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val__SHIFT 0xd |
45436 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3__SHIFT 0x13 |
45437 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0x14 |
45438 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en__SHIFT 0x16 |
45439 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare__SHIFT 0x17 |
45440 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_valid_MASK 0x00000001L |
45441 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated0_MASK 0x00000006L |
45442 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_override_val_MASK 0x000001F8L |
45443 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated1_MASK 0x00000200L |
45444 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x00000C00L |
45445 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated2_MASK 0x00001000L |
45446 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_override_val_MASK 0x0007E000L |
45447 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_unpopulated3_MASK 0x00080000L |
45448 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x00300000L |
45449 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_refresh_cal_en_MASK 0x00400000L |
45450 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE1__fuse1_spare_MASK 0xFF800000L |
45451 | //DC_COMBOPHYCMREGS3_COMMON_FUSE2 |
45452 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 |
45453 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated__SHIFT 0x1 |
45454 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr__SHIFT 0x9 |
45455 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare__SHIFT 0xe |
45456 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_valid_MASK 0x00000001L |
45457 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_unpopulated_MASK 0x000001FEL |
45458 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_tx_fifo_ptr_MASK 0x00003E00L |
45459 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE2__fuse2_spare_MASK 0xFFFFC000L |
45460 | //DC_COMBOPHYCMREGS3_COMMON_FUSE3 |
45461 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 |
45462 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated__SHIFT 0x1 |
45463 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel__SHIFT 0xa |
45464 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel__SHIFT 0xd |
45465 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer__SHIFT 0x10 |
45466 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz__SHIFT 0x12 |
45467 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val__SHIFT 0x14 |
45468 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel__SHIFT 0x15 |
45469 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight__SHIFT 0x16 |
45470 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio__SHIFT 0x1a |
45471 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d |
45472 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_valid_MASK 0x00000001L |
45473 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_unpopulated_MASK 0x000003FEL |
45474 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_ei_det_thresh_sel_MASK 0x00001C00L |
45475 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_dac_safeval_sel_MASK 0x0000E000L |
45476 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_freq_lock_timer_MASK 0x00030000L |
45477 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cal_dac_stpsz_MASK 0x000C0000L |
45478 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_byp_init_val_MASK 0x00100000L |
45479 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_icostart_sel_MASK 0x00200000L |
45480 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_bbweight_MASK 0x03C00000L |
45481 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__cdr_cur_mirr_ratio_MASK 0x1C000000L |
45482 | #define DC_COMBOPHYCMREGS3_COMMON_FUSE3__fuse3_spare_MASK 0xE0000000L |
45483 | //DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM |
45484 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 |
45485 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 |
45486 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 |
45487 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 |
45488 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0x000000FFL |
45489 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0x0000FF00L |
45490 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0x00FF0000L |
45491 | #define DC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xFF000000L |
45492 | //DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT |
45493 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 |
45494 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 |
45495 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en__SHIFT 0xb |
45496 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgdelay_MASK 0x0000000FL |
45497 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__pgmask_MASK 0x000003F0L |
45498 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT__vprot_en_MASK 0x00000800L |
45499 | //DC_COMBOPHYCMREGS3_COMMON_TXCNTRL |
45500 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3__SHIFT 0x0 |
45501 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis__SHIFT 0x5 |
45502 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1__SHIFT 0x6 |
45503 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2__SHIFT 0x9 |
45504 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3__SHIFT 0xc |
45505 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__rdptr_rst_val_gen3_MASK 0x0000001FL |
45506 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__clkgate_dis_MASK 0x00000020L |
45507 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen1_MASK 0x000001C0L |
45508 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen2_MASK 0x00000E00L |
45509 | #define DC_COMBOPHYCMREGS3_COMMON_TXCNTRL__slew_rate_ctl_gen3_MASK 0x00007000L |
45510 | //DC_COMBOPHYCMREGS3_COMMON_TMDP |
45511 | #define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare__SHIFT 0x0 |
45512 | #define DC_COMBOPHYCMREGS3_COMMON_TMDP__tmdp_spare_MASK 0xFFFFFFFFL |
45513 | //DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS |
45514 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l__SHIFT 0x0 |
45515 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l__SHIFT 0x1 |
45516 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l__SHIFT 0x2 |
45517 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l__SHIFT 0x3 |
45518 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l__SHIFT 0x4 |
45519 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l__SHIFT 0x5 |
45520 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l__SHIFT 0x6 |
45521 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l__SHIFT 0x7 |
45522 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_0_reset_l_MASK 0x00000001L |
45523 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_1_reset_l_MASK 0x00000002L |
45524 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_2_reset_l_MASK 0x00000004L |
45525 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_3_reset_l_MASK 0x00000008L |
45526 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_4_reset_l_MASK 0x00000010L |
45527 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_5_reset_l_MASK 0x00000020L |
45528 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_6_reset_l_MASK 0x00000040L |
45529 | #define DC_COMBOPHYCMREGS3_COMMON_LANE_RESETS__lane_7_reset_l_MASK 0x00000080L |
45530 | //DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL |
45531 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override__SHIFT 0x0 |
45532 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val__SHIFT 0x1 |
45533 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val__SHIFT 0x6 |
45534 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms__SHIFT 0x15 |
45535 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__zcalcode_override_MASK 0x00000001L |
45536 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_binary_code_override_val_MASK 0x0000003EL |
45537 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__rx_therm_code_override_val_MASK 0x001FFFC0L |
45538 | #define DC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL__tx_driver_fifty_ohms_MASK 0x00200000L |
45539 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 |
45540 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1__SHIFT 0x0 |
45541 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU1__rfu_value1_MASK 0xFFFFFFFFL |
45542 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 |
45543 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2__SHIFT 0x0 |
45544 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU2__rfu_value2_MASK 0xFFFFFFFFL |
45545 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 |
45546 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3__SHIFT 0x0 |
45547 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU3__rfu_value3_MASK 0xFFFFFFFFL |
45548 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 |
45549 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4__SHIFT 0x0 |
45550 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU4__rfu_value4_MASK 0xFFFFFFFFL |
45551 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 |
45552 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5__SHIFT 0x0 |
45553 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU5__rfu_value5_MASK 0xFFFFFFFFL |
45554 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 |
45555 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6__SHIFT 0x0 |
45556 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU6__rfu_value6_MASK 0xFFFFFFFFL |
45557 | //DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 |
45558 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7__SHIFT 0x0 |
45559 | #define DC_COMBOPHYCMREGS3_COMMON_DISP_RFU7__rfu_value7_MASK 0xFFFFFFFFL |
45560 | |
45561 | |
45562 | // addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec |
45563 | //DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 |
45564 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 |
45565 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 |
45566 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy__SHIFT 0x8 |
45567 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x00000007L |
45568 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x00000018L |
45569 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0__tx_rdy_MASK 0x00000100L |
45570 | //DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 |
45571 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel__SHIFT 0x0 |
45572 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel__SHIFT 0x3 |
45573 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en__SHIFT 0x5 |
45574 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__txmarg_sel_MASK 0x00000007L |
45575 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__deemph_sel_MASK 0x00000018L |
45576 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0__tx_margin_en_MASK 0x00000020L |
45577 | //DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 |
45578 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x1 |
45579 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x3 |
45580 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 |
45581 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate__SHIFT 0x8 |
45582 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq__SHIFT 0xa |
45583 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken__SHIFT 0xc |
45584 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone__SHIFT 0xd |
45585 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on__SHIFT 0xe |
45586 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en__SHIFT 0xf |
45587 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj__SHIFT 0x10 |
45588 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en__SHIFT 0x14 |
45589 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset__SHIFT 0x16 |
45590 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x00000006L |
45591 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x00000018L |
45592 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0x000000E0L |
45593 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__max_linkrate_MASK 0x00000300L |
45594 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_freq_MASK 0x00000C00L |
45595 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clken_MASK 0x00001000L |
45596 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pcs_clkdone_MASK 0x00002000L |
45597 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__pll1_always_on_MASK 0x00004000L |
45598 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__rdclk_div2_en_MASK 0x00008000L |
45599 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_adj_MASK 0x000F0000L |
45600 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_boost_en_MASK 0x00100000L |
45601 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0__tx_binary_ron_code_offset_MASK 0x00C00000L |
45602 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 |
45603 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0__SHIFT 0x0 |
45604 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0__rfu_value0_MASK 0xFFFFFFFFL |
45605 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 |
45606 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1__SHIFT 0x0 |
45607 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0__rfu_value1_MASK 0xFFFFFFFFL |
45608 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 |
45609 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2__SHIFT 0x0 |
45610 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0__rfu_value2_MASK 0xFFFFFFFFL |
45611 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 |
45612 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3__SHIFT 0x0 |
45613 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0__rfu_value3_MASK 0xFFFFFFFFL |
45614 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 |
45615 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4__SHIFT 0x0 |
45616 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0__rfu_value4_MASK 0xFFFFFFFFL |
45617 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 |
45618 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5__SHIFT 0x0 |
45619 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0__rfu_value5_MASK 0xFFFFFFFFL |
45620 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 |
45621 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6__SHIFT 0x0 |
45622 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0__rfu_value6_MASK 0xFFFFFFFFL |
45623 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 |
45624 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7__SHIFT 0x0 |
45625 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0__rfu_value7_MASK 0xFFFFFFFFL |
45626 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 |
45627 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8__SHIFT 0x0 |
45628 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0__rfu_value8_MASK 0xFFFFFFFFL |
45629 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 |
45630 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9__SHIFT 0x0 |
45631 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0__rfu_value9_MASK 0xFFFFFFFFL |
45632 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 |
45633 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10__SHIFT 0x0 |
45634 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0__rfu_value10_MASK 0xFFFFFFFFL |
45635 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 |
45636 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11__SHIFT 0x0 |
45637 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0__rfu_value11_MASK 0xFFFFFFFFL |
45638 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 |
45639 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12__SHIFT 0x0 |
45640 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0__rfu_value12_MASK 0xFFFFFFFFL |
45641 | //DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 |
45642 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 |
45643 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 |
45644 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy__SHIFT 0x8 |
45645 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x00000007L |
45646 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x00000018L |
45647 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1__tx_rdy_MASK 0x00000100L |
45648 | //DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 |
45649 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel__SHIFT 0x0 |
45650 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel__SHIFT 0x3 |
45651 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en__SHIFT 0x5 |
45652 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__txmarg_sel_MASK 0x00000007L |
45653 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__deemph_sel_MASK 0x00000018L |
45654 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1__tx_margin_en_MASK 0x00000020L |
45655 | //DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 |
45656 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x1 |
45657 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x3 |
45658 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 |
45659 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate__SHIFT 0x8 |
45660 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq__SHIFT 0xa |
45661 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken__SHIFT 0xc |
45662 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone__SHIFT 0xd |
45663 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on__SHIFT 0xe |
45664 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en__SHIFT 0xf |
45665 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj__SHIFT 0x10 |
45666 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en__SHIFT 0x14 |
45667 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset__SHIFT 0x16 |
45668 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x00000006L |
45669 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x00000018L |
45670 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0x000000E0L |
45671 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__max_linkrate_MASK 0x00000300L |
45672 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_freq_MASK 0x00000C00L |
45673 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clken_MASK 0x00001000L |
45674 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pcs_clkdone_MASK 0x00002000L |
45675 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__pll1_always_on_MASK 0x00004000L |
45676 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__rdclk_div2_en_MASK 0x00008000L |
45677 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_adj_MASK 0x000F0000L |
45678 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_boost_en_MASK 0x00100000L |
45679 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1__tx_binary_ron_code_offset_MASK 0x00C00000L |
45680 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 |
45681 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0__SHIFT 0x0 |
45682 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1__rfu_value0_MASK 0xFFFFFFFFL |
45683 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 |
45684 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1__SHIFT 0x0 |
45685 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1__rfu_value1_MASK 0xFFFFFFFFL |
45686 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 |
45687 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2__SHIFT 0x0 |
45688 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1__rfu_value2_MASK 0xFFFFFFFFL |
45689 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 |
45690 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3__SHIFT 0x0 |
45691 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1__rfu_value3_MASK 0xFFFFFFFFL |
45692 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 |
45693 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4__SHIFT 0x0 |
45694 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1__rfu_value4_MASK 0xFFFFFFFFL |
45695 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 |
45696 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5__SHIFT 0x0 |
45697 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1__rfu_value5_MASK 0xFFFFFFFFL |
45698 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 |
45699 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6__SHIFT 0x0 |
45700 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1__rfu_value6_MASK 0xFFFFFFFFL |
45701 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 |
45702 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7__SHIFT 0x0 |
45703 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1__rfu_value7_MASK 0xFFFFFFFFL |
45704 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 |
45705 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8__SHIFT 0x0 |
45706 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1__rfu_value8_MASK 0xFFFFFFFFL |
45707 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 |
45708 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9__SHIFT 0x0 |
45709 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1__rfu_value9_MASK 0xFFFFFFFFL |
45710 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 |
45711 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10__SHIFT 0x0 |
45712 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1__rfu_value10_MASK 0xFFFFFFFFL |
45713 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 |
45714 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11__SHIFT 0x0 |
45715 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1__rfu_value11_MASK 0xFFFFFFFFL |
45716 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 |
45717 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12__SHIFT 0x0 |
45718 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1__rfu_value12_MASK 0xFFFFFFFFL |
45719 | //DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 |
45720 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 |
45721 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 |
45722 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy__SHIFT 0x8 |
45723 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x00000007L |
45724 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x00000018L |
45725 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2__tx_rdy_MASK 0x00000100L |
45726 | //DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 |
45727 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel__SHIFT 0x0 |
45728 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel__SHIFT 0x3 |
45729 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en__SHIFT 0x5 |
45730 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__txmarg_sel_MASK 0x00000007L |
45731 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__deemph_sel_MASK 0x00000018L |
45732 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2__tx_margin_en_MASK 0x00000020L |
45733 | //DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 |
45734 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x1 |
45735 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x3 |
45736 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 |
45737 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate__SHIFT 0x8 |
45738 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq__SHIFT 0xa |
45739 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken__SHIFT 0xc |
45740 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone__SHIFT 0xd |
45741 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on__SHIFT 0xe |
45742 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en__SHIFT 0xf |
45743 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj__SHIFT 0x10 |
45744 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en__SHIFT 0x14 |
45745 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset__SHIFT 0x16 |
45746 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x00000006L |
45747 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x00000018L |
45748 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0x000000E0L |
45749 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__max_linkrate_MASK 0x00000300L |
45750 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_freq_MASK 0x00000C00L |
45751 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clken_MASK 0x00001000L |
45752 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pcs_clkdone_MASK 0x00002000L |
45753 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__pll1_always_on_MASK 0x00004000L |
45754 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__rdclk_div2_en_MASK 0x00008000L |
45755 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_adj_MASK 0x000F0000L |
45756 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_boost_en_MASK 0x00100000L |
45757 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2__tx_binary_ron_code_offset_MASK 0x00C00000L |
45758 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 |
45759 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0__SHIFT 0x0 |
45760 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2__rfu_value0_MASK 0xFFFFFFFFL |
45761 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 |
45762 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1__SHIFT 0x0 |
45763 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2__rfu_value1_MASK 0xFFFFFFFFL |
45764 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 |
45765 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2__SHIFT 0x0 |
45766 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2__rfu_value2_MASK 0xFFFFFFFFL |
45767 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 |
45768 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3__SHIFT 0x0 |
45769 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2__rfu_value3_MASK 0xFFFFFFFFL |
45770 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 |
45771 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4__SHIFT 0x0 |
45772 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2__rfu_value4_MASK 0xFFFFFFFFL |
45773 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 |
45774 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5__SHIFT 0x0 |
45775 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2__rfu_value5_MASK 0xFFFFFFFFL |
45776 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 |
45777 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6__SHIFT 0x0 |
45778 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2__rfu_value6_MASK 0xFFFFFFFFL |
45779 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 |
45780 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7__SHIFT 0x0 |
45781 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2__rfu_value7_MASK 0xFFFFFFFFL |
45782 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 |
45783 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8__SHIFT 0x0 |
45784 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2__rfu_value8_MASK 0xFFFFFFFFL |
45785 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 |
45786 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9__SHIFT 0x0 |
45787 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2__rfu_value9_MASK 0xFFFFFFFFL |
45788 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 |
45789 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10__SHIFT 0x0 |
45790 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2__rfu_value10_MASK 0xFFFFFFFFL |
45791 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 |
45792 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11__SHIFT 0x0 |
45793 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2__rfu_value11_MASK 0xFFFFFFFFL |
45794 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 |
45795 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12__SHIFT 0x0 |
45796 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2__rfu_value12_MASK 0xFFFFFFFFL |
45797 | //DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 |
45798 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 |
45799 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 |
45800 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy__SHIFT 0x8 |
45801 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x00000007L |
45802 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x00000018L |
45803 | #define DC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3__tx_rdy_MASK 0x00000100L |
45804 | //DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 |
45805 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel__SHIFT 0x0 |
45806 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel__SHIFT 0x3 |
45807 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en__SHIFT 0x5 |
45808 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__txmarg_sel_MASK 0x00000007L |
45809 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__deemph_sel_MASK 0x00000018L |
45810 | #define DC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3__tx_margin_en_MASK 0x00000020L |
45811 | //DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 |
45812 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x1 |
45813 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x3 |
45814 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 |
45815 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate__SHIFT 0x8 |
45816 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq__SHIFT 0xa |
45817 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken__SHIFT 0xc |
45818 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone__SHIFT 0xd |
45819 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on__SHIFT 0xe |
45820 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en__SHIFT 0xf |
45821 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj__SHIFT 0x10 |
45822 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en__SHIFT 0x14 |
45823 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset__SHIFT 0x16 |
45824 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x00000006L |
45825 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x00000018L |
45826 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0x000000E0L |
45827 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__max_linkrate_MASK 0x00000300L |
45828 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_freq_MASK 0x00000C00L |
45829 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clken_MASK 0x00001000L |
45830 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pcs_clkdone_MASK 0x00002000L |
45831 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__pll1_always_on_MASK 0x00004000L |
45832 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__rdclk_div2_en_MASK 0x00008000L |
45833 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_adj_MASK 0x000F0000L |
45834 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_boost_en_MASK 0x00100000L |
45835 | #define DC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3__tx_binary_ron_code_offset_MASK 0x00C00000L |
45836 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 |
45837 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0__SHIFT 0x0 |
45838 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3__rfu_value0_MASK 0xFFFFFFFFL |
45839 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 |
45840 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1__SHIFT 0x0 |
45841 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3__rfu_value1_MASK 0xFFFFFFFFL |
45842 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 |
45843 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2__SHIFT 0x0 |
45844 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3__rfu_value2_MASK 0xFFFFFFFFL |
45845 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 |
45846 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3__SHIFT 0x0 |
45847 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3__rfu_value3_MASK 0xFFFFFFFFL |
45848 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 |
45849 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4__SHIFT 0x0 |
45850 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3__rfu_value4_MASK 0xFFFFFFFFL |
45851 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 |
45852 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5__SHIFT 0x0 |
45853 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3__rfu_value5_MASK 0xFFFFFFFFL |
45854 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 |
45855 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6__SHIFT 0x0 |
45856 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3__rfu_value6_MASK 0xFFFFFFFFL |
45857 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 |
45858 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7__SHIFT 0x0 |
45859 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3__rfu_value7_MASK 0xFFFFFFFFL |
45860 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 |
45861 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8__SHIFT 0x0 |
45862 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3__rfu_value8_MASK 0xFFFFFFFFL |
45863 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 |
45864 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9__SHIFT 0x0 |
45865 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3__rfu_value9_MASK 0xFFFFFFFFL |
45866 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 |
45867 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10__SHIFT 0x0 |
45868 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3__rfu_value10_MASK 0xFFFFFFFFL |
45869 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 |
45870 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11__SHIFT 0x0 |
45871 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3__rfu_value11_MASK 0xFFFFFFFFL |
45872 | //DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 |
45873 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12__SHIFT 0x0 |
45874 | #define DC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3__rfu_value12_MASK 0xFFFFFFFFL |
45875 | |
45876 | |
45877 | // addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec |
45878 | //DC_COMBOPHYPLLREGS3_FREQ_CTRL0 |
45879 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac__SHIFT 0x0 |
45880 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int__SHIFT 0x10 |
45881 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_frac_MASK 0x0000FFFFL |
45882 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL0__fcw0_int_MASK 0x01FF0000L |
45883 | //DC_COMBOPHYPLLREGS3_FREQ_CTRL1 |
45884 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac__SHIFT 0x0 |
45885 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int__SHIFT 0x10 |
45886 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_frac_MASK 0x0000FFFFL |
45887 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL1__fcw1_int_MASK 0x01FF0000L |
45888 | //DC_COMBOPHYPLLREGS3_FREQ_CTRL2 |
45889 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom__SHIFT 0x0 |
45890 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac__SHIFT 0x10 |
45891 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_denom_MASK 0x0000FFFFL |
45892 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL2__fcw_slew_frac_MASK 0xFFFF0000L |
45893 | //DC_COMBOPHYPLLREGS3_FREQ_CTRL3 |
45894 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div__SHIFT 0x0 |
45895 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div__SHIFT 0x3 |
45896 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en__SHIFT 0x6 |
45897 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en__SHIFT 0x8 |
45898 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel__SHIFT 0xa |
45899 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en__SHIFT 0xc |
45900 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution__SHIFT 0x10 |
45901 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1__SHIFT 0x18 |
45902 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__refclk_div_MASK 0x00000003L |
45903 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__vco_pre_div_MASK 0x00000018L |
45904 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fracn_en_MASK 0x00000040L |
45905 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__ssc_en_MASK 0x00000100L |
45906 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__fcw_sel_MASK 0x00000400L |
45907 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__freq_jump_en_MASK 0x00001000L |
45908 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__tdc_resolution_MASK 0x00FF0000L |
45909 | #define DC_COMBOPHYPLLREGS3_FREQ_CTRL3__dpll_cfg_1_MASK 0xFF000000L |
45910 | //DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE |
45911 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant__SHIFT 0x0 |
45912 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp__SHIFT 0x2 |
45913 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant__SHIFT 0x7 |
45914 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp__SHIFT 0xc |
45915 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res__SHIFT 0x11 |
45916 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res__SHIFT 0x18 |
45917 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_mant_MASK 0x00000003L |
45918 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gi_coarse_exp_MASK 0x0000003CL |
45919 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_mant_MASK 0x00000780L |
45920 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__gp_coarse_exp_MASK 0x0000F000L |
45921 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_res_MASK 0x007E0000L |
45922 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_COARSE__nctl_coarse_frac_res_MASK 0x03000000L |
45923 | //DC_COMBOPHYPLLREGS3_BW_CTRL_FINE |
45924 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3__SHIFT 0x0 |
45925 | #define DC_COMBOPHYPLLREGS3_BW_CTRL_FINE__dpll_cfg_3_MASK 0x000003FFL |
45926 | //DC_COMBOPHYPLLREGS3_CAL_CTRL |
45927 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock__SHIFT 0x0 |
45928 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en__SHIFT 0x1 |
45929 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl__SHIFT 0x3 |
45930 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel__SHIFT 0x9 |
45931 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis__SHIFT 0xb |
45932 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio__SHIFT 0xd |
45933 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis__SHIFT 0x16 |
45934 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis__SHIFT 0x17 |
45935 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate__SHIFT 0x18 |
45936 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__bypass_freq_lock_MASK 0x00000001L |
45937 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_en_MASK 0x00000002L |
45938 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__tdc_cal_ctrl_MASK 0x000001F8L |
45939 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__meas_win_sel_MASK 0x00000600L |
45940 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_cal_dis_MASK 0x00000800L |
45941 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_ratio_MASK 0x001FE000L |
45942 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__kdco_incr_cal_dis_MASK 0x00400000L |
45943 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__nctl_adj_dis_MASK 0x00800000L |
45944 | #define DC_COMBOPHYPLLREGS3_CAL_CTRL__refclk_rate_MASK 0xFF000000L |
45945 | //DC_COMBOPHYPLLREGS3_LOOP_CTRL |
45946 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en__SHIFT 0x0 |
45947 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis__SHIFT 0x2 |
45948 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel__SHIFT 0x4 |
45949 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel__SHIFT 0x7 |
45950 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel__SHIFT 0xa |
45951 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis__SHIFT 0xc |
45952 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk__SHIFT 0xe |
45953 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en__SHIFT 0x10 |
45954 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en__SHIFT 0x12 |
45955 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset__SHIFT 0x14 |
45956 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbdiv_mask_en_MASK 0x00000001L |
45957 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fb_slip_dis_MASK 0x00000004L |
45958 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_tdc_sel_MASK 0x00000030L |
45959 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__clk_nctl_sel_MASK 0x00000180L |
45960 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__sig_del_patt_sel_MASK 0x00000400L |
45961 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__nctl_sig_del_dis_MASK 0x00001000L |
45962 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__fbclk_track_refclk_MASK 0x00004000L |
45963 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__prbs_en_MASK 0x00010000L |
45964 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__tdc_clk_gate_en_MASK 0x00040000L |
45965 | #define DC_COMBOPHYPLLREGS3_LOOP_CTRL__phase_offset_MASK 0x07F00000L |
45966 | //DC_COMBOPHYPLLREGS3_VREG_CFG |
45967 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac__SHIFT 0x0 |
45968 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en__SHIFT 0x1 |
45969 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2__SHIFT 0x2 |
45970 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel__SHIFT 0x3 |
45971 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode__SHIFT 0x5 |
45972 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel__SHIFT 0x7 |
45973 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi__SHIFT 0xb |
45974 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo__SHIFT 0xc |
45975 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver__SHIFT 0xd |
45976 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump__SHIFT 0xf |
45977 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x__SHIFT 0x10 |
45978 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x__SHIFT 0x11 |
45979 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on__SHIFT 0x12 |
45980 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2__SHIFT 0x14 |
45981 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_ac_MASK 0x00000001L |
45982 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__bleeder_en_MASK 0x00000002L |
45983 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__is_1p2_MASK 0x00000004L |
45984 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_obs_sel_MASK 0x00000018L |
45985 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_on_mode_MASK 0x00000060L |
45986 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__rlad_tap_sel_MASK 0x00000780L |
45987 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_hi_MASK 0x00000800L |
45988 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__reg_off_lo_MASK 0x00001000L |
45989 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__scale_driver_MASK 0x00006000L |
45990 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_bump_MASK 0x00008000L |
45991 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__sel_rladder_x_MASK 0x00010000L |
45992 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__short_rc_filt_x_MASK 0x00020000L |
45993 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__vref_pwr_on_MASK 0x00040000L |
45994 | #define DC_COMBOPHYPLLREGS3_VREG_CFG__dpll_cfg_2_MASK 0x0FF00000L |
45995 | //DC_COMBOPHYPLLREGS3_OBSERVE0 |
45996 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps__SHIFT 0x0 |
45997 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock__SHIFT 0x6 |
45998 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis__SHIFT 0x8 |
45999 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg__SHIFT 0xa |
46000 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel__SHIFT 0x15 |
46001 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_tdc_steps_MASK 0x0000001FL |
46002 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__clear_sticky_lock_MASK 0x00000040L |
46003 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__lock_det_dis_MASK 0x00000100L |
46004 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__dco_cfg_MASK 0x0003FC00L |
46005 | #define DC_COMBOPHYPLLREGS3_OBSERVE0__anaobs_sel_MASK 0x00E00000L |
46006 | //DC_COMBOPHYPLLREGS3_OBSERVE1 |
46007 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel__SHIFT 0x0 |
46008 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel__SHIFT 0x5 |
46009 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div__SHIFT 0xa |
46010 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div__SHIFT 0xd |
46011 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer__SHIFT 0x10 |
46012 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_sel_MASK 0x0000000FL |
46013 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_sel_MASK 0x000001E0L |
46014 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_div_MASK 0x00000C00L |
46015 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__digobs_trig_div_MASK 0x00006000L |
46016 | #define DC_COMBOPHYPLLREGS3_OBSERVE1__lock_timer_MASK 0x3FFF0000L |
46017 | //DC_COMBOPHYPLLREGS3_DFT_OUT |
46018 | #define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data__SHIFT 0x0 |
46019 | #define DC_COMBOPHYPLLREGS3_DFT_OUT__dft_data_MASK 0xFFFFFFFFL |
46020 | //DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 |
46021 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT 0x0 |
46022 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK 0x00000003L |
46023 | //DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL |
46024 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT 0x0 |
46025 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT 0x1 |
46026 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT 0x2 |
46027 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT 0x5 |
46028 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT 0x8 |
46029 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT 0xa |
46030 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT 0xd |
46031 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT 0xe |
46032 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT 0xf |
46033 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT 0x10 |
46034 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT 0x11 |
46035 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK 0x00000001L |
46036 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK 0x00000002L |
46037 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK 0x0000000CL |
46038 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK 0x000000E0L |
46039 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK 0x00000100L |
46040 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK 0x00000400L |
46041 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK 0x00002000L |
46042 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK 0x00004000L |
46043 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK 0x00008000L |
46044 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK 0x00010000L |
46045 | #define DC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK 0x000E0000L |
46046 | |
46047 | |
46048 | // addressBlock: dce_dc_dcio_dcio_zcal_dispdec |
46049 | //ZCAL_MACRO_CNTL_RESERVED0 |
46050 | #define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
46051 | #define ZCAL_MACRO_CNTL_RESERVED0__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
46052 | //ZCAL_MACRO_CNTL_RESERVED1 |
46053 | #define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
46054 | #define ZCAL_MACRO_CNTL_RESERVED1__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
46055 | //ZCAL_MACRO_CNTL_RESERVED2 |
46056 | #define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
46057 | #define ZCAL_MACRO_CNTL_RESERVED2__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
46058 | //ZCAL_MACRO_CNTL_RESERVED3 |
46059 | #define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
46060 | #define ZCAL_MACRO_CNTL_RESERVED3__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
46061 | //ZCAL_MACRO_CNTL_RESERVED4 |
46062 | #define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED__SHIFT 0x0 |
46063 | #define ZCAL_MACRO_CNTL_RESERVED4__ZCAL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL |
46064 | |
46065 | |
46066 | // addressBlock: dce_dc_zcal_dc_zcalregs_dispdec |
46067 | //COMP_EN_CTL |
46068 | #define COMP_EN_CTL__comp_en__SHIFT 0x0 |
46069 | #define COMP_EN_CTL__comp_en_override__SHIFT 0x2 |
46070 | #define COMP_EN_CTL__comp_done__SHIFT 0x4 |
46071 | #define COMP_EN_CTL__zcal_code_override__SHIFT 0x6 |
46072 | #define COMP_EN_CTL__zcal_cal_rtt__SHIFT 0x7 |
46073 | #define COMP_EN_CTL__zcal_base_en__SHIFT 0x8 |
46074 | #define COMP_EN_CTL__zcal_ht_rtt_sel__SHIFT 0x9 |
46075 | #define COMP_EN_CTL__zcal_code__SHIFT 0xa |
46076 | #define COMP_EN_CTL__zcal_ron_cal_mode__SHIFT 0x10 |
46077 | #define COMP_EN_CTL__zcal_ana_dbg_sel__SHIFT 0x11 |
46078 | #define COMP_EN_CTL__cfg_cml_cmos_sel__SHIFT 0x13 |
46079 | #define COMP_EN_CTL__dsm_sel__SHIFT 0x14 |
46080 | #define COMP_EN_CTL__comp_en_MASK 0x00000001L |
46081 | #define COMP_EN_CTL__comp_en_override_MASK 0x00000004L |
46082 | #define COMP_EN_CTL__comp_done_MASK 0x00000010L |
46083 | #define COMP_EN_CTL__zcal_code_override_MASK 0x00000040L |
46084 | #define COMP_EN_CTL__zcal_cal_rtt_MASK 0x00000080L |
46085 | #define COMP_EN_CTL__zcal_base_en_MASK 0x00000100L |
46086 | #define COMP_EN_CTL__zcal_ht_rtt_sel_MASK 0x00000200L |
46087 | #define COMP_EN_CTL__zcal_code_MASK 0x00007C00L |
46088 | #define COMP_EN_CTL__zcal_ron_cal_mode_MASK 0x00010000L |
46089 | #define COMP_EN_CTL__zcal_ana_dbg_sel_MASK 0x00060000L |
46090 | #define COMP_EN_CTL__cfg_cml_cmos_sel_MASK 0x00080000L |
46091 | #define COMP_EN_CTL__dsm_sel_MASK 0x00F00000L |
46092 | //COMP_EN_DFX |
46093 | #define COMP_EN_DFX__autocal_ron_code__SHIFT 0x0 |
46094 | #define COMP_EN_DFX__autocal_rtt_code__SHIFT 0x5 |
46095 | #define COMP_EN_DFX__pre_fused_ron_code__SHIFT 0xb |
46096 | #define COMP_EN_DFX__pre_fused_rtt_code__SHIFT 0x10 |
46097 | #define COMP_EN_DFX__broadcast_ron_code__SHIFT 0x16 |
46098 | #define COMP_EN_DFX__broadcast_rtt_code__SHIFT 0x1b |
46099 | #define COMP_EN_DFX__autocal_ron_code_MASK 0x0000001FL |
46100 | #define COMP_EN_DFX__autocal_rtt_code_MASK 0x000003E0L |
46101 | #define COMP_EN_DFX__pre_fused_ron_code_MASK 0x0000F800L |
46102 | #define COMP_EN_DFX__pre_fused_rtt_code_MASK 0x001F0000L |
46103 | #define COMP_EN_DFX__broadcast_ron_code_MASK 0x07C00000L |
46104 | #define COMP_EN_DFX__broadcast_rtt_code_MASK 0xF8000000L |
46105 | //ZCAL_FUSES |
46106 | #define ZCAL_FUSES__fuse_valid__SHIFT 0x0 |
46107 | #define ZCAL_FUSES__fuse_ron_override_val__SHIFT 0x3 |
46108 | #define ZCAL_FUSES__fuse_ron_ctl__SHIFT 0xa |
46109 | #define ZCAL_FUSES__fuse_rtt_override_val__SHIFT 0xd |
46110 | #define ZCAL_FUSES__fuse_rtt_ctl__SHIFT 0x14 |
46111 | #define ZCAL_FUSES__fuse_refresh_cal_en__SHIFT 0x16 |
46112 | #define ZCAL_FUSES__fuse_spare__SHIFT 0x17 |
46113 | #define ZCAL_FUSES__fuse_valid_MASK 0x00000001L |
46114 | #define ZCAL_FUSES__fuse_ron_override_val_MASK 0x000001F8L |
46115 | #define ZCAL_FUSES__fuse_ron_ctl_MASK 0x00000C00L |
46116 | #define ZCAL_FUSES__fuse_rtt_override_val_MASK 0x0007E000L |
46117 | #define ZCAL_FUSES__fuse_rtt_ctl_MASK 0x00300000L |
46118 | #define ZCAL_FUSES__fuse_refresh_cal_en_MASK 0x00400000L |
46119 | #define ZCAL_FUSES__fuse_spare_MASK 0xFF800000L |
46120 | |
46121 | |
46122 | // addressBlock: vga_vgaseqind |
46123 | //SEQ00 |
46124 | #define SEQ00__SEQ_RST0B__SHIFT 0x0 |
46125 | #define SEQ00__SEQ_RST1B__SHIFT 0x1 |
46126 | #define SEQ00__SEQ_RST0B_MASK 0x01L |
46127 | #define SEQ00__SEQ_RST1B_MASK 0x02L |
46128 | //SEQ01 |
46129 | #define SEQ01__SEQ_DOT8__SHIFT 0x0 |
46130 | #define SEQ01__SEQ_SHIFT2__SHIFT 0x2 |
46131 | #define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 |
46132 | #define SEQ01__SEQ_SHIFT4__SHIFT 0x4 |
46133 | #define SEQ01__SEQ_MAXBW__SHIFT 0x5 |
46134 | #define SEQ01__SEQ_DOT8_MASK 0x01L |
46135 | #define SEQ01__SEQ_SHIFT2_MASK 0x04L |
46136 | #define SEQ01__SEQ_PCLKBY2_MASK 0x08L |
46137 | #define SEQ01__SEQ_SHIFT4_MASK 0x10L |
46138 | #define SEQ01__SEQ_MAXBW_MASK 0x20L |
46139 | //SEQ02 |
46140 | #define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 |
46141 | #define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 |
46142 | #define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 |
46143 | #define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 |
46144 | #define SEQ02__SEQ_MAP0_EN_MASK 0x01L |
46145 | #define SEQ02__SEQ_MAP1_EN_MASK 0x02L |
46146 | #define SEQ02__SEQ_MAP2_EN_MASK 0x04L |
46147 | #define SEQ02__SEQ_MAP3_EN_MASK 0x08L |
46148 | //SEQ03 |
46149 | #define SEQ03__SEQ_FONT_B1__SHIFT 0x0 |
46150 | #define SEQ03__SEQ_FONT_B2__SHIFT 0x1 |
46151 | #define SEQ03__SEQ_FONT_A1__SHIFT 0x2 |
46152 | #define SEQ03__SEQ_FONT_A2__SHIFT 0x3 |
46153 | #define SEQ03__SEQ_FONT_B0__SHIFT 0x4 |
46154 | #define SEQ03__SEQ_FONT_A0__SHIFT 0x5 |
46155 | #define SEQ03__SEQ_FONT_B1_MASK 0x01L |
46156 | #define SEQ03__SEQ_FONT_B2_MASK 0x02L |
46157 | #define SEQ03__SEQ_FONT_A1_MASK 0x04L |
46158 | #define SEQ03__SEQ_FONT_A2_MASK 0x08L |
46159 | #define SEQ03__SEQ_FONT_B0_MASK 0x10L |
46160 | #define SEQ03__SEQ_FONT_A0_MASK 0x20L |
46161 | //SEQ04 |
46162 | #define SEQ04__SEQ_256K__SHIFT 0x1 |
46163 | #define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 |
46164 | #define SEQ04__SEQ_CHAIN__SHIFT 0x3 |
46165 | #define SEQ04__SEQ_256K_MASK 0x02L |
46166 | #define SEQ04__SEQ_ODDEVEN_MASK 0x04L |
46167 | #define SEQ04__SEQ_CHAIN_MASK 0x08L |
46168 | |
46169 | |
46170 | // addressBlock: vga_vgacrtind |
46171 | //CRT00 |
46172 | #define CRT00__H_TOTAL__SHIFT 0x0 |
46173 | #define CRT00__H_TOTAL_MASK 0xFFL |
46174 | //CRT01 |
46175 | #define CRT01__H_DISP_END__SHIFT 0x0 |
46176 | #define CRT01__H_DISP_END_MASK 0xFFL |
46177 | //CRT02 |
46178 | #define CRT02__H_BLANK_START__SHIFT 0x0 |
46179 | #define CRT02__H_BLANK_START_MASK 0xFFL |
46180 | //CRT03 |
46181 | #define CRT03__H_BLANK_END__SHIFT 0x0 |
46182 | #define CRT03__H_DE_SKEW__SHIFT 0x5 |
46183 | #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 |
46184 | #define CRT03__H_BLANK_END_MASK 0x1FL |
46185 | #define CRT03__H_DE_SKEW_MASK 0x60L |
46186 | #define CRT03__CR10CR11_R_DIS_B_MASK 0x80L |
46187 | //CRT04 |
46188 | #define CRT04__H_SYNC_START__SHIFT 0x0 |
46189 | #define CRT04__H_SYNC_START_MASK 0xFFL |
46190 | //CRT05 |
46191 | #define CRT05__H_SYNC_END__SHIFT 0x0 |
46192 | #define CRT05__H_SYNC_SKEW__SHIFT 0x5 |
46193 | #define CRT05__H_BLANK_END_B5__SHIFT 0x7 |
46194 | #define CRT05__H_SYNC_END_MASK 0x1FL |
46195 | #define CRT05__H_SYNC_SKEW_MASK 0x60L |
46196 | #define CRT05__H_BLANK_END_B5_MASK 0x80L |
46197 | //CRT06 |
46198 | #define CRT06__V_TOTAL__SHIFT 0x0 |
46199 | #define CRT06__V_TOTAL_MASK 0xFFL |
46200 | //CRT07 |
46201 | #define CRT07__V_TOTAL_B8__SHIFT 0x0 |
46202 | #define CRT07__V_DISP_END_B8__SHIFT 0x1 |
46203 | #define CRT07__V_SYNC_START_B8__SHIFT 0x2 |
46204 | #define CRT07__V_BLANK_START_B8__SHIFT 0x3 |
46205 | #define CRT07__LINE_CMP_B8__SHIFT 0x4 |
46206 | #define CRT07__V_TOTAL_B9__SHIFT 0x5 |
46207 | #define CRT07__V_DISP_END_B9__SHIFT 0x6 |
46208 | #define CRT07__V_SYNC_START_B9__SHIFT 0x7 |
46209 | #define CRT07__V_TOTAL_B8_MASK 0x01L |
46210 | #define CRT07__V_DISP_END_B8_MASK 0x02L |
46211 | #define CRT07__V_SYNC_START_B8_MASK 0x04L |
46212 | #define CRT07__V_BLANK_START_B8_MASK 0x08L |
46213 | #define CRT07__LINE_CMP_B8_MASK 0x10L |
46214 | #define CRT07__V_TOTAL_B9_MASK 0x20L |
46215 | #define CRT07__V_DISP_END_B9_MASK 0x40L |
46216 | #define CRT07__V_SYNC_START_B9_MASK 0x80L |
46217 | //CRT08 |
46218 | #define CRT08__ROW_SCAN_START__SHIFT 0x0 |
46219 | #define CRT08__BYTE_PAN__SHIFT 0x5 |
46220 | #define CRT08__ROW_SCAN_START_MASK 0x1FL |
46221 | #define CRT08__BYTE_PAN_MASK 0x60L |
46222 | //CRT09 |
46223 | #define CRT09__MAX_ROW_SCAN__SHIFT 0x0 |
46224 | #define CRT09__V_BLANK_START_B9__SHIFT 0x5 |
46225 | #define CRT09__LINE_CMP_B9__SHIFT 0x6 |
46226 | #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 |
46227 | #define CRT09__MAX_ROW_SCAN_MASK 0x1FL |
46228 | #define CRT09__V_BLANK_START_B9_MASK 0x20L |
46229 | #define CRT09__LINE_CMP_B9_MASK 0x40L |
46230 | #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L |
46231 | //CRT0A |
46232 | #define CRT0A__CURSOR_START__SHIFT 0x0 |
46233 | #define CRT0A__CURSOR_DISABLE__SHIFT 0x5 |
46234 | #define CRT0A__CURSOR_START_MASK 0x1FL |
46235 | #define CRT0A__CURSOR_DISABLE_MASK 0x20L |
46236 | //CRT0B |
46237 | #define CRT0B__CURSOR_END__SHIFT 0x0 |
46238 | #define CRT0B__CURSOR_SKEW__SHIFT 0x5 |
46239 | #define CRT0B__CURSOR_END_MASK 0x1FL |
46240 | #define CRT0B__CURSOR_SKEW_MASK 0x60L |
46241 | //CRT0C |
46242 | #define CRT0C__DISP_START__SHIFT 0x0 |
46243 | #define CRT0C__DISP_START_MASK 0xFFL |
46244 | //CRT0D |
46245 | #define CRT0D__DISP_START__SHIFT 0x0 |
46246 | #define CRT0D__DISP_START_MASK 0xFFL |
46247 | //CRT0E |
46248 | #define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 |
46249 | #define CRT0E__CURSOR_LOC_HI_MASK 0xFFL |
46250 | //CRT0F |
46251 | #define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 |
46252 | #define CRT0F__CURSOR_LOC_LO_MASK 0xFFL |
46253 | //CRT10 |
46254 | #define CRT10__V_SYNC_START__SHIFT 0x0 |
46255 | #define CRT10__V_SYNC_START_MASK 0xFFL |
46256 | //CRT11 |
46257 | #define CRT11__V_SYNC_END__SHIFT 0x0 |
46258 | #define CRT11__V_INTR_CLR__SHIFT 0x4 |
46259 | #define CRT11__V_INTR_EN__SHIFT 0x5 |
46260 | #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 |
46261 | #define CRT11__C0T7_WR_ONLY__SHIFT 0x7 |
46262 | #define CRT11__V_SYNC_END_MASK 0x0FL |
46263 | #define CRT11__V_INTR_CLR_MASK 0x10L |
46264 | #define CRT11__V_INTR_EN_MASK 0x20L |
46265 | #define CRT11__SEL5_REFRESH_CYC_MASK 0x40L |
46266 | #define CRT11__C0T7_WR_ONLY_MASK 0x80L |
46267 | //CRT12 |
46268 | #define CRT12__V_DISP_END__SHIFT 0x0 |
46269 | #define CRT12__V_DISP_END_MASK 0xFFL |
46270 | //CRT13 |
46271 | #define CRT13__DISP_PITCH__SHIFT 0x0 |
46272 | #define CRT13__DISP_PITCH_MASK 0xFFL |
46273 | //CRT14 |
46274 | #define CRT14__UNDRLN_LOC__SHIFT 0x0 |
46275 | #define CRT14__ADDR_CNT_BY4__SHIFT 0x5 |
46276 | #define CRT14__DOUBLE_WORD__SHIFT 0x6 |
46277 | #define CRT14__UNDRLN_LOC_MASK 0x1FL |
46278 | #define CRT14__ADDR_CNT_BY4_MASK 0x20L |
46279 | #define CRT14__DOUBLE_WORD_MASK 0x40L |
46280 | //CRT15 |
46281 | #define CRT15__V_BLANK_START__SHIFT 0x0 |
46282 | #define CRT15__V_BLANK_START_MASK 0xFFL |
46283 | //CRT16 |
46284 | #define CRT16__V_BLANK_END__SHIFT 0x0 |
46285 | #define CRT16__V_BLANK_END_MASK 0xFFL |
46286 | //CRT17 |
46287 | #define CRT17__RA0_AS_A13B__SHIFT 0x0 |
46288 | #define CRT17__RA1_AS_A14B__SHIFT 0x1 |
46289 | #define CRT17__VCOUNT_BY2__SHIFT 0x2 |
46290 | #define CRT17__ADDR_CNT_BY2__SHIFT 0x3 |
46291 | #define CRT17__WRAP_A15TOA0__SHIFT 0x5 |
46292 | #define CRT17__BYTE_MODE__SHIFT 0x6 |
46293 | #define CRT17__CRTC_SYNC_EN__SHIFT 0x7 |
46294 | #define CRT17__RA0_AS_A13B_MASK 0x01L |
46295 | #define CRT17__RA1_AS_A14B_MASK 0x02L |
46296 | #define CRT17__VCOUNT_BY2_MASK 0x04L |
46297 | #define CRT17__ADDR_CNT_BY2_MASK 0x08L |
46298 | #define CRT17__WRAP_A15TOA0_MASK 0x20L |
46299 | #define CRT17__BYTE_MODE_MASK 0x40L |
46300 | #define CRT17__CRTC_SYNC_EN_MASK 0x80L |
46301 | //CRT18 |
46302 | #define CRT18__LINE_CMP__SHIFT 0x0 |
46303 | #define CRT18__LINE_CMP_MASK 0xFFL |
46304 | //CRT1E |
46305 | #define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 |
46306 | #define CRT1E__GRPH_DEC_RD1_MASK 0x02L |
46307 | //CRT1F |
46308 | #define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 |
46309 | #define CRT1F__GRPH_DEC_RD0_MASK 0xFFL |
46310 | //CRT22 |
46311 | #define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 |
46312 | #define CRT22__GRPH_LATCH_DATA_MASK 0xFFL |
46313 | |
46314 | |
46315 | // addressBlock: vga_vgagrphind |
46316 | //GRA00 |
46317 | #define GRA00__GRPH_SET_RESET0__SHIFT 0x0 |
46318 | #define GRA00__GRPH_SET_RESET1__SHIFT 0x1 |
46319 | #define GRA00__GRPH_SET_RESET2__SHIFT 0x2 |
46320 | #define GRA00__GRPH_SET_RESET3__SHIFT 0x3 |
46321 | #define GRA00__GRPH_SET_RESET0_MASK 0x01L |
46322 | #define GRA00__GRPH_SET_RESET1_MASK 0x02L |
46323 | #define GRA00__GRPH_SET_RESET2_MASK 0x04L |
46324 | #define GRA00__GRPH_SET_RESET3_MASK 0x08L |
46325 | //GRA01 |
46326 | #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 |
46327 | #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 |
46328 | #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 |
46329 | #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 |
46330 | #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L |
46331 | #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L |
46332 | #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L |
46333 | #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L |
46334 | //GRA02 |
46335 | #define GRA02__GRPH_CCOMP__SHIFT 0x0 |
46336 | #define GRA02__GRPH_CCOMP_MASK 0x0FL |
46337 | //GRA03 |
46338 | #define GRA03__GRPH_ROTATE__SHIFT 0x0 |
46339 | #define GRA03__GRPH_FN_SEL__SHIFT 0x3 |
46340 | #define GRA03__GRPH_ROTATE_MASK 0x07L |
46341 | #define GRA03__GRPH_FN_SEL_MASK 0x18L |
46342 | //GRA04 |
46343 | #define GRA04__GRPH_RMAP__SHIFT 0x0 |
46344 | #define GRA04__GRPH_RMAP_MASK 0x03L |
46345 | //GRA05 |
46346 | #define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 |
46347 | #define GRA05__GRPH_READ1__SHIFT 0x3 |
46348 | #define GRA05__CGA_ODDEVEN__SHIFT 0x4 |
46349 | #define GRA05__GRPH_OES__SHIFT 0x5 |
46350 | #define GRA05__GRPH_PACK__SHIFT 0x6 |
46351 | #define GRA05__GRPH_WRITE_MODE_MASK 0x03L |
46352 | #define GRA05__GRPH_READ1_MASK 0x08L |
46353 | #define GRA05__CGA_ODDEVEN_MASK 0x10L |
46354 | #define GRA05__GRPH_OES_MASK 0x20L |
46355 | #define GRA05__GRPH_PACK_MASK 0x40L |
46356 | //GRA06 |
46357 | #define GRA06__GRPH_GRAPHICS__SHIFT 0x0 |
46358 | #define GRA06__GRPH_ODDEVEN__SHIFT 0x1 |
46359 | #define GRA06__GRPH_ADRSEL__SHIFT 0x2 |
46360 | #define GRA06__GRPH_GRAPHICS_MASK 0x01L |
46361 | #define GRA06__GRPH_ODDEVEN_MASK 0x02L |
46362 | #define GRA06__GRPH_ADRSEL_MASK 0x0CL |
46363 | //GRA07 |
46364 | #define GRA07__GRPH_XCARE0__SHIFT 0x0 |
46365 | #define GRA07__GRPH_XCARE1__SHIFT 0x1 |
46366 | #define GRA07__GRPH_XCARE2__SHIFT 0x2 |
46367 | #define GRA07__GRPH_XCARE3__SHIFT 0x3 |
46368 | #define GRA07__GRPH_XCARE0_MASK 0x01L |
46369 | #define GRA07__GRPH_XCARE1_MASK 0x02L |
46370 | #define GRA07__GRPH_XCARE2_MASK 0x04L |
46371 | #define GRA07__GRPH_XCARE3_MASK 0x08L |
46372 | //GRA08 |
46373 | #define GRA08__GRPH_BMSK__SHIFT 0x0 |
46374 | #define GRA08__GRPH_BMSK_MASK 0xFFL |
46375 | |
46376 | |
46377 | // addressBlock: vga_vgaattrind |
46378 | //ATTR00 |
46379 | #define ATTR00__ATTR_PAL__SHIFT 0x0 |
46380 | #define ATTR00__ATTR_PAL_MASK 0x3FL |
46381 | //ATTR01 |
46382 | #define ATTR01__ATTR_PAL__SHIFT 0x0 |
46383 | #define ATTR01__ATTR_PAL_MASK 0x3FL |
46384 | //ATTR02 |
46385 | #define ATTR02__ATTR_PAL__SHIFT 0x0 |
46386 | #define ATTR02__ATTR_PAL_MASK 0x3FL |
46387 | //ATTR03 |
46388 | #define ATTR03__ATTR_PAL__SHIFT 0x0 |
46389 | #define ATTR03__ATTR_PAL_MASK 0x3FL |
46390 | //ATTR04 |
46391 | #define ATTR04__ATTR_PAL__SHIFT 0x0 |
46392 | #define ATTR04__ATTR_PAL_MASK 0x3FL |
46393 | //ATTR05 |
46394 | #define ATTR05__ATTR_PAL__SHIFT 0x0 |
46395 | #define ATTR05__ATTR_PAL_MASK 0x3FL |
46396 | //ATTR06 |
46397 | #define ATTR06__ATTR_PAL__SHIFT 0x0 |
46398 | #define ATTR06__ATTR_PAL_MASK 0x3FL |
46399 | //ATTR07 |
46400 | #define ATTR07__ATTR_PAL__SHIFT 0x0 |
46401 | #define ATTR07__ATTR_PAL_MASK 0x3FL |
46402 | //ATTR08 |
46403 | #define ATTR08__ATTR_PAL__SHIFT 0x0 |
46404 | #define ATTR08__ATTR_PAL_MASK 0x3FL |
46405 | //ATTR09 |
46406 | #define ATTR09__ATTR_PAL__SHIFT 0x0 |
46407 | #define ATTR09__ATTR_PAL_MASK 0x3FL |
46408 | //ATTR0A |
46409 | #define ATTR0A__ATTR_PAL__SHIFT 0x0 |
46410 | #define ATTR0A__ATTR_PAL_MASK 0x3FL |
46411 | //ATTR0B |
46412 | #define ATTR0B__ATTR_PAL__SHIFT 0x0 |
46413 | #define ATTR0B__ATTR_PAL_MASK 0x3FL |
46414 | //ATTR0C |
46415 | #define ATTR0C__ATTR_PAL__SHIFT 0x0 |
46416 | #define ATTR0C__ATTR_PAL_MASK 0x3FL |
46417 | //ATTR0D |
46418 | #define ATTR0D__ATTR_PAL__SHIFT 0x0 |
46419 | #define ATTR0D__ATTR_PAL_MASK 0x3FL |
46420 | //ATTR0E |
46421 | #define ATTR0E__ATTR_PAL__SHIFT 0x0 |
46422 | #define ATTR0E__ATTR_PAL_MASK 0x3FL |
46423 | //ATTR0F |
46424 | #define ATTR0F__ATTR_PAL__SHIFT 0x0 |
46425 | #define ATTR0F__ATTR_PAL_MASK 0x3FL |
46426 | //ATTR10 |
46427 | #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 |
46428 | #define ATTR10__ATTR_MONO_EN__SHIFT 0x1 |
46429 | #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 |
46430 | #define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 |
46431 | #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 |
46432 | #define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 |
46433 | #define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 |
46434 | #define ATTR10__ATTR_GRPH_MODE_MASK 0x01L |
46435 | #define ATTR10__ATTR_MONO_EN_MASK 0x02L |
46436 | #define ATTR10__ATTR_LGRPH_EN_MASK 0x04L |
46437 | #define ATTR10__ATTR_BLINK_EN_MASK 0x08L |
46438 | #define ATTR10__ATTR_PANTOPONLY_MASK 0x20L |
46439 | #define ATTR10__ATTR_PCLKBY2_MASK 0x40L |
46440 | #define ATTR10__ATTR_CSEL_EN_MASK 0x80L |
46441 | //ATTR11 |
46442 | #define ATTR11__ATTR_OVSC__SHIFT 0x0 |
46443 | #define ATTR11__ATTR_OVSC_MASK 0xFFL |
46444 | //ATTR12 |
46445 | #define ATTR12__ATTR_MAP_EN__SHIFT 0x0 |
46446 | #define ATTR12__ATTR_VSMUX__SHIFT 0x4 |
46447 | #define ATTR12__ATTR_MAP_EN_MASK 0x0FL |
46448 | #define ATTR12__ATTR_VSMUX_MASK 0x30L |
46449 | //ATTR13 |
46450 | #define ATTR13__ATTR_PPAN__SHIFT 0x0 |
46451 | #define ATTR13__ATTR_PPAN_MASK 0x0FL |
46452 | //ATTR14 |
46453 | #define ATTR14__ATTR_CSEL1__SHIFT 0x0 |
46454 | #define ATTR14__ATTR_CSEL2__SHIFT 0x2 |
46455 | #define ATTR14__ATTR_CSEL1_MASK 0x03L |
46456 | #define ATTR14__ATTR_CSEL2_MASK 0x0CL |
46457 | |
46458 | |
46459 | |
46460 | |
46461 | |
46462 | |
46463 | |
46464 | |
46465 | |
46466 | |
46467 | |
46468 | |
46469 | |
46470 | |
46471 | |
46472 | |
46473 | |
46474 | |
46475 | |
46476 | |
46477 | |
46478 | |
46479 | |
46480 | |
46481 | |
46482 | |
46483 | |
46484 | |
46485 | |
46486 | |
46487 | |
46488 | |
46489 | |
46490 | |
46491 | |
46492 | |
46493 | |
46494 | |
46495 | |
46496 | |
46497 | |
46498 | |
46499 | |
46500 | |
46501 | |
46502 | |
46503 | |
46504 | |
46505 | |
46506 | |
46507 | |
46508 | |
46509 | |
46510 | |
46511 | |
46512 | |
46513 | |
46514 | |
46515 | |
46516 | |
46517 | |
46518 | |
46519 | |
46520 | |
46521 | |
46522 | |
46523 | |
46524 | |
46525 | |
46526 | |
46527 | |
46528 | |
46529 | // addressBlock: azendpoint_f2codecind |
46530 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
46531 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
46532 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
46533 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
46534 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
46535 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
46536 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
46537 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf |
46538 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
46539 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
46540 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
46541 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
46542 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
46543 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
46544 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L |
46545 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
46546 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
46547 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
46548 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
46549 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
46550 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
46551 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
46552 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
46553 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
46554 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
46555 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
46556 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
46557 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
46558 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
46559 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
46560 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
46561 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
46562 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
46563 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
46564 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
46565 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
46566 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
46567 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
46568 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
46569 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
46570 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
46571 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 |
46572 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 |
46573 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL |
46574 | //AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL |
46575 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
46576 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
46577 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
46578 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
46579 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 |
46580 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 |
46581 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L |
46582 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE |
46583 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
46584 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
46585 | //AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
46586 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
46587 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
46588 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
46589 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
46590 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
46591 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
46592 | //AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
46593 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
46594 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
46595 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
46596 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
46597 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
46598 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
46599 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
46600 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
46601 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
46602 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
46603 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
46604 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
46605 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
46606 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
46607 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
46608 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
46609 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
46610 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
46611 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
46612 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
46613 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
46614 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
46615 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
46616 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
46617 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
46618 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
46619 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
46620 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
46621 | //AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
46622 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
46623 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
46624 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
46625 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
46626 | //AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
46627 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
46628 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
46629 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY |
46630 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 |
46631 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL |
46632 | //AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL |
46633 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
46634 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
46635 | //AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
46636 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
46637 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
46638 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
46639 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
46640 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
46641 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
46642 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
46643 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
46644 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
46645 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
46646 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
46647 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
46648 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
46649 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
46650 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
46651 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
46652 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
46653 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
46654 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
46655 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
46656 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
46657 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
46658 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
46659 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
46660 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
46661 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
46662 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 |
46663 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 |
46664 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 |
46665 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL |
46666 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L |
46667 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 |
46668 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 |
46669 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 |
46670 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL |
46671 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L |
46672 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 |
46673 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 |
46674 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 |
46675 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL |
46676 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L |
46677 | //AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION |
46678 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 |
46679 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 |
46680 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 |
46681 | #define 0xa |
46682 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL |
46683 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L |
46684 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L |
46685 | #define 0x0000FC00L |
46686 | //AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION |
46687 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
46688 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
46689 | //AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO |
46690 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 |
46691 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 |
46692 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 |
46693 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L |
46694 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L |
46695 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L |
46696 | //AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR |
46697 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 |
46698 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 |
46699 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46700 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46701 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46702 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L |
46703 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L |
46704 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46705 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46706 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46707 | //AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA |
46708 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 |
46709 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL |
46710 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE |
46711 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
46712 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
46713 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
46714 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
46715 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
46716 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
46717 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE |
46718 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 |
46719 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 |
46720 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 |
46721 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L |
46722 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L |
46723 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L |
46724 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE |
46725 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 |
46726 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 |
46727 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 |
46728 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L |
46729 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L |
46730 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L |
46731 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE |
46732 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 |
46733 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 |
46734 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 |
46735 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L |
46736 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L |
46737 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L |
46738 | //AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC |
46739 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
46740 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
46741 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
46742 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
46743 | //AZALIA_F2_CODEC_PIN_CONTROL_HBR |
46744 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 |
46745 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 |
46746 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L |
46747 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L |
46748 | //AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX |
46749 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 |
46750 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL |
46751 | //AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA |
46752 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 |
46753 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL |
46754 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE |
46755 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
46756 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 |
46757 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
46758 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
46759 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L |
46760 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
46761 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE |
46762 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 |
46763 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 |
46764 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 |
46765 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L |
46766 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L |
46767 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L |
46768 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE |
46769 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 |
46770 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 |
46771 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 |
46772 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L |
46773 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L |
46774 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L |
46775 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE |
46776 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 |
46777 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 |
46778 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 |
46779 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L |
46780 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L |
46781 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L |
46782 | //AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
46783 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
46784 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
46785 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
46786 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
46787 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
46788 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
46789 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
46790 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
46791 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
46792 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
46793 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
46794 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
46795 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
46796 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
46797 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
46798 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
46799 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
46800 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
46801 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
46802 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
46803 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
46804 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
46805 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
46806 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
46807 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
46808 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
46809 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
46810 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
46811 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
46812 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
46813 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
46814 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
46815 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
46816 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
46817 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
46818 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
46819 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
46820 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
46821 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
46822 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
46823 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
46824 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
46825 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
46826 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
46827 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
46828 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
46829 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
46830 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
46831 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
46832 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
46833 | //AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
46834 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
46835 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
46836 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
46837 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
46838 | //AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO |
46839 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
46840 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
46841 | //AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
46842 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
46843 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
46844 | //AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
46845 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
46846 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
46847 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
46848 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
46849 | //AZALIA_F2_CODEC_PIN_CONTROL_LPIB |
46850 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
46851 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
46852 | //AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
46853 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
46854 | #define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
46855 | //AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE |
46856 | #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
46857 | #define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
46858 | //AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED |
46859 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
46860 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
46861 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
46862 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
46863 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
46864 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
46865 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
46866 | #define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
46867 | //AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
46868 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
46869 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
46870 | //AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
46871 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
46872 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
46873 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
46874 | #define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
46875 | //AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
46876 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
46877 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
46878 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
46879 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
46880 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
46881 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
46882 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
46883 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
46884 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
46885 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
46886 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
46887 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
46888 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
46889 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
46890 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
46891 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
46892 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
46893 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
46894 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
46895 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
46896 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
46897 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
46898 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
46899 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
46900 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
46901 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
46902 | //AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES |
46903 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
46904 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
46905 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
46906 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
46907 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
46908 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
46909 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
46910 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
46911 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
46912 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
46913 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
46914 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
46915 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
46916 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
46917 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
46918 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
46919 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
46920 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
46921 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
46922 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
46923 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
46924 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
46925 | //AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH |
46926 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 |
46927 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL |
46928 | |
46929 | |
46930 | // addressBlock: azendpoint_descriptorind |
46931 | //AUDIO_DESCRIPTOR0 |
46932 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
46933 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46934 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46935 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46936 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
46937 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46938 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46939 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46940 | //AUDIO_DESCRIPTOR1 |
46941 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
46942 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46943 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46944 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46945 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
46946 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46947 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46948 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46949 | //AUDIO_DESCRIPTOR2 |
46950 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
46951 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46952 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46953 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46954 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
46955 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46956 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46957 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46958 | //AUDIO_DESCRIPTOR3 |
46959 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
46960 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46961 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46962 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46963 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
46964 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46965 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46966 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46967 | //AUDIO_DESCRIPTOR4 |
46968 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
46969 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46970 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46971 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46972 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
46973 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46974 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46975 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46976 | //AUDIO_DESCRIPTOR5 |
46977 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
46978 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46979 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46980 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46981 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
46982 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46983 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46984 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46985 | //AUDIO_DESCRIPTOR6 |
46986 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
46987 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46988 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46989 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46990 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
46991 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
46992 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
46993 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
46994 | //AUDIO_DESCRIPTOR7 |
46995 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
46996 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
46997 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
46998 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
46999 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
47000 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47001 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47002 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47003 | //AUDIO_DESCRIPTOR8 |
47004 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
47005 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47006 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47007 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47008 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
47009 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47010 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47011 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47012 | //AUDIO_DESCRIPTOR9 |
47013 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
47014 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47015 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47016 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47017 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
47018 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47019 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47020 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47021 | //AUDIO_DESCRIPTOR10 |
47022 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
47023 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47024 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47025 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47026 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
47027 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47028 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47029 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47030 | //AUDIO_DESCRIPTOR11 |
47031 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
47032 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47033 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47034 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47035 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
47036 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47037 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47038 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47039 | //AUDIO_DESCRIPTOR12 |
47040 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
47041 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47042 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47043 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47044 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
47045 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47046 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47047 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47048 | //AUDIO_DESCRIPTOR13 |
47049 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
47050 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
47051 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
47052 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
47053 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
47054 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
47055 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
47056 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
47057 | |
47058 | |
47059 | // addressBlock: azendpoint_sinkinfoind |
47060 | //AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID |
47061 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 |
47062 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL |
47063 | //AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID |
47064 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 |
47065 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL |
47066 | //AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN |
47067 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
47068 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
47069 | //AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 |
47070 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 |
47071 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL |
47072 | //AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 |
47073 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 |
47074 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL |
47075 | //SINK_DESCRIPTION0 |
47076 | #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 |
47077 | #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL |
47078 | //SINK_DESCRIPTION1 |
47079 | #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 |
47080 | #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL |
47081 | //SINK_DESCRIPTION2 |
47082 | #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 |
47083 | #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL |
47084 | //SINK_DESCRIPTION3 |
47085 | #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 |
47086 | #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL |
47087 | //SINK_DESCRIPTION4 |
47088 | #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 |
47089 | #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL |
47090 | //SINK_DESCRIPTION5 |
47091 | #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 |
47092 | #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL |
47093 | //SINK_DESCRIPTION6 |
47094 | #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 |
47095 | #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL |
47096 | //SINK_DESCRIPTION7 |
47097 | #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 |
47098 | #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL |
47099 | //SINK_DESCRIPTION8 |
47100 | #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 |
47101 | #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL |
47102 | //SINK_DESCRIPTION9 |
47103 | #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 |
47104 | #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL |
47105 | //SINK_DESCRIPTION10 |
47106 | #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 |
47107 | #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL |
47108 | //SINK_DESCRIPTION11 |
47109 | #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 |
47110 | #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL |
47111 | //SINK_DESCRIPTION12 |
47112 | #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 |
47113 | #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL |
47114 | //SINK_DESCRIPTION13 |
47115 | #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 |
47116 | #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL |
47117 | //SINK_DESCRIPTION14 |
47118 | #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 |
47119 | #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL |
47120 | //SINK_DESCRIPTION15 |
47121 | #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 |
47122 | #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL |
47123 | //SINK_DESCRIPTION16 |
47124 | #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 |
47125 | #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL |
47126 | //SINK_DESCRIPTION17 |
47127 | #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 |
47128 | #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL |
47129 | |
47130 | |
47131 | // addressBlock: azf0controller_azinputcrc0resultind |
47132 | //AZALIA_INPUT_CRC0_CHANNEL0 |
47133 | #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 |
47134 | #define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL |
47135 | //AZALIA_INPUT_CRC0_CHANNEL1 |
47136 | #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 |
47137 | #define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL |
47138 | //AZALIA_INPUT_CRC0_CHANNEL2 |
47139 | #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 |
47140 | #define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL |
47141 | //AZALIA_INPUT_CRC0_CHANNEL3 |
47142 | #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 |
47143 | #define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL |
47144 | //AZALIA_INPUT_CRC0_CHANNEL4 |
47145 | #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 |
47146 | #define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL |
47147 | //AZALIA_INPUT_CRC0_CHANNEL5 |
47148 | #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 |
47149 | #define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL |
47150 | //AZALIA_INPUT_CRC0_CHANNEL6 |
47151 | #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 |
47152 | #define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL |
47153 | //AZALIA_INPUT_CRC0_CHANNEL7 |
47154 | #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 |
47155 | #define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL |
47156 | |
47157 | |
47158 | // addressBlock: azf0controller_azinputcrc1resultind |
47159 | //AZALIA_INPUT_CRC1_CHANNEL0 |
47160 | #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 |
47161 | #define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL |
47162 | //AZALIA_INPUT_CRC1_CHANNEL1 |
47163 | #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 |
47164 | #define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL |
47165 | //AZALIA_INPUT_CRC1_CHANNEL2 |
47166 | #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 |
47167 | #define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL |
47168 | //AZALIA_INPUT_CRC1_CHANNEL3 |
47169 | #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 |
47170 | #define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL |
47171 | //AZALIA_INPUT_CRC1_CHANNEL4 |
47172 | #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 |
47173 | #define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL |
47174 | //AZALIA_INPUT_CRC1_CHANNEL5 |
47175 | #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 |
47176 | #define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL |
47177 | //AZALIA_INPUT_CRC1_CHANNEL6 |
47178 | #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 |
47179 | #define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL |
47180 | //AZALIA_INPUT_CRC1_CHANNEL7 |
47181 | #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 |
47182 | #define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL |
47183 | |
47184 | |
47185 | // addressBlock: azf0controller_azcrc0resultind |
47186 | //AZALIA_CRC0_CHANNEL0 |
47187 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
47188 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL |
47189 | //AZALIA_CRC0_CHANNEL1 |
47190 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
47191 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL |
47192 | //AZALIA_CRC0_CHANNEL2 |
47193 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
47194 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL |
47195 | //AZALIA_CRC0_CHANNEL3 |
47196 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
47197 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL |
47198 | //AZALIA_CRC0_CHANNEL4 |
47199 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
47200 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL |
47201 | //AZALIA_CRC0_CHANNEL5 |
47202 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
47203 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL |
47204 | //AZALIA_CRC0_CHANNEL6 |
47205 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
47206 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL |
47207 | //AZALIA_CRC0_CHANNEL7 |
47208 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
47209 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL |
47210 | |
47211 | |
47212 | // addressBlock: azf0controller_azcrc1resultind |
47213 | //AZALIA_CRC1_CHANNEL0 |
47214 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
47215 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL |
47216 | //AZALIA_CRC1_CHANNEL1 |
47217 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
47218 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL |
47219 | //AZALIA_CRC1_CHANNEL2 |
47220 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
47221 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL |
47222 | //AZALIA_CRC1_CHANNEL3 |
47223 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
47224 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL |
47225 | //AZALIA_CRC1_CHANNEL4 |
47226 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
47227 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL |
47228 | //AZALIA_CRC1_CHANNEL5 |
47229 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
47230 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL |
47231 | //AZALIA_CRC1_CHANNEL6 |
47232 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
47233 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL |
47234 | //AZALIA_CRC1_CHANNEL7 |
47235 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
47236 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL |
47237 | |
47238 | |
47239 | // addressBlock: azinputendpoint_f2codecind |
47240 | //AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
47241 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
47242 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
47243 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
47244 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
47245 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
47246 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
47247 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
47248 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
47249 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
47250 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
47251 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
47252 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
47253 | //AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
47254 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
47255 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
47256 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
47257 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
47258 | //AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
47259 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
47260 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
47261 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
47262 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
47263 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
47264 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
47265 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
47266 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
47267 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
47268 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
47269 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
47270 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
47271 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
47272 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
47273 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
47274 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
47275 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
47276 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
47277 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
47278 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
47279 | //AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
47280 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
47281 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
47282 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
47283 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
47284 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
47285 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
47286 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
47287 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
47288 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
47289 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
47290 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
47291 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
47292 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
47293 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
47294 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
47295 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
47296 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
47297 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
47298 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
47299 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
47300 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
47301 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
47302 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
47303 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
47304 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
47305 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
47306 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
47307 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
47308 | //AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
47309 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
47310 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
47311 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
47312 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
47313 | //AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
47314 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
47315 | #define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
47316 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
47317 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
47318 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
47319 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
47320 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
47321 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
47322 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
47323 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
47324 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE |
47325 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
47326 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
47327 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
47328 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
47329 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
47330 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
47331 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
47332 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
47333 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
47334 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
47335 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
47336 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
47337 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
47338 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
47339 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
47340 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
47341 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
47342 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
47343 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
47344 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
47345 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
47346 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 |
47347 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 |
47348 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 |
47349 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL |
47350 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L |
47351 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 |
47352 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 |
47353 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 |
47354 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL |
47355 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L |
47356 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 |
47357 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 |
47358 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 |
47359 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL |
47360 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L |
47361 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
47362 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
47363 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
47364 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE |
47365 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
47366 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
47367 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
47368 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
47369 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
47370 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
47371 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE |
47372 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 |
47373 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 |
47374 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 |
47375 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L |
47376 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L |
47377 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L |
47378 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE |
47379 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
47380 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 |
47381 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
47382 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
47383 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L |
47384 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
47385 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE |
47386 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 |
47387 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 |
47388 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 |
47389 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L |
47390 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L |
47391 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L |
47392 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR |
47393 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 |
47394 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 |
47395 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L |
47396 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L |
47397 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE |
47398 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
47399 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 |
47400 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
47401 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
47402 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L |
47403 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
47404 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE |
47405 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 |
47406 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 |
47407 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 |
47408 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L |
47409 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L |
47410 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L |
47411 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE |
47412 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 |
47413 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 |
47414 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 |
47415 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L |
47416 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L |
47417 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L |
47418 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE |
47419 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 |
47420 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 |
47421 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 |
47422 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L |
47423 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L |
47424 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L |
47425 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
47426 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
47427 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
47428 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
47429 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
47430 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB |
47431 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
47432 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
47433 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
47434 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
47435 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
47436 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
47437 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
47438 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
47439 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
47440 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
47441 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
47442 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
47443 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
47444 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
47445 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
47446 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
47447 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
47448 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
47449 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
47450 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
47451 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
47452 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
47453 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
47454 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L |
47455 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 |
47456 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL |
47457 | //AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H |
47458 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 |
47459 | #define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL |
47460 | //AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
47461 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
47462 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
47463 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
47464 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
47465 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
47466 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
47467 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
47468 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
47469 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
47470 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
47471 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
47472 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
47473 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
47474 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
47475 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
47476 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
47477 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
47478 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
47479 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
47480 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
47481 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
47482 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
47483 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
47484 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
47485 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
47486 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
47487 | //AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
47488 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
47489 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
47490 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
47491 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
47492 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
47493 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
47494 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
47495 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
47496 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
47497 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
47498 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
47499 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
47500 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
47501 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
47502 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
47503 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
47504 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
47505 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
47506 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
47507 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
47508 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
47509 | #define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
47510 | |
47511 | |
47512 | // addressBlock: azroot_f2codecind |
47513 | //AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID |
47514 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
47515 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL |
47516 | //AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID |
47517 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
47518 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL |
47519 | //AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT |
47520 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
47521 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL |
47522 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE |
47523 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
47524 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
47525 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
47526 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
47527 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL |
47528 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L |
47529 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L |
47530 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L |
47531 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID |
47532 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
47533 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
47534 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
47535 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
47536 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL |
47537 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L |
47538 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L |
47539 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L |
47540 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 |
47541 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 |
47542 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL |
47543 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 |
47544 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 |
47545 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL |
47546 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 |
47547 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 |
47548 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL |
47549 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION |
47550 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
47551 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL |
47552 | //AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET |
47553 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
47554 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L |
47555 | //AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT |
47556 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
47557 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL |
47558 | //AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE |
47559 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
47560 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL |
47561 | //AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES |
47562 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
47563 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
47564 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
47565 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
47566 | //AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS |
47567 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
47568 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL |
47569 | //AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES |
47570 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
47571 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
47572 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
47573 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL |
47574 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L |
47575 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L |
47576 | |
47577 | |
47578 | // addressBlock: azf0stream0_streamind |
47579 | //AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL |
47580 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47581 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47582 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47583 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47584 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47585 | #define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47586 | //AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL |
47587 | #define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47588 | #define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47589 | //AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT |
47590 | #define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47591 | #define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47592 | //AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT |
47593 | #define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47594 | #define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47595 | //AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT |
47596 | #define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47597 | #define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47598 | |
47599 | |
47600 | // addressBlock: azf0stream1_streamind |
47601 | //AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL |
47602 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47603 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47604 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47605 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47606 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47607 | #define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47608 | //AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL |
47609 | #define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47610 | #define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47611 | //AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT |
47612 | #define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47613 | #define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47614 | //AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT |
47615 | #define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47616 | #define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47617 | //AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT |
47618 | #define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47619 | #define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47620 | |
47621 | |
47622 | // addressBlock: azf0stream2_streamind |
47623 | //AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL |
47624 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47625 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47626 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47627 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47628 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47629 | #define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47630 | //AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL |
47631 | #define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47632 | #define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47633 | //AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT |
47634 | #define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47635 | #define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47636 | //AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT |
47637 | #define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47638 | #define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47639 | //AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT |
47640 | #define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47641 | #define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47642 | |
47643 | |
47644 | // addressBlock: azf0stream3_streamind |
47645 | //AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL |
47646 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47647 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47648 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47649 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47650 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47651 | #define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47652 | //AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL |
47653 | #define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47654 | #define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47655 | //AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT |
47656 | #define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47657 | #define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47658 | //AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT |
47659 | #define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47660 | #define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47661 | //AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT |
47662 | #define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47663 | #define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47664 | |
47665 | |
47666 | // addressBlock: azf0stream4_streamind |
47667 | //AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL |
47668 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47669 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47670 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47671 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47672 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47673 | #define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47674 | //AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL |
47675 | #define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47676 | #define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47677 | //AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT |
47678 | #define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47679 | #define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47680 | //AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT |
47681 | #define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47682 | #define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47683 | //AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT |
47684 | #define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47685 | #define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47686 | |
47687 | |
47688 | // addressBlock: azf0stream5_streamind |
47689 | //AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL |
47690 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47691 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47692 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47693 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47694 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47695 | #define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47696 | //AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL |
47697 | #define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47698 | #define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47699 | //AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT |
47700 | #define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47701 | #define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47702 | //AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT |
47703 | #define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47704 | #define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47705 | //AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT |
47706 | #define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47707 | #define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47708 | |
47709 | |
47710 | // addressBlock: azf0stream6_streamind |
47711 | //AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL |
47712 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47713 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47714 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47715 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47716 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47717 | #define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47718 | //AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL |
47719 | #define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47720 | #define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47721 | //AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT |
47722 | #define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47723 | #define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47724 | //AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT |
47725 | #define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47726 | #define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47727 | //AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT |
47728 | #define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47729 | #define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47730 | |
47731 | |
47732 | // addressBlock: azf0stream7_streamind |
47733 | //AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL |
47734 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47735 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47736 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47737 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47738 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47739 | #define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47740 | //AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL |
47741 | #define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47742 | #define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47743 | //AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT |
47744 | #define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47745 | #define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47746 | //AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT |
47747 | #define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47748 | #define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47749 | //AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT |
47750 | #define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47751 | #define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47752 | |
47753 | |
47754 | // addressBlock: azf0stream8_streamind |
47755 | //AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL |
47756 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47757 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47758 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47759 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47760 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47761 | #define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47762 | //AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL |
47763 | #define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47764 | #define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47765 | //AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT |
47766 | #define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47767 | #define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47768 | //AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT |
47769 | #define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47770 | #define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47771 | //AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT |
47772 | #define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47773 | #define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47774 | |
47775 | |
47776 | // addressBlock: azf0stream9_streamind |
47777 | //AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL |
47778 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47779 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47780 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47781 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47782 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47783 | #define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47784 | //AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL |
47785 | #define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47786 | #define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47787 | //AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT |
47788 | #define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47789 | #define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47790 | //AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT |
47791 | #define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47792 | #define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47793 | //AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT |
47794 | #define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47795 | #define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47796 | |
47797 | |
47798 | // addressBlock: azf0stream10_streamind |
47799 | //AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL |
47800 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47801 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47802 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47803 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47804 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47805 | #define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47806 | //AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL |
47807 | #define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47808 | #define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47809 | //AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT |
47810 | #define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47811 | #define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47812 | //AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT |
47813 | #define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47814 | #define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47815 | //AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT |
47816 | #define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47817 | #define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47818 | |
47819 | |
47820 | // addressBlock: azf0stream11_streamind |
47821 | //AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL |
47822 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47823 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47824 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47825 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47826 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47827 | #define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47828 | //AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL |
47829 | #define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47830 | #define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47831 | //AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT |
47832 | #define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47833 | #define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47834 | //AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT |
47835 | #define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47836 | #define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47837 | //AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT |
47838 | #define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47839 | #define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47840 | |
47841 | |
47842 | // addressBlock: azf0stream12_streamind |
47843 | //AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL |
47844 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47845 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47846 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47847 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47848 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47849 | #define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47850 | //AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL |
47851 | #define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47852 | #define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47853 | //AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT |
47854 | #define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47855 | #define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47856 | //AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT |
47857 | #define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47858 | #define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47859 | //AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT |
47860 | #define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47861 | #define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47862 | |
47863 | |
47864 | // addressBlock: azf0stream13_streamind |
47865 | //AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL |
47866 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47867 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47868 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47869 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47870 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47871 | #define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47872 | //AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL |
47873 | #define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47874 | #define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47875 | //AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT |
47876 | #define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47877 | #define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47878 | //AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT |
47879 | #define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47880 | #define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47881 | //AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT |
47882 | #define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47883 | #define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47884 | |
47885 | |
47886 | // addressBlock: azf0stream14_streamind |
47887 | //AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL |
47888 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47889 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47890 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47891 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47892 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47893 | #define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47894 | //AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL |
47895 | #define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47896 | #define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47897 | //AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT |
47898 | #define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47899 | #define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47900 | //AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT |
47901 | #define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47902 | #define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47903 | //AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT |
47904 | #define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47905 | #define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47906 | |
47907 | |
47908 | // addressBlock: azf0stream15_streamind |
47909 | //AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL |
47910 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
47911 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
47912 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
47913 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL |
47914 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L |
47915 | #define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L |
47916 | //AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL |
47917 | #define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
47918 | #define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L |
47919 | //AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT |
47920 | #define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
47921 | #define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47922 | //AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT |
47923 | #define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
47924 | #define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL |
47925 | //AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT |
47926 | #define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
47927 | #define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL |
47928 | |
47929 | |
47930 | // addressBlock: azf0endpoint0_endpointind |
47931 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
47932 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
47933 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
47934 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
47935 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
47936 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
47937 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
47938 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
47939 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
47940 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
47941 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
47942 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
47943 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
47944 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
47945 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
47946 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
47947 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
47948 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
47949 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
47950 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
47951 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
47952 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
47953 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
47954 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
47955 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
47956 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
47957 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
47958 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
47959 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
47960 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
47961 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
47962 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
47963 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
47964 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
47965 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
47966 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
47967 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
47968 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
47969 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
47970 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
47971 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
47972 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
47973 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
47974 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
47975 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
47976 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
47977 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
47978 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
47979 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
47980 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
47981 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
47982 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
47983 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
47984 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
47985 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
47986 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
47987 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
47988 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
47989 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
47990 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
47991 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
47992 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
47993 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
47994 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
47995 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
47996 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
47997 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
47998 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
47999 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
48000 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
48001 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
48002 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
48003 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
48004 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
48005 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
48006 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
48007 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
48008 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
48009 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
48010 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
48011 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
48012 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
48013 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
48014 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
48015 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
48016 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
48017 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
48018 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
48019 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
48020 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
48021 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
48022 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
48023 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
48024 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
48025 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
48026 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
48027 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
48028 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
48029 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
48030 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
48031 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
48032 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
48033 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
48034 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
48035 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
48036 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
48037 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
48038 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
48039 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
48040 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
48041 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
48042 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
48043 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
48044 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
48045 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
48046 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
48047 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
48048 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
48049 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
48050 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
48051 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
48052 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
48053 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
48054 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
48055 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
48056 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
48057 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
48058 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
48059 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
48060 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
48061 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
48062 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
48063 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
48064 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
48065 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
48066 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
48067 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
48068 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
48069 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
48070 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
48071 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
48072 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
48073 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
48074 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
48075 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
48076 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
48077 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
48078 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
48079 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
48080 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
48081 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
48082 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
48083 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
48084 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
48085 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
48086 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
48087 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
48088 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
48089 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
48090 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
48091 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
48092 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
48093 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
48094 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
48095 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
48096 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
48097 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
48098 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
48099 | #define 0x12 |
48100 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
48101 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
48102 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
48103 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
48104 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
48105 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
48106 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
48107 | #define 0x00FC0000L |
48108 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
48109 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
48110 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
48111 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
48112 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
48113 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48114 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48115 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
48116 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
48117 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48118 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48119 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
48120 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
48121 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
48122 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48123 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48124 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
48125 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48126 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48127 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
48128 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
48129 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48130 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48131 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
48132 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48133 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48134 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
48135 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
48136 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48137 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48138 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
48139 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48140 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48141 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
48142 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
48143 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48144 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48145 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
48146 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48147 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48148 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
48149 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
48150 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48151 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48152 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
48153 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48154 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48155 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
48156 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
48157 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48158 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48159 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
48160 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48161 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48162 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
48163 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
48164 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48165 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48166 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
48167 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48168 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48169 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
48170 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
48171 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48172 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48173 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
48174 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48175 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48176 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
48177 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
48178 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48179 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48180 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
48181 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48182 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48183 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
48184 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
48185 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48186 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48187 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
48188 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48189 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48190 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
48191 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
48192 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48193 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48194 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
48195 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48196 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48197 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
48198 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
48199 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48200 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48201 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
48202 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48203 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48204 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
48205 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
48206 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48207 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48208 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
48209 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48210 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48211 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
48212 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
48213 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
48214 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
48215 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
48216 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
48217 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
48218 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
48219 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
48220 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
48221 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
48222 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
48223 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
48224 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
48225 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
48226 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
48227 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
48228 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
48229 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
48230 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
48231 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
48232 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
48233 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
48234 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
48235 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
48236 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
48237 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
48238 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
48239 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
48240 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
48241 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
48242 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
48243 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
48244 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
48245 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
48246 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
48247 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
48248 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
48249 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
48250 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
48251 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
48252 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
48253 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
48254 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
48255 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
48256 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
48257 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
48258 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
48259 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
48260 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
48261 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
48262 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
48263 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
48264 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
48265 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
48266 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
48267 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
48268 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
48269 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
48270 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
48271 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
48272 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
48273 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
48274 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
48275 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
48276 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
48277 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
48278 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
48279 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
48280 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
48281 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
48282 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
48283 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
48284 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
48285 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
48286 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
48287 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
48288 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
48289 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
48290 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
48291 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
48292 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
48293 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
48294 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
48295 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
48296 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
48297 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
48298 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
48299 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
48300 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
48301 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
48302 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
48303 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
48304 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
48305 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
48306 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
48307 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
48308 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
48309 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
48310 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
48311 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
48312 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
48313 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
48314 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
48315 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
48316 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
48317 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
48318 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
48319 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
48320 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
48321 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
48322 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
48323 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
48324 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
48325 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
48326 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
48327 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
48328 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
48329 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
48330 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
48331 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
48332 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
48333 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
48334 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
48335 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
48336 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
48337 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
48338 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
48339 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
48340 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
48341 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
48342 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
48343 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
48344 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
48345 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
48346 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
48347 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
48348 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
48349 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
48350 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
48351 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
48352 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
48353 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
48354 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
48355 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
48356 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
48357 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
48358 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
48359 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
48360 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
48361 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
48362 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
48363 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
48364 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
48365 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
48366 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
48367 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
48368 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
48369 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
48370 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
48371 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
48372 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
48373 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
48374 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
48375 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
48376 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
48377 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
48378 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
48379 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
48380 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
48381 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
48382 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
48383 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
48384 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
48385 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
48386 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
48387 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
48388 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
48389 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
48390 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
48391 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
48392 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
48393 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
48394 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
48395 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
48396 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
48397 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
48398 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
48399 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
48400 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
48401 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
48402 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
48403 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
48404 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
48405 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
48406 | //AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
48407 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
48408 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
48409 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
48410 | #define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
48411 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
48412 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
48413 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
48414 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
48415 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
48416 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
48417 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
48418 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
48419 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
48420 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
48421 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
48422 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
48423 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
48424 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
48425 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
48426 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
48427 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
48428 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
48429 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
48430 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
48431 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
48432 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
48433 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
48434 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
48435 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
48436 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
48437 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
48438 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
48439 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
48440 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
48441 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
48442 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
48443 | //AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
48444 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
48445 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
48446 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
48447 | #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
48448 | //AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS |
48449 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
48450 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
48451 | //AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
48452 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
48453 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
48454 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
48455 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
48456 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
48457 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
48458 | //AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
48459 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
48460 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
48461 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
48462 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
48463 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
48464 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
48465 | //AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
48466 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
48467 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
48468 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
48469 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
48470 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
48471 | #define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
48472 | |
48473 | |
48474 | // addressBlock: azf0endpoint1_endpointind |
48475 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
48476 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
48477 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
48478 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
48479 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
48480 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
48481 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
48482 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
48483 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
48484 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
48485 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
48486 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
48487 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
48488 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
48489 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
48490 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
48491 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
48492 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
48493 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
48494 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
48495 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
48496 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
48497 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
48498 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
48499 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
48500 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
48501 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
48502 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
48503 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
48504 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
48505 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
48506 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
48507 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
48508 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
48509 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
48510 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
48511 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
48512 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
48513 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
48514 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
48515 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
48516 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
48517 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
48518 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
48519 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
48520 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
48521 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
48522 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
48523 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
48524 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
48525 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
48526 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
48527 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
48528 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
48529 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
48530 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
48531 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
48532 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
48533 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
48534 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
48535 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
48536 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
48537 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
48538 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
48539 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
48540 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
48541 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
48542 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
48543 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
48544 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
48545 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
48546 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
48547 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
48548 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
48549 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
48550 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
48551 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
48552 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
48553 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
48554 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
48555 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
48556 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
48557 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
48558 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
48559 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
48560 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
48561 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
48562 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
48563 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
48564 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
48565 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
48566 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
48567 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
48568 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
48569 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
48570 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
48571 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
48572 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
48573 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
48574 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
48575 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
48576 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
48577 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
48578 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
48579 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
48580 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
48581 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
48582 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
48583 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
48584 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
48585 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
48586 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
48587 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
48588 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
48589 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
48590 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
48591 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
48592 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
48593 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
48594 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
48595 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
48596 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
48597 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
48598 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
48599 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
48600 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
48601 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
48602 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
48603 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
48604 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
48605 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
48606 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
48607 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
48608 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
48609 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
48610 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
48611 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
48612 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
48613 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
48614 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
48615 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
48616 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
48617 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
48618 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
48619 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
48620 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
48621 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
48622 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
48623 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
48624 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
48625 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
48626 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
48627 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
48628 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
48629 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
48630 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
48631 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
48632 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
48633 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
48634 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
48635 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
48636 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
48637 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
48638 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
48639 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
48640 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
48641 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
48642 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
48643 | #define 0x12 |
48644 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
48645 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
48646 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
48647 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
48648 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
48649 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
48650 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
48651 | #define 0x00FC0000L |
48652 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
48653 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
48654 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
48655 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
48656 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
48657 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48658 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48659 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
48660 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
48661 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48662 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48663 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
48664 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
48665 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
48666 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48667 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48668 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
48669 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48670 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48671 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
48672 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
48673 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48674 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48675 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
48676 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48677 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48678 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
48679 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
48680 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48681 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48682 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
48683 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48684 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48685 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
48686 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
48687 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48688 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48689 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
48690 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48691 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48692 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
48693 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
48694 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48695 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48696 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
48697 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48698 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48699 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
48700 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
48701 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48702 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48703 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
48704 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48705 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48706 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
48707 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
48708 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48709 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48710 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
48711 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48712 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48713 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
48714 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
48715 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48716 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48717 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
48718 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48719 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48720 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
48721 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
48722 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48723 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48724 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
48725 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48726 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48727 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
48728 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
48729 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48730 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48731 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
48732 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48733 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48734 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
48735 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
48736 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48737 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48738 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
48739 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48740 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48741 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
48742 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
48743 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48744 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48745 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
48746 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48747 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48748 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
48749 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
48750 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
48751 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
48752 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
48753 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
48754 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
48755 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
48756 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
48757 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
48758 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
48759 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
48760 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
48761 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
48762 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
48763 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
48764 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
48765 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
48766 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
48767 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
48768 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
48769 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
48770 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
48771 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
48772 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
48773 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
48774 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
48775 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
48776 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
48777 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
48778 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
48779 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
48780 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
48781 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
48782 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
48783 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
48784 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
48785 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
48786 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
48787 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
48788 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
48789 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
48790 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
48791 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
48792 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
48793 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
48794 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
48795 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
48796 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
48797 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
48798 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
48799 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
48800 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
48801 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
48802 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
48803 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
48804 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
48805 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
48806 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
48807 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
48808 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
48809 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
48810 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
48811 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
48812 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
48813 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
48814 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
48815 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
48816 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
48817 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
48818 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
48819 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
48820 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
48821 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
48822 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
48823 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
48824 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
48825 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
48826 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
48827 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
48828 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
48829 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
48830 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
48831 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
48832 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
48833 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
48834 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
48835 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
48836 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
48837 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
48838 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
48839 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
48840 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
48841 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
48842 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
48843 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
48844 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
48845 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
48846 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
48847 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
48848 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
48849 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
48850 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
48851 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
48852 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
48853 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
48854 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
48855 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
48856 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
48857 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
48858 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
48859 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
48860 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
48861 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
48862 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
48863 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
48864 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
48865 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
48866 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
48867 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
48868 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
48869 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
48870 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
48871 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
48872 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
48873 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
48874 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
48875 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
48876 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
48877 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
48878 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
48879 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
48880 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
48881 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
48882 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
48883 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
48884 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
48885 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
48886 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
48887 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
48888 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
48889 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
48890 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
48891 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
48892 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
48893 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
48894 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
48895 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
48896 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
48897 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
48898 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
48899 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
48900 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
48901 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
48902 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
48903 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
48904 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
48905 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
48906 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
48907 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
48908 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
48909 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
48910 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
48911 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
48912 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
48913 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
48914 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
48915 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
48916 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
48917 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
48918 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
48919 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
48920 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
48921 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
48922 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
48923 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
48924 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
48925 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
48926 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
48927 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
48928 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
48929 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
48930 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
48931 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
48932 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
48933 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
48934 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
48935 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
48936 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
48937 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
48938 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
48939 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
48940 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
48941 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
48942 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
48943 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
48944 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
48945 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
48946 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
48947 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
48948 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
48949 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
48950 | //AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
48951 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
48952 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
48953 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
48954 | #define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
48955 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
48956 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
48957 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
48958 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
48959 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
48960 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
48961 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
48962 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
48963 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
48964 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
48965 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
48966 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
48967 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
48968 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
48969 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
48970 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
48971 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
48972 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
48973 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
48974 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
48975 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
48976 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
48977 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
48978 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
48979 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
48980 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
48981 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
48982 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
48983 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
48984 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
48985 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
48986 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
48987 | //AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
48988 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
48989 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
48990 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
48991 | #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
48992 | //AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS |
48993 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
48994 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
48995 | //AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
48996 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
48997 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
48998 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
48999 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
49000 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
49001 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
49002 | //AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
49003 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
49004 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
49005 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
49006 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
49007 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
49008 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
49009 | //AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
49010 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
49011 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
49012 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
49013 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
49014 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
49015 | #define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
49016 | |
49017 | |
49018 | // addressBlock: azf0endpoint2_endpointind |
49019 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
49020 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
49021 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
49022 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
49023 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
49024 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
49025 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
49026 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
49027 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
49028 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
49029 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
49030 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
49031 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
49032 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
49033 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
49034 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
49035 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
49036 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
49037 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
49038 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
49039 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
49040 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
49041 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
49042 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
49043 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
49044 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
49045 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
49046 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
49047 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
49048 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
49049 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
49050 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
49051 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
49052 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
49053 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
49054 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
49055 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
49056 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
49057 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
49058 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
49059 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
49060 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
49061 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
49062 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
49063 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
49064 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
49065 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
49066 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
49067 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
49068 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
49069 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
49070 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
49071 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
49072 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
49073 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
49074 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
49075 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
49076 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
49077 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
49078 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
49079 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
49080 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
49081 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
49082 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
49083 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
49084 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
49085 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
49086 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
49087 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
49088 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
49089 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
49090 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
49091 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
49092 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
49093 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
49094 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
49095 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
49096 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
49097 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
49098 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
49099 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
49100 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
49101 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
49102 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
49103 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
49104 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
49105 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
49106 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
49107 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
49108 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
49109 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
49110 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
49111 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
49112 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
49113 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
49114 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
49115 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
49116 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
49117 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
49118 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
49119 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
49120 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
49121 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
49122 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
49123 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
49124 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
49125 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
49126 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
49127 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
49128 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
49129 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
49130 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
49131 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
49132 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
49133 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
49134 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
49135 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
49136 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
49137 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
49138 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
49139 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
49140 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
49141 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
49142 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
49143 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
49144 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
49145 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
49146 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
49147 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
49148 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
49149 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
49150 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
49151 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
49152 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
49153 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
49154 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
49155 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
49156 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
49157 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
49158 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
49159 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
49160 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
49161 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
49162 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
49163 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
49164 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
49165 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
49166 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
49167 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
49168 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
49169 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
49170 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
49171 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
49172 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
49173 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
49174 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
49175 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
49176 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
49177 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
49178 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
49179 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
49180 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
49181 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
49182 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
49183 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
49184 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
49185 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
49186 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
49187 | #define 0x12 |
49188 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
49189 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
49190 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
49191 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
49192 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
49193 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
49194 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
49195 | #define 0x00FC0000L |
49196 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
49197 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
49198 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
49199 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
49200 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
49201 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49202 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49203 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
49204 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
49205 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49206 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49207 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
49208 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
49209 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
49210 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49211 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49212 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
49213 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49214 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49215 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
49216 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
49217 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49218 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49219 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
49220 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49221 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49222 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
49223 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
49224 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49225 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49226 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
49227 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49228 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49229 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
49230 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
49231 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49232 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49233 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
49234 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49235 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49236 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
49237 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
49238 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49239 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49240 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
49241 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49242 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49243 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
49244 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
49245 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49246 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49247 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
49248 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49249 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49250 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
49251 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
49252 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49253 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49254 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
49255 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49256 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49257 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
49258 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
49259 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49260 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49261 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
49262 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49263 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49264 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
49265 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
49266 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49267 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49268 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
49269 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49270 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49271 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
49272 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
49273 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49274 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49275 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
49276 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49277 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49278 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
49279 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
49280 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49281 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49282 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
49283 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49284 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49285 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
49286 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
49287 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49288 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49289 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
49290 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49291 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49292 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
49293 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
49294 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49295 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49296 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
49297 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49298 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49299 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
49300 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
49301 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
49302 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
49303 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
49304 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
49305 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
49306 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
49307 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
49308 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
49309 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
49310 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
49311 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
49312 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
49313 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
49314 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
49315 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
49316 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
49317 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
49318 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
49319 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
49320 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
49321 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
49322 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
49323 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
49324 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
49325 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
49326 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
49327 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
49328 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
49329 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
49330 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
49331 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
49332 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
49333 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
49334 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
49335 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
49336 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
49337 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
49338 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
49339 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
49340 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
49341 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
49342 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
49343 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
49344 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
49345 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
49346 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
49347 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
49348 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
49349 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
49350 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
49351 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
49352 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
49353 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
49354 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
49355 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
49356 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
49357 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
49358 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
49359 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
49360 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
49361 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
49362 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
49363 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
49364 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
49365 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
49366 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
49367 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
49368 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
49369 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
49370 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
49371 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
49372 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
49373 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
49374 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
49375 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
49376 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
49377 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
49378 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
49379 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
49380 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
49381 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
49382 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
49383 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
49384 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
49385 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
49386 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
49387 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
49388 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
49389 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
49390 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
49391 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
49392 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
49393 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
49394 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
49395 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
49396 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
49397 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
49398 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
49399 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
49400 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
49401 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
49402 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
49403 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
49404 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
49405 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
49406 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
49407 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
49408 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
49409 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
49410 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
49411 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
49412 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
49413 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
49414 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
49415 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
49416 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
49417 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
49418 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
49419 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
49420 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
49421 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
49422 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
49423 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
49424 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
49425 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
49426 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
49427 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
49428 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
49429 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
49430 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
49431 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
49432 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
49433 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
49434 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
49435 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
49436 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
49437 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
49438 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
49439 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
49440 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
49441 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
49442 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
49443 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
49444 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
49445 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
49446 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
49447 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
49448 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
49449 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
49450 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
49451 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
49452 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
49453 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
49454 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
49455 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
49456 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
49457 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
49458 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
49459 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
49460 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
49461 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
49462 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
49463 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
49464 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
49465 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
49466 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
49467 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
49468 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
49469 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
49470 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
49471 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
49472 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
49473 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
49474 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
49475 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
49476 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
49477 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
49478 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
49479 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
49480 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
49481 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
49482 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
49483 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
49484 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
49485 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
49486 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
49487 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
49488 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
49489 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
49490 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
49491 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
49492 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
49493 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
49494 | //AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
49495 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
49496 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
49497 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
49498 | #define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
49499 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
49500 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
49501 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
49502 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
49503 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
49504 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
49505 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
49506 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
49507 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
49508 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
49509 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
49510 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
49511 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
49512 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
49513 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
49514 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
49515 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
49516 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
49517 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
49518 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
49519 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
49520 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
49521 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
49522 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
49523 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
49524 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
49525 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
49526 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
49527 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
49528 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
49529 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
49530 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
49531 | //AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
49532 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
49533 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
49534 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
49535 | #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
49536 | //AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS |
49537 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
49538 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
49539 | //AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
49540 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
49541 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
49542 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
49543 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
49544 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
49545 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
49546 | //AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
49547 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
49548 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
49549 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
49550 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
49551 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
49552 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
49553 | //AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
49554 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
49555 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
49556 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
49557 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
49558 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
49559 | #define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
49560 | |
49561 | |
49562 | // addressBlock: azf0endpoint3_endpointind |
49563 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
49564 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
49565 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
49566 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
49567 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
49568 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
49569 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
49570 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
49571 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
49572 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
49573 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
49574 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
49575 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
49576 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
49577 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
49578 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
49579 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
49580 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
49581 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
49582 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
49583 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
49584 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
49585 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
49586 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
49587 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
49588 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
49589 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
49590 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
49591 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
49592 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
49593 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
49594 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
49595 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
49596 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
49597 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
49598 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
49599 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
49600 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
49601 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
49602 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
49603 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
49604 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
49605 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
49606 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
49607 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
49608 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
49609 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
49610 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
49611 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
49612 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
49613 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
49614 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
49615 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
49616 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
49617 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
49618 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
49619 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
49620 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
49621 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
49622 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
49623 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
49624 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
49625 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
49626 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
49627 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
49628 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
49629 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
49630 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
49631 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
49632 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
49633 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
49634 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
49635 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
49636 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
49637 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
49638 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
49639 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
49640 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
49641 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
49642 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
49643 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
49644 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
49645 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
49646 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
49647 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
49648 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
49649 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
49650 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
49651 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
49652 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
49653 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
49654 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
49655 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
49656 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
49657 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
49658 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
49659 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
49660 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
49661 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
49662 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
49663 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
49664 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
49665 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
49666 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
49667 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
49668 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
49669 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
49670 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
49671 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
49672 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
49673 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
49674 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
49675 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
49676 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
49677 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
49678 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
49679 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
49680 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
49681 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
49682 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
49683 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
49684 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
49685 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
49686 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
49687 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
49688 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
49689 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
49690 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
49691 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
49692 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
49693 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
49694 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
49695 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
49696 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
49697 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
49698 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
49699 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
49700 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
49701 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
49702 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
49703 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
49704 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
49705 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
49706 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
49707 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
49708 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
49709 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
49710 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
49711 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
49712 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
49713 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
49714 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
49715 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
49716 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
49717 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
49718 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
49719 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
49720 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
49721 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
49722 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
49723 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
49724 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
49725 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
49726 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
49727 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
49728 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
49729 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
49730 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
49731 | #define 0x12 |
49732 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
49733 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
49734 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
49735 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
49736 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
49737 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
49738 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
49739 | #define 0x00FC0000L |
49740 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
49741 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
49742 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
49743 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
49744 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
49745 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49746 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49747 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
49748 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
49749 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49750 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49751 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
49752 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
49753 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
49754 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49755 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49756 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
49757 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49758 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49759 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
49760 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
49761 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49762 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49763 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
49764 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49765 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49766 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
49767 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
49768 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49769 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49770 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
49771 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49772 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49773 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
49774 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
49775 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49776 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49777 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
49778 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49779 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49780 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
49781 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
49782 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49783 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49784 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
49785 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49786 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49787 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
49788 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
49789 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49790 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49791 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
49792 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49793 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49794 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
49795 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
49796 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49797 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49798 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
49799 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49800 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49801 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
49802 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
49803 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49804 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49805 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
49806 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49807 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49808 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
49809 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
49810 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49811 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49812 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
49813 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49814 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49815 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
49816 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
49817 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49818 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49819 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
49820 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49821 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49822 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
49823 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
49824 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49825 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49826 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
49827 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49828 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49829 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
49830 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
49831 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49832 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49833 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
49834 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49835 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49836 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
49837 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
49838 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
49839 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
49840 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
49841 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
49842 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
49843 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
49844 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
49845 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
49846 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
49847 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
49848 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
49849 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
49850 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
49851 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
49852 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
49853 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
49854 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
49855 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
49856 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
49857 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
49858 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
49859 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
49860 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
49861 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
49862 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
49863 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
49864 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
49865 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
49866 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
49867 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
49868 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
49869 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
49870 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
49871 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
49872 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
49873 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
49874 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
49875 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
49876 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
49877 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
49878 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
49879 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
49880 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
49881 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
49882 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
49883 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
49884 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
49885 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
49886 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
49887 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
49888 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
49889 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
49890 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
49891 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
49892 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
49893 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
49894 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
49895 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
49896 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
49897 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
49898 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
49899 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
49900 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
49901 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
49902 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
49903 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
49904 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
49905 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
49906 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
49907 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
49908 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
49909 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
49910 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
49911 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
49912 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
49913 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
49914 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
49915 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
49916 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
49917 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
49918 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
49919 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
49920 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
49921 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
49922 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
49923 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
49924 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
49925 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
49926 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
49927 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
49928 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
49929 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
49930 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
49931 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
49932 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
49933 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
49934 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
49935 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
49936 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
49937 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
49938 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
49939 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
49940 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
49941 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
49942 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
49943 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
49944 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
49945 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
49946 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
49947 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
49948 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
49949 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
49950 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
49951 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
49952 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
49953 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
49954 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
49955 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
49956 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
49957 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
49958 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
49959 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
49960 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
49961 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
49962 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
49963 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
49964 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
49965 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
49966 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
49967 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
49968 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
49969 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
49970 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
49971 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
49972 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
49973 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
49974 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
49975 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
49976 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
49977 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
49978 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
49979 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
49980 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
49981 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
49982 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
49983 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
49984 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
49985 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
49986 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
49987 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
49988 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
49989 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
49990 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
49991 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
49992 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
49993 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
49994 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
49995 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
49996 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
49997 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
49998 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
49999 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
50000 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
50001 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
50002 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
50003 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
50004 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
50005 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
50006 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
50007 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
50008 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
50009 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
50010 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
50011 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
50012 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
50013 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
50014 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
50015 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
50016 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
50017 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
50018 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
50019 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
50020 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
50021 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
50022 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
50023 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
50024 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
50025 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
50026 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
50027 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
50028 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
50029 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
50030 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
50031 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
50032 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
50033 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
50034 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
50035 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
50036 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
50037 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
50038 | //AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
50039 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
50040 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
50041 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
50042 | #define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
50043 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
50044 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
50045 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
50046 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
50047 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
50048 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
50049 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
50050 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
50051 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
50052 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
50053 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
50054 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
50055 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
50056 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
50057 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
50058 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
50059 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
50060 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
50061 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
50062 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
50063 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
50064 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
50065 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
50066 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
50067 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
50068 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
50069 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
50070 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
50071 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
50072 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
50073 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
50074 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
50075 | //AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
50076 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
50077 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
50078 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
50079 | #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
50080 | //AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS |
50081 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
50082 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
50083 | //AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
50084 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
50085 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
50086 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
50087 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
50088 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
50089 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
50090 | //AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
50091 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
50092 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
50093 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
50094 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
50095 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
50096 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
50097 | //AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
50098 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
50099 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
50100 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
50101 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
50102 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
50103 | #define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
50104 | |
50105 | |
50106 | // addressBlock: azf0endpoint4_endpointind |
50107 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
50108 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
50109 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
50110 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
50111 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
50112 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
50113 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
50114 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
50115 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
50116 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
50117 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
50118 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
50119 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
50120 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
50121 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
50122 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
50123 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
50124 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
50125 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
50126 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
50127 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
50128 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
50129 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
50130 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
50131 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
50132 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
50133 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
50134 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
50135 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
50136 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
50137 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
50138 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
50139 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
50140 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
50141 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
50142 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
50143 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
50144 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
50145 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
50146 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
50147 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
50148 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
50149 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
50150 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
50151 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
50152 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
50153 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
50154 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
50155 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
50156 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
50157 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
50158 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
50159 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
50160 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
50161 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
50162 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
50163 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
50164 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
50165 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
50166 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
50167 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
50168 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
50169 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
50170 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
50171 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
50172 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
50173 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
50174 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
50175 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
50176 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
50177 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
50178 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
50179 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
50180 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
50181 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
50182 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
50183 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
50184 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
50185 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
50186 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
50187 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
50188 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
50189 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
50190 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
50191 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
50192 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
50193 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
50194 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
50195 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
50196 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
50197 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
50198 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
50199 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
50200 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
50201 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
50202 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
50203 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
50204 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
50205 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
50206 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
50207 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
50208 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
50209 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
50210 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
50211 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
50212 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
50213 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
50214 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
50215 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
50216 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
50217 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
50218 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
50219 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
50220 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
50221 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
50222 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
50223 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
50224 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
50225 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
50226 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
50227 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
50228 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
50229 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
50230 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
50231 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
50232 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
50233 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
50234 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
50235 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
50236 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
50237 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
50238 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
50239 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
50240 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
50241 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
50242 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
50243 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
50244 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
50245 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
50246 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
50247 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
50248 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
50249 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
50250 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
50251 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
50252 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
50253 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
50254 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
50255 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
50256 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
50257 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
50258 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
50259 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
50260 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
50261 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
50262 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
50263 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
50264 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
50265 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
50266 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
50267 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
50268 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
50269 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
50270 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
50271 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
50272 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
50273 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
50274 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
50275 | #define 0x12 |
50276 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
50277 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
50278 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
50279 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
50280 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
50281 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
50282 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
50283 | #define 0x00FC0000L |
50284 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
50285 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
50286 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
50287 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
50288 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
50289 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50290 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50291 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
50292 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
50293 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50294 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50295 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
50296 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
50297 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
50298 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50299 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50300 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
50301 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50302 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50303 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
50304 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
50305 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50306 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50307 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
50308 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50309 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50310 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
50311 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
50312 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50313 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50314 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
50315 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50316 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50317 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
50318 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
50319 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50320 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50321 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
50322 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50323 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50324 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
50325 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
50326 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50327 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50328 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
50329 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50330 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50331 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
50332 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
50333 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50334 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50335 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
50336 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50337 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50338 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
50339 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
50340 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50341 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50342 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
50343 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50344 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50345 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
50346 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
50347 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50348 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50349 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
50350 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50351 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50352 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
50353 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
50354 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50355 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50356 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
50357 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50358 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50359 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
50360 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
50361 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50362 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50363 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
50364 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50365 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50366 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
50367 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
50368 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50369 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50370 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
50371 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50372 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50373 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
50374 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
50375 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50376 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50377 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
50378 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50379 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50380 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
50381 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
50382 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50383 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50384 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
50385 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50386 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50387 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
50388 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
50389 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
50390 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
50391 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
50392 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
50393 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
50394 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
50395 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
50396 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
50397 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
50398 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
50399 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
50400 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
50401 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
50402 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
50403 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
50404 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
50405 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
50406 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
50407 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
50408 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
50409 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
50410 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
50411 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
50412 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
50413 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
50414 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
50415 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
50416 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
50417 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
50418 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
50419 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
50420 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
50421 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
50422 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
50423 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
50424 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
50425 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
50426 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
50427 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
50428 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
50429 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
50430 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
50431 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
50432 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
50433 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
50434 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
50435 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
50436 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
50437 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
50438 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
50439 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
50440 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
50441 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
50442 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
50443 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
50444 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
50445 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
50446 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
50447 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
50448 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
50449 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
50450 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
50451 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
50452 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
50453 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
50454 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
50455 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
50456 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
50457 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
50458 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
50459 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
50460 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
50461 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
50462 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
50463 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
50464 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
50465 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
50466 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
50467 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
50468 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
50469 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
50470 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
50471 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
50472 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
50473 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
50474 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
50475 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
50476 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
50477 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
50478 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
50479 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
50480 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
50481 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
50482 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
50483 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
50484 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
50485 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
50486 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
50487 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
50488 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
50489 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
50490 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
50491 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
50492 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
50493 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
50494 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
50495 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
50496 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
50497 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
50498 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
50499 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
50500 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
50501 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
50502 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
50503 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
50504 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
50505 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
50506 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
50507 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
50508 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
50509 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
50510 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
50511 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
50512 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
50513 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
50514 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
50515 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
50516 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
50517 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
50518 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
50519 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
50520 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
50521 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
50522 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
50523 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
50524 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
50525 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
50526 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
50527 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
50528 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
50529 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
50530 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
50531 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
50532 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
50533 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
50534 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
50535 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
50536 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
50537 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
50538 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
50539 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
50540 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
50541 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
50542 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
50543 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
50544 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
50545 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
50546 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
50547 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
50548 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
50549 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
50550 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
50551 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
50552 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
50553 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
50554 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
50555 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
50556 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
50557 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
50558 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
50559 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
50560 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
50561 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
50562 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
50563 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
50564 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
50565 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
50566 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
50567 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
50568 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
50569 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
50570 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
50571 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
50572 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
50573 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
50574 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
50575 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
50576 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
50577 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
50578 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
50579 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
50580 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
50581 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
50582 | //AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
50583 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
50584 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
50585 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
50586 | #define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
50587 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
50588 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
50589 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
50590 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
50591 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
50592 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
50593 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
50594 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
50595 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
50596 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
50597 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
50598 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
50599 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
50600 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
50601 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
50602 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
50603 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
50604 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
50605 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
50606 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
50607 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
50608 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
50609 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
50610 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
50611 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
50612 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
50613 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
50614 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
50615 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
50616 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
50617 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
50618 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
50619 | //AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
50620 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
50621 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
50622 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
50623 | #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
50624 | //AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS |
50625 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
50626 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
50627 | //AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
50628 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
50629 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
50630 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
50631 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
50632 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
50633 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
50634 | //AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
50635 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
50636 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
50637 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
50638 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
50639 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
50640 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
50641 | //AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
50642 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
50643 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
50644 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
50645 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
50646 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
50647 | #define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
50648 | |
50649 | |
50650 | // addressBlock: azf0endpoint5_endpointind |
50651 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
50652 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
50653 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
50654 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
50655 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
50656 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
50657 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
50658 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
50659 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
50660 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
50661 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
50662 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
50663 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
50664 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
50665 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
50666 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
50667 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
50668 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
50669 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
50670 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
50671 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
50672 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
50673 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
50674 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
50675 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
50676 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
50677 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
50678 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
50679 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
50680 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
50681 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
50682 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
50683 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
50684 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
50685 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
50686 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
50687 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
50688 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
50689 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
50690 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
50691 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
50692 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
50693 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
50694 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
50695 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
50696 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
50697 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
50698 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
50699 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
50700 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
50701 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
50702 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
50703 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
50704 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
50705 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
50706 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
50707 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
50708 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
50709 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
50710 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
50711 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
50712 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
50713 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
50714 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
50715 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
50716 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
50717 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
50718 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
50719 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
50720 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
50721 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
50722 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
50723 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
50724 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
50725 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
50726 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
50727 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
50728 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
50729 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
50730 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
50731 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
50732 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
50733 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
50734 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
50735 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
50736 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
50737 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
50738 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
50739 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
50740 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
50741 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
50742 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
50743 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
50744 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
50745 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
50746 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
50747 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
50748 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
50749 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
50750 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
50751 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
50752 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
50753 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
50754 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
50755 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
50756 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
50757 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
50758 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
50759 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
50760 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
50761 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
50762 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
50763 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
50764 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
50765 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
50766 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
50767 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
50768 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
50769 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
50770 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
50771 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
50772 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
50773 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
50774 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
50775 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
50776 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
50777 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
50778 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
50779 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
50780 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
50781 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
50782 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
50783 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
50784 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
50785 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
50786 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
50787 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
50788 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
50789 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
50790 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
50791 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
50792 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
50793 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
50794 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
50795 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
50796 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
50797 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
50798 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
50799 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
50800 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
50801 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
50802 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
50803 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
50804 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
50805 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
50806 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
50807 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
50808 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
50809 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
50810 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
50811 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
50812 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
50813 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
50814 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
50815 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
50816 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
50817 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
50818 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
50819 | #define 0x12 |
50820 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
50821 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
50822 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
50823 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
50824 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
50825 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
50826 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
50827 | #define 0x00FC0000L |
50828 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
50829 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
50830 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
50831 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
50832 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
50833 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50834 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50835 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
50836 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
50837 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50838 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50839 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
50840 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
50841 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
50842 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50843 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50844 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
50845 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50846 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50847 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
50848 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
50849 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50850 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50851 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
50852 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50853 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50854 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
50855 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
50856 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50857 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50858 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
50859 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50860 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50861 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
50862 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
50863 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50864 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50865 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
50866 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50867 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50868 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
50869 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
50870 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50871 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50872 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
50873 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50874 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50875 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
50876 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
50877 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50878 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50879 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
50880 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50881 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50882 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
50883 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
50884 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50885 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50886 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
50887 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50888 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50889 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
50890 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
50891 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50892 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50893 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
50894 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50895 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50896 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
50897 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
50898 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50899 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50900 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
50901 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50902 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50903 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
50904 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
50905 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50906 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50907 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
50908 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50909 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50910 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
50911 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
50912 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50913 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50914 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
50915 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50916 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50917 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
50918 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
50919 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50920 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50921 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
50922 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50923 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50924 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
50925 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
50926 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
50927 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
50928 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
50929 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
50930 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
50931 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
50932 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
50933 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
50934 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
50935 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
50936 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
50937 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
50938 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
50939 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
50940 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
50941 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
50942 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
50943 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
50944 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
50945 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
50946 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
50947 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
50948 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
50949 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
50950 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
50951 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
50952 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
50953 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
50954 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
50955 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
50956 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
50957 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
50958 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
50959 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
50960 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
50961 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
50962 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
50963 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
50964 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
50965 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
50966 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
50967 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
50968 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
50969 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
50970 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
50971 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
50972 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
50973 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
50974 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
50975 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
50976 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
50977 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
50978 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
50979 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
50980 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
50981 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
50982 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
50983 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
50984 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
50985 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
50986 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
50987 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
50988 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
50989 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
50990 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
50991 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
50992 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
50993 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
50994 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
50995 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
50996 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
50997 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
50998 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
50999 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
51000 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
51001 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
51002 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
51003 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
51004 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
51005 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
51006 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
51007 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
51008 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
51009 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
51010 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
51011 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
51012 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
51013 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
51014 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
51015 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
51016 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
51017 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
51018 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
51019 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
51020 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
51021 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
51022 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
51023 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
51024 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
51025 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
51026 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
51027 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
51028 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
51029 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
51030 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
51031 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
51032 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
51033 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
51034 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
51035 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
51036 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
51037 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
51038 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
51039 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
51040 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
51041 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
51042 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
51043 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
51044 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
51045 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
51046 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
51047 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
51048 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
51049 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
51050 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
51051 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
51052 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
51053 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
51054 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
51055 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
51056 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
51057 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
51058 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
51059 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
51060 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
51061 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
51062 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
51063 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
51064 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
51065 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
51066 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
51067 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
51068 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
51069 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
51070 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
51071 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
51072 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
51073 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
51074 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
51075 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
51076 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
51077 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
51078 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
51079 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
51080 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
51081 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
51082 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
51083 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
51084 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
51085 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
51086 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
51087 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
51088 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
51089 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
51090 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
51091 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
51092 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
51093 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
51094 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
51095 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
51096 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
51097 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
51098 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
51099 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
51100 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
51101 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
51102 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
51103 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
51104 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
51105 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
51106 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
51107 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
51108 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
51109 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
51110 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
51111 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
51112 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
51113 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
51114 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
51115 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
51116 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
51117 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
51118 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
51119 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
51120 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
51121 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
51122 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
51123 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
51124 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
51125 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
51126 | //AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
51127 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
51128 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
51129 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
51130 | #define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
51131 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
51132 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
51133 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
51134 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
51135 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
51136 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
51137 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
51138 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
51139 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
51140 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
51141 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
51142 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
51143 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
51144 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
51145 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
51146 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
51147 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
51148 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
51149 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
51150 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
51151 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
51152 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
51153 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
51154 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
51155 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
51156 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
51157 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
51158 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
51159 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
51160 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
51161 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
51162 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
51163 | //AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
51164 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
51165 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
51166 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
51167 | #define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
51168 | //AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS |
51169 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
51170 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
51171 | //AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
51172 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
51173 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
51174 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
51175 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
51176 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
51177 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
51178 | //AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
51179 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
51180 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
51181 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
51182 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
51183 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
51184 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
51185 | //AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
51186 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
51187 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
51188 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
51189 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
51190 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
51191 | #define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
51192 | |
51193 | |
51194 | // addressBlock: azf0endpoint6_endpointind |
51195 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
51196 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
51197 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
51198 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
51199 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
51200 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
51201 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
51202 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
51203 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
51204 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
51205 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
51206 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
51207 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
51208 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
51209 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
51210 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
51211 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
51212 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
51213 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
51214 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
51215 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
51216 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
51217 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
51218 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
51219 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
51220 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
51221 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
51222 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
51223 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
51224 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
51225 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
51226 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
51227 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
51228 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
51229 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
51230 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
51231 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
51232 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
51233 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
51234 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
51235 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
51236 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
51237 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
51238 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
51239 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
51240 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
51241 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
51242 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
51243 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
51244 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
51245 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
51246 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
51247 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
51248 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
51249 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
51250 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
51251 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
51252 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
51253 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
51254 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
51255 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
51256 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
51257 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
51258 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
51259 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
51260 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
51261 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
51262 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
51263 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
51264 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
51265 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
51266 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
51267 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
51268 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
51269 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
51270 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
51271 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
51272 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
51273 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
51274 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
51275 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
51276 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
51277 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
51278 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
51279 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
51280 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
51281 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
51282 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
51283 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
51284 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
51285 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
51286 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
51287 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
51288 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
51289 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
51290 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
51291 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
51292 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
51293 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
51294 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
51295 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
51296 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
51297 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
51298 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
51299 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
51300 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
51301 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
51302 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
51303 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
51304 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
51305 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
51306 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
51307 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
51308 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
51309 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
51310 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
51311 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
51312 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
51313 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
51314 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
51315 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
51316 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
51317 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
51318 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
51319 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
51320 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
51321 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
51322 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
51323 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
51324 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
51325 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
51326 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
51327 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
51328 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
51329 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
51330 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
51331 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
51332 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
51333 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
51334 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
51335 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
51336 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
51337 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
51338 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
51339 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
51340 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
51341 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
51342 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
51343 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
51344 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
51345 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
51346 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
51347 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
51348 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
51349 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
51350 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
51351 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
51352 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
51353 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
51354 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
51355 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
51356 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
51357 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
51358 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
51359 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
51360 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
51361 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
51362 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
51363 | #define 0x12 |
51364 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
51365 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
51366 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
51367 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
51368 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
51369 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
51370 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
51371 | #define 0x00FC0000L |
51372 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
51373 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
51374 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
51375 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
51376 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
51377 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51378 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51379 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
51380 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
51381 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51382 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51383 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
51384 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
51385 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
51386 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51387 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51388 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
51389 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51390 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51391 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
51392 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
51393 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51394 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51395 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
51396 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51397 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51398 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
51399 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
51400 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51401 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51402 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
51403 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51404 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51405 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
51406 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
51407 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51408 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51409 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
51410 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51411 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51412 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
51413 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
51414 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51415 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51416 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
51417 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51418 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51419 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
51420 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
51421 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51422 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51423 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
51424 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51425 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51426 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
51427 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
51428 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51429 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51430 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
51431 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51432 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51433 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
51434 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
51435 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51436 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51437 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
51438 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51439 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51440 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
51441 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
51442 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51443 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51444 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
51445 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51446 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51447 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
51448 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
51449 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51450 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51451 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
51452 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51453 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51454 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
51455 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
51456 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51457 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51458 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
51459 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51460 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51461 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
51462 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
51463 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51464 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51465 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
51466 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51467 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51468 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
51469 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
51470 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51471 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51472 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
51473 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51474 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51475 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
51476 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
51477 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
51478 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
51479 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
51480 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
51481 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
51482 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
51483 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
51484 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
51485 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
51486 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
51487 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
51488 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
51489 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
51490 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
51491 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
51492 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
51493 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
51494 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
51495 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
51496 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
51497 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
51498 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
51499 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
51500 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
51501 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
51502 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
51503 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
51504 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
51505 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
51506 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
51507 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
51508 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
51509 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
51510 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
51511 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
51512 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
51513 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
51514 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
51515 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
51516 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
51517 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
51518 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
51519 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
51520 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
51521 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
51522 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
51523 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
51524 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
51525 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
51526 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
51527 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
51528 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
51529 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
51530 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
51531 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
51532 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
51533 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
51534 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
51535 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
51536 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
51537 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
51538 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
51539 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
51540 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
51541 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
51542 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
51543 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
51544 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
51545 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
51546 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
51547 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
51548 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
51549 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
51550 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
51551 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
51552 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
51553 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
51554 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
51555 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
51556 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
51557 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
51558 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
51559 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
51560 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
51561 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
51562 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
51563 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
51564 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
51565 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
51566 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
51567 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
51568 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
51569 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
51570 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
51571 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
51572 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
51573 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
51574 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
51575 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
51576 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
51577 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
51578 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
51579 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
51580 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
51581 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
51582 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
51583 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
51584 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
51585 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
51586 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
51587 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
51588 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
51589 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
51590 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
51591 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
51592 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
51593 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
51594 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
51595 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
51596 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
51597 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
51598 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
51599 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
51600 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
51601 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
51602 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
51603 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
51604 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
51605 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
51606 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
51607 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
51608 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
51609 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
51610 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
51611 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
51612 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
51613 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
51614 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
51615 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
51616 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
51617 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
51618 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
51619 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
51620 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
51621 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
51622 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
51623 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
51624 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
51625 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
51626 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
51627 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
51628 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
51629 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
51630 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
51631 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
51632 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
51633 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
51634 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
51635 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
51636 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
51637 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
51638 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
51639 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
51640 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
51641 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
51642 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
51643 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
51644 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
51645 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
51646 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
51647 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
51648 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
51649 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
51650 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
51651 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
51652 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
51653 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
51654 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
51655 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
51656 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
51657 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
51658 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
51659 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
51660 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
51661 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
51662 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
51663 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
51664 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
51665 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
51666 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
51667 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
51668 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
51669 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
51670 | //AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
51671 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
51672 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
51673 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
51674 | #define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
51675 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
51676 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
51677 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
51678 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
51679 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
51680 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
51681 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
51682 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
51683 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
51684 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
51685 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
51686 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
51687 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
51688 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
51689 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
51690 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
51691 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
51692 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
51693 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
51694 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
51695 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
51696 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
51697 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
51698 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
51699 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
51700 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
51701 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
51702 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
51703 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
51704 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
51705 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
51706 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
51707 | //AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
51708 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
51709 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
51710 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
51711 | #define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
51712 | //AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS |
51713 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
51714 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
51715 | //AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
51716 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
51717 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
51718 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
51719 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
51720 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
51721 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
51722 | //AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
51723 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
51724 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
51725 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
51726 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
51727 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
51728 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
51729 | //AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
51730 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
51731 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
51732 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
51733 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
51734 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
51735 | #define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
51736 | |
51737 | |
51738 | // addressBlock: azf0endpoint7_endpointind |
51739 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
51740 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
51741 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
51742 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
51743 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
51744 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
51745 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
51746 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
51747 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
51748 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
51749 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
51750 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
51751 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
51752 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
51753 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
51754 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
51755 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
51756 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
51757 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
51758 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
51759 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
51760 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
51761 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
51762 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
51763 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
51764 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
51765 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
51766 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
51767 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
51768 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT |
51769 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
51770 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
51771 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
51772 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
51773 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
51774 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
51775 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
51776 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
51777 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
51778 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
51779 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
51780 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
51781 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
51782 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
51783 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
51784 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
51785 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
51786 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER |
51787 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
51788 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
51789 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
51790 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
51791 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
51792 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
51793 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
51794 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
51795 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
51796 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
51797 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
51798 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
51799 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
51800 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
51801 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
51802 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
51803 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
51804 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
51805 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
51806 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
51807 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS |
51808 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
51809 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
51810 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
51811 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
51812 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
51813 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
51814 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
51815 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL |
51816 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
51817 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
51818 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L |
51819 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L |
51820 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE |
51821 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
51822 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL |
51823 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING |
51824 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
51825 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
51826 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
51827 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
51828 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L |
51829 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L |
51830 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L |
51831 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L |
51832 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA |
51833 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
51834 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL |
51835 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN |
51836 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
51837 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL |
51838 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX |
51839 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
51840 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL |
51841 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
51842 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
51843 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
51844 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
51845 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
51846 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
51847 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
51848 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
51849 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
51850 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
51851 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
51852 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
51853 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
51854 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
51855 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
51856 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
51857 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
51858 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
51859 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
51860 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
51861 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
51862 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
51863 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
51864 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
51865 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
51866 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
51867 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
51868 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES |
51869 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
51870 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
51871 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
51872 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
51873 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
51874 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
51875 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
51876 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
51877 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
51878 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
51879 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
51880 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
51881 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
51882 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
51883 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
51884 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
51885 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
51886 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
51887 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
51888 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
51889 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
51890 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
51891 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE |
51892 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
51893 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
51894 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
51895 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
51896 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE |
51897 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
51898 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
51899 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL |
51900 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
51901 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L |
51902 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER |
51903 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
51904 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
51905 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
51906 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
51907 | #define 0x12 |
51908 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 |
51909 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
51910 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
51911 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL |
51912 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
51913 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L |
51914 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L |
51915 | #define 0x00FC0000L |
51916 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L |
51917 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L |
51918 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L |
51919 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 |
51920 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
51921 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51922 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51923 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
51924 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L |
51925 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51926 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51927 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L |
51928 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 |
51929 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
51930 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51931 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51932 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L |
51933 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51934 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51935 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 |
51936 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
51937 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51938 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51939 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L |
51940 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51941 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51942 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 |
51943 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
51944 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51945 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51946 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L |
51947 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51948 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51949 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 |
51950 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
51951 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51952 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51953 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L |
51954 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51955 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51956 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 |
51957 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
51958 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51959 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51960 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L |
51961 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51962 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51963 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 |
51964 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
51965 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51966 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51967 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L |
51968 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51969 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51970 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 |
51971 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
51972 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51973 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51974 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L |
51975 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51976 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51977 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 |
51978 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
51979 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51980 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51981 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L |
51982 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51983 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51984 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 |
51985 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
51986 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51987 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51988 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L |
51989 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51990 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51991 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 |
51992 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
51993 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
51994 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
51995 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L |
51996 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
51997 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
51998 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 |
51999 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
52000 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
52001 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
52002 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L |
52003 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
52004 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
52005 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 |
52006 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
52007 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
52008 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
52009 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L |
52010 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
52011 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
52012 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 |
52013 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
52014 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
52015 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
52016 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L |
52017 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L |
52018 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L |
52019 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE |
52020 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
52021 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
52022 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
52023 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
52024 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
52025 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
52026 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
52027 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
52028 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
52029 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
52030 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
52031 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
52032 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L |
52033 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L |
52034 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L |
52035 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L |
52036 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L |
52037 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L |
52038 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L |
52039 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L |
52040 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L |
52041 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L |
52042 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L |
52043 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L |
52044 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC |
52045 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
52046 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
52047 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL |
52048 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L |
52049 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR |
52050 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
52051 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
52052 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
52053 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
52054 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 |
52055 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
52056 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
52057 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL |
52058 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L |
52059 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 |
52060 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
52061 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL |
52062 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 |
52063 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
52064 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL |
52065 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 |
52066 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
52067 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL |
52068 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 |
52069 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
52070 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
52071 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
52072 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
52073 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL |
52074 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L |
52075 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L |
52076 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L |
52077 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 |
52078 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
52079 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
52080 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
52081 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
52082 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL |
52083 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L |
52084 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L |
52085 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L |
52086 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 |
52087 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
52088 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
52089 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
52090 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
52091 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL |
52092 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L |
52093 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L |
52094 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L |
52095 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 |
52096 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
52097 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
52098 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
52099 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
52100 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL |
52101 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L |
52102 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L |
52103 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L |
52104 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 |
52105 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
52106 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
52107 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL |
52108 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L |
52109 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL |
52110 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
52111 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
52112 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
52113 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
52114 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
52115 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
52116 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
52117 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
52118 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
52119 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
52120 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
52121 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
52122 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
52123 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
52124 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
52125 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
52126 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
52127 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
52128 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
52129 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
52130 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
52131 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
52132 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
52133 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
52134 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
52135 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
52136 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
52137 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
52138 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
52139 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
52140 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
52141 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
52142 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
52143 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
52144 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
52145 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
52146 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
52147 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
52148 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
52149 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
52150 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
52151 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L |
52152 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L |
52153 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L |
52154 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L |
52155 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L |
52156 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L |
52157 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L |
52158 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L |
52159 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L |
52160 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
52161 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
52162 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
52163 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE |
52164 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
52165 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L |
52166 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 |
52167 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
52168 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
52169 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L |
52170 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL |
52171 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 |
52172 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
52173 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
52174 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
52175 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
52176 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L |
52177 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L |
52178 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L |
52179 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L |
52180 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 |
52181 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
52182 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
52183 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL |
52184 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L |
52185 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 |
52186 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
52187 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
52188 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL |
52189 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L |
52190 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 |
52191 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
52192 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
52193 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
52194 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
52195 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL |
52196 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L |
52197 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L |
52198 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L |
52199 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 |
52200 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
52201 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
52202 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL |
52203 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L |
52204 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 |
52205 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
52206 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
52207 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL |
52208 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L |
52209 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 |
52210 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
52211 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
52212 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL |
52213 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L |
52214 | //AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 |
52215 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
52216 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
52217 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL |
52218 | #define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L |
52219 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO |
52220 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
52221 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL |
52222 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS |
52223 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
52224 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L |
52225 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
52226 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
52227 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
52228 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
52229 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
52230 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB |
52231 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
52232 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
52233 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
52234 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
52235 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
52236 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE |
52237 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 |
52238 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL |
52239 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED |
52240 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 |
52241 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 |
52242 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 |
52243 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 |
52244 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L |
52245 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L |
52246 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L |
52247 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L |
52248 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION |
52249 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 |
52250 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L |
52251 | //AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE |
52252 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 |
52253 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 |
52254 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L |
52255 | #define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L |
52256 | //AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS |
52257 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 |
52258 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L |
52259 | //AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS |
52260 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 |
52261 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 |
52262 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 |
52263 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L |
52264 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L |
52265 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L |
52266 | //AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS |
52267 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 |
52268 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 |
52269 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 |
52270 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L |
52271 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L |
52272 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L |
52273 | //AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS |
52274 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 |
52275 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 |
52276 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 |
52277 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L |
52278 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L |
52279 | #define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L |
52280 | |
52281 | |
52282 | // addressBlock: azf0inputendpoint0_inputendpointind |
52283 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52284 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52285 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52286 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52287 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52288 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
52289 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52290 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52291 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52292 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52293 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52294 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52295 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52296 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52297 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52298 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52299 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52300 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52301 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52302 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
52303 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52304 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52305 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52306 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52307 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52308 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52309 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52310 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52311 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52312 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
52313 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
52314 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
52315 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
52316 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
52317 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
52318 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
52319 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
52320 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
52321 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
52322 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
52323 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
52324 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
52325 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
52326 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
52327 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
52328 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
52329 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
52330 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
52331 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
52332 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
52333 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
52334 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
52335 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
52336 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
52337 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
52338 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
52339 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
52340 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
52341 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
52342 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
52343 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
52344 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
52345 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
52346 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
52347 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
52348 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
52349 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
52350 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
52351 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
52352 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
52353 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
52354 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
52355 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
52356 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
52357 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
52358 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
52359 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52360 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52361 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52362 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52363 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52364 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52365 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52366 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52367 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52368 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52369 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52370 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52371 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52372 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52373 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52374 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52375 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52376 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52377 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52378 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52379 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52380 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52381 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52382 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52383 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52384 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52385 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52386 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
52387 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
52388 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
52389 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
52390 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
52391 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
52392 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
52393 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
52394 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
52395 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
52396 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
52397 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
52398 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
52399 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
52400 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
52401 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
52402 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
52403 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
52404 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
52405 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
52406 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
52407 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
52408 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
52409 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
52410 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
52411 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
52412 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
52413 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
52414 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
52415 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
52416 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
52417 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
52418 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
52419 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
52420 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
52421 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
52422 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
52423 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
52424 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
52425 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
52426 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
52427 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
52428 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
52429 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
52430 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
52431 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
52432 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
52433 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
52434 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
52435 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
52436 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
52437 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
52438 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
52439 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
52440 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
52441 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
52442 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
52443 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
52444 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
52445 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
52446 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
52447 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
52448 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
52449 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
52450 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
52451 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
52452 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
52453 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
52454 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
52455 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
52456 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
52457 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
52458 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
52459 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
52460 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
52461 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
52462 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
52463 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
52464 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
52465 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
52466 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
52467 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
52468 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
52469 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
52470 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
52471 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
52472 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
52473 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
52474 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
52475 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
52476 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
52477 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
52478 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
52479 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
52480 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
52481 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
52482 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
52483 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
52484 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
52485 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
52486 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
52487 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
52488 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
52489 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
52490 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
52491 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
52492 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
52493 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
52494 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
52495 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
52496 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
52497 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
52498 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
52499 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
52500 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
52501 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
52502 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
52503 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
52504 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
52505 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
52506 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
52507 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
52508 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
52509 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
52510 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
52511 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
52512 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
52513 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
52514 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
52515 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
52516 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
52517 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
52518 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
52519 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
52520 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
52521 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
52522 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
52523 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
52524 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
52525 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
52526 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
52527 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
52528 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
52529 | //AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
52530 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
52531 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
52532 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
52533 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
52534 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
52535 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
52536 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
52537 | #define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
52538 | |
52539 | |
52540 | // addressBlock: azf0inputendpoint1_inputendpointind |
52541 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52542 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52543 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52544 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52545 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52546 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
52547 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52548 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52549 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52550 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52551 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52552 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52553 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52554 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52555 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52556 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52557 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52558 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52559 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52560 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
52561 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52562 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52563 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52564 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52565 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52566 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52567 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52568 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52569 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52570 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
52571 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
52572 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
52573 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
52574 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
52575 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
52576 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
52577 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
52578 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
52579 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
52580 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
52581 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
52582 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
52583 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
52584 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
52585 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
52586 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
52587 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
52588 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
52589 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
52590 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
52591 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
52592 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
52593 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
52594 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
52595 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
52596 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
52597 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
52598 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
52599 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
52600 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
52601 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
52602 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
52603 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
52604 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
52605 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
52606 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
52607 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
52608 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
52609 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
52610 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
52611 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
52612 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
52613 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
52614 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
52615 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
52616 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
52617 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52618 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52619 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52620 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52621 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52622 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52623 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52624 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52625 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52626 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52627 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52628 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52629 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52630 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52631 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52632 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52633 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52634 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52635 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52636 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52637 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52638 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52639 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52640 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52641 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52642 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52643 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52644 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
52645 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
52646 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
52647 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
52648 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
52649 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
52650 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
52651 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
52652 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
52653 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
52654 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
52655 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
52656 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
52657 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
52658 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
52659 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
52660 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
52661 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
52662 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
52663 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
52664 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
52665 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
52666 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
52667 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
52668 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
52669 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
52670 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
52671 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
52672 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
52673 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
52674 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
52675 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
52676 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
52677 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
52678 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
52679 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
52680 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
52681 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
52682 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
52683 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
52684 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
52685 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
52686 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
52687 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
52688 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
52689 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
52690 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
52691 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
52692 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
52693 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
52694 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
52695 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
52696 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
52697 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
52698 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
52699 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
52700 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
52701 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
52702 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
52703 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
52704 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
52705 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
52706 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
52707 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
52708 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
52709 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
52710 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
52711 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
52712 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
52713 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
52714 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
52715 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
52716 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
52717 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
52718 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
52719 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
52720 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
52721 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
52722 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
52723 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
52724 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
52725 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
52726 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
52727 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
52728 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
52729 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
52730 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
52731 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
52732 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
52733 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
52734 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
52735 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
52736 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
52737 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
52738 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
52739 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
52740 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
52741 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
52742 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
52743 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
52744 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
52745 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
52746 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
52747 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
52748 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
52749 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
52750 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
52751 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
52752 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
52753 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
52754 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
52755 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
52756 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
52757 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
52758 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
52759 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
52760 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
52761 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
52762 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
52763 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
52764 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
52765 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
52766 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
52767 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
52768 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
52769 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
52770 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
52771 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
52772 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
52773 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
52774 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
52775 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
52776 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
52777 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
52778 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
52779 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
52780 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
52781 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
52782 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
52783 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
52784 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
52785 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
52786 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
52787 | //AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
52788 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
52789 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
52790 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
52791 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
52792 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
52793 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
52794 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
52795 | #define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
52796 | |
52797 | |
52798 | // addressBlock: azf0inputendpoint2_inputendpointind |
52799 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52800 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52801 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52802 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52803 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52804 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
52805 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52806 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52807 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52808 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52809 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52810 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52811 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52812 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52813 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52814 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52815 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52816 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52817 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52818 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
52819 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52820 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52821 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52822 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52823 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52824 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52825 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52826 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52827 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52828 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
52829 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
52830 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
52831 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
52832 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
52833 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
52834 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
52835 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
52836 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
52837 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
52838 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
52839 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
52840 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
52841 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
52842 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
52843 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
52844 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
52845 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
52846 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
52847 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
52848 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
52849 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
52850 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
52851 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
52852 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
52853 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
52854 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
52855 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
52856 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
52857 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
52858 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
52859 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
52860 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
52861 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
52862 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
52863 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
52864 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
52865 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
52866 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
52867 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
52868 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
52869 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
52870 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
52871 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
52872 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
52873 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
52874 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
52875 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
52876 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
52877 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
52878 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
52879 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
52880 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
52881 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
52882 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
52883 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
52884 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
52885 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
52886 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
52887 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
52888 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
52889 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
52890 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
52891 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
52892 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
52893 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
52894 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
52895 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
52896 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
52897 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
52898 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
52899 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
52900 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
52901 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
52902 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
52903 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
52904 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
52905 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
52906 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
52907 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
52908 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
52909 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
52910 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
52911 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
52912 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
52913 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
52914 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
52915 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
52916 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
52917 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
52918 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
52919 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
52920 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
52921 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
52922 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
52923 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
52924 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
52925 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
52926 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
52927 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
52928 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
52929 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
52930 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
52931 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
52932 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
52933 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
52934 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
52935 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
52936 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
52937 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
52938 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
52939 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
52940 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
52941 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
52942 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
52943 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
52944 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
52945 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
52946 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
52947 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
52948 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
52949 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
52950 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
52951 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
52952 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
52953 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
52954 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
52955 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
52956 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
52957 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
52958 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
52959 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
52960 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
52961 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
52962 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
52963 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
52964 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
52965 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
52966 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
52967 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
52968 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
52969 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
52970 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
52971 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
52972 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
52973 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
52974 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
52975 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
52976 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
52977 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
52978 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
52979 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
52980 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
52981 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
52982 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
52983 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
52984 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
52985 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
52986 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
52987 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
52988 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
52989 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
52990 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
52991 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
52992 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
52993 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
52994 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
52995 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
52996 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
52997 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
52998 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
52999 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
53000 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
53001 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
53002 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
53003 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
53004 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
53005 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
53006 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
53007 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
53008 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
53009 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
53010 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
53011 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
53012 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
53013 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
53014 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
53015 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
53016 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
53017 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
53018 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
53019 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
53020 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
53021 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
53022 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
53023 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
53024 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
53025 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
53026 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
53027 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
53028 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
53029 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
53030 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
53031 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
53032 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
53033 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
53034 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
53035 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
53036 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
53037 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
53038 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
53039 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
53040 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
53041 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
53042 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
53043 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
53044 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
53045 | //AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
53046 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
53047 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
53048 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
53049 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
53050 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
53051 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
53052 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
53053 | #define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
53054 | |
53055 | |
53056 | // addressBlock: azf0inputendpoint3_inputendpointind |
53057 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53058 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53059 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53060 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53061 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53062 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
53063 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53064 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53065 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53066 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53067 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53068 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53069 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53070 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53071 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53072 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53073 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53074 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53075 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53076 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
53077 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53078 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53079 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53080 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53081 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53082 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53083 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53084 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53085 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53086 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
53087 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
53088 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
53089 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
53090 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
53091 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
53092 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
53093 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
53094 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
53095 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
53096 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
53097 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
53098 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
53099 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
53100 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
53101 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
53102 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
53103 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
53104 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
53105 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
53106 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
53107 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
53108 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
53109 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
53110 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
53111 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
53112 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
53113 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
53114 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
53115 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
53116 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
53117 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
53118 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
53119 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
53120 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
53121 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
53122 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
53123 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
53124 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
53125 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
53126 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
53127 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
53128 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
53129 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
53130 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
53131 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
53132 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
53133 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53134 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53135 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53136 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53137 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53138 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53139 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53140 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53141 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53142 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53143 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53144 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53145 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53146 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53147 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53148 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53149 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53150 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53151 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53152 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53153 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53154 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53155 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53156 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53157 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53158 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53159 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53160 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
53161 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
53162 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
53163 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
53164 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
53165 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
53166 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
53167 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
53168 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
53169 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
53170 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
53171 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
53172 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
53173 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
53174 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
53175 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
53176 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
53177 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
53178 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
53179 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
53180 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
53181 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
53182 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
53183 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
53184 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
53185 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
53186 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
53187 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
53188 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
53189 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
53190 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
53191 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
53192 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
53193 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
53194 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
53195 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
53196 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
53197 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
53198 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
53199 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
53200 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
53201 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
53202 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
53203 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
53204 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
53205 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
53206 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
53207 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
53208 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
53209 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
53210 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
53211 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
53212 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
53213 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
53214 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
53215 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
53216 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
53217 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
53218 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
53219 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
53220 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
53221 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
53222 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
53223 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
53224 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
53225 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
53226 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
53227 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
53228 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
53229 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
53230 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
53231 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
53232 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
53233 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
53234 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
53235 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
53236 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
53237 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
53238 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
53239 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
53240 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
53241 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
53242 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
53243 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
53244 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
53245 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
53246 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
53247 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
53248 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
53249 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
53250 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
53251 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
53252 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
53253 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
53254 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
53255 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
53256 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
53257 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
53258 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
53259 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
53260 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
53261 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
53262 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
53263 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
53264 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
53265 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
53266 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
53267 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
53268 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
53269 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
53270 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
53271 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
53272 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
53273 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
53274 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
53275 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
53276 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
53277 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
53278 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
53279 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
53280 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
53281 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
53282 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
53283 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
53284 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
53285 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
53286 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
53287 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
53288 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
53289 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
53290 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
53291 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
53292 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
53293 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
53294 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
53295 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
53296 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
53297 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
53298 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
53299 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
53300 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
53301 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
53302 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
53303 | //AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
53304 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
53305 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
53306 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
53307 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
53308 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
53309 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
53310 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
53311 | #define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
53312 | |
53313 | |
53314 | // addressBlock: azf0inputendpoint4_inputendpointind |
53315 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53316 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53317 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53318 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53319 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53320 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
53321 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53322 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53323 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53324 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53325 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53326 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53327 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53328 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53329 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53330 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53331 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53332 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53333 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53334 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
53335 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53336 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53337 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53338 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53339 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53340 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53341 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53342 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53343 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53344 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
53345 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
53346 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
53347 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
53348 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
53349 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
53350 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
53351 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
53352 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
53353 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
53354 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
53355 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
53356 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
53357 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
53358 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
53359 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
53360 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
53361 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
53362 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
53363 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
53364 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
53365 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
53366 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
53367 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
53368 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
53369 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
53370 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
53371 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
53372 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
53373 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
53374 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
53375 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
53376 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
53377 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
53378 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
53379 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
53380 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
53381 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
53382 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
53383 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
53384 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
53385 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
53386 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
53387 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
53388 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
53389 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
53390 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
53391 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53392 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53393 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53394 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53395 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53396 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53397 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53398 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53399 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53400 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53401 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53402 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53403 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53404 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53405 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53406 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53407 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53408 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53409 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53410 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53411 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53412 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53413 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53414 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53415 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53416 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53417 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53418 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
53419 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
53420 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
53421 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
53422 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
53423 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
53424 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
53425 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
53426 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
53427 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
53428 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
53429 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
53430 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
53431 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
53432 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
53433 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
53434 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
53435 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
53436 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
53437 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
53438 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
53439 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
53440 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
53441 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
53442 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
53443 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
53444 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
53445 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
53446 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
53447 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
53448 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
53449 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
53450 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
53451 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
53452 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
53453 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
53454 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
53455 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
53456 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
53457 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
53458 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
53459 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
53460 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
53461 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
53462 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
53463 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
53464 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
53465 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
53466 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
53467 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
53468 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
53469 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
53470 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
53471 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
53472 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
53473 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
53474 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
53475 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
53476 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
53477 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
53478 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
53479 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
53480 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
53481 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
53482 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
53483 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
53484 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
53485 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
53486 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
53487 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
53488 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
53489 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
53490 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
53491 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
53492 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
53493 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
53494 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
53495 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
53496 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
53497 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
53498 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
53499 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
53500 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
53501 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
53502 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
53503 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
53504 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
53505 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
53506 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
53507 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
53508 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
53509 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
53510 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
53511 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
53512 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
53513 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
53514 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
53515 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
53516 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
53517 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
53518 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
53519 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
53520 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
53521 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
53522 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
53523 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
53524 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
53525 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
53526 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
53527 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
53528 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
53529 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
53530 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
53531 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
53532 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
53533 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
53534 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
53535 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
53536 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
53537 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
53538 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
53539 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
53540 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
53541 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
53542 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
53543 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
53544 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
53545 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
53546 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
53547 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
53548 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
53549 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
53550 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
53551 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
53552 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
53553 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
53554 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
53555 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
53556 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
53557 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
53558 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
53559 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
53560 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
53561 | //AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
53562 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
53563 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
53564 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
53565 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
53566 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
53567 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
53568 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
53569 | #define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
53570 | |
53571 | |
53572 | // addressBlock: azf0inputendpoint5_inputendpointind |
53573 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53574 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53575 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53576 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53577 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53578 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
53579 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53580 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53581 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53582 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53583 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53584 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53585 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53586 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53587 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53588 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53589 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53590 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53591 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53592 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
53593 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53594 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53595 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53596 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53597 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53598 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53599 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53600 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53601 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53602 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
53603 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
53604 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
53605 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
53606 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
53607 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
53608 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
53609 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
53610 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
53611 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
53612 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
53613 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
53614 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
53615 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
53616 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
53617 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
53618 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
53619 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
53620 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
53621 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
53622 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
53623 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
53624 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
53625 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
53626 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
53627 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
53628 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
53629 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
53630 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
53631 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
53632 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
53633 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
53634 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
53635 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
53636 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
53637 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
53638 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
53639 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
53640 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
53641 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
53642 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
53643 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
53644 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
53645 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
53646 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
53647 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
53648 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
53649 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53650 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53651 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53652 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53653 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53654 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53655 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53656 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53657 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53658 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53659 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53660 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53661 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53662 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53663 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53664 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53665 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53666 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53667 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53668 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53669 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53670 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53671 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53672 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53673 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53674 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53675 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53676 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
53677 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
53678 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
53679 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
53680 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
53681 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
53682 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
53683 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
53684 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
53685 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
53686 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
53687 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
53688 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
53689 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
53690 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
53691 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
53692 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
53693 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
53694 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
53695 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
53696 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
53697 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
53698 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
53699 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
53700 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
53701 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
53702 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
53703 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
53704 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
53705 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
53706 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
53707 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
53708 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
53709 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
53710 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
53711 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
53712 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
53713 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
53714 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
53715 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
53716 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
53717 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
53718 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
53719 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
53720 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
53721 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
53722 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
53723 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
53724 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
53725 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
53726 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
53727 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
53728 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
53729 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
53730 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
53731 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
53732 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
53733 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
53734 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
53735 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
53736 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
53737 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
53738 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
53739 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
53740 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
53741 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
53742 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
53743 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
53744 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
53745 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
53746 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
53747 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
53748 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
53749 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
53750 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
53751 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
53752 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
53753 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
53754 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
53755 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
53756 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
53757 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
53758 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
53759 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
53760 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
53761 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
53762 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
53763 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
53764 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
53765 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
53766 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
53767 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
53768 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
53769 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
53770 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
53771 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
53772 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
53773 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
53774 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
53775 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
53776 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
53777 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
53778 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
53779 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
53780 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
53781 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
53782 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
53783 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
53784 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
53785 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
53786 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
53787 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
53788 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
53789 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
53790 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
53791 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
53792 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
53793 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
53794 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
53795 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
53796 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
53797 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
53798 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
53799 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
53800 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
53801 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
53802 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
53803 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
53804 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
53805 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
53806 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
53807 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
53808 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
53809 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
53810 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
53811 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
53812 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
53813 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
53814 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
53815 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
53816 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
53817 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
53818 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
53819 | //AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
53820 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
53821 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
53822 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
53823 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
53824 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
53825 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
53826 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
53827 | #define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
53828 | |
53829 | |
53830 | // addressBlock: azf0inputendpoint6_inputendpointind |
53831 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53832 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53833 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53834 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53835 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53836 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
53837 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53838 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53839 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53840 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53841 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53842 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53843 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53844 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53845 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53846 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53847 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53848 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53849 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53850 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
53851 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53852 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53853 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53854 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53855 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53856 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53857 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53858 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53859 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53860 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
53861 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
53862 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
53863 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
53864 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
53865 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
53866 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
53867 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
53868 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
53869 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
53870 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
53871 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
53872 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
53873 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
53874 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
53875 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
53876 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
53877 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
53878 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
53879 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
53880 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
53881 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
53882 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
53883 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
53884 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
53885 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
53886 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
53887 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
53888 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
53889 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
53890 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
53891 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
53892 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
53893 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
53894 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
53895 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
53896 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
53897 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
53898 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
53899 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
53900 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
53901 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
53902 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
53903 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
53904 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
53905 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
53906 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
53907 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
53908 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
53909 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
53910 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
53911 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
53912 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
53913 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
53914 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
53915 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
53916 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
53917 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
53918 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
53919 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
53920 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
53921 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
53922 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
53923 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
53924 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
53925 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
53926 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
53927 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
53928 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
53929 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
53930 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
53931 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
53932 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
53933 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
53934 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
53935 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
53936 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
53937 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
53938 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
53939 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
53940 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
53941 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
53942 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
53943 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
53944 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
53945 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
53946 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
53947 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
53948 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
53949 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
53950 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
53951 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
53952 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
53953 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
53954 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
53955 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
53956 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
53957 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
53958 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
53959 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
53960 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
53961 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
53962 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
53963 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
53964 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
53965 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
53966 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
53967 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
53968 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
53969 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
53970 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
53971 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
53972 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
53973 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
53974 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
53975 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
53976 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
53977 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
53978 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
53979 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
53980 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
53981 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
53982 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
53983 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
53984 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
53985 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
53986 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
53987 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
53988 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
53989 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
53990 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
53991 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
53992 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
53993 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
53994 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
53995 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
53996 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
53997 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
53998 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
53999 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
54000 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
54001 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
54002 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
54003 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
54004 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
54005 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
54006 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
54007 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
54008 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
54009 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
54010 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
54011 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
54012 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
54013 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
54014 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
54015 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
54016 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
54017 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
54018 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
54019 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
54020 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
54021 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
54022 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
54023 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
54024 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
54025 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
54026 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
54027 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
54028 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
54029 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
54030 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
54031 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
54032 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
54033 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
54034 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
54035 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
54036 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
54037 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
54038 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
54039 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
54040 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
54041 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
54042 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
54043 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
54044 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
54045 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
54046 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
54047 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
54048 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
54049 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
54050 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
54051 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
54052 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
54053 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
54054 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
54055 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
54056 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
54057 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
54058 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
54059 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
54060 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
54061 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
54062 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
54063 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
54064 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
54065 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
54066 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
54067 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
54068 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
54069 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
54070 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
54071 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
54072 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
54073 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
54074 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
54075 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
54076 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
54077 | //AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
54078 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
54079 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
54080 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
54081 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
54082 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
54083 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
54084 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
54085 | #define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
54086 | |
54087 | |
54088 | // addressBlock: azf0inputendpoint7_inputendpointind |
54089 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
54090 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
54091 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
54092 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
54093 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
54094 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
54095 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
54096 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
54097 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
54098 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
54099 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
54100 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
54101 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
54102 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
54103 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
54104 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
54105 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
54106 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
54107 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
54108 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L |
54109 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
54110 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
54111 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
54112 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
54113 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
54114 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
54115 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
54116 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
54117 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
54118 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT |
54119 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
54120 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
54121 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
54122 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
54123 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
54124 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
54125 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL |
54126 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L |
54127 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L |
54128 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L |
54129 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L |
54130 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L |
54131 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID |
54132 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
54133 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
54134 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL |
54135 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L |
54136 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER |
54137 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
54138 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
54139 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
54140 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
54141 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
54142 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
54143 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
54144 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
54145 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
54146 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
54147 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L |
54148 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L |
54149 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L |
54150 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L |
54151 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L |
54152 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L |
54153 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L |
54154 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L |
54155 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L |
54156 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L |
54157 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS |
54158 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
54159 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL |
54160 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES |
54161 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
54162 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
54163 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL |
54164 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L |
54165 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES |
54166 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
54167 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
54168 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
54169 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
54170 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
54171 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
54172 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
54173 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
54174 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
54175 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
54176 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
54177 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
54178 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
54179 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L |
54180 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L |
54181 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L |
54182 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L |
54183 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L |
54184 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L |
54185 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L |
54186 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L |
54187 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L |
54188 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L |
54189 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L |
54190 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L |
54191 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L |
54192 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES |
54193 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
54194 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
54195 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
54196 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
54197 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
54198 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
54199 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
54200 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
54201 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
54202 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
54203 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
54204 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L |
54205 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L |
54206 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L |
54207 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L |
54208 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L |
54209 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L |
54210 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L |
54211 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L |
54212 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L |
54213 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L |
54214 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L |
54215 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE |
54216 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
54217 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
54218 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL |
54219 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L |
54220 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE |
54221 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
54222 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
54223 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL |
54224 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L |
54225 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL |
54226 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 |
54227 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L |
54228 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE |
54229 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 |
54230 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 |
54231 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 |
54232 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 |
54233 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 |
54234 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc |
54235 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 |
54236 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 |
54237 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 |
54238 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 |
54239 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 |
54240 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c |
54241 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L |
54242 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L |
54243 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L |
54244 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L |
54245 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L |
54246 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L |
54247 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L |
54248 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L |
54249 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L |
54250 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L |
54251 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L |
54252 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L |
54253 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 |
54254 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 |
54255 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 |
54256 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 |
54257 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 |
54258 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 |
54259 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc |
54260 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 |
54261 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 |
54262 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 |
54263 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
54264 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
54265 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
54266 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L |
54267 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L |
54268 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L |
54269 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L |
54270 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L |
54271 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L |
54272 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L |
54273 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L |
54274 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L |
54275 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L |
54276 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L |
54277 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L |
54278 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR |
54279 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
54280 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
54281 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L |
54282 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L |
54283 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION |
54284 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
54285 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL |
54286 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL |
54287 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
54288 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
54289 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
54290 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L |
54291 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L |
54292 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L |
54293 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE |
54294 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
54295 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
54296 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL |
54297 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L |
54298 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT |
54299 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
54300 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
54301 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
54302 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
54303 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
54304 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
54305 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
54306 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
54307 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL |
54308 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L |
54309 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L |
54310 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L |
54311 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L |
54312 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L |
54313 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L |
54314 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L |
54315 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL |
54316 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 |
54317 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 |
54318 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L |
54319 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L |
54320 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB |
54321 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 |
54322 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL |
54323 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT |
54324 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 |
54325 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL |
54326 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL |
54327 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 |
54328 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 |
54329 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 |
54330 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 |
54331 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L |
54332 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L |
54333 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L |
54334 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L |
54335 | //AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME |
54336 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 |
54337 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 |
54338 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 |
54339 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f |
54340 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L |
54341 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L |
54342 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L |
54343 | #define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L |
54344 | |
54345 | #endif |
54346 | |