1 | /* |
2 | * Copyright (C) 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _dpcs_4_2_0_OFFSET_HEADER |
22 | #define |
23 | |
24 | |
25 | |
26 | // addressBlock: dpcssys_dpcssys_cr0_dispdec |
27 | // base address: 0x0 |
28 | #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 |
29 | #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 |
30 | #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 |
31 | #define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 |
32 | |
33 | |
34 | // addressBlock: dpcssys_dpcssys_cr1_dispdec |
35 | // base address: 0x360 |
36 | #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c |
37 | #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 |
38 | #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d |
39 | #define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 |
40 | |
41 | |
42 | // addressBlock: dpcssys_dpcssys_cr2_dispdec |
43 | // base address: 0x6c0 |
44 | #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 |
45 | #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 |
46 | #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 |
47 | #define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 |
48 | |
49 | |
50 | // addressBlock: dpcssys_dpcssys_cr3_dispdec |
51 | // base address: 0xa20 |
52 | #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc |
53 | #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 |
54 | #define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd |
55 | #define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 |
56 | |
57 | |
58 | // addressBlock: dpcssys_dpcssys_cr4_dispdec |
59 | // base address: 0xd80 |
60 | #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 |
61 | #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 |
62 | #define regDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 |
63 | #define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 |
64 | |
65 | |
66 | // addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec |
67 | // base address: 0x0 |
68 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 |
69 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
70 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 |
71 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
72 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 |
73 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
74 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 |
75 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
76 | #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 |
77 | #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
78 | #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 |
79 | #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
80 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 |
81 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
82 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 |
83 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
84 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 |
85 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
86 | #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 |
87 | #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 |
88 | #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a |
89 | #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 |
90 | #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b |
91 | #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
92 | #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c |
93 | #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
94 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d |
95 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
96 | #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 |
97 | #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 |
98 | |
99 | |
100 | // addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec |
101 | // base address: 0x1b0 |
102 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c |
103 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
104 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d |
105 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
106 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e |
107 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
108 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f |
109 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
110 | #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 |
111 | #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
112 | #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 |
113 | #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
114 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 |
115 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
116 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 |
117 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
118 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 |
119 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
120 | #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 |
121 | #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 |
122 | #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 |
123 | #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 |
124 | #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 |
125 | #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
126 | #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 |
127 | #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
128 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 |
129 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
130 | #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d |
131 | #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 |
132 | |
133 | |
134 | // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec |
135 | // base address: 0x0 |
136 | #define regRDPCSTX0_RDPCSTX_CNTL 0x2930 |
137 | #define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 |
138 | #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 |
139 | #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
140 | #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 |
141 | #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
142 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0x2933 |
143 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 |
144 | #define regRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 |
145 | #define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
146 | #define regRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 |
147 | #define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 |
148 | #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 |
149 | #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 |
150 | #define regRDPCSTX0_RDPCSTX_SCRATCH 0x2937 |
151 | #define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 |
152 | #define regRDPCSTX0_RDPCSTX_SPARE 0x2938 |
153 | #define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 |
154 | #define regRDPCSTX0_RDPCSTX_CNTL2 0x2939 |
155 | #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 |
156 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c |
157 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 |
158 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 |
159 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
160 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 |
161 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
162 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 |
163 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
164 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 |
165 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
166 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 |
167 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
168 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 |
169 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
170 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 |
171 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
172 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 |
173 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
174 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 |
175 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
176 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 |
177 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
178 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a |
179 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
180 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b |
181 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
182 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c |
183 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
184 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d |
185 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
186 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e |
187 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
188 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f |
189 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 |
190 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 |
191 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 |
192 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 |
193 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 |
194 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 |
195 | #define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 |
196 | #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 |
197 | #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 |
198 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 |
199 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 |
200 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 |
201 | #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 |
202 | #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 |
203 | #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 |
204 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 |
205 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 |
206 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 |
207 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 |
208 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a |
209 | #define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 |
210 | #define regRDPCSTX0_RDPCS_CNTL3 0x295c |
211 | #define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX 2 |
212 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x295d |
213 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 |
214 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x295e |
215 | #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 |
216 | |
217 | |
218 | // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec |
219 | // base address: 0x360 |
220 | #define regRDPCSTX1_RDPCSTX_CNTL 0x2a08 |
221 | #define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 |
222 | #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 |
223 | #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
224 | #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a |
225 | #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
226 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0x2a0b |
227 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 |
228 | #define regRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c |
229 | #define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
230 | #define regRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d |
231 | #define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 |
232 | #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e |
233 | #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 |
234 | #define regRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f |
235 | #define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 |
236 | #define regRDPCSTX1_RDPCSTX_SPARE 0x2a10 |
237 | #define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 |
238 | #define regRDPCSTX1_RDPCSTX_CNTL2 0x2a11 |
239 | #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 |
240 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 |
241 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 |
242 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 |
243 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
244 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 |
245 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
246 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a |
247 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
248 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b |
249 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
250 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c |
251 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
252 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d |
253 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
254 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e |
255 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
256 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f |
257 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
258 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 |
259 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
260 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 |
261 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
262 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 |
263 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
264 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 |
265 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
266 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 |
267 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
268 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 |
269 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
270 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 |
271 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
272 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 |
273 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 |
274 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 |
275 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 |
276 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 |
277 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 |
278 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a |
279 | #define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 |
280 | #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b |
281 | #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 |
282 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c |
283 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 |
284 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d |
285 | #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 |
286 | #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e |
287 | #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 |
288 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 |
289 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 |
290 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 |
291 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 |
292 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 |
293 | #define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 |
294 | #define regRDPCSTX1_RDPCS_CNTL3 0x2a34 |
295 | #define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX 2 |
296 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2a35 |
297 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 |
298 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2a36 |
299 | #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 |
300 | |
301 | |
302 | // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec |
303 | // base address: 0x6c0 |
304 | #define regRDPCSTX2_RDPCSTX_CNTL 0x2ae0 |
305 | #define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 |
306 | #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 |
307 | #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
308 | #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 |
309 | #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
310 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0x2ae3 |
311 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 |
312 | #define regRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 |
313 | #define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
314 | #define regRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 |
315 | #define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 |
316 | #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 |
317 | #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 |
318 | #define regRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7 |
319 | #define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 |
320 | #define regRDPCSTX2_RDPCSTX_SPARE 0x2ae8 |
321 | #define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 |
322 | #define regRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 |
323 | #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 |
324 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec |
325 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 |
326 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 |
327 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
328 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 |
329 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
330 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 |
331 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
332 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 |
333 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
334 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 |
335 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
336 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 |
337 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
338 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 |
339 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
340 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 |
341 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
342 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 |
343 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
344 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 |
345 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
346 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa |
347 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
348 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb |
349 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
350 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc |
351 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
352 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd |
353 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
354 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe |
355 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
356 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff |
357 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 |
358 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 |
359 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 |
360 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 |
361 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 |
362 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 |
363 | #define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 |
364 | #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 |
365 | #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 |
366 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 |
367 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 |
368 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 |
369 | #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 |
370 | #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 |
371 | #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 |
372 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 |
373 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 |
374 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 |
375 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 |
376 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a |
377 | #define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 |
378 | #define regRDPCSTX2_RDPCS_CNTL3 0x2b0c |
379 | #define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX 2 |
380 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2b0d |
381 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 |
382 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2b0e |
383 | #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 |
384 | |
385 | |
386 | // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec |
387 | // base address: 0xa20 |
388 | #define regRDPCSTX3_RDPCSTX_CNTL 0x2bb8 |
389 | #define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 |
390 | #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 |
391 | #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
392 | #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba |
393 | #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
394 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0x2bbb |
395 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 |
396 | #define regRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc |
397 | #define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
398 | #define regRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd |
399 | #define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 |
400 | #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe |
401 | #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 |
402 | #define regRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf |
403 | #define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 |
404 | #define regRDPCSTX3_RDPCSTX_SPARE 0x2bc0 |
405 | #define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 |
406 | #define regRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 |
407 | #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 |
408 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 |
409 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 |
410 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 |
411 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
412 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 |
413 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
414 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca |
415 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
416 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb |
417 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
418 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc |
419 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
420 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd |
421 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
422 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce |
423 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
424 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf |
425 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
426 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 |
427 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
428 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 |
429 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
430 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 |
431 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
432 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 |
433 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
434 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 |
435 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
436 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 |
437 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
438 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 |
439 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
440 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 |
441 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 |
442 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 |
443 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 |
444 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 |
445 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 |
446 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda |
447 | #define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 |
448 | #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb |
449 | #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 |
450 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc |
451 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 |
452 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd |
453 | #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 |
454 | #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde |
455 | #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 |
456 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 |
457 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 |
458 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 |
459 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 |
460 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 |
461 | #define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 |
462 | #define regRDPCSTX3_RDPCS_CNTL3 0x2be4 |
463 | #define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX 2 |
464 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2be5 |
465 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 |
466 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2be6 |
467 | #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 |
468 | |
469 | |
470 | // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec |
471 | // base address: 0xd80 |
472 | #define regRDPCSTX4_RDPCSTX_CNTL 0x2c90 |
473 | #define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 |
474 | #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 |
475 | #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 |
476 | #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 |
477 | #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 |
478 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA 0x2c93 |
479 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 |
480 | #define regRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 |
481 | #define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 |
482 | #define regRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 |
483 | #define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 |
484 | #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 |
485 | #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 |
486 | #define regRDPCSTX4_RDPCSTX_SCRATCH 0x2c97 |
487 | #define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 |
488 | #define regRDPCSTX4_RDPCSTX_SPARE 0x2c98 |
489 | #define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2 |
490 | #define regRDPCSTX4_RDPCSTX_CNTL2 0x2c99 |
491 | #define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 |
492 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c |
493 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 |
494 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 |
495 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 |
496 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 |
497 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 |
498 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 |
499 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 |
500 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 |
501 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 |
502 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 |
503 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 |
504 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 |
505 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 |
506 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 |
507 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 |
508 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 |
509 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 |
510 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 |
511 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 |
512 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 |
513 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 |
514 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa |
515 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 |
516 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab |
517 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 |
518 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac |
519 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 |
520 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad |
521 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 |
522 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae |
523 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 |
524 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf |
525 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 |
526 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 |
527 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 |
528 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 |
529 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 |
530 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 |
531 | #define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 |
532 | #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 |
533 | #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 |
534 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 |
535 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 |
536 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 |
537 | #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 |
538 | #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 |
539 | #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 |
540 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8 |
541 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2 |
542 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9 |
543 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2 |
544 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba |
545 | #define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2 |
546 | #define regRDPCSTX4_RDPCS_CNTL3 0x2cbc |
547 | #define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX 2 |
548 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2cbd |
549 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 |
550 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2cbe |
551 | #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 |
552 | |
553 | |
554 | // addressBlock: dpcssys_dcio_dcio_dispdec |
555 | // base address: 0x0 |
556 | #define regDC_GENERICA 0x2868 |
557 | #define regDC_GENERICA_BASE_IDX 2 |
558 | #define regDC_GENERICB 0x2869 |
559 | #define regDC_GENERICB_BASE_IDX 2 |
560 | #define regDCIO_CLOCK_CNTL 0x286a |
561 | #define regDCIO_CLOCK_CNTL_BASE_IDX 2 |
562 | #define regDC_REF_CLK_CNTL 0x286b |
563 | #define regDC_REF_CLK_CNTL_BASE_IDX 2 |
564 | #define regUNIPHYA_LINK_CNTL 0x286d |
565 | #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 |
566 | #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e |
567 | #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
568 | #define regUNIPHYB_LINK_CNTL 0x286f |
569 | #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 |
570 | #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 |
571 | #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
572 | #define regUNIPHYC_LINK_CNTL 0x2871 |
573 | #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 |
574 | #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 |
575 | #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
576 | #define regUNIPHYD_LINK_CNTL 0x2873 |
577 | #define regUNIPHYD_LINK_CNTL_BASE_IDX 2 |
578 | #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 |
579 | #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
580 | #define regUNIPHYE_LINK_CNTL 0x2875 |
581 | #define regUNIPHYE_LINK_CNTL_BASE_IDX 2 |
582 | #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 |
583 | #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
584 | #define regDCIO_WRCMD_DELAY 0x287e |
585 | #define regDCIO_WRCMD_DELAY_BASE_IDX 2 |
586 | #define regDC_PINSTRAPS 0x2880 |
587 | #define regDC_PINSTRAPS_BASE_IDX 2 |
588 | #define regINTERCEPT_STATE 0x2884 |
589 | #define regINTERCEPT_STATE_BASE_IDX 2 |
590 | #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b |
591 | #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 |
592 | #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c |
593 | #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 |
594 | #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d |
595 | #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 |
596 | #define regDCIO_SOFT_RESET 0x289e |
597 | #define regDCIO_SOFT_RESET_BASE_IDX 2 |
598 | |
599 | |
600 | // addressBlock: dpcssys_dcio_dcio_chip_dispdec |
601 | // base address: 0x0 |
602 | #define regDC_GPIO_GENERIC_MASK 0x28c8 |
603 | #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 |
604 | #define regDC_GPIO_GENERIC_A 0x28c9 |
605 | #define regDC_GPIO_GENERIC_A_BASE_IDX 2 |
606 | #define regDC_GPIO_GENERIC_EN 0x28ca |
607 | #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 |
608 | #define regDC_GPIO_GENERIC_Y 0x28cb |
609 | #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 |
610 | #define regDC_GPIO_DDC1_MASK 0x28d0 |
611 | #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 |
612 | #define regDC_GPIO_DDC1_A 0x28d1 |
613 | #define regDC_GPIO_DDC1_A_BASE_IDX 2 |
614 | #define regDC_GPIO_DDC1_EN 0x28d2 |
615 | #define regDC_GPIO_DDC1_EN_BASE_IDX 2 |
616 | #define regDC_GPIO_DDC1_Y 0x28d3 |
617 | #define regDC_GPIO_DDC1_Y_BASE_IDX 2 |
618 | #define regDC_GPIO_DDC2_MASK 0x28d4 |
619 | #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 |
620 | #define regDC_GPIO_DDC2_A 0x28d5 |
621 | #define regDC_GPIO_DDC2_A_BASE_IDX 2 |
622 | #define regDC_GPIO_DDC2_EN 0x28d6 |
623 | #define regDC_GPIO_DDC2_EN_BASE_IDX 2 |
624 | #define regDC_GPIO_DDC2_Y 0x28d7 |
625 | #define regDC_GPIO_DDC2_Y_BASE_IDX 2 |
626 | #define regDC_GPIO_DDC3_MASK 0x28d8 |
627 | #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 |
628 | #define regDC_GPIO_DDC3_A 0x28d9 |
629 | #define regDC_GPIO_DDC3_A_BASE_IDX 2 |
630 | #define regDC_GPIO_DDC3_EN 0x28da |
631 | #define regDC_GPIO_DDC3_EN_BASE_IDX 2 |
632 | #define regDC_GPIO_DDC3_Y 0x28db |
633 | #define regDC_GPIO_DDC3_Y_BASE_IDX 2 |
634 | #define regDC_GPIO_DDC4_MASK 0x28dc |
635 | #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 |
636 | #define regDC_GPIO_DDC4_A 0x28dd |
637 | #define regDC_GPIO_DDC4_A_BASE_IDX 2 |
638 | #define regDC_GPIO_DDC4_EN 0x28de |
639 | #define regDC_GPIO_DDC4_EN_BASE_IDX 2 |
640 | #define regDC_GPIO_DDC4_Y 0x28df |
641 | #define regDC_GPIO_DDC4_Y_BASE_IDX 2 |
642 | #define regDC_GPIO_DDC5_MASK 0x28e0 |
643 | #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 |
644 | #define regDC_GPIO_DDC5_A 0x28e1 |
645 | #define regDC_GPIO_DDC5_A_BASE_IDX 2 |
646 | #define regDC_GPIO_DDC5_EN 0x28e2 |
647 | #define regDC_GPIO_DDC5_EN_BASE_IDX 2 |
648 | #define regDC_GPIO_DDC5_Y 0x28e3 |
649 | #define regDC_GPIO_DDC5_Y_BASE_IDX 2 |
650 | #define regDC_GPIO_DDCVGA_MASK 0x28e8 |
651 | #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 |
652 | #define regDC_GPIO_DDCVGA_A 0x28e9 |
653 | #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 |
654 | #define regDC_GPIO_DDCVGA_EN 0x28ea |
655 | #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 |
656 | #define regDC_GPIO_DDCVGA_Y 0x28eb |
657 | #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 |
658 | #define regDC_GPIO_GENLK_MASK 0x28f0 |
659 | #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 |
660 | #define regDC_GPIO_GENLK_A 0x28f1 |
661 | #define regDC_GPIO_GENLK_A_BASE_IDX 2 |
662 | #define regDC_GPIO_GENLK_EN 0x28f2 |
663 | #define regDC_GPIO_GENLK_EN_BASE_IDX 2 |
664 | #define regDC_GPIO_GENLK_Y 0x28f3 |
665 | #define regDC_GPIO_GENLK_Y_BASE_IDX 2 |
666 | #define regDC_GPIO_HPD_MASK 0x28f4 |
667 | #define regDC_GPIO_HPD_MASK_BASE_IDX 2 |
668 | #define regDC_GPIO_HPD_A 0x28f5 |
669 | #define regDC_GPIO_HPD_A_BASE_IDX 2 |
670 | #define regDC_GPIO_HPD_EN 0x28f6 |
671 | #define regDC_GPIO_HPD_EN_BASE_IDX 2 |
672 | #define regDC_GPIO_HPD_Y 0x28f7 |
673 | #define regDC_GPIO_HPD_Y_BASE_IDX 2 |
674 | #define regDC_GPIO_PWRSEQ0_EN 0x28fa |
675 | #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 |
676 | #define regDC_GPIO_PAD_STRENGTH_1 0x28fc |
677 | #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 |
678 | #define regDC_GPIO_PAD_STRENGTH_2 0x28fd |
679 | #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 |
680 | #define regPHY_AUX_CNTL 0x28ff |
681 | #define regPHY_AUX_CNTL_BASE_IDX 2 |
682 | #define regDC_GPIO_PWRSEQ1_EN 0x2902 |
683 | #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 |
684 | #define regDC_GPIO_TX12_EN 0x2915 |
685 | #define regDC_GPIO_TX12_EN_BASE_IDX 2 |
686 | #define regDC_GPIO_AUX_CTRL_0 0x2916 |
687 | #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 |
688 | #define regDC_GPIO_AUX_CTRL_1 0x2917 |
689 | #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 |
690 | #define regDC_GPIO_AUX_CTRL_2 0x2918 |
691 | #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 |
692 | #define regDC_GPIO_RXEN 0x2919 |
693 | #define regDC_GPIO_RXEN_BASE_IDX 2 |
694 | #define regDC_GPIO_PULLUPEN 0x291a |
695 | #define regDC_GPIO_PULLUPEN_BASE_IDX 2 |
696 | #define regDC_GPIO_AUX_CTRL_3 0x291b |
697 | #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 |
698 | #define regDC_GPIO_AUX_CTRL_4 0x291c |
699 | #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 |
700 | #define regDC_GPIO_AUX_CTRL_5 0x291d |
701 | #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 |
702 | #define regAUXI2C_PAD_ALL_PWR_OK 0x291e |
703 | #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 |
704 | |
705 | |
706 | // addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec |
707 | // base address: 0x360 |
708 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 |
709 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
710 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 |
711 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
712 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 |
713 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
714 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 |
715 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
716 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 |
717 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
718 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 |
719 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
720 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 |
721 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
722 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 |
723 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
724 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 |
725 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
726 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 |
727 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
728 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a |
729 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
730 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b |
731 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
732 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c |
733 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
734 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d |
735 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
736 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e |
737 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
738 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f |
739 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
740 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 |
741 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
742 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 |
743 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
744 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 |
745 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
746 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 |
747 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
748 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 |
749 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
750 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 |
751 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
752 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 |
753 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
754 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 |
755 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
756 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 |
757 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
758 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 |
759 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
760 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a |
761 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
762 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b |
763 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
764 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c |
765 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
766 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d |
767 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
768 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e |
769 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
770 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f |
771 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
772 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 |
773 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
774 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 |
775 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
776 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 |
777 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
778 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 |
779 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
780 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 |
781 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
782 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 |
783 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
784 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 |
785 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
786 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 |
787 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
788 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 |
789 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
790 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 |
791 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
792 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a |
793 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
794 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b |
795 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
796 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c |
797 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
798 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d |
799 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
800 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e |
801 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
802 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f |
803 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
804 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 |
805 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
806 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 |
807 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
808 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 |
809 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
810 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 |
811 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
812 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 |
813 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
814 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 |
815 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
816 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 |
817 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
818 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 |
819 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
820 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 |
821 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
822 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 |
823 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
824 | |
825 | |
826 | // addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec |
827 | // base address: 0x6c0 |
828 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 |
829 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
830 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 |
831 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
832 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada |
833 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
834 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb |
835 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
836 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc |
837 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
838 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add |
839 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
840 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade |
841 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
842 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf |
843 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
844 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 |
845 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
846 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 |
847 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
848 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 |
849 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
850 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 |
851 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
852 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 |
853 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
854 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 |
855 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
856 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 |
857 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
858 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 |
859 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
860 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 |
861 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
862 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 |
863 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
864 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea |
865 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
866 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb |
867 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
868 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec |
869 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
870 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed |
871 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
872 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee |
873 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
874 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef |
875 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
876 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 |
877 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
878 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 |
879 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
880 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 |
881 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
882 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 |
883 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
884 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 |
885 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
886 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 |
887 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
888 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 |
889 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
890 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 |
891 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
892 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 |
893 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
894 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 |
895 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
896 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa |
897 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
898 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb |
899 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
900 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc |
901 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
902 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd |
903 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
904 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe |
905 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
906 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff |
907 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
908 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 |
909 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
910 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 |
911 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
912 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 |
913 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
914 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 |
915 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
916 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 |
917 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
918 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 |
919 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
920 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 |
921 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
922 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 |
923 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
924 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 |
925 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
926 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 |
927 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
928 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a |
929 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
930 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b |
931 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
932 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c |
933 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
934 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d |
935 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
936 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e |
937 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
938 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f |
939 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
940 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 |
941 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
942 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 |
943 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
944 | |
945 | |
946 | // addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec |
947 | // base address: 0xa20 |
948 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 |
949 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
950 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 |
951 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
952 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 |
953 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
954 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 |
955 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
956 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 |
957 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
958 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 |
959 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
960 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 |
961 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
962 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 |
963 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
964 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 |
965 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
966 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 |
967 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
968 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba |
969 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
970 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb |
971 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
972 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc |
973 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
974 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd |
975 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
976 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe |
977 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
978 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf |
979 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
980 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 |
981 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
982 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 |
983 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
984 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 |
985 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
986 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 |
987 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
988 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 |
989 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
990 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 |
991 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
992 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 |
993 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
994 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 |
995 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
996 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 |
997 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
998 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 |
999 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
1000 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca |
1001 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
1002 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb |
1003 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
1004 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc |
1005 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
1006 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd |
1007 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
1008 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce |
1009 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
1010 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf |
1011 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
1012 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 |
1013 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
1014 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 |
1015 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
1016 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 |
1017 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
1018 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 |
1019 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
1020 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 |
1021 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
1022 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 |
1023 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
1024 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 |
1025 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
1026 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 |
1027 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
1028 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 |
1029 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
1030 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 |
1031 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
1032 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda |
1033 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
1034 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb |
1035 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
1036 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc |
1037 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
1038 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd |
1039 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
1040 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde |
1041 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
1042 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf |
1043 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
1044 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 |
1045 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
1046 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 |
1047 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
1048 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 |
1049 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
1050 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 |
1051 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
1052 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 |
1053 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
1054 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 |
1055 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
1056 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 |
1057 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
1058 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 |
1059 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
1060 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 |
1061 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
1062 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 |
1063 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
1064 | |
1065 | |
1066 | // addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec |
1067 | // base address: 0xd80 |
1068 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 |
1069 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
1070 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 |
1071 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
1072 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a |
1073 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
1074 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b |
1075 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
1076 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c |
1077 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
1078 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d |
1079 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
1080 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e |
1081 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
1082 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f |
1083 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
1084 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 |
1085 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
1086 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 |
1087 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
1088 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 |
1089 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
1090 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 |
1091 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
1092 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 |
1093 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
1094 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 |
1095 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
1096 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 |
1097 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
1098 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 |
1099 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
1100 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 |
1101 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
1102 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 |
1103 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
1104 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a |
1105 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
1106 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b |
1107 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
1108 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c |
1109 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
1110 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d |
1111 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
1112 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e |
1113 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
1114 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f |
1115 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
1116 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 |
1117 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
1118 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 |
1119 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
1120 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 |
1121 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
1122 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 |
1123 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
1124 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 |
1125 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
1126 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 |
1127 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
1128 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 |
1129 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
1130 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 |
1131 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
1132 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 |
1133 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
1134 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 |
1135 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
1136 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa |
1137 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
1138 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab |
1139 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
1140 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac |
1141 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
1142 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad |
1143 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
1144 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae |
1145 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
1146 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf |
1147 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
1148 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 |
1149 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
1150 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 |
1151 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
1152 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 |
1153 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
1154 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 |
1155 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
1156 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 |
1157 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
1158 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 |
1159 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
1160 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 |
1161 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
1162 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 |
1163 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
1164 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 |
1165 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
1166 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 |
1167 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
1168 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba |
1169 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
1170 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb |
1171 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
1172 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc |
1173 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
1174 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd |
1175 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
1176 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe |
1177 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
1178 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf |
1179 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
1180 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 |
1181 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
1182 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 |
1183 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
1184 | |
1185 | |
1186 | // addressBlock: dpcssys_cr0_rdpcstxcrind |
1187 | // base address: 0x0 |
1188 | #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000 |
1189 | #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001 |
1190 | #define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002 |
1191 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 |
1192 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 |
1193 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 |
1194 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 |
1195 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 |
1196 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 |
1197 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 |
1198 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a |
1199 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b |
1200 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c |
1201 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d |
1202 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3 0x000e |
1203 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4 0x000f |
1204 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 |
1205 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 |
1206 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 |
1207 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 |
1208 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 |
1209 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 |
1210 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 |
1211 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 |
1212 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 |
1213 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 |
1214 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3 0x001a |
1215 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4 0x001b |
1216 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5 0x001c |
1217 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d |
1218 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e |
1219 | #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN 0x001f |
1220 | #define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN 0x0020 |
1221 | #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT 0x0021 |
1222 | #define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN 0x0022 |
1223 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 |
1224 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 |
1225 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 |
1226 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 |
1227 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 |
1228 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 |
1229 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6 0x002a |
1230 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0 0x002b |
1231 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1 0x002c |
1232 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2 0x002d |
1233 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3 0x002e |
1234 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4 0x002f |
1235 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 |
1236 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 |
1237 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 |
1238 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 |
1239 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 |
1240 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 |
1241 | #define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN 0x0036 |
1242 | #define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN 0x0037 |
1243 | #define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN 0x0038 |
1244 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 |
1245 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a |
1246 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b |
1247 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c |
1248 | #define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL 0x0040 |
1249 | #define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL 0x0041 |
1250 | #define ixDPCSSYS_CR0_SUP_ANA_BG1 0x0042 |
1251 | #define ixDPCSSYS_CR0_SUP_ANA_BG2 0x0043 |
1252 | #define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS 0x0044 |
1253 | #define ixDPCSSYS_CR0_SUP_ANA_BG3 0x0045 |
1254 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1 0x0046 |
1255 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2 0x0047 |
1256 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD 0x0048 |
1257 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1 0x0049 |
1258 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2 0x004a |
1259 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3 0x004b |
1260 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1 0x004c |
1261 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2 0x004d |
1262 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3 0x004e |
1263 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4 0x004f |
1264 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5 0x0050 |
1265 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1 0x0051 |
1266 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2 0x0052 |
1267 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1 0x0053 |
1268 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2 0x0054 |
1269 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD 0x0055 |
1270 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1 0x0056 |
1271 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2 0x0057 |
1272 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3 0x0058 |
1273 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1 0x0059 |
1274 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2 0x005a |
1275 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3 0x005b |
1276 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4 0x005c |
1277 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5 0x005d |
1278 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1 0x005e |
1279 | #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2 0x005f |
1280 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 |
1281 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 |
1282 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 |
1283 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 |
1284 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 |
1285 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 |
1286 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 |
1287 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 |
1288 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 |
1289 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b |
1290 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d |
1291 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e |
1292 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f |
1293 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 |
1294 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 |
1295 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 |
1296 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 |
1297 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 |
1298 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 |
1299 | #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 |
1300 | #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 |
1301 | #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 |
1302 | #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a |
1303 | #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b |
1304 | #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD 0x007c |
1305 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG 0x0081 |
1306 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT 0x0082 |
1307 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 |
1308 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 |
1309 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 |
1310 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT 0x0086 |
1311 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT 0x0087 |
1312 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT 0x0088 |
1313 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 |
1314 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a |
1315 | #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b |
1316 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c |
1317 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d |
1318 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e |
1319 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f |
1320 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 |
1321 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 |
1322 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 |
1323 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT 0x0093 |
1324 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 |
1325 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 |
1326 | #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 |
1327 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 |
1328 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 |
1329 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 |
1330 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 |
1331 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 |
1332 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 |
1333 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 |
1334 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f |
1335 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 |
1336 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 |
1337 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 |
1338 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 |
1339 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 |
1340 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b |
1341 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d |
1342 | #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e |
1343 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 |
1344 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 |
1345 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 |
1346 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 |
1347 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 |
1348 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 |
1349 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 |
1350 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 |
1351 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 |
1352 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 |
1353 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a |
1354 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b |
1355 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c |
1356 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d |
1357 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e |
1358 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f |
1359 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 |
1360 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 |
1361 | #define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL 0x1032 |
1362 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 |
1363 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 |
1364 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 |
1365 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 |
1366 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 |
1367 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 |
1368 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 |
1369 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 |
1370 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 |
1371 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 |
1372 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a |
1373 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b |
1374 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c |
1375 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d |
1376 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e |
1377 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f |
1378 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 |
1379 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 |
1380 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 |
1381 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 |
1382 | #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 |
1383 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 |
1384 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 |
1385 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 |
1386 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 |
1387 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 |
1388 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 |
1389 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 |
1390 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 |
1391 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 |
1392 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0 0x10bb |
1393 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 |
1394 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 |
1395 | #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 |
1396 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS 0x10e0 |
1397 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD 0x10e1 |
1398 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS 0x10e2 |
1399 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1 0x10e3 |
1400 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2 0x10e4 |
1401 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC 0x10e5 |
1402 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1 0x10e6 |
1403 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE 0x10e7 |
1404 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 |
1405 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK 0x10e9 |
1406 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1 0x10ea |
1407 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2 0x10eb |
1408 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3 0x10ec |
1409 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2 0x10ed |
1410 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3 0x10ee |
1411 | #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4 0x10ef |
1412 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 |
1413 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 |
1414 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 |
1415 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 |
1416 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 |
1417 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 |
1418 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 |
1419 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 |
1420 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 |
1421 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 |
1422 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a |
1423 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b |
1424 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c |
1425 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d |
1426 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e |
1427 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f |
1428 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 |
1429 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 |
1430 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 |
1431 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 |
1432 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 |
1433 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 |
1434 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 |
1435 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 |
1436 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 |
1437 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 |
1438 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a |
1439 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b |
1440 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c |
1441 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d |
1442 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e |
1443 | #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA 0x111f |
1444 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 |
1445 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 |
1446 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 |
1447 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 |
1448 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 |
1449 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 |
1450 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 |
1451 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 |
1452 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 |
1453 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 |
1454 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a |
1455 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b |
1456 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c |
1457 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d |
1458 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e |
1459 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f |
1460 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 |
1461 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 |
1462 | #define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL 0x1132 |
1463 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 |
1464 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 |
1465 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 |
1466 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 |
1467 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 |
1468 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 |
1469 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 |
1470 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 |
1471 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 |
1472 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a |
1473 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b |
1474 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c |
1475 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d |
1476 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e |
1477 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f |
1478 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 |
1479 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL 0x1151 |
1480 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR 0x1152 |
1481 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 |
1482 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 |
1483 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 |
1484 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 |
1485 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 |
1486 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT 0x1158 |
1487 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ 0x1159 |
1488 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a |
1489 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b |
1490 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 |
1491 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 |
1492 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 |
1493 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 |
1494 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 |
1495 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 |
1496 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 |
1497 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 |
1498 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 |
1499 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 |
1500 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a |
1501 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b |
1502 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c |
1503 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d |
1504 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e |
1505 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f |
1506 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 |
1507 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 |
1508 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 |
1509 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 |
1510 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 |
1511 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 |
1512 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 |
1513 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 |
1514 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 |
1515 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 |
1516 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a |
1517 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b |
1518 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c |
1519 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d |
1520 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e |
1521 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f |
1522 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 |
1523 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 |
1524 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 |
1525 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 |
1526 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 |
1527 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 |
1528 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 |
1529 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 |
1530 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 |
1531 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 |
1532 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a |
1533 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b |
1534 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c |
1535 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d |
1536 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e |
1537 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f |
1538 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 |
1539 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 |
1540 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 |
1541 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 |
1542 | #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 |
1543 | #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 |
1544 | #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 |
1545 | #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 |
1546 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 |
1547 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 |
1548 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 |
1549 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 |
1550 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 |
1551 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 |
1552 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 |
1553 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 |
1554 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 |
1555 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 |
1556 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa |
1557 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab |
1558 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac |
1559 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad |
1560 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL 0x11ae |
1561 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af |
1562 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 |
1563 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 |
1564 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 |
1565 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 |
1566 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE 0x11b4 |
1567 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 |
1568 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 |
1569 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 |
1570 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 |
1571 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 |
1572 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba |
1573 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0 0x11bb |
1574 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1 0x11bc |
1575 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd |
1576 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be |
1577 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf |
1578 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 |
1579 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 |
1580 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 |
1581 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 |
1582 | #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 |
1583 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS 0x11e0 |
1584 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD 0x11e1 |
1585 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS 0x11e2 |
1586 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1 0x11e3 |
1587 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2 0x11e4 |
1588 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC 0x11e5 |
1589 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1 0x11e6 |
1590 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE 0x11e7 |
1591 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 |
1592 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK 0x11e9 |
1593 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1 0x11ea |
1594 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2 0x11eb |
1595 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3 0x11ec |
1596 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2 0x11ed |
1597 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3 0x11ee |
1598 | #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4 0x11ef |
1599 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1 0x11f0 |
1600 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2 0x11f1 |
1601 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES 0x11f2 |
1602 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL 0x11f3 |
1603 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1 0x11f4 |
1604 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2 0x11f5 |
1605 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ 0x11f6 |
1606 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1 0x11f7 |
1607 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2 0x11f8 |
1608 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF 0x11f9 |
1609 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1 0x11fa |
1610 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2 0x11fb |
1611 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3 0x11fc |
1612 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4 0x11fd |
1613 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC 0x11fe |
1614 | #define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1 0x11ff |
1615 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 |
1616 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 |
1617 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 |
1618 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 |
1619 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 |
1620 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 |
1621 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 |
1622 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 |
1623 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 |
1624 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 |
1625 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a |
1626 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b |
1627 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c |
1628 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d |
1629 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e |
1630 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f |
1631 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 |
1632 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 |
1633 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 |
1634 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 |
1635 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 |
1636 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 |
1637 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 |
1638 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 |
1639 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 |
1640 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 |
1641 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a |
1642 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b |
1643 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c |
1644 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d |
1645 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e |
1646 | #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA 0x121f |
1647 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 |
1648 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 |
1649 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 |
1650 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 |
1651 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 |
1652 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 |
1653 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 |
1654 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 |
1655 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 |
1656 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 |
1657 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a |
1658 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b |
1659 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c |
1660 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d |
1661 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e |
1662 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f |
1663 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 |
1664 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 |
1665 | #define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL 0x1232 |
1666 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 |
1667 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 |
1668 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 |
1669 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 |
1670 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 |
1671 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 |
1672 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 |
1673 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 |
1674 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 |
1675 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a |
1676 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b |
1677 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c |
1678 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d |
1679 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e |
1680 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f |
1681 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 |
1682 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL 0x1251 |
1683 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR 0x1252 |
1684 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 |
1685 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 |
1686 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 |
1687 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 |
1688 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 |
1689 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT 0x1258 |
1690 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ 0x1259 |
1691 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a |
1692 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b |
1693 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 |
1694 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 |
1695 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 |
1696 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 |
1697 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 |
1698 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 |
1699 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 |
1700 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 |
1701 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 |
1702 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 |
1703 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a |
1704 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b |
1705 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c |
1706 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d |
1707 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e |
1708 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f |
1709 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 |
1710 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 |
1711 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 |
1712 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 |
1713 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 |
1714 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 |
1715 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 |
1716 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 |
1717 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 |
1718 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 |
1719 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a |
1720 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b |
1721 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c |
1722 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d |
1723 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e |
1724 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f |
1725 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 |
1726 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 |
1727 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 |
1728 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 |
1729 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 |
1730 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 |
1731 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 |
1732 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 |
1733 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 |
1734 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 |
1735 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a |
1736 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b |
1737 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c |
1738 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d |
1739 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e |
1740 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f |
1741 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 |
1742 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 |
1743 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 |
1744 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 |
1745 | #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 |
1746 | #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 |
1747 | #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 |
1748 | #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 |
1749 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 |
1750 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 |
1751 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 |
1752 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 |
1753 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 |
1754 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 |
1755 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 |
1756 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 |
1757 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 |
1758 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 |
1759 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa |
1760 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab |
1761 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac |
1762 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad |
1763 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL 0x12ae |
1764 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af |
1765 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 |
1766 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 |
1767 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 |
1768 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 |
1769 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE 0x12b4 |
1770 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 |
1771 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 |
1772 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 |
1773 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 |
1774 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 |
1775 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba |
1776 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0 0x12bb |
1777 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1 0x12bc |
1778 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd |
1779 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be |
1780 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf |
1781 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 |
1782 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 |
1783 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 |
1784 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 |
1785 | #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 |
1786 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS 0x12e0 |
1787 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD 0x12e1 |
1788 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS 0x12e2 |
1789 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1 0x12e3 |
1790 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2 0x12e4 |
1791 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC 0x12e5 |
1792 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1 0x12e6 |
1793 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE 0x12e7 |
1794 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 |
1795 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK 0x12e9 |
1796 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1 0x12ea |
1797 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2 0x12eb |
1798 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3 0x12ec |
1799 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2 0x12ed |
1800 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3 0x12ee |
1801 | #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4 0x12ef |
1802 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1 0x12f0 |
1803 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2 0x12f1 |
1804 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES 0x12f2 |
1805 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL 0x12f3 |
1806 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1 0x12f4 |
1807 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2 0x12f5 |
1808 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ 0x12f6 |
1809 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1 0x12f7 |
1810 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2 0x12f8 |
1811 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF 0x12f9 |
1812 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1 0x12fa |
1813 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2 0x12fb |
1814 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3 0x12fc |
1815 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4 0x12fd |
1816 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC 0x12fe |
1817 | #define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1 0x12ff |
1818 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 |
1819 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 |
1820 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 |
1821 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 |
1822 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 |
1823 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 |
1824 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 |
1825 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f |
1826 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 |
1827 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 |
1828 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 |
1829 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 |
1830 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 |
1831 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b |
1832 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d |
1833 | #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e |
1834 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 |
1835 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 |
1836 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 |
1837 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 |
1838 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 |
1839 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 |
1840 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 |
1841 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 |
1842 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 |
1843 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 |
1844 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a |
1845 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b |
1846 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c |
1847 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d |
1848 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e |
1849 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f |
1850 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 |
1851 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 |
1852 | #define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL 0x1332 |
1853 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 |
1854 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 |
1855 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 |
1856 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 |
1857 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 |
1858 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 |
1859 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 |
1860 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 |
1861 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 |
1862 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 |
1863 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a |
1864 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b |
1865 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c |
1866 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d |
1867 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e |
1868 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f |
1869 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 |
1870 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 |
1871 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 |
1872 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 |
1873 | #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 |
1874 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 |
1875 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 |
1876 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 |
1877 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 |
1878 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 |
1879 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 |
1880 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 |
1881 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 |
1882 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 |
1883 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0 0x13bb |
1884 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 |
1885 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 |
1886 | #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 |
1887 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS 0x13e0 |
1888 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD 0x13e1 |
1889 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS 0x13e2 |
1890 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1 0x13e3 |
1891 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2 0x13e4 |
1892 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC 0x13e5 |
1893 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1 0x13e6 |
1894 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE 0x13e7 |
1895 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 |
1896 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK 0x13e9 |
1897 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1 0x13ea |
1898 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2 0x13eb |
1899 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3 0x13ec |
1900 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2 0x13ed |
1901 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3 0x13ee |
1902 | #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4 0x13ef |
1903 | #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL 0x2000 |
1904 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 |
1905 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 |
1906 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 |
1907 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 |
1908 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 |
1909 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 |
1910 | #define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 |
1911 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 |
1912 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 |
1913 | #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1 0x200a |
1914 | #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL 0x200b |
1915 | #define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE 0x200c |
1916 | #define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE 0x200d |
1917 | #define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA 0x200e |
1918 | #define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD 0x200f |
1919 | #define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 |
1920 | #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1 0x2011 |
1921 | #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2 0x2012 |
1922 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 |
1923 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 |
1924 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 |
1925 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 |
1926 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 |
1927 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 |
1928 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 |
1929 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 |
1930 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 |
1931 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 |
1932 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a |
1933 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b |
1934 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c |
1935 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d |
1936 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e |
1937 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f |
1938 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 |
1939 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 |
1940 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 |
1941 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 |
1942 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 |
1943 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 |
1944 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 |
1945 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 |
1946 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 |
1947 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 |
1948 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a |
1949 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b |
1950 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c |
1951 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d |
1952 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e |
1953 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f |
1954 | #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 |
1955 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 |
1956 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 |
1957 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 |
1958 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 |
1959 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 |
1960 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 |
1961 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 |
1962 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 |
1963 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 |
1964 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 |
1965 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a |
1966 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b |
1967 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c |
1968 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d |
1969 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e |
1970 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f |
1971 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 |
1972 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 |
1973 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 |
1974 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 |
1975 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 |
1976 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 |
1977 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 |
1978 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 |
1979 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 |
1980 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 |
1981 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a |
1982 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b |
1983 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c |
1984 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d |
1985 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e |
1986 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f |
1987 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 |
1988 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 |
1989 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 |
1990 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 |
1991 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 |
1992 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 |
1993 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 |
1994 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 |
1995 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 |
1996 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 |
1997 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a |
1998 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b |
1999 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP 0x302c |
2000 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d |
2001 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e |
2002 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f |
2003 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 |
2004 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 |
2005 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 |
2006 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 |
2007 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 |
2008 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 |
2009 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 |
2010 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 |
2011 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 |
2012 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 |
2013 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a |
2014 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b |
2015 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA 0x303c |
2016 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d |
2017 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e |
2018 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f |
2019 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 |
2020 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 |
2021 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 |
2022 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 |
2023 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 |
2024 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 |
2025 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 |
2026 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 |
2027 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 |
2028 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 |
2029 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a |
2030 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b |
2031 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c |
2032 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d |
2033 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e |
2034 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f |
2035 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 |
2036 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 |
2037 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 |
2038 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 |
2039 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 |
2040 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 |
2041 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 |
2042 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 |
2043 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 |
2044 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 |
2045 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a |
2046 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b |
2047 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 |
2048 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 |
2049 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 |
2050 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 |
2051 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 |
2052 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 |
2053 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 |
2054 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 |
2055 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 |
2056 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 |
2057 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a |
2058 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b |
2059 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c |
2060 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 |
2061 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 |
2062 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 |
2063 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 |
2064 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 |
2065 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 |
2066 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 |
2067 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 |
2068 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 |
2069 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 |
2070 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 |
2071 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 |
2072 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 |
2073 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 |
2074 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 |
2075 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 |
2076 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 |
2077 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 |
2078 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 |
2079 | #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 |
2080 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 |
2081 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 |
2082 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 |
2083 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 |
2084 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 |
2085 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 |
2086 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 |
2087 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 |
2088 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 |
2089 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 |
2090 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a |
2091 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b |
2092 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c |
2093 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d |
2094 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e |
2095 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f |
2096 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 |
2097 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 |
2098 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 |
2099 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 |
2100 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 |
2101 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 |
2102 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 |
2103 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 |
2104 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 |
2105 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 |
2106 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a |
2107 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b |
2108 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c |
2109 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d |
2110 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e |
2111 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f |
2112 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 |
2113 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 |
2114 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 |
2115 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 |
2116 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 |
2117 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 |
2118 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 |
2119 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 |
2120 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 |
2121 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 |
2122 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a |
2123 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b |
2124 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP 0x312c |
2125 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d |
2126 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e |
2127 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f |
2128 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 |
2129 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 |
2130 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 |
2131 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 |
2132 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 |
2133 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 |
2134 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 |
2135 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 |
2136 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 |
2137 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 |
2138 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a |
2139 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b |
2140 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA 0x313c |
2141 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d |
2142 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e |
2143 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f |
2144 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 |
2145 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 |
2146 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 |
2147 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 |
2148 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 |
2149 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 |
2150 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 |
2151 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 |
2152 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 |
2153 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 |
2154 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a |
2155 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b |
2156 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c |
2157 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d |
2158 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e |
2159 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f |
2160 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 |
2161 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 |
2162 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 |
2163 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 |
2164 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 |
2165 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 |
2166 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 |
2167 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 |
2168 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 |
2169 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 |
2170 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a |
2171 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b |
2172 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 |
2173 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 |
2174 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 |
2175 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 |
2176 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 |
2177 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 |
2178 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 |
2179 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 |
2180 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 |
2181 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 |
2182 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a |
2183 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b |
2184 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c |
2185 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 |
2186 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 |
2187 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 |
2188 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 |
2189 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 |
2190 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 |
2191 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 |
2192 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 |
2193 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 |
2194 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 |
2195 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 |
2196 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 |
2197 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 |
2198 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 |
2199 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 |
2200 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 |
2201 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 |
2202 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 |
2203 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 |
2204 | #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 |
2205 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 |
2206 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 |
2207 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 |
2208 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 |
2209 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 |
2210 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 |
2211 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 |
2212 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 |
2213 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 |
2214 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 |
2215 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a |
2216 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b |
2217 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c |
2218 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d |
2219 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e |
2220 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f |
2221 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 |
2222 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 |
2223 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 |
2224 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 |
2225 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 |
2226 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 |
2227 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 |
2228 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 |
2229 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 |
2230 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 |
2231 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a |
2232 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b |
2233 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c |
2234 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d |
2235 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e |
2236 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f |
2237 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 |
2238 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 |
2239 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 |
2240 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 |
2241 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 |
2242 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 |
2243 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 |
2244 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 |
2245 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 |
2246 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 |
2247 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a |
2248 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b |
2249 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP 0x322c |
2250 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d |
2251 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e |
2252 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f |
2253 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 |
2254 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 |
2255 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 |
2256 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 |
2257 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 |
2258 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 |
2259 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 |
2260 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 |
2261 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 |
2262 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 |
2263 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a |
2264 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b |
2265 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA 0x323c |
2266 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d |
2267 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e |
2268 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f |
2269 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 |
2270 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 |
2271 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 |
2272 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 |
2273 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 |
2274 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 |
2275 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 |
2276 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 |
2277 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 |
2278 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 |
2279 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a |
2280 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b |
2281 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c |
2282 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d |
2283 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e |
2284 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f |
2285 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 |
2286 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 |
2287 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 |
2288 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 |
2289 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 |
2290 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 |
2291 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 |
2292 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 |
2293 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 |
2294 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 |
2295 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a |
2296 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b |
2297 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 |
2298 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 |
2299 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 |
2300 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 |
2301 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 |
2302 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 |
2303 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 |
2304 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 |
2305 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 |
2306 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 |
2307 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a |
2308 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b |
2309 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c |
2310 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 |
2311 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 |
2312 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 |
2313 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 |
2314 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 |
2315 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 |
2316 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 |
2317 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 |
2318 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 |
2319 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 |
2320 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 |
2321 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 |
2322 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 |
2323 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 |
2324 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 |
2325 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 |
2326 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 |
2327 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 |
2328 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 |
2329 | #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 |
2330 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 |
2331 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 |
2332 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 |
2333 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 |
2334 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 |
2335 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 |
2336 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 |
2337 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 |
2338 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 |
2339 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 |
2340 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a |
2341 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b |
2342 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c |
2343 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d |
2344 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e |
2345 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f |
2346 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 |
2347 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 |
2348 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 |
2349 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 |
2350 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 |
2351 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 |
2352 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 |
2353 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 |
2354 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 |
2355 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 |
2356 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a |
2357 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b |
2358 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c |
2359 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d |
2360 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e |
2361 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f |
2362 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 |
2363 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 |
2364 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 |
2365 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 |
2366 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 |
2367 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 |
2368 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 |
2369 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 |
2370 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 |
2371 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 |
2372 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a |
2373 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b |
2374 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP 0x332c |
2375 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d |
2376 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e |
2377 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f |
2378 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 |
2379 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 |
2380 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 |
2381 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 |
2382 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 |
2383 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 |
2384 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 |
2385 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 |
2386 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 |
2387 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 |
2388 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a |
2389 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b |
2390 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA 0x333c |
2391 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d |
2392 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e |
2393 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f |
2394 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 |
2395 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 |
2396 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 |
2397 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 |
2398 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 |
2399 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 |
2400 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 |
2401 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 |
2402 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 |
2403 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 |
2404 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a |
2405 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b |
2406 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c |
2407 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d |
2408 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e |
2409 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f |
2410 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 |
2411 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 |
2412 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 |
2413 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 |
2414 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 |
2415 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 |
2416 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 |
2417 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 |
2418 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 |
2419 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 |
2420 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a |
2421 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b |
2422 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 |
2423 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 |
2424 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 |
2425 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 |
2426 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 |
2427 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 |
2428 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 |
2429 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 |
2430 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 |
2431 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 |
2432 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a |
2433 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b |
2434 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c |
2435 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 |
2436 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 |
2437 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 |
2438 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 |
2439 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 |
2440 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 |
2441 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 |
2442 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 |
2443 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 |
2444 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 |
2445 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 |
2446 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 |
2447 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 |
2448 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 |
2449 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 |
2450 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 |
2451 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 |
2452 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 |
2453 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 |
2454 | #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 |
2455 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 |
2456 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 |
2457 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 |
2458 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 |
2459 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 |
2460 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 |
2461 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 |
2462 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 |
2463 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 |
2464 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 |
2465 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a |
2466 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b |
2467 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c |
2468 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d |
2469 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e |
2470 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f |
2471 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 |
2472 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 |
2473 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 |
2474 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 |
2475 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 |
2476 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 |
2477 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 |
2478 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 |
2479 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 |
2480 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 |
2481 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a |
2482 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b |
2483 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS 0x401c |
2484 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d |
2485 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e |
2486 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f |
2487 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 |
2488 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 |
2489 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 |
2490 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 |
2491 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 |
2492 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 |
2493 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 |
2494 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 |
2495 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 |
2496 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 |
2497 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a |
2498 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b |
2499 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c |
2500 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d |
2501 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e |
2502 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f |
2503 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 |
2504 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 |
2505 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS 0x4032 |
2506 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 |
2507 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 |
2508 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 |
2509 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 |
2510 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 |
2511 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 |
2512 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 |
2513 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a |
2514 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b |
2515 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c |
2516 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d |
2517 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e |
2518 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f |
2519 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 |
2520 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 |
2521 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 |
2522 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 |
2523 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 |
2524 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 |
2525 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 |
2526 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 |
2527 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 |
2528 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 |
2529 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a |
2530 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b |
2531 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c |
2532 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d |
2533 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e |
2534 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f |
2535 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 |
2536 | #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 |
2537 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 |
2538 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 |
2539 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 |
2540 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 |
2541 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 |
2542 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 |
2543 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 |
2544 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 |
2545 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 |
2546 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 |
2547 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a |
2548 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b |
2549 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c |
2550 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d |
2551 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e |
2552 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f |
2553 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 |
2554 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 |
2555 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 |
2556 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 |
2557 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 |
2558 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 |
2559 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 |
2560 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 |
2561 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 |
2562 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 |
2563 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a |
2564 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b |
2565 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS 0x411c |
2566 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d |
2567 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e |
2568 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f |
2569 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 |
2570 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 |
2571 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 |
2572 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 |
2573 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 |
2574 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 |
2575 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 |
2576 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 |
2577 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 |
2578 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 |
2579 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a |
2580 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b |
2581 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c |
2582 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d |
2583 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e |
2584 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f |
2585 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 |
2586 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 |
2587 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS 0x4132 |
2588 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 |
2589 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 |
2590 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 |
2591 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 |
2592 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 |
2593 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 |
2594 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 |
2595 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a |
2596 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b |
2597 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c |
2598 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d |
2599 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e |
2600 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f |
2601 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 |
2602 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 |
2603 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 |
2604 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 |
2605 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 |
2606 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 |
2607 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 |
2608 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 |
2609 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 |
2610 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 |
2611 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a |
2612 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b |
2613 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c |
2614 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d |
2615 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e |
2616 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f |
2617 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 |
2618 | #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 |
2619 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 |
2620 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 |
2621 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 |
2622 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 |
2623 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 |
2624 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 |
2625 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 |
2626 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 |
2627 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 |
2628 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 |
2629 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a |
2630 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b |
2631 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c |
2632 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d |
2633 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e |
2634 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f |
2635 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 |
2636 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 |
2637 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 |
2638 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 |
2639 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 |
2640 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 |
2641 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 |
2642 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 |
2643 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 |
2644 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 |
2645 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a |
2646 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b |
2647 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS 0x421c |
2648 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d |
2649 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e |
2650 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f |
2651 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 |
2652 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 |
2653 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 |
2654 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 |
2655 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 |
2656 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 |
2657 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 |
2658 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 |
2659 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 |
2660 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 |
2661 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a |
2662 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b |
2663 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c |
2664 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d |
2665 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e |
2666 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f |
2667 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 |
2668 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 |
2669 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS 0x4232 |
2670 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 |
2671 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 |
2672 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 |
2673 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 |
2674 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 |
2675 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 |
2676 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 |
2677 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a |
2678 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b |
2679 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c |
2680 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d |
2681 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e |
2682 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f |
2683 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 |
2684 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 |
2685 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 |
2686 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 |
2687 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 |
2688 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 |
2689 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 |
2690 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 |
2691 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 |
2692 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 |
2693 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a |
2694 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b |
2695 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c |
2696 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d |
2697 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e |
2698 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f |
2699 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 |
2700 | #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 |
2701 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 |
2702 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 |
2703 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 |
2704 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 |
2705 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 |
2706 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 |
2707 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 |
2708 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 |
2709 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 |
2710 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 |
2711 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a |
2712 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b |
2713 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c |
2714 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d |
2715 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e |
2716 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f |
2717 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 |
2718 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 |
2719 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 |
2720 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 |
2721 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 |
2722 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 |
2723 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 |
2724 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 |
2725 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 |
2726 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 |
2727 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a |
2728 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b |
2729 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS 0x431c |
2730 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d |
2731 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e |
2732 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f |
2733 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 |
2734 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 |
2735 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 |
2736 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 |
2737 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 |
2738 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 |
2739 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 |
2740 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 |
2741 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 |
2742 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 |
2743 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a |
2744 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b |
2745 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c |
2746 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d |
2747 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e |
2748 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f |
2749 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 |
2750 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 |
2751 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS 0x4332 |
2752 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 |
2753 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 |
2754 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 |
2755 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 |
2756 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 |
2757 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 |
2758 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 |
2759 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a |
2760 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b |
2761 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c |
2762 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d |
2763 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e |
2764 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f |
2765 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 |
2766 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 |
2767 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 |
2768 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 |
2769 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 |
2770 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 |
2771 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 |
2772 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 |
2773 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 |
2774 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 |
2775 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a |
2776 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b |
2777 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c |
2778 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d |
2779 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e |
2780 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f |
2781 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 |
2782 | #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 |
2783 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 |
2784 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 |
2785 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 |
2786 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 |
2787 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 |
2788 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 |
2789 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 |
2790 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 |
2791 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 |
2792 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 |
2793 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a |
2794 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b |
2795 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c |
2796 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d |
2797 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e |
2798 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f |
2799 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 |
2800 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 |
2801 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 |
2802 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 |
2803 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 |
2804 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 |
2805 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 |
2806 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 |
2807 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 |
2808 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 |
2809 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a |
2810 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b |
2811 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS 0x701c |
2812 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d |
2813 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e |
2814 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f |
2815 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 |
2816 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 |
2817 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 |
2818 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 |
2819 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 |
2820 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 |
2821 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 |
2822 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 |
2823 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 |
2824 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 |
2825 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a |
2826 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b |
2827 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c |
2828 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d |
2829 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e |
2830 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f |
2831 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 |
2832 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 |
2833 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS 0x7032 |
2834 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 |
2835 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 |
2836 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 |
2837 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 |
2838 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 |
2839 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 |
2840 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 |
2841 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a |
2842 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b |
2843 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c |
2844 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d |
2845 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e |
2846 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f |
2847 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 |
2848 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 |
2849 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 |
2850 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 |
2851 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 |
2852 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 |
2853 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 |
2854 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 |
2855 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 |
2856 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 |
2857 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a |
2858 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b |
2859 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c |
2860 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d |
2861 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e |
2862 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f |
2863 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 |
2864 | #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 |
2865 | #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO 0x8000 |
2866 | #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI 0x8001 |
2867 | #define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN 0x8002 |
2868 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 |
2869 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 |
2870 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 |
2871 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 |
2872 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 |
2873 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 |
2874 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 |
2875 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a |
2876 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b |
2877 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c |
2878 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d |
2879 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e |
2880 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f |
2881 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 |
2882 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 |
2883 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 |
2884 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 |
2885 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 |
2886 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 |
2887 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 |
2888 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 |
2889 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 |
2890 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 |
2891 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a |
2892 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b |
2893 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c |
2894 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d |
2895 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e |
2896 | #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN 0x801f |
2897 | #define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 |
2898 | #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT 0x8021 |
2899 | #define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN 0x8022 |
2900 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 |
2901 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 |
2902 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 |
2903 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 |
2904 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 |
2905 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 |
2906 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a |
2907 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b |
2908 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c |
2909 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d |
2910 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e |
2911 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f |
2912 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 |
2913 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 |
2914 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 |
2915 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 |
2916 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 |
2917 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 |
2918 | #define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN 0x8036 |
2919 | #define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN 0x8037 |
2920 | #define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 |
2921 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 |
2922 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a |
2923 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b |
2924 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c |
2925 | #define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL 0x8040 |
2926 | #define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL 0x8041 |
2927 | #define ixDPCSSYS_CR0_SUPX_ANA_BG1 0x8042 |
2928 | #define ixDPCSSYS_CR0_SUPX_ANA_BG2 0x8043 |
2929 | #define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 |
2930 | #define ixDPCSSYS_CR0_SUPX_ANA_BG3 0x8045 |
2931 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1 0x8046 |
2932 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2 0x8047 |
2933 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD 0x8048 |
2934 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1 0x8049 |
2935 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2 0x804a |
2936 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3 0x804b |
2937 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1 0x804c |
2938 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2 0x804d |
2939 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3 0x804e |
2940 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4 0x804f |
2941 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5 0x8050 |
2942 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1 0x8051 |
2943 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2 0x8052 |
2944 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1 0x8053 |
2945 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2 0x8054 |
2946 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD 0x8055 |
2947 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1 0x8056 |
2948 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2 0x8057 |
2949 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3 0x8058 |
2950 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1 0x8059 |
2951 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2 0x805a |
2952 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3 0x805b |
2953 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4 0x805c |
2954 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5 0x805d |
2955 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1 0x805e |
2956 | #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2 0x805f |
2957 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 |
2958 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 |
2959 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 |
2960 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 |
2961 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 |
2962 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 |
2963 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 |
2964 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 |
2965 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 |
2966 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b |
2967 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d |
2968 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e |
2969 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f |
2970 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 |
2971 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 |
2972 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 |
2973 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 |
2974 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 |
2975 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 |
2976 | #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 |
2977 | #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 |
2978 | #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 |
2979 | #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a |
2980 | #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b |
2981 | #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c |
2982 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG 0x8081 |
2983 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT 0x8082 |
2984 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 |
2985 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 |
2986 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 |
2987 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT 0x8086 |
2988 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 |
2989 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 |
2990 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 |
2991 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a |
2992 | #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b |
2993 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c |
2994 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d |
2995 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e |
2996 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f |
2997 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 |
2998 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 |
2999 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 |
3000 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT 0x8093 |
3001 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 |
3002 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 |
3003 | #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 |
3004 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 |
3005 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 |
3006 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 |
3007 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 |
3008 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 |
3009 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 |
3010 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 |
3011 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 |
3012 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 |
3013 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 |
3014 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a |
3015 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b |
3016 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c |
3017 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d |
3018 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e |
3019 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f |
3020 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 |
3021 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 |
3022 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 |
3023 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 |
3024 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 |
3025 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 |
3026 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 |
3027 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 |
3028 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 |
3029 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 |
3030 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a |
3031 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b |
3032 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c |
3033 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d |
3034 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e |
3035 | #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA 0x901f |
3036 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 |
3037 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 |
3038 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 |
3039 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 |
3040 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 |
3041 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 |
3042 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 |
3043 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 |
3044 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 |
3045 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 |
3046 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a |
3047 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b |
3048 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c |
3049 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d |
3050 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e |
3051 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f |
3052 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 |
3053 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 |
3054 | #define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL 0x9032 |
3055 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 |
3056 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 |
3057 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 |
3058 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 |
3059 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 |
3060 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 |
3061 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 |
3062 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 |
3063 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 |
3064 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a |
3065 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b |
3066 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c |
3067 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d |
3068 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e |
3069 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f |
3070 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 |
3071 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL 0x9051 |
3072 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR 0x9052 |
3073 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 |
3074 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 |
3075 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 |
3076 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 |
3077 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 |
3078 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT 0x9058 |
3079 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ 0x9059 |
3080 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a |
3081 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b |
3082 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 |
3083 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 |
3084 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 |
3085 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 |
3086 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 |
3087 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 |
3088 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 |
3089 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 |
3090 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 |
3091 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 |
3092 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a |
3093 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b |
3094 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c |
3095 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d |
3096 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e |
3097 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f |
3098 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 |
3099 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 |
3100 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 |
3101 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 |
3102 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 |
3103 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 |
3104 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 |
3105 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 |
3106 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 |
3107 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 |
3108 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a |
3109 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b |
3110 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c |
3111 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d |
3112 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e |
3113 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f |
3114 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 |
3115 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 |
3116 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 |
3117 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 |
3118 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 |
3119 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 |
3120 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 |
3121 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 |
3122 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 |
3123 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 |
3124 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a |
3125 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b |
3126 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c |
3127 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d |
3128 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e |
3129 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f |
3130 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 |
3131 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 |
3132 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 |
3133 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 |
3134 | #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 |
3135 | #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 |
3136 | #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 |
3137 | #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 |
3138 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 |
3139 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 |
3140 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 |
3141 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 |
3142 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 |
3143 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 |
3144 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 |
3145 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 |
3146 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 |
3147 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 |
3148 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa |
3149 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab |
3150 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac |
3151 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad |
3152 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL 0x90ae |
3153 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af |
3154 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 |
3155 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 |
3156 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 |
3157 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 |
3158 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE 0x90b4 |
3159 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 |
3160 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 |
3161 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 |
3162 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 |
3163 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 |
3164 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba |
3165 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0 0x90bb |
3166 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1 0x90bc |
3167 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd |
3168 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be |
3169 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf |
3170 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 |
3171 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 |
3172 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 |
3173 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 |
3174 | #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 |
3175 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS 0x90e0 |
3176 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD 0x90e1 |
3177 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS 0x90e2 |
3178 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1 0x90e3 |
3179 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2 0x90e4 |
3180 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC 0x90e5 |
3181 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1 0x90e6 |
3182 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE 0x90e7 |
3183 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 |
3184 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK 0x90e9 |
3185 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1 0x90ea |
3186 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2 0x90eb |
3187 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3 0x90ec |
3188 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2 0x90ed |
3189 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3 0x90ee |
3190 | #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4 0x90ef |
3191 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1 0x90f0 |
3192 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2 0x90f1 |
3193 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES 0x90f2 |
3194 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL 0x90f3 |
3195 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1 0x90f4 |
3196 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2 0x90f5 |
3197 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ 0x90f6 |
3198 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1 0x90f7 |
3199 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2 0x90f8 |
3200 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF 0x90f9 |
3201 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1 0x90fa |
3202 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2 0x90fb |
3203 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3 0x90fc |
3204 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4 0x90fd |
3205 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC 0x90fe |
3206 | #define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1 0x90ff |
3207 | #define ixDPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 |
3208 | #define ixDPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 |
3209 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 |
3210 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 |
3211 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 |
3212 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 |
3213 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 |
3214 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 |
3215 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 |
3216 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 |
3217 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 |
3218 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 |
3219 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a |
3220 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b |
3221 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c |
3222 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d |
3223 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e |
3224 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f |
3225 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 |
3226 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 |
3227 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 |
3228 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 |
3229 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 |
3230 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 |
3231 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 |
3232 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 |
3233 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 |
3234 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 |
3235 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a |
3236 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b |
3237 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c |
3238 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d |
3239 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e |
3240 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f |
3241 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 |
3242 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 |
3243 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 |
3244 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 |
3245 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 |
3246 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 |
3247 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 |
3248 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 |
3249 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 |
3250 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 |
3251 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a |
3252 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b |
3253 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c |
3254 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d |
3255 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e |
3256 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f |
3257 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 |
3258 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 |
3259 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 |
3260 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 |
3261 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 |
3262 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 |
3263 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 |
3264 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 |
3265 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 |
3266 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 |
3267 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a |
3268 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b |
3269 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA 0xe03c |
3270 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d |
3271 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e |
3272 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f |
3273 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 |
3274 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 |
3275 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 |
3276 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 |
3277 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 |
3278 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 |
3279 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 |
3280 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 |
3281 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 |
3282 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 |
3283 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a |
3284 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b |
3285 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c |
3286 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d |
3287 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e |
3288 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f |
3289 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 |
3290 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 |
3291 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 |
3292 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 |
3293 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 |
3294 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 |
3295 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 |
3296 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 |
3297 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 |
3298 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 |
3299 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a |
3300 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b |
3301 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 |
3302 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 |
3303 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 |
3304 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 |
3305 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 |
3306 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 |
3307 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 |
3308 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 |
3309 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 |
3310 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 |
3311 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a |
3312 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b |
3313 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c |
3314 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 |
3315 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 |
3316 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 |
3317 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 |
3318 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 |
3319 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 |
3320 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 |
3321 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 |
3322 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 |
3323 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 |
3324 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 |
3325 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 |
3326 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 |
3327 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 |
3328 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 |
3329 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 |
3330 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 |
3331 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 |
3332 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 |
3333 | #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 |
3334 | |
3335 | |
3336 | // addressBlock: dpcssys_cr1_rdpcstxcrind |
3337 | // base address: 0x0 |
3338 | #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO 0x0000 |
3339 | #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI 0x0001 |
3340 | #define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN 0x0002 |
3341 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 |
3342 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 |
3343 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 |
3344 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 |
3345 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 |
3346 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 |
3347 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 |
3348 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a |
3349 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b |
3350 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c |
3351 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d |
3352 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3 0x000e |
3353 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4 0x000f |
3354 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 |
3355 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 |
3356 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 |
3357 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 |
3358 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 |
3359 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 |
3360 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 |
3361 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 |
3362 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 |
3363 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 |
3364 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3 0x001a |
3365 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4 0x001b |
3366 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5 0x001c |
3367 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d |
3368 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e |
3369 | #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN 0x001f |
3370 | #define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN 0x0020 |
3371 | #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT 0x0021 |
3372 | #define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN 0x0022 |
3373 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 |
3374 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 |
3375 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 |
3376 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 |
3377 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 |
3378 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 |
3379 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6 0x002a |
3380 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0 0x002b |
3381 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1 0x002c |
3382 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2 0x002d |
3383 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3 0x002e |
3384 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4 0x002f |
3385 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 |
3386 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 |
3387 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 |
3388 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 |
3389 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 |
3390 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 |
3391 | #define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN 0x0036 |
3392 | #define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN 0x0037 |
3393 | #define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN 0x0038 |
3394 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 |
3395 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a |
3396 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b |
3397 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c |
3398 | #define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL 0x0040 |
3399 | #define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL 0x0041 |
3400 | #define ixDPCSSYS_CR1_SUP_ANA_BG1 0x0042 |
3401 | #define ixDPCSSYS_CR1_SUP_ANA_BG2 0x0043 |
3402 | #define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS 0x0044 |
3403 | #define ixDPCSSYS_CR1_SUP_ANA_BG3 0x0045 |
3404 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1 0x0046 |
3405 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2 0x0047 |
3406 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD 0x0048 |
3407 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1 0x0049 |
3408 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2 0x004a |
3409 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3 0x004b |
3410 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1 0x004c |
3411 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2 0x004d |
3412 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3 0x004e |
3413 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4 0x004f |
3414 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5 0x0050 |
3415 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1 0x0051 |
3416 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2 0x0052 |
3417 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1 0x0053 |
3418 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2 0x0054 |
3419 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD 0x0055 |
3420 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1 0x0056 |
3421 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2 0x0057 |
3422 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3 0x0058 |
3423 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1 0x0059 |
3424 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2 0x005a |
3425 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3 0x005b |
3426 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4 0x005c |
3427 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5 0x005d |
3428 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1 0x005e |
3429 | #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2 0x005f |
3430 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 |
3431 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 |
3432 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 |
3433 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 |
3434 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 |
3435 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 |
3436 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 |
3437 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 |
3438 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 |
3439 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b |
3440 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d |
3441 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e |
3442 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f |
3443 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 |
3444 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 |
3445 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 |
3446 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 |
3447 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 |
3448 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 |
3449 | #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 |
3450 | #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 |
3451 | #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 |
3452 | #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a |
3453 | #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b |
3454 | #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD 0x007c |
3455 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG 0x0081 |
3456 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT 0x0082 |
3457 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 |
3458 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 |
3459 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 |
3460 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT 0x0086 |
3461 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT 0x0087 |
3462 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT 0x0088 |
3463 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 |
3464 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a |
3465 | #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b |
3466 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c |
3467 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d |
3468 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e |
3469 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f |
3470 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 |
3471 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 |
3472 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 |
3473 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT 0x0093 |
3474 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 |
3475 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 |
3476 | #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 |
3477 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 |
3478 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 |
3479 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 |
3480 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 |
3481 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 |
3482 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 |
3483 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 |
3484 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f |
3485 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 |
3486 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 |
3487 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 |
3488 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 |
3489 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 |
3490 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b |
3491 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d |
3492 | #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e |
3493 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 |
3494 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 |
3495 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 |
3496 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 |
3497 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 |
3498 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 |
3499 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 |
3500 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 |
3501 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 |
3502 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 |
3503 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a |
3504 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b |
3505 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c |
3506 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d |
3507 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e |
3508 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f |
3509 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 |
3510 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 |
3511 | #define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL 0x1032 |
3512 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 |
3513 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 |
3514 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 |
3515 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 |
3516 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 |
3517 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 |
3518 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 |
3519 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 |
3520 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 |
3521 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 |
3522 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a |
3523 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b |
3524 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c |
3525 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d |
3526 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e |
3527 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f |
3528 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 |
3529 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 |
3530 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 |
3531 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 |
3532 | #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 |
3533 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 |
3534 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 |
3535 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 |
3536 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 |
3537 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 |
3538 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 |
3539 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 |
3540 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 |
3541 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 |
3542 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0 0x10bb |
3543 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 |
3544 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 |
3545 | #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 |
3546 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS 0x10e0 |
3547 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD 0x10e1 |
3548 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS 0x10e2 |
3549 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1 0x10e3 |
3550 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2 0x10e4 |
3551 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC 0x10e5 |
3552 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1 0x10e6 |
3553 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE 0x10e7 |
3554 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 |
3555 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK 0x10e9 |
3556 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1 0x10ea |
3557 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2 0x10eb |
3558 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3 0x10ec |
3559 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2 0x10ed |
3560 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3 0x10ee |
3561 | #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4 0x10ef |
3562 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 |
3563 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 |
3564 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 |
3565 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 |
3566 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 |
3567 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 |
3568 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 |
3569 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 |
3570 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 |
3571 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 |
3572 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a |
3573 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b |
3574 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c |
3575 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d |
3576 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e |
3577 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f |
3578 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 |
3579 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 |
3580 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 |
3581 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 |
3582 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 |
3583 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 |
3584 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 |
3585 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 |
3586 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 |
3587 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 |
3588 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a |
3589 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b |
3590 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c |
3591 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d |
3592 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e |
3593 | #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA 0x111f |
3594 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 |
3595 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 |
3596 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 |
3597 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 |
3598 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 |
3599 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 |
3600 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 |
3601 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 |
3602 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 |
3603 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 |
3604 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a |
3605 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b |
3606 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c |
3607 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d |
3608 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e |
3609 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f |
3610 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 |
3611 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 |
3612 | #define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL 0x1132 |
3613 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 |
3614 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 |
3615 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 |
3616 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 |
3617 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 |
3618 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 |
3619 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 |
3620 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 |
3621 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 |
3622 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a |
3623 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b |
3624 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c |
3625 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d |
3626 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e |
3627 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f |
3628 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 |
3629 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL 0x1151 |
3630 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR 0x1152 |
3631 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 |
3632 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 |
3633 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 |
3634 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 |
3635 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 |
3636 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT 0x1158 |
3637 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ 0x1159 |
3638 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a |
3639 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b |
3640 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 |
3641 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 |
3642 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 |
3643 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 |
3644 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 |
3645 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 |
3646 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 |
3647 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 |
3648 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 |
3649 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 |
3650 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a |
3651 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b |
3652 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c |
3653 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d |
3654 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e |
3655 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f |
3656 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 |
3657 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 |
3658 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 |
3659 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 |
3660 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 |
3661 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 |
3662 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 |
3663 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 |
3664 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 |
3665 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 |
3666 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a |
3667 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b |
3668 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c |
3669 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d |
3670 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e |
3671 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f |
3672 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 |
3673 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 |
3674 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 |
3675 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 |
3676 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 |
3677 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 |
3678 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 |
3679 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 |
3680 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 |
3681 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 |
3682 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a |
3683 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b |
3684 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c |
3685 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d |
3686 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e |
3687 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f |
3688 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 |
3689 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 |
3690 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 |
3691 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 |
3692 | #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 |
3693 | #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 |
3694 | #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 |
3695 | #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 |
3696 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 |
3697 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 |
3698 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 |
3699 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 |
3700 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 |
3701 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 |
3702 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 |
3703 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 |
3704 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 |
3705 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 |
3706 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa |
3707 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab |
3708 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac |
3709 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad |
3710 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL 0x11ae |
3711 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af |
3712 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 |
3713 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 |
3714 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 |
3715 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 |
3716 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE 0x11b4 |
3717 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 |
3718 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 |
3719 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 |
3720 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 |
3721 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 |
3722 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba |
3723 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0 0x11bb |
3724 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1 0x11bc |
3725 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd |
3726 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be |
3727 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf |
3728 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 |
3729 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 |
3730 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 |
3731 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 |
3732 | #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 |
3733 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS 0x11e0 |
3734 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD 0x11e1 |
3735 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS 0x11e2 |
3736 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1 0x11e3 |
3737 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2 0x11e4 |
3738 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC 0x11e5 |
3739 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1 0x11e6 |
3740 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE 0x11e7 |
3741 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 |
3742 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK 0x11e9 |
3743 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1 0x11ea |
3744 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2 0x11eb |
3745 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3 0x11ec |
3746 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2 0x11ed |
3747 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3 0x11ee |
3748 | #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4 0x11ef |
3749 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1 0x11f0 |
3750 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2 0x11f1 |
3751 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES 0x11f2 |
3752 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL 0x11f3 |
3753 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1 0x11f4 |
3754 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2 0x11f5 |
3755 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ 0x11f6 |
3756 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1 0x11f7 |
3757 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2 0x11f8 |
3758 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF 0x11f9 |
3759 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1 0x11fa |
3760 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2 0x11fb |
3761 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3 0x11fc |
3762 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4 0x11fd |
3763 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC 0x11fe |
3764 | #define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1 0x11ff |
3765 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 |
3766 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 |
3767 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 |
3768 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 |
3769 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 |
3770 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 |
3771 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 |
3772 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 |
3773 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 |
3774 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 |
3775 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a |
3776 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b |
3777 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c |
3778 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d |
3779 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e |
3780 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f |
3781 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 |
3782 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 |
3783 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 |
3784 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 |
3785 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 |
3786 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 |
3787 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 |
3788 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 |
3789 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 |
3790 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 |
3791 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a |
3792 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b |
3793 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c |
3794 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d |
3795 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e |
3796 | #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA 0x121f |
3797 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 |
3798 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 |
3799 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 |
3800 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 |
3801 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 |
3802 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 |
3803 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 |
3804 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 |
3805 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 |
3806 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 |
3807 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a |
3808 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b |
3809 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c |
3810 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d |
3811 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e |
3812 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f |
3813 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 |
3814 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 |
3815 | #define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL 0x1232 |
3816 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 |
3817 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 |
3818 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 |
3819 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 |
3820 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 |
3821 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 |
3822 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 |
3823 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 |
3824 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 |
3825 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a |
3826 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b |
3827 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c |
3828 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d |
3829 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e |
3830 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f |
3831 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 |
3832 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL 0x1251 |
3833 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR 0x1252 |
3834 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 |
3835 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 |
3836 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 |
3837 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 |
3838 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 |
3839 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT 0x1258 |
3840 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ 0x1259 |
3841 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a |
3842 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b |
3843 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 |
3844 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 |
3845 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 |
3846 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 |
3847 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 |
3848 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 |
3849 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 |
3850 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 |
3851 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 |
3852 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 |
3853 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a |
3854 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b |
3855 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c |
3856 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d |
3857 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e |
3858 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f |
3859 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 |
3860 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 |
3861 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 |
3862 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 |
3863 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 |
3864 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 |
3865 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 |
3866 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 |
3867 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 |
3868 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 |
3869 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a |
3870 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b |
3871 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c |
3872 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d |
3873 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e |
3874 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f |
3875 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 |
3876 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 |
3877 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 |
3878 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 |
3879 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 |
3880 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 |
3881 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 |
3882 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 |
3883 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 |
3884 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 |
3885 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a |
3886 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b |
3887 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c |
3888 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d |
3889 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e |
3890 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f |
3891 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 |
3892 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 |
3893 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 |
3894 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 |
3895 | #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 |
3896 | #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 |
3897 | #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 |
3898 | #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 |
3899 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 |
3900 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 |
3901 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 |
3902 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 |
3903 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 |
3904 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 |
3905 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 |
3906 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 |
3907 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 |
3908 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 |
3909 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa |
3910 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab |
3911 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac |
3912 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad |
3913 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL 0x12ae |
3914 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af |
3915 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 |
3916 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 |
3917 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 |
3918 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 |
3919 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE 0x12b4 |
3920 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 |
3921 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 |
3922 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 |
3923 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 |
3924 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 |
3925 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba |
3926 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0 0x12bb |
3927 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1 0x12bc |
3928 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd |
3929 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be |
3930 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf |
3931 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 |
3932 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 |
3933 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 |
3934 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 |
3935 | #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 |
3936 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS 0x12e0 |
3937 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD 0x12e1 |
3938 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS 0x12e2 |
3939 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1 0x12e3 |
3940 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2 0x12e4 |
3941 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC 0x12e5 |
3942 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1 0x12e6 |
3943 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE 0x12e7 |
3944 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 |
3945 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK 0x12e9 |
3946 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1 0x12ea |
3947 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2 0x12eb |
3948 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3 0x12ec |
3949 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2 0x12ed |
3950 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3 0x12ee |
3951 | #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4 0x12ef |
3952 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1 0x12f0 |
3953 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2 0x12f1 |
3954 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES 0x12f2 |
3955 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL 0x12f3 |
3956 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1 0x12f4 |
3957 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2 0x12f5 |
3958 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ 0x12f6 |
3959 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1 0x12f7 |
3960 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2 0x12f8 |
3961 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF 0x12f9 |
3962 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1 0x12fa |
3963 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2 0x12fb |
3964 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3 0x12fc |
3965 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4 0x12fd |
3966 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC 0x12fe |
3967 | #define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1 0x12ff |
3968 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 |
3969 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 |
3970 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 |
3971 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 |
3972 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 |
3973 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 |
3974 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 |
3975 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f |
3976 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 |
3977 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 |
3978 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 |
3979 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 |
3980 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 |
3981 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b |
3982 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d |
3983 | #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e |
3984 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 |
3985 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 |
3986 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 |
3987 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 |
3988 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 |
3989 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 |
3990 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 |
3991 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 |
3992 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 |
3993 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 |
3994 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a |
3995 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b |
3996 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c |
3997 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d |
3998 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e |
3999 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f |
4000 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 |
4001 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 |
4002 | #define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL 0x1332 |
4003 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 |
4004 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 |
4005 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 |
4006 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 |
4007 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 |
4008 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 |
4009 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 |
4010 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 |
4011 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 |
4012 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 |
4013 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a |
4014 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b |
4015 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c |
4016 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d |
4017 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e |
4018 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f |
4019 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 |
4020 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 |
4021 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 |
4022 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 |
4023 | #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 |
4024 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 |
4025 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 |
4026 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 |
4027 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 |
4028 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 |
4029 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 |
4030 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 |
4031 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 |
4032 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 |
4033 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0 0x13bb |
4034 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 |
4035 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 |
4036 | #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 |
4037 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS 0x13e0 |
4038 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD 0x13e1 |
4039 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS 0x13e2 |
4040 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1 0x13e3 |
4041 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2 0x13e4 |
4042 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC 0x13e5 |
4043 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1 0x13e6 |
4044 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE 0x13e7 |
4045 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 |
4046 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK 0x13e9 |
4047 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1 0x13ea |
4048 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2 0x13eb |
4049 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3 0x13ec |
4050 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2 0x13ed |
4051 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3 0x13ee |
4052 | #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4 0x13ef |
4053 | #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL 0x2000 |
4054 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 |
4055 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 |
4056 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 |
4057 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 |
4058 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 |
4059 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 |
4060 | #define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 |
4061 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 |
4062 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 |
4063 | #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1 0x200a |
4064 | #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL 0x200b |
4065 | #define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE 0x200c |
4066 | #define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE 0x200d |
4067 | #define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA 0x200e |
4068 | #define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD 0x200f |
4069 | #define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 |
4070 | #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1 0x2011 |
4071 | #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2 0x2012 |
4072 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 |
4073 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 |
4074 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 |
4075 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 |
4076 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 |
4077 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 |
4078 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 |
4079 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 |
4080 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 |
4081 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 |
4082 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a |
4083 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b |
4084 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c |
4085 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d |
4086 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e |
4087 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f |
4088 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 |
4089 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 |
4090 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 |
4091 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 |
4092 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 |
4093 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 |
4094 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 |
4095 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 |
4096 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 |
4097 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 |
4098 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a |
4099 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b |
4100 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c |
4101 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d |
4102 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e |
4103 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f |
4104 | #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 |
4105 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 |
4106 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 |
4107 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 |
4108 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 |
4109 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 |
4110 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 |
4111 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 |
4112 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 |
4113 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 |
4114 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 |
4115 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a |
4116 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b |
4117 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c |
4118 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d |
4119 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e |
4120 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f |
4121 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 |
4122 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 |
4123 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 |
4124 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 |
4125 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 |
4126 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 |
4127 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 |
4128 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 |
4129 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 |
4130 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 |
4131 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a |
4132 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b |
4133 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c |
4134 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d |
4135 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e |
4136 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f |
4137 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 |
4138 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 |
4139 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 |
4140 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 |
4141 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 |
4142 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 |
4143 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 |
4144 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 |
4145 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 |
4146 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 |
4147 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a |
4148 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b |
4149 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP 0x302c |
4150 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d |
4151 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e |
4152 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f |
4153 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 |
4154 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 |
4155 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 |
4156 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 |
4157 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 |
4158 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 |
4159 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 |
4160 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 |
4161 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 |
4162 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 |
4163 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a |
4164 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b |
4165 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA 0x303c |
4166 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d |
4167 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e |
4168 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f |
4169 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 |
4170 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 |
4171 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 |
4172 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 |
4173 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 |
4174 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 |
4175 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 |
4176 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 |
4177 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 |
4178 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 |
4179 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a |
4180 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b |
4181 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c |
4182 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d |
4183 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e |
4184 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f |
4185 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 |
4186 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 |
4187 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 |
4188 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 |
4189 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 |
4190 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 |
4191 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 |
4192 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 |
4193 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 |
4194 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 |
4195 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a |
4196 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b |
4197 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 |
4198 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 |
4199 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 |
4200 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 |
4201 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 |
4202 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 |
4203 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 |
4204 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 |
4205 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 |
4206 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 |
4207 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a |
4208 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b |
4209 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c |
4210 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 |
4211 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 |
4212 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 |
4213 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 |
4214 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 |
4215 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 |
4216 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 |
4217 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 |
4218 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 |
4219 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 |
4220 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 |
4221 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 |
4222 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 |
4223 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 |
4224 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 |
4225 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 |
4226 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 |
4227 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 |
4228 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 |
4229 | #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 |
4230 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 |
4231 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 |
4232 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 |
4233 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 |
4234 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 |
4235 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 |
4236 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 |
4237 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 |
4238 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 |
4239 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 |
4240 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a |
4241 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b |
4242 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c |
4243 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d |
4244 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e |
4245 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f |
4246 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 |
4247 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 |
4248 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 |
4249 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 |
4250 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 |
4251 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 |
4252 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 |
4253 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 |
4254 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 |
4255 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 |
4256 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a |
4257 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b |
4258 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c |
4259 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d |
4260 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e |
4261 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f |
4262 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 |
4263 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 |
4264 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 |
4265 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 |
4266 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 |
4267 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 |
4268 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 |
4269 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 |
4270 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 |
4271 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 |
4272 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a |
4273 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b |
4274 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP 0x312c |
4275 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d |
4276 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e |
4277 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f |
4278 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 |
4279 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 |
4280 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 |
4281 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 |
4282 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 |
4283 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 |
4284 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 |
4285 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 |
4286 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 |
4287 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 |
4288 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a |
4289 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b |
4290 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA 0x313c |
4291 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d |
4292 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e |
4293 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f |
4294 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 |
4295 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 |
4296 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 |
4297 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 |
4298 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 |
4299 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 |
4300 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 |
4301 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 |
4302 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 |
4303 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 |
4304 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a |
4305 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b |
4306 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c |
4307 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d |
4308 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e |
4309 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f |
4310 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 |
4311 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 |
4312 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 |
4313 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 |
4314 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 |
4315 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 |
4316 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 |
4317 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 |
4318 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 |
4319 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 |
4320 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a |
4321 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b |
4322 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 |
4323 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 |
4324 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 |
4325 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 |
4326 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 |
4327 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 |
4328 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 |
4329 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 |
4330 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 |
4331 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 |
4332 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a |
4333 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b |
4334 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c |
4335 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 |
4336 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 |
4337 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 |
4338 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 |
4339 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 |
4340 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 |
4341 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 |
4342 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 |
4343 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 |
4344 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 |
4345 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 |
4346 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 |
4347 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 |
4348 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 |
4349 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 |
4350 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 |
4351 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 |
4352 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 |
4353 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 |
4354 | #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 |
4355 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 |
4356 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 |
4357 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 |
4358 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 |
4359 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 |
4360 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 |
4361 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 |
4362 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 |
4363 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 |
4364 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 |
4365 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a |
4366 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b |
4367 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c |
4368 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d |
4369 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e |
4370 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f |
4371 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 |
4372 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 |
4373 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 |
4374 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 |
4375 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 |
4376 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 |
4377 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 |
4378 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 |
4379 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 |
4380 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 |
4381 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a |
4382 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b |
4383 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c |
4384 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d |
4385 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e |
4386 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f |
4387 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 |
4388 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 |
4389 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 |
4390 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 |
4391 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 |
4392 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 |
4393 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 |
4394 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 |
4395 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 |
4396 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 |
4397 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a |
4398 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b |
4399 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP 0x322c |
4400 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d |
4401 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e |
4402 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f |
4403 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 |
4404 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 |
4405 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 |
4406 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 |
4407 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 |
4408 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 |
4409 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 |
4410 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 |
4411 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 |
4412 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 |
4413 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a |
4414 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b |
4415 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA 0x323c |
4416 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d |
4417 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e |
4418 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f |
4419 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 |
4420 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 |
4421 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 |
4422 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 |
4423 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 |
4424 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 |
4425 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 |
4426 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 |
4427 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 |
4428 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 |
4429 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a |
4430 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b |
4431 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c |
4432 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d |
4433 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e |
4434 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f |
4435 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 |
4436 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 |
4437 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 |
4438 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 |
4439 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 |
4440 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 |
4441 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 |
4442 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 |
4443 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 |
4444 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 |
4445 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a |
4446 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b |
4447 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 |
4448 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 |
4449 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 |
4450 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 |
4451 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 |
4452 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 |
4453 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 |
4454 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 |
4455 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 |
4456 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 |
4457 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a |
4458 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b |
4459 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c |
4460 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 |
4461 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 |
4462 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 |
4463 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 |
4464 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 |
4465 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 |
4466 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 |
4467 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 |
4468 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 |
4469 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 |
4470 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 |
4471 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 |
4472 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 |
4473 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 |
4474 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 |
4475 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 |
4476 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 |
4477 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 |
4478 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 |
4479 | #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 |
4480 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 |
4481 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 |
4482 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 |
4483 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 |
4484 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 |
4485 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 |
4486 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 |
4487 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 |
4488 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 |
4489 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 |
4490 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a |
4491 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b |
4492 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c |
4493 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d |
4494 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e |
4495 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f |
4496 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 |
4497 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 |
4498 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 |
4499 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 |
4500 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 |
4501 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 |
4502 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 |
4503 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 |
4504 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 |
4505 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 |
4506 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a |
4507 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b |
4508 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c |
4509 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d |
4510 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e |
4511 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f |
4512 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 |
4513 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 |
4514 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 |
4515 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 |
4516 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 |
4517 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 |
4518 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 |
4519 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 |
4520 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 |
4521 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 |
4522 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a |
4523 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b |
4524 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP 0x332c |
4525 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d |
4526 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e |
4527 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f |
4528 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 |
4529 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 |
4530 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 |
4531 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 |
4532 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 |
4533 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 |
4534 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 |
4535 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 |
4536 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 |
4537 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 |
4538 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a |
4539 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b |
4540 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA 0x333c |
4541 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d |
4542 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e |
4543 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f |
4544 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 |
4545 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 |
4546 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 |
4547 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 |
4548 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 |
4549 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 |
4550 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 |
4551 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 |
4552 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 |
4553 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 |
4554 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a |
4555 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b |
4556 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c |
4557 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d |
4558 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e |
4559 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f |
4560 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 |
4561 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 |
4562 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 |
4563 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 |
4564 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 |
4565 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 |
4566 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 |
4567 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 |
4568 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 |
4569 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 |
4570 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a |
4571 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b |
4572 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 |
4573 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 |
4574 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 |
4575 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 |
4576 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 |
4577 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 |
4578 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 |
4579 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 |
4580 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 |
4581 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 |
4582 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a |
4583 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b |
4584 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c |
4585 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 |
4586 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 |
4587 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 |
4588 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 |
4589 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 |
4590 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 |
4591 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 |
4592 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 |
4593 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 |
4594 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 |
4595 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 |
4596 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 |
4597 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 |
4598 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 |
4599 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 |
4600 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 |
4601 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 |
4602 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 |
4603 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 |
4604 | #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 |
4605 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 |
4606 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 |
4607 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 |
4608 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 |
4609 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 |
4610 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 |
4611 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 |
4612 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 |
4613 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 |
4614 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 |
4615 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a |
4616 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b |
4617 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c |
4618 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d |
4619 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e |
4620 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f |
4621 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 |
4622 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 |
4623 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 |
4624 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 |
4625 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 |
4626 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 |
4627 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 |
4628 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 |
4629 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 |
4630 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 |
4631 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a |
4632 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b |
4633 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS 0x401c |
4634 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d |
4635 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e |
4636 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f |
4637 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 |
4638 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 |
4639 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 |
4640 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 |
4641 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 |
4642 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 |
4643 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 |
4644 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 |
4645 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 |
4646 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 |
4647 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a |
4648 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b |
4649 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c |
4650 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d |
4651 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e |
4652 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f |
4653 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 |
4654 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 |
4655 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS 0x4032 |
4656 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 |
4657 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 |
4658 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 |
4659 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 |
4660 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 |
4661 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 |
4662 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 |
4663 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a |
4664 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b |
4665 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c |
4666 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d |
4667 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e |
4668 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f |
4669 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 |
4670 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 |
4671 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 |
4672 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 |
4673 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 |
4674 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 |
4675 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 |
4676 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 |
4677 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 |
4678 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 |
4679 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a |
4680 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b |
4681 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c |
4682 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d |
4683 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e |
4684 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f |
4685 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 |
4686 | #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 |
4687 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 |
4688 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 |
4689 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 |
4690 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 |
4691 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 |
4692 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 |
4693 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 |
4694 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 |
4695 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 |
4696 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 |
4697 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a |
4698 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b |
4699 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c |
4700 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d |
4701 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e |
4702 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f |
4703 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 |
4704 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 |
4705 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 |
4706 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 |
4707 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 |
4708 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 |
4709 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 |
4710 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 |
4711 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 |
4712 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 |
4713 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a |
4714 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b |
4715 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS 0x411c |
4716 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d |
4717 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e |
4718 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f |
4719 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 |
4720 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 |
4721 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 |
4722 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 |
4723 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 |
4724 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 |
4725 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 |
4726 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 |
4727 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 |
4728 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 |
4729 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a |
4730 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b |
4731 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c |
4732 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d |
4733 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e |
4734 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f |
4735 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 |
4736 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 |
4737 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS 0x4132 |
4738 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 |
4739 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 |
4740 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 |
4741 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 |
4742 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 |
4743 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 |
4744 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 |
4745 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a |
4746 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b |
4747 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c |
4748 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d |
4749 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e |
4750 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f |
4751 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 |
4752 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 |
4753 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 |
4754 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 |
4755 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 |
4756 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 |
4757 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 |
4758 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 |
4759 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 |
4760 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 |
4761 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a |
4762 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b |
4763 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c |
4764 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d |
4765 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e |
4766 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f |
4767 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 |
4768 | #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 |
4769 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 |
4770 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 |
4771 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 |
4772 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 |
4773 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 |
4774 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 |
4775 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 |
4776 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 |
4777 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 |
4778 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 |
4779 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a |
4780 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b |
4781 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c |
4782 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d |
4783 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e |
4784 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f |
4785 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 |
4786 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 |
4787 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 |
4788 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 |
4789 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 |
4790 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 |
4791 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 |
4792 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 |
4793 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 |
4794 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 |
4795 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a |
4796 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b |
4797 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS 0x421c |
4798 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d |
4799 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e |
4800 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f |
4801 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 |
4802 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 |
4803 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 |
4804 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 |
4805 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 |
4806 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 |
4807 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 |
4808 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 |
4809 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 |
4810 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 |
4811 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a |
4812 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b |
4813 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c |
4814 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d |
4815 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e |
4816 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f |
4817 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 |
4818 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 |
4819 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS 0x4232 |
4820 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 |
4821 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 |
4822 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 |
4823 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 |
4824 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 |
4825 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 |
4826 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 |
4827 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a |
4828 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b |
4829 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c |
4830 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d |
4831 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e |
4832 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f |
4833 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 |
4834 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 |
4835 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 |
4836 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 |
4837 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 |
4838 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 |
4839 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 |
4840 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 |
4841 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 |
4842 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 |
4843 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a |
4844 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b |
4845 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c |
4846 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d |
4847 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e |
4848 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f |
4849 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 |
4850 | #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 |
4851 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 |
4852 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 |
4853 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 |
4854 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 |
4855 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 |
4856 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 |
4857 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 |
4858 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 |
4859 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 |
4860 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 |
4861 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a |
4862 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b |
4863 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c |
4864 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d |
4865 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e |
4866 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f |
4867 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 |
4868 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 |
4869 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 |
4870 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 |
4871 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 |
4872 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 |
4873 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 |
4874 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 |
4875 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 |
4876 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 |
4877 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a |
4878 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b |
4879 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS 0x431c |
4880 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d |
4881 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e |
4882 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f |
4883 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 |
4884 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 |
4885 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 |
4886 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 |
4887 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 |
4888 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 |
4889 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 |
4890 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 |
4891 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 |
4892 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 |
4893 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a |
4894 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b |
4895 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c |
4896 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d |
4897 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e |
4898 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f |
4899 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 |
4900 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 |
4901 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS 0x4332 |
4902 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 |
4903 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 |
4904 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 |
4905 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 |
4906 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 |
4907 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 |
4908 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 |
4909 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a |
4910 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b |
4911 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c |
4912 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d |
4913 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e |
4914 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f |
4915 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 |
4916 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 |
4917 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 |
4918 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 |
4919 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 |
4920 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 |
4921 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 |
4922 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 |
4923 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 |
4924 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 |
4925 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a |
4926 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b |
4927 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c |
4928 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d |
4929 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e |
4930 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f |
4931 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 |
4932 | #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 |
4933 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 |
4934 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 |
4935 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 |
4936 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 |
4937 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 |
4938 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 |
4939 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 |
4940 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 |
4941 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 |
4942 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 |
4943 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a |
4944 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b |
4945 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c |
4946 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d |
4947 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e |
4948 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f |
4949 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 |
4950 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 |
4951 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 |
4952 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 |
4953 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 |
4954 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 |
4955 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 |
4956 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 |
4957 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 |
4958 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 |
4959 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a |
4960 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b |
4961 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS 0x701c |
4962 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d |
4963 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e |
4964 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f |
4965 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 |
4966 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 |
4967 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 |
4968 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 |
4969 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 |
4970 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 |
4971 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 |
4972 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 |
4973 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 |
4974 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 |
4975 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a |
4976 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b |
4977 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c |
4978 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d |
4979 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e |
4980 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f |
4981 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 |
4982 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 |
4983 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS 0x7032 |
4984 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 |
4985 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 |
4986 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 |
4987 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 |
4988 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 |
4989 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 |
4990 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 |
4991 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a |
4992 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b |
4993 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c |
4994 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d |
4995 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e |
4996 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f |
4997 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 |
4998 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 |
4999 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 |
5000 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 |
5001 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 |
5002 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 |
5003 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 |
5004 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 |
5005 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 |
5006 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 |
5007 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a |
5008 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b |
5009 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c |
5010 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d |
5011 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e |
5012 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f |
5013 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 |
5014 | #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 |
5015 | #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO 0x8000 |
5016 | #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI 0x8001 |
5017 | #define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN 0x8002 |
5018 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 |
5019 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 |
5020 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 |
5021 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 |
5022 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 |
5023 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 |
5024 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 |
5025 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a |
5026 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b |
5027 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c |
5028 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d |
5029 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e |
5030 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f |
5031 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 |
5032 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 |
5033 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 |
5034 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 |
5035 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 |
5036 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 |
5037 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 |
5038 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 |
5039 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 |
5040 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 |
5041 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a |
5042 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b |
5043 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c |
5044 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d |
5045 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e |
5046 | #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN 0x801f |
5047 | #define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 |
5048 | #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT 0x8021 |
5049 | #define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN 0x8022 |
5050 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 |
5051 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 |
5052 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 |
5053 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 |
5054 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 |
5055 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 |
5056 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a |
5057 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b |
5058 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c |
5059 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d |
5060 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e |
5061 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f |
5062 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 |
5063 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 |
5064 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 |
5065 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 |
5066 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 |
5067 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 |
5068 | #define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN 0x8036 |
5069 | #define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN 0x8037 |
5070 | #define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 |
5071 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 |
5072 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a |
5073 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b |
5074 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c |
5075 | #define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL 0x8040 |
5076 | #define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL 0x8041 |
5077 | #define ixDPCSSYS_CR1_SUPX_ANA_BG1 0x8042 |
5078 | #define ixDPCSSYS_CR1_SUPX_ANA_BG2 0x8043 |
5079 | #define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 |
5080 | #define ixDPCSSYS_CR1_SUPX_ANA_BG3 0x8045 |
5081 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1 0x8046 |
5082 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2 0x8047 |
5083 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD 0x8048 |
5084 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1 0x8049 |
5085 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2 0x804a |
5086 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3 0x804b |
5087 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1 0x804c |
5088 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2 0x804d |
5089 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3 0x804e |
5090 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4 0x804f |
5091 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5 0x8050 |
5092 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1 0x8051 |
5093 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2 0x8052 |
5094 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1 0x8053 |
5095 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2 0x8054 |
5096 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD 0x8055 |
5097 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1 0x8056 |
5098 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2 0x8057 |
5099 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3 0x8058 |
5100 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1 0x8059 |
5101 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2 0x805a |
5102 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3 0x805b |
5103 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4 0x805c |
5104 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5 0x805d |
5105 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1 0x805e |
5106 | #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2 0x805f |
5107 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 |
5108 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 |
5109 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 |
5110 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 |
5111 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 |
5112 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 |
5113 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 |
5114 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 |
5115 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 |
5116 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b |
5117 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d |
5118 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e |
5119 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f |
5120 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 |
5121 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 |
5122 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 |
5123 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 |
5124 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 |
5125 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 |
5126 | #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 |
5127 | #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 |
5128 | #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 |
5129 | #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a |
5130 | #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b |
5131 | #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c |
5132 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG 0x8081 |
5133 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT 0x8082 |
5134 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 |
5135 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 |
5136 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 |
5137 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT 0x8086 |
5138 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 |
5139 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 |
5140 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 |
5141 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a |
5142 | #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b |
5143 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c |
5144 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d |
5145 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e |
5146 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f |
5147 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 |
5148 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 |
5149 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 |
5150 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT 0x8093 |
5151 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 |
5152 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 |
5153 | #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 |
5154 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 |
5155 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 |
5156 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 |
5157 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 |
5158 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 |
5159 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 |
5160 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 |
5161 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 |
5162 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 |
5163 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 |
5164 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a |
5165 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b |
5166 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c |
5167 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d |
5168 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e |
5169 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f |
5170 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 |
5171 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 |
5172 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 |
5173 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 |
5174 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 |
5175 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 |
5176 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 |
5177 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 |
5178 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 |
5179 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 |
5180 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a |
5181 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b |
5182 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c |
5183 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d |
5184 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e |
5185 | #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA 0x901f |
5186 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 |
5187 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 |
5188 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 |
5189 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 |
5190 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 |
5191 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 |
5192 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 |
5193 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 |
5194 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 |
5195 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 |
5196 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a |
5197 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b |
5198 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c |
5199 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d |
5200 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e |
5201 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f |
5202 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 |
5203 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 |
5204 | #define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL 0x9032 |
5205 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 |
5206 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 |
5207 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 |
5208 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 |
5209 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 |
5210 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 |
5211 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 |
5212 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 |
5213 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 |
5214 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a |
5215 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b |
5216 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c |
5217 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d |
5218 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e |
5219 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f |
5220 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 |
5221 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL 0x9051 |
5222 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR 0x9052 |
5223 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 |
5224 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 |
5225 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 |
5226 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 |
5227 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 |
5228 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT 0x9058 |
5229 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ 0x9059 |
5230 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a |
5231 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b |
5232 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 |
5233 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 |
5234 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 |
5235 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 |
5236 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 |
5237 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 |
5238 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 |
5239 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 |
5240 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 |
5241 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 |
5242 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a |
5243 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b |
5244 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c |
5245 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d |
5246 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e |
5247 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f |
5248 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 |
5249 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 |
5250 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 |
5251 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 |
5252 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 |
5253 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 |
5254 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 |
5255 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 |
5256 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 |
5257 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 |
5258 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a |
5259 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b |
5260 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c |
5261 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d |
5262 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e |
5263 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f |
5264 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 |
5265 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 |
5266 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 |
5267 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 |
5268 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 |
5269 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 |
5270 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 |
5271 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 |
5272 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 |
5273 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 |
5274 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a |
5275 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b |
5276 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c |
5277 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d |
5278 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e |
5279 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f |
5280 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 |
5281 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 |
5282 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 |
5283 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 |
5284 | #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 |
5285 | #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 |
5286 | #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 |
5287 | #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 |
5288 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 |
5289 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 |
5290 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 |
5291 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 |
5292 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 |
5293 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 |
5294 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 |
5295 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 |
5296 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 |
5297 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 |
5298 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa |
5299 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab |
5300 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac |
5301 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad |
5302 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL 0x90ae |
5303 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af |
5304 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 |
5305 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 |
5306 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 |
5307 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 |
5308 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE 0x90b4 |
5309 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 |
5310 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 |
5311 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 |
5312 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 |
5313 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 |
5314 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba |
5315 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0 0x90bb |
5316 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1 0x90bc |
5317 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd |
5318 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be |
5319 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf |
5320 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 |
5321 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 |
5322 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 |
5323 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 |
5324 | #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 |
5325 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS 0x90e0 |
5326 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD 0x90e1 |
5327 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS 0x90e2 |
5328 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1 0x90e3 |
5329 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2 0x90e4 |
5330 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC 0x90e5 |
5331 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1 0x90e6 |
5332 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE 0x90e7 |
5333 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 |
5334 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK 0x90e9 |
5335 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1 0x90ea |
5336 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2 0x90eb |
5337 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3 0x90ec |
5338 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2 0x90ed |
5339 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3 0x90ee |
5340 | #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4 0x90ef |
5341 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1 0x90f0 |
5342 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2 0x90f1 |
5343 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES 0x90f2 |
5344 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL 0x90f3 |
5345 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1 0x90f4 |
5346 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2 0x90f5 |
5347 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ 0x90f6 |
5348 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1 0x90f7 |
5349 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2 0x90f8 |
5350 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF 0x90f9 |
5351 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1 0x90fa |
5352 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2 0x90fb |
5353 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3 0x90fc |
5354 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4 0x90fd |
5355 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC 0x90fe |
5356 | #define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1 0x90ff |
5357 | #define ixDPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 |
5358 | #define ixDPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 |
5359 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 |
5360 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 |
5361 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 |
5362 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 |
5363 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 |
5364 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 |
5365 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 |
5366 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 |
5367 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 |
5368 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 |
5369 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a |
5370 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b |
5371 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c |
5372 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d |
5373 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e |
5374 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f |
5375 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 |
5376 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 |
5377 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 |
5378 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 |
5379 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 |
5380 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 |
5381 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 |
5382 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 |
5383 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 |
5384 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 |
5385 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a |
5386 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b |
5387 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c |
5388 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d |
5389 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e |
5390 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f |
5391 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 |
5392 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 |
5393 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 |
5394 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 |
5395 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 |
5396 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 |
5397 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 |
5398 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 |
5399 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 |
5400 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 |
5401 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a |
5402 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b |
5403 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c |
5404 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d |
5405 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e |
5406 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f |
5407 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 |
5408 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 |
5409 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 |
5410 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 |
5411 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 |
5412 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 |
5413 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 |
5414 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 |
5415 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 |
5416 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 |
5417 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a |
5418 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b |
5419 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA 0xe03c |
5420 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d |
5421 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e |
5422 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f |
5423 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 |
5424 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 |
5425 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 |
5426 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 |
5427 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 |
5428 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 |
5429 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 |
5430 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 |
5431 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 |
5432 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 |
5433 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a |
5434 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b |
5435 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c |
5436 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d |
5437 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e |
5438 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f |
5439 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 |
5440 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 |
5441 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 |
5442 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 |
5443 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 |
5444 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 |
5445 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 |
5446 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 |
5447 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 |
5448 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 |
5449 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a |
5450 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b |
5451 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 |
5452 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 |
5453 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 |
5454 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 |
5455 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 |
5456 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 |
5457 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 |
5458 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 |
5459 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 |
5460 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 |
5461 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a |
5462 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b |
5463 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c |
5464 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 |
5465 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 |
5466 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 |
5467 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 |
5468 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 |
5469 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 |
5470 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 |
5471 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 |
5472 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 |
5473 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 |
5474 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 |
5475 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 |
5476 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 |
5477 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 |
5478 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 |
5479 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 |
5480 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 |
5481 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 |
5482 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 |
5483 | #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 |
5484 | |
5485 | |
5486 | // addressBlock: dpcssys_cr2_rdpcstxcrind |
5487 | // base address: 0x0 |
5488 | #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO 0x0000 |
5489 | #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI 0x0001 |
5490 | #define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN 0x0002 |
5491 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 |
5492 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 |
5493 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 |
5494 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 |
5495 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 |
5496 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 |
5497 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 |
5498 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a |
5499 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b |
5500 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c |
5501 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d |
5502 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3 0x000e |
5503 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4 0x000f |
5504 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 |
5505 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 |
5506 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 |
5507 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 |
5508 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 |
5509 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 |
5510 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 |
5511 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 |
5512 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 |
5513 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 |
5514 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3 0x001a |
5515 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4 0x001b |
5516 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5 0x001c |
5517 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d |
5518 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e |
5519 | #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN 0x001f |
5520 | #define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN 0x0020 |
5521 | #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT 0x0021 |
5522 | #define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN 0x0022 |
5523 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 |
5524 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 |
5525 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 |
5526 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 |
5527 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 |
5528 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 |
5529 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6 0x002a |
5530 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0 0x002b |
5531 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1 0x002c |
5532 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2 0x002d |
5533 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3 0x002e |
5534 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4 0x002f |
5535 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 |
5536 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 |
5537 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 |
5538 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 |
5539 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 |
5540 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 |
5541 | #define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN 0x0036 |
5542 | #define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN 0x0037 |
5543 | #define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN 0x0038 |
5544 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 |
5545 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a |
5546 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b |
5547 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c |
5548 | #define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL 0x0040 |
5549 | #define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL 0x0041 |
5550 | #define ixDPCSSYS_CR2_SUP_ANA_BG1 0x0042 |
5551 | #define ixDPCSSYS_CR2_SUP_ANA_BG2 0x0043 |
5552 | #define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS 0x0044 |
5553 | #define ixDPCSSYS_CR2_SUP_ANA_BG3 0x0045 |
5554 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1 0x0046 |
5555 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2 0x0047 |
5556 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD 0x0048 |
5557 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1 0x0049 |
5558 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2 0x004a |
5559 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3 0x004b |
5560 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1 0x004c |
5561 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2 0x004d |
5562 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3 0x004e |
5563 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4 0x004f |
5564 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5 0x0050 |
5565 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1 0x0051 |
5566 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2 0x0052 |
5567 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1 0x0053 |
5568 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2 0x0054 |
5569 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD 0x0055 |
5570 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1 0x0056 |
5571 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2 0x0057 |
5572 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3 0x0058 |
5573 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1 0x0059 |
5574 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2 0x005a |
5575 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3 0x005b |
5576 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4 0x005c |
5577 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5 0x005d |
5578 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1 0x005e |
5579 | #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2 0x005f |
5580 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 |
5581 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 |
5582 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 |
5583 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 |
5584 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 |
5585 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 |
5586 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 |
5587 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 |
5588 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 |
5589 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b |
5590 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d |
5591 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e |
5592 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f |
5593 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 |
5594 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 |
5595 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 |
5596 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 |
5597 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 |
5598 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 |
5599 | #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 |
5600 | #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 |
5601 | #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 |
5602 | #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a |
5603 | #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b |
5604 | #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD 0x007c |
5605 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG 0x0081 |
5606 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT 0x0082 |
5607 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 |
5608 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 |
5609 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 |
5610 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT 0x0086 |
5611 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT 0x0087 |
5612 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT 0x0088 |
5613 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 |
5614 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a |
5615 | #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b |
5616 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c |
5617 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d |
5618 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e |
5619 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f |
5620 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 |
5621 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 |
5622 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 |
5623 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT 0x0093 |
5624 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 |
5625 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 |
5626 | #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 |
5627 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 |
5628 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 |
5629 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 |
5630 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 |
5631 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 |
5632 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 |
5633 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 |
5634 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f |
5635 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 |
5636 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 |
5637 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 |
5638 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 |
5639 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 |
5640 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b |
5641 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d |
5642 | #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e |
5643 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 |
5644 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 |
5645 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 |
5646 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 |
5647 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 |
5648 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 |
5649 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 |
5650 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 |
5651 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 |
5652 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 |
5653 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a |
5654 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b |
5655 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c |
5656 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d |
5657 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e |
5658 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f |
5659 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 |
5660 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 |
5661 | #define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL 0x1032 |
5662 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 |
5663 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 |
5664 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 |
5665 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 |
5666 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 |
5667 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 |
5668 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 |
5669 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 |
5670 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 |
5671 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 |
5672 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a |
5673 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b |
5674 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c |
5675 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d |
5676 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e |
5677 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f |
5678 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 |
5679 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 |
5680 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 |
5681 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 |
5682 | #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 |
5683 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 |
5684 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 |
5685 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 |
5686 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 |
5687 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 |
5688 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 |
5689 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 |
5690 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 |
5691 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 |
5692 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0 0x10bb |
5693 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 |
5694 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 |
5695 | #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 |
5696 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS 0x10e0 |
5697 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD 0x10e1 |
5698 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS 0x10e2 |
5699 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1 0x10e3 |
5700 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2 0x10e4 |
5701 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC 0x10e5 |
5702 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1 0x10e6 |
5703 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE 0x10e7 |
5704 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 |
5705 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK 0x10e9 |
5706 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1 0x10ea |
5707 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2 0x10eb |
5708 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3 0x10ec |
5709 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2 0x10ed |
5710 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3 0x10ee |
5711 | #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4 0x10ef |
5712 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 |
5713 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 |
5714 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 |
5715 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 |
5716 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 |
5717 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 |
5718 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 |
5719 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 |
5720 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 |
5721 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 |
5722 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a |
5723 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b |
5724 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c |
5725 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d |
5726 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e |
5727 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f |
5728 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 |
5729 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 |
5730 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 |
5731 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 |
5732 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 |
5733 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 |
5734 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 |
5735 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 |
5736 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 |
5737 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 |
5738 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a |
5739 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b |
5740 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c |
5741 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d |
5742 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e |
5743 | #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA 0x111f |
5744 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 |
5745 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 |
5746 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 |
5747 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 |
5748 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 |
5749 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 |
5750 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 |
5751 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 |
5752 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 |
5753 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 |
5754 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a |
5755 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b |
5756 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c |
5757 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d |
5758 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e |
5759 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f |
5760 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 |
5761 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 |
5762 | #define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL 0x1132 |
5763 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 |
5764 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 |
5765 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 |
5766 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 |
5767 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 |
5768 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 |
5769 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 |
5770 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 |
5771 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 |
5772 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a |
5773 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b |
5774 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c |
5775 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d |
5776 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e |
5777 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f |
5778 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 |
5779 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL 0x1151 |
5780 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR 0x1152 |
5781 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 |
5782 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 |
5783 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 |
5784 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 |
5785 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 |
5786 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT 0x1158 |
5787 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ 0x1159 |
5788 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a |
5789 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b |
5790 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 |
5791 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 |
5792 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 |
5793 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 |
5794 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 |
5795 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 |
5796 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 |
5797 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 |
5798 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 |
5799 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 |
5800 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a |
5801 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b |
5802 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c |
5803 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d |
5804 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e |
5805 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f |
5806 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 |
5807 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 |
5808 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 |
5809 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 |
5810 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 |
5811 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 |
5812 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 |
5813 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 |
5814 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 |
5815 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 |
5816 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a |
5817 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b |
5818 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c |
5819 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d |
5820 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e |
5821 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f |
5822 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 |
5823 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 |
5824 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 |
5825 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 |
5826 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 |
5827 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 |
5828 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 |
5829 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 |
5830 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 |
5831 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 |
5832 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a |
5833 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b |
5834 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c |
5835 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d |
5836 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e |
5837 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f |
5838 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 |
5839 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 |
5840 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 |
5841 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 |
5842 | #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 |
5843 | #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 |
5844 | #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 |
5845 | #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 |
5846 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 |
5847 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 |
5848 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 |
5849 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 |
5850 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 |
5851 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 |
5852 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 |
5853 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 |
5854 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 |
5855 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 |
5856 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa |
5857 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab |
5858 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac |
5859 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad |
5860 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL 0x11ae |
5861 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af |
5862 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 |
5863 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 |
5864 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 |
5865 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 |
5866 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE 0x11b4 |
5867 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 |
5868 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 |
5869 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 |
5870 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 |
5871 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 |
5872 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba |
5873 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0 0x11bb |
5874 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1 0x11bc |
5875 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd |
5876 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be |
5877 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf |
5878 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 |
5879 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 |
5880 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 |
5881 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 |
5882 | #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 |
5883 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS 0x11e0 |
5884 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD 0x11e1 |
5885 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS 0x11e2 |
5886 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1 0x11e3 |
5887 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2 0x11e4 |
5888 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC 0x11e5 |
5889 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1 0x11e6 |
5890 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE 0x11e7 |
5891 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 |
5892 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK 0x11e9 |
5893 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1 0x11ea |
5894 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2 0x11eb |
5895 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3 0x11ec |
5896 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2 0x11ed |
5897 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3 0x11ee |
5898 | #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4 0x11ef |
5899 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1 0x11f0 |
5900 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2 0x11f1 |
5901 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES 0x11f2 |
5902 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL 0x11f3 |
5903 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1 0x11f4 |
5904 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2 0x11f5 |
5905 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ 0x11f6 |
5906 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1 0x11f7 |
5907 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2 0x11f8 |
5908 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF 0x11f9 |
5909 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1 0x11fa |
5910 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2 0x11fb |
5911 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3 0x11fc |
5912 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4 0x11fd |
5913 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC 0x11fe |
5914 | #define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1 0x11ff |
5915 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 |
5916 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 |
5917 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 |
5918 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 |
5919 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 |
5920 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 |
5921 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 |
5922 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 |
5923 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 |
5924 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 |
5925 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a |
5926 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b |
5927 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c |
5928 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d |
5929 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e |
5930 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f |
5931 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 |
5932 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 |
5933 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 |
5934 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 |
5935 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 |
5936 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 |
5937 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 |
5938 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 |
5939 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 |
5940 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 |
5941 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a |
5942 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b |
5943 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c |
5944 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d |
5945 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e |
5946 | #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA 0x121f |
5947 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 |
5948 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 |
5949 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 |
5950 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 |
5951 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 |
5952 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 |
5953 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 |
5954 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 |
5955 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 |
5956 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 |
5957 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a |
5958 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b |
5959 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c |
5960 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d |
5961 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e |
5962 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f |
5963 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 |
5964 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 |
5965 | #define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL 0x1232 |
5966 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 |
5967 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 |
5968 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 |
5969 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 |
5970 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 |
5971 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 |
5972 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 |
5973 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 |
5974 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 |
5975 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a |
5976 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b |
5977 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c |
5978 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d |
5979 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e |
5980 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f |
5981 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 |
5982 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL 0x1251 |
5983 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR 0x1252 |
5984 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 |
5985 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 |
5986 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 |
5987 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 |
5988 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 |
5989 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT 0x1258 |
5990 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ 0x1259 |
5991 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a |
5992 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b |
5993 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 |
5994 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 |
5995 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 |
5996 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 |
5997 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 |
5998 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 |
5999 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 |
6000 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 |
6001 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 |
6002 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 |
6003 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a |
6004 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b |
6005 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c |
6006 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d |
6007 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e |
6008 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f |
6009 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 |
6010 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 |
6011 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 |
6012 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 |
6013 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 |
6014 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 |
6015 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 |
6016 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 |
6017 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 |
6018 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 |
6019 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a |
6020 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b |
6021 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c |
6022 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d |
6023 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e |
6024 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f |
6025 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 |
6026 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 |
6027 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 |
6028 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 |
6029 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 |
6030 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 |
6031 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 |
6032 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 |
6033 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 |
6034 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 |
6035 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a |
6036 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b |
6037 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c |
6038 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d |
6039 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e |
6040 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f |
6041 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 |
6042 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 |
6043 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 |
6044 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 |
6045 | #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 |
6046 | #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 |
6047 | #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 |
6048 | #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 |
6049 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 |
6050 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 |
6051 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 |
6052 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 |
6053 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 |
6054 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 |
6055 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 |
6056 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 |
6057 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 |
6058 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 |
6059 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa |
6060 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab |
6061 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac |
6062 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad |
6063 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL 0x12ae |
6064 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af |
6065 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 |
6066 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 |
6067 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 |
6068 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 |
6069 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE 0x12b4 |
6070 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 |
6071 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 |
6072 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 |
6073 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 |
6074 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 |
6075 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba |
6076 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0 0x12bb |
6077 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1 0x12bc |
6078 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd |
6079 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be |
6080 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf |
6081 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 |
6082 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 |
6083 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 |
6084 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 |
6085 | #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 |
6086 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS 0x12e0 |
6087 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD 0x12e1 |
6088 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS 0x12e2 |
6089 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1 0x12e3 |
6090 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2 0x12e4 |
6091 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC 0x12e5 |
6092 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1 0x12e6 |
6093 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE 0x12e7 |
6094 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 |
6095 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK 0x12e9 |
6096 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1 0x12ea |
6097 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2 0x12eb |
6098 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3 0x12ec |
6099 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2 0x12ed |
6100 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3 0x12ee |
6101 | #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4 0x12ef |
6102 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1 0x12f0 |
6103 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2 0x12f1 |
6104 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES 0x12f2 |
6105 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL 0x12f3 |
6106 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1 0x12f4 |
6107 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2 0x12f5 |
6108 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ 0x12f6 |
6109 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1 0x12f7 |
6110 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2 0x12f8 |
6111 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF 0x12f9 |
6112 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1 0x12fa |
6113 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2 0x12fb |
6114 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3 0x12fc |
6115 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4 0x12fd |
6116 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC 0x12fe |
6117 | #define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1 0x12ff |
6118 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 |
6119 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 |
6120 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 |
6121 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 |
6122 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 |
6123 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 |
6124 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 |
6125 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f |
6126 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 |
6127 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 |
6128 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 |
6129 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 |
6130 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 |
6131 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b |
6132 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d |
6133 | #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e |
6134 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 |
6135 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 |
6136 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 |
6137 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 |
6138 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 |
6139 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 |
6140 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 |
6141 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 |
6142 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 |
6143 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 |
6144 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a |
6145 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b |
6146 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c |
6147 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d |
6148 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e |
6149 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f |
6150 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 |
6151 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 |
6152 | #define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL 0x1332 |
6153 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 |
6154 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 |
6155 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 |
6156 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 |
6157 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 |
6158 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 |
6159 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 |
6160 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 |
6161 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 |
6162 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 |
6163 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a |
6164 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b |
6165 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c |
6166 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d |
6167 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e |
6168 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f |
6169 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 |
6170 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 |
6171 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 |
6172 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 |
6173 | #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 |
6174 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 |
6175 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 |
6176 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 |
6177 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 |
6178 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 |
6179 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 |
6180 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 |
6181 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 |
6182 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 |
6183 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0 0x13bb |
6184 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 |
6185 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 |
6186 | #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 |
6187 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS 0x13e0 |
6188 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD 0x13e1 |
6189 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS 0x13e2 |
6190 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1 0x13e3 |
6191 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2 0x13e4 |
6192 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC 0x13e5 |
6193 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1 0x13e6 |
6194 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE 0x13e7 |
6195 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 |
6196 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK 0x13e9 |
6197 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1 0x13ea |
6198 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2 0x13eb |
6199 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3 0x13ec |
6200 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2 0x13ed |
6201 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3 0x13ee |
6202 | #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4 0x13ef |
6203 | #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL 0x2000 |
6204 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 |
6205 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 |
6206 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 |
6207 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 |
6208 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 |
6209 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 |
6210 | #define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 |
6211 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 |
6212 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 |
6213 | #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1 0x200a |
6214 | #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL 0x200b |
6215 | #define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE 0x200c |
6216 | #define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE 0x200d |
6217 | #define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA 0x200e |
6218 | #define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD 0x200f |
6219 | #define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 |
6220 | #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1 0x2011 |
6221 | #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2 0x2012 |
6222 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 |
6223 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 |
6224 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 |
6225 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 |
6226 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 |
6227 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 |
6228 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 |
6229 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 |
6230 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 |
6231 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 |
6232 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a |
6233 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b |
6234 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c |
6235 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d |
6236 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e |
6237 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f |
6238 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 |
6239 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 |
6240 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 |
6241 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 |
6242 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 |
6243 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 |
6244 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 |
6245 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 |
6246 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 |
6247 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 |
6248 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a |
6249 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b |
6250 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c |
6251 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d |
6252 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e |
6253 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f |
6254 | #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 |
6255 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 |
6256 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 |
6257 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 |
6258 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 |
6259 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 |
6260 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 |
6261 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 |
6262 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 |
6263 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 |
6264 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 |
6265 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a |
6266 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b |
6267 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c |
6268 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d |
6269 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e |
6270 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f |
6271 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 |
6272 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 |
6273 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 |
6274 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 |
6275 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 |
6276 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 |
6277 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 |
6278 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 |
6279 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 |
6280 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 |
6281 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a |
6282 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b |
6283 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c |
6284 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d |
6285 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e |
6286 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f |
6287 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 |
6288 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 |
6289 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 |
6290 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 |
6291 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 |
6292 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 |
6293 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 |
6294 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 |
6295 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 |
6296 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 |
6297 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a |
6298 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b |
6299 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP 0x302c |
6300 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d |
6301 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e |
6302 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f |
6303 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 |
6304 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 |
6305 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 |
6306 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 |
6307 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 |
6308 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 |
6309 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 |
6310 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 |
6311 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 |
6312 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 |
6313 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a |
6314 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b |
6315 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA 0x303c |
6316 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d |
6317 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e |
6318 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f |
6319 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 |
6320 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 |
6321 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 |
6322 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 |
6323 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 |
6324 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 |
6325 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 |
6326 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 |
6327 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 |
6328 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 |
6329 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a |
6330 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b |
6331 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c |
6332 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d |
6333 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e |
6334 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f |
6335 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 |
6336 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 |
6337 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 |
6338 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 |
6339 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 |
6340 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 |
6341 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 |
6342 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 |
6343 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 |
6344 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 |
6345 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a |
6346 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b |
6347 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 |
6348 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 |
6349 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 |
6350 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 |
6351 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 |
6352 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 |
6353 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 |
6354 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 |
6355 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 |
6356 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 |
6357 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a |
6358 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b |
6359 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c |
6360 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 |
6361 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 |
6362 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 |
6363 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 |
6364 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 |
6365 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 |
6366 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 |
6367 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 |
6368 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 |
6369 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 |
6370 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 |
6371 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 |
6372 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 |
6373 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 |
6374 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 |
6375 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 |
6376 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 |
6377 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 |
6378 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 |
6379 | #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 |
6380 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 |
6381 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 |
6382 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 |
6383 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 |
6384 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 |
6385 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 |
6386 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 |
6387 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 |
6388 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 |
6389 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 |
6390 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a |
6391 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b |
6392 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c |
6393 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d |
6394 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e |
6395 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f |
6396 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 |
6397 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 |
6398 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 |
6399 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 |
6400 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 |
6401 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 |
6402 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 |
6403 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 |
6404 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 |
6405 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 |
6406 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a |
6407 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b |
6408 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c |
6409 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d |
6410 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e |
6411 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f |
6412 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 |
6413 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 |
6414 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 |
6415 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 |
6416 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 |
6417 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 |
6418 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 |
6419 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 |
6420 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 |
6421 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 |
6422 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a |
6423 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b |
6424 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP 0x312c |
6425 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d |
6426 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e |
6427 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f |
6428 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 |
6429 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 |
6430 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 |
6431 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 |
6432 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 |
6433 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 |
6434 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 |
6435 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 |
6436 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 |
6437 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 |
6438 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a |
6439 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b |
6440 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA 0x313c |
6441 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d |
6442 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e |
6443 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f |
6444 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 |
6445 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 |
6446 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 |
6447 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 |
6448 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 |
6449 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 |
6450 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 |
6451 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 |
6452 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 |
6453 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 |
6454 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a |
6455 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b |
6456 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c |
6457 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d |
6458 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e |
6459 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f |
6460 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 |
6461 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 |
6462 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 |
6463 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 |
6464 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 |
6465 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 |
6466 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 |
6467 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 |
6468 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 |
6469 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 |
6470 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a |
6471 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b |
6472 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 |
6473 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 |
6474 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 |
6475 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 |
6476 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 |
6477 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 |
6478 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 |
6479 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 |
6480 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 |
6481 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 |
6482 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a |
6483 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b |
6484 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c |
6485 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 |
6486 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 |
6487 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 |
6488 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 |
6489 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 |
6490 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 |
6491 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 |
6492 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 |
6493 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 |
6494 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 |
6495 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 |
6496 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 |
6497 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 |
6498 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 |
6499 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 |
6500 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 |
6501 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 |
6502 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 |
6503 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 |
6504 | #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 |
6505 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 |
6506 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 |
6507 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 |
6508 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 |
6509 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 |
6510 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 |
6511 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 |
6512 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 |
6513 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 |
6514 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 |
6515 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a |
6516 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b |
6517 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c |
6518 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d |
6519 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e |
6520 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f |
6521 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 |
6522 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 |
6523 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 |
6524 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 |
6525 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 |
6526 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 |
6527 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 |
6528 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 |
6529 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 |
6530 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 |
6531 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a |
6532 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b |
6533 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c |
6534 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d |
6535 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e |
6536 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f |
6537 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 |
6538 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 |
6539 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 |
6540 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 |
6541 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 |
6542 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 |
6543 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 |
6544 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 |
6545 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 |
6546 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 |
6547 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a |
6548 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b |
6549 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP 0x322c |
6550 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d |
6551 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e |
6552 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f |
6553 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 |
6554 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 |
6555 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 |
6556 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 |
6557 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 |
6558 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 |
6559 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 |
6560 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 |
6561 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 |
6562 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 |
6563 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a |
6564 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b |
6565 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA 0x323c |
6566 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d |
6567 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e |
6568 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f |
6569 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 |
6570 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 |
6571 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 |
6572 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 |
6573 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 |
6574 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 |
6575 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 |
6576 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 |
6577 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 |
6578 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 |
6579 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a |
6580 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b |
6581 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c |
6582 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d |
6583 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e |
6584 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f |
6585 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 |
6586 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 |
6587 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 |
6588 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 |
6589 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 |
6590 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 |
6591 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 |
6592 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 |
6593 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 |
6594 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 |
6595 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a |
6596 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b |
6597 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 |
6598 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 |
6599 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 |
6600 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 |
6601 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 |
6602 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 |
6603 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 |
6604 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 |
6605 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 |
6606 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 |
6607 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a |
6608 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b |
6609 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c |
6610 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 |
6611 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 |
6612 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 |
6613 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 |
6614 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 |
6615 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 |
6616 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 |
6617 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 |
6618 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 |
6619 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 |
6620 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 |
6621 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 |
6622 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 |
6623 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 |
6624 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 |
6625 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 |
6626 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 |
6627 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 |
6628 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 |
6629 | #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 |
6630 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 |
6631 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 |
6632 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 |
6633 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 |
6634 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 |
6635 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 |
6636 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 |
6637 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 |
6638 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 |
6639 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 |
6640 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a |
6641 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b |
6642 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c |
6643 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d |
6644 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e |
6645 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f |
6646 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 |
6647 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 |
6648 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 |
6649 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 |
6650 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 |
6651 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 |
6652 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 |
6653 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 |
6654 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 |
6655 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 |
6656 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a |
6657 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b |
6658 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c |
6659 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d |
6660 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e |
6661 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f |
6662 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 |
6663 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 |
6664 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 |
6665 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 |
6666 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 |
6667 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 |
6668 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 |
6669 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 |
6670 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 |
6671 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 |
6672 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a |
6673 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b |
6674 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP 0x332c |
6675 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d |
6676 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e |
6677 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f |
6678 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 |
6679 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 |
6680 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 |
6681 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 |
6682 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 |
6683 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 |
6684 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 |
6685 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 |
6686 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 |
6687 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 |
6688 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a |
6689 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b |
6690 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA 0x333c |
6691 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d |
6692 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e |
6693 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f |
6694 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 |
6695 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 |
6696 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 |
6697 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 |
6698 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 |
6699 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 |
6700 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 |
6701 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 |
6702 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 |
6703 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 |
6704 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a |
6705 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b |
6706 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c |
6707 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d |
6708 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e |
6709 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f |
6710 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 |
6711 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 |
6712 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 |
6713 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 |
6714 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 |
6715 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 |
6716 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 |
6717 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 |
6718 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 |
6719 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 |
6720 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a |
6721 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b |
6722 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 |
6723 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 |
6724 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 |
6725 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 |
6726 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 |
6727 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 |
6728 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 |
6729 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 |
6730 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 |
6731 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 |
6732 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a |
6733 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b |
6734 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c |
6735 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 |
6736 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 |
6737 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 |
6738 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 |
6739 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 |
6740 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 |
6741 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 |
6742 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 |
6743 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 |
6744 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 |
6745 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 |
6746 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 |
6747 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 |
6748 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 |
6749 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 |
6750 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 |
6751 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 |
6752 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 |
6753 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 |
6754 | #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 |
6755 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 |
6756 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 |
6757 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 |
6758 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 |
6759 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 |
6760 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 |
6761 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 |
6762 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 |
6763 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 |
6764 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 |
6765 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a |
6766 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b |
6767 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c |
6768 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d |
6769 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e |
6770 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f |
6771 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 |
6772 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 |
6773 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 |
6774 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 |
6775 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 |
6776 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 |
6777 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 |
6778 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 |
6779 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 |
6780 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 |
6781 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a |
6782 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b |
6783 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS 0x401c |
6784 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d |
6785 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e |
6786 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f |
6787 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 |
6788 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 |
6789 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 |
6790 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 |
6791 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 |
6792 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 |
6793 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 |
6794 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 |
6795 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 |
6796 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 |
6797 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a |
6798 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b |
6799 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c |
6800 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d |
6801 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e |
6802 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f |
6803 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 |
6804 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 |
6805 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS 0x4032 |
6806 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 |
6807 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 |
6808 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 |
6809 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 |
6810 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 |
6811 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 |
6812 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 |
6813 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a |
6814 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b |
6815 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c |
6816 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d |
6817 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e |
6818 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f |
6819 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 |
6820 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 |
6821 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 |
6822 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 |
6823 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 |
6824 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 |
6825 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 |
6826 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 |
6827 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 |
6828 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 |
6829 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a |
6830 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b |
6831 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c |
6832 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d |
6833 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e |
6834 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f |
6835 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 |
6836 | #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 |
6837 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 |
6838 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 |
6839 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 |
6840 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 |
6841 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 |
6842 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 |
6843 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 |
6844 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 |
6845 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 |
6846 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 |
6847 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a |
6848 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b |
6849 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c |
6850 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d |
6851 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e |
6852 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f |
6853 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 |
6854 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 |
6855 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 |
6856 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 |
6857 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 |
6858 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 |
6859 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 |
6860 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 |
6861 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 |
6862 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 |
6863 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a |
6864 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b |
6865 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS 0x411c |
6866 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d |
6867 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e |
6868 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f |
6869 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 |
6870 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 |
6871 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 |
6872 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 |
6873 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 |
6874 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 |
6875 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 |
6876 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 |
6877 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 |
6878 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 |
6879 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a |
6880 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b |
6881 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c |
6882 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d |
6883 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e |
6884 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f |
6885 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 |
6886 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 |
6887 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS 0x4132 |
6888 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 |
6889 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 |
6890 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 |
6891 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 |
6892 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 |
6893 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 |
6894 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 |
6895 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a |
6896 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b |
6897 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c |
6898 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d |
6899 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e |
6900 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f |
6901 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 |
6902 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 |
6903 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 |
6904 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 |
6905 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 |
6906 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 |
6907 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 |
6908 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 |
6909 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 |
6910 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 |
6911 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a |
6912 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b |
6913 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c |
6914 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d |
6915 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e |
6916 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f |
6917 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 |
6918 | #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 |
6919 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 |
6920 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 |
6921 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 |
6922 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 |
6923 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 |
6924 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 |
6925 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 |
6926 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 |
6927 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 |
6928 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 |
6929 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a |
6930 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b |
6931 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c |
6932 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d |
6933 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e |
6934 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f |
6935 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 |
6936 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 |
6937 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 |
6938 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 |
6939 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 |
6940 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 |
6941 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 |
6942 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 |
6943 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 |
6944 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 |
6945 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a |
6946 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b |
6947 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS 0x421c |
6948 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d |
6949 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e |
6950 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f |
6951 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 |
6952 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 |
6953 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 |
6954 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 |
6955 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 |
6956 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 |
6957 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 |
6958 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 |
6959 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 |
6960 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 |
6961 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a |
6962 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b |
6963 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c |
6964 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d |
6965 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e |
6966 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f |
6967 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 |
6968 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 |
6969 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS 0x4232 |
6970 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 |
6971 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 |
6972 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 |
6973 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 |
6974 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 |
6975 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 |
6976 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 |
6977 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a |
6978 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b |
6979 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c |
6980 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d |
6981 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e |
6982 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f |
6983 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 |
6984 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 |
6985 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 |
6986 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 |
6987 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 |
6988 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 |
6989 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 |
6990 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 |
6991 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 |
6992 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 |
6993 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a |
6994 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b |
6995 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c |
6996 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d |
6997 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e |
6998 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f |
6999 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 |
7000 | #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 |
7001 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 |
7002 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 |
7003 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 |
7004 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 |
7005 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 |
7006 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 |
7007 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 |
7008 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 |
7009 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 |
7010 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 |
7011 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a |
7012 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b |
7013 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c |
7014 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d |
7015 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e |
7016 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f |
7017 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 |
7018 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 |
7019 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 |
7020 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 |
7021 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 |
7022 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 |
7023 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 |
7024 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 |
7025 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 |
7026 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 |
7027 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a |
7028 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b |
7029 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS 0x431c |
7030 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d |
7031 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e |
7032 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f |
7033 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 |
7034 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 |
7035 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 |
7036 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 |
7037 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 |
7038 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 |
7039 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 |
7040 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 |
7041 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 |
7042 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 |
7043 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a |
7044 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b |
7045 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c |
7046 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d |
7047 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e |
7048 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f |
7049 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 |
7050 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 |
7051 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS 0x4332 |
7052 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 |
7053 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 |
7054 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 |
7055 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 |
7056 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 |
7057 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 |
7058 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 |
7059 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a |
7060 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b |
7061 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c |
7062 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d |
7063 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e |
7064 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f |
7065 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 |
7066 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 |
7067 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 |
7068 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 |
7069 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 |
7070 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 |
7071 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 |
7072 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 |
7073 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 |
7074 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 |
7075 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a |
7076 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b |
7077 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c |
7078 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d |
7079 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e |
7080 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f |
7081 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 |
7082 | #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 |
7083 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 |
7084 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 |
7085 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 |
7086 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 |
7087 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 |
7088 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 |
7089 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 |
7090 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 |
7091 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 |
7092 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 |
7093 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a |
7094 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b |
7095 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c |
7096 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d |
7097 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e |
7098 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f |
7099 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 |
7100 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 |
7101 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 |
7102 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 |
7103 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 |
7104 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 |
7105 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 |
7106 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 |
7107 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 |
7108 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 |
7109 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a |
7110 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b |
7111 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS 0x701c |
7112 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d |
7113 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e |
7114 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f |
7115 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 |
7116 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 |
7117 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 |
7118 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 |
7119 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 |
7120 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 |
7121 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 |
7122 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 |
7123 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 |
7124 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 |
7125 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a |
7126 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b |
7127 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c |
7128 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d |
7129 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e |
7130 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f |
7131 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 |
7132 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 |
7133 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS 0x7032 |
7134 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 |
7135 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 |
7136 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 |
7137 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 |
7138 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 |
7139 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 |
7140 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 |
7141 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a |
7142 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b |
7143 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c |
7144 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d |
7145 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e |
7146 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f |
7147 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 |
7148 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 |
7149 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 |
7150 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 |
7151 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 |
7152 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 |
7153 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 |
7154 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 |
7155 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 |
7156 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 |
7157 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a |
7158 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b |
7159 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c |
7160 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d |
7161 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e |
7162 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f |
7163 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 |
7164 | #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 |
7165 | #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO 0x8000 |
7166 | #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI 0x8001 |
7167 | #define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN 0x8002 |
7168 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 |
7169 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 |
7170 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 |
7171 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 |
7172 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 |
7173 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 |
7174 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 |
7175 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a |
7176 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b |
7177 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c |
7178 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d |
7179 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e |
7180 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f |
7181 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 |
7182 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 |
7183 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 |
7184 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 |
7185 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 |
7186 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 |
7187 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 |
7188 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 |
7189 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 |
7190 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 |
7191 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a |
7192 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b |
7193 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c |
7194 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d |
7195 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e |
7196 | #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN 0x801f |
7197 | #define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 |
7198 | #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT 0x8021 |
7199 | #define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN 0x8022 |
7200 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 |
7201 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 |
7202 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 |
7203 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 |
7204 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 |
7205 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 |
7206 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a |
7207 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b |
7208 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c |
7209 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d |
7210 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e |
7211 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f |
7212 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 |
7213 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 |
7214 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 |
7215 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 |
7216 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 |
7217 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 |
7218 | #define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN 0x8036 |
7219 | #define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN 0x8037 |
7220 | #define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 |
7221 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 |
7222 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a |
7223 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b |
7224 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c |
7225 | #define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL 0x8040 |
7226 | #define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL 0x8041 |
7227 | #define ixDPCSSYS_CR2_SUPX_ANA_BG1 0x8042 |
7228 | #define ixDPCSSYS_CR2_SUPX_ANA_BG2 0x8043 |
7229 | #define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 |
7230 | #define ixDPCSSYS_CR2_SUPX_ANA_BG3 0x8045 |
7231 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1 0x8046 |
7232 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2 0x8047 |
7233 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD 0x8048 |
7234 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1 0x8049 |
7235 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2 0x804a |
7236 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3 0x804b |
7237 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1 0x804c |
7238 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2 0x804d |
7239 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3 0x804e |
7240 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4 0x804f |
7241 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5 0x8050 |
7242 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1 0x8051 |
7243 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2 0x8052 |
7244 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1 0x8053 |
7245 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2 0x8054 |
7246 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD 0x8055 |
7247 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1 0x8056 |
7248 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2 0x8057 |
7249 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3 0x8058 |
7250 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1 0x8059 |
7251 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2 0x805a |
7252 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3 0x805b |
7253 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4 0x805c |
7254 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5 0x805d |
7255 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1 0x805e |
7256 | #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2 0x805f |
7257 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 |
7258 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 |
7259 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 |
7260 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 |
7261 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 |
7262 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 |
7263 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 |
7264 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 |
7265 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 |
7266 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b |
7267 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d |
7268 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e |
7269 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f |
7270 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 |
7271 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 |
7272 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 |
7273 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 |
7274 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 |
7275 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 |
7276 | #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 |
7277 | #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 |
7278 | #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 |
7279 | #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a |
7280 | #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b |
7281 | #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c |
7282 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG 0x8081 |
7283 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT 0x8082 |
7284 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 |
7285 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 |
7286 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 |
7287 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT 0x8086 |
7288 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 |
7289 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 |
7290 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 |
7291 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a |
7292 | #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b |
7293 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c |
7294 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d |
7295 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e |
7296 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f |
7297 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 |
7298 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 |
7299 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 |
7300 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT 0x8093 |
7301 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 |
7302 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 |
7303 | #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 |
7304 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 |
7305 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 |
7306 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 |
7307 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 |
7308 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 |
7309 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 |
7310 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 |
7311 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 |
7312 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 |
7313 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 |
7314 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a |
7315 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b |
7316 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c |
7317 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d |
7318 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e |
7319 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f |
7320 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 |
7321 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 |
7322 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 |
7323 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 |
7324 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 |
7325 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 |
7326 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 |
7327 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 |
7328 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 |
7329 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 |
7330 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a |
7331 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b |
7332 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c |
7333 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d |
7334 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e |
7335 | #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA 0x901f |
7336 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 |
7337 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 |
7338 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 |
7339 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 |
7340 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 |
7341 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 |
7342 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 |
7343 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 |
7344 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 |
7345 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 |
7346 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a |
7347 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b |
7348 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c |
7349 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d |
7350 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e |
7351 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f |
7352 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 |
7353 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 |
7354 | #define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL 0x9032 |
7355 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 |
7356 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 |
7357 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 |
7358 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 |
7359 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 |
7360 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 |
7361 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 |
7362 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 |
7363 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 |
7364 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a |
7365 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b |
7366 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c |
7367 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d |
7368 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e |
7369 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f |
7370 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 |
7371 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL 0x9051 |
7372 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR 0x9052 |
7373 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 |
7374 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 |
7375 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 |
7376 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 |
7377 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 |
7378 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT 0x9058 |
7379 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ 0x9059 |
7380 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a |
7381 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b |
7382 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 |
7383 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 |
7384 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 |
7385 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 |
7386 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 |
7387 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 |
7388 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 |
7389 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 |
7390 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 |
7391 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 |
7392 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a |
7393 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b |
7394 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c |
7395 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d |
7396 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e |
7397 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f |
7398 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 |
7399 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 |
7400 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 |
7401 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 |
7402 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 |
7403 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 |
7404 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 |
7405 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 |
7406 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 |
7407 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 |
7408 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a |
7409 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b |
7410 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c |
7411 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d |
7412 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e |
7413 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f |
7414 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 |
7415 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 |
7416 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 |
7417 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 |
7418 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 |
7419 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 |
7420 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 |
7421 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 |
7422 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 |
7423 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 |
7424 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a |
7425 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b |
7426 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c |
7427 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d |
7428 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e |
7429 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f |
7430 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 |
7431 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 |
7432 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 |
7433 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 |
7434 | #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 |
7435 | #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 |
7436 | #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 |
7437 | #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 |
7438 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 |
7439 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 |
7440 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 |
7441 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 |
7442 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 |
7443 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 |
7444 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 |
7445 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 |
7446 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 |
7447 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 |
7448 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa |
7449 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab |
7450 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac |
7451 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad |
7452 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL 0x90ae |
7453 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af |
7454 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 |
7455 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 |
7456 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 |
7457 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 |
7458 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE 0x90b4 |
7459 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 |
7460 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 |
7461 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 |
7462 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 |
7463 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 |
7464 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba |
7465 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0 0x90bb |
7466 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1 0x90bc |
7467 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd |
7468 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be |
7469 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf |
7470 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 |
7471 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 |
7472 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 |
7473 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 |
7474 | #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 |
7475 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS 0x90e0 |
7476 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD 0x90e1 |
7477 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS 0x90e2 |
7478 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1 0x90e3 |
7479 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2 0x90e4 |
7480 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC 0x90e5 |
7481 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1 0x90e6 |
7482 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE 0x90e7 |
7483 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 |
7484 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK 0x90e9 |
7485 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1 0x90ea |
7486 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2 0x90eb |
7487 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3 0x90ec |
7488 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2 0x90ed |
7489 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3 0x90ee |
7490 | #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4 0x90ef |
7491 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1 0x90f0 |
7492 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2 0x90f1 |
7493 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES 0x90f2 |
7494 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL 0x90f3 |
7495 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1 0x90f4 |
7496 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2 0x90f5 |
7497 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ 0x90f6 |
7498 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1 0x90f7 |
7499 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2 0x90f8 |
7500 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF 0x90f9 |
7501 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1 0x90fa |
7502 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2 0x90fb |
7503 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3 0x90fc |
7504 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4 0x90fd |
7505 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC 0x90fe |
7506 | #define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1 0x90ff |
7507 | #define ixDPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 |
7508 | #define ixDPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 |
7509 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 |
7510 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 |
7511 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 |
7512 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 |
7513 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 |
7514 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 |
7515 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 |
7516 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 |
7517 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 |
7518 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 |
7519 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a |
7520 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b |
7521 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c |
7522 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d |
7523 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e |
7524 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f |
7525 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 |
7526 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 |
7527 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 |
7528 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 |
7529 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 |
7530 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 |
7531 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 |
7532 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 |
7533 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 |
7534 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 |
7535 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a |
7536 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b |
7537 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c |
7538 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d |
7539 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e |
7540 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f |
7541 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 |
7542 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 |
7543 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 |
7544 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 |
7545 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 |
7546 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 |
7547 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 |
7548 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 |
7549 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 |
7550 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 |
7551 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a |
7552 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b |
7553 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c |
7554 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d |
7555 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e |
7556 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f |
7557 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 |
7558 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 |
7559 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 |
7560 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 |
7561 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 |
7562 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 |
7563 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 |
7564 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 |
7565 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 |
7566 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 |
7567 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a |
7568 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b |
7569 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA 0xe03c |
7570 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d |
7571 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e |
7572 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f |
7573 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 |
7574 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 |
7575 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 |
7576 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 |
7577 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 |
7578 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 |
7579 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 |
7580 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 |
7581 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 |
7582 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 |
7583 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a |
7584 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b |
7585 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c |
7586 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d |
7587 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e |
7588 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f |
7589 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 |
7590 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 |
7591 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 |
7592 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 |
7593 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 |
7594 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 |
7595 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 |
7596 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 |
7597 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 |
7598 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 |
7599 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a |
7600 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b |
7601 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 |
7602 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 |
7603 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 |
7604 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 |
7605 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 |
7606 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 |
7607 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 |
7608 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 |
7609 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 |
7610 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 |
7611 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a |
7612 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b |
7613 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c |
7614 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 |
7615 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 |
7616 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 |
7617 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 |
7618 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 |
7619 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 |
7620 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 |
7621 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 |
7622 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 |
7623 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 |
7624 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 |
7625 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 |
7626 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 |
7627 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 |
7628 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 |
7629 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 |
7630 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 |
7631 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 |
7632 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 |
7633 | #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 |
7634 | |
7635 | |
7636 | // addressBlock: dpcssys_cr3_rdpcstxcrind |
7637 | // base address: 0x0 |
7638 | #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO 0x0000 |
7639 | #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI 0x0001 |
7640 | #define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN 0x0002 |
7641 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 |
7642 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 |
7643 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 |
7644 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 |
7645 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 |
7646 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 |
7647 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 |
7648 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a |
7649 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b |
7650 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c |
7651 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d |
7652 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3 0x000e |
7653 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4 0x000f |
7654 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 |
7655 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 |
7656 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 |
7657 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 |
7658 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 |
7659 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 |
7660 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 |
7661 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 |
7662 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 |
7663 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 |
7664 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3 0x001a |
7665 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4 0x001b |
7666 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5 0x001c |
7667 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d |
7668 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e |
7669 | #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN 0x001f |
7670 | #define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN 0x0020 |
7671 | #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT 0x0021 |
7672 | #define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN 0x0022 |
7673 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 |
7674 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 |
7675 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 |
7676 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 |
7677 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 |
7678 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 |
7679 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6 0x002a |
7680 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0 0x002b |
7681 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1 0x002c |
7682 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2 0x002d |
7683 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3 0x002e |
7684 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4 0x002f |
7685 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 |
7686 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 |
7687 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 |
7688 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 |
7689 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 |
7690 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 |
7691 | #define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN 0x0036 |
7692 | #define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN 0x0037 |
7693 | #define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN 0x0038 |
7694 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 |
7695 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a |
7696 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b |
7697 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c |
7698 | #define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL 0x0040 |
7699 | #define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL 0x0041 |
7700 | #define ixDPCSSYS_CR3_SUP_ANA_BG1 0x0042 |
7701 | #define ixDPCSSYS_CR3_SUP_ANA_BG2 0x0043 |
7702 | #define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS 0x0044 |
7703 | #define ixDPCSSYS_CR3_SUP_ANA_BG3 0x0045 |
7704 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1 0x0046 |
7705 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2 0x0047 |
7706 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD 0x0048 |
7707 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1 0x0049 |
7708 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2 0x004a |
7709 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3 0x004b |
7710 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1 0x004c |
7711 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2 0x004d |
7712 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3 0x004e |
7713 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4 0x004f |
7714 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5 0x0050 |
7715 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1 0x0051 |
7716 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2 0x0052 |
7717 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1 0x0053 |
7718 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2 0x0054 |
7719 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD 0x0055 |
7720 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1 0x0056 |
7721 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2 0x0057 |
7722 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3 0x0058 |
7723 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1 0x0059 |
7724 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2 0x005a |
7725 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3 0x005b |
7726 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4 0x005c |
7727 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5 0x005d |
7728 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1 0x005e |
7729 | #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2 0x005f |
7730 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 |
7731 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 |
7732 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 |
7733 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 |
7734 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 |
7735 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 |
7736 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 |
7737 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 |
7738 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 |
7739 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b |
7740 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d |
7741 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e |
7742 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f |
7743 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 |
7744 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 |
7745 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 |
7746 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 |
7747 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 |
7748 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 |
7749 | #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 |
7750 | #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 |
7751 | #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 |
7752 | #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a |
7753 | #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b |
7754 | #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD 0x007c |
7755 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG 0x0081 |
7756 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT 0x0082 |
7757 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 |
7758 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 |
7759 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 |
7760 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT 0x0086 |
7761 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT 0x0087 |
7762 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT 0x0088 |
7763 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 |
7764 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a |
7765 | #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b |
7766 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c |
7767 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d |
7768 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e |
7769 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f |
7770 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 |
7771 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 |
7772 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 |
7773 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT 0x0093 |
7774 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 |
7775 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 |
7776 | #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 |
7777 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 |
7778 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 |
7779 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 |
7780 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 |
7781 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 |
7782 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 |
7783 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 |
7784 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f |
7785 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 |
7786 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 |
7787 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 |
7788 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 |
7789 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 |
7790 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b |
7791 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d |
7792 | #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e |
7793 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 |
7794 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 |
7795 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 |
7796 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 |
7797 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 |
7798 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 |
7799 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 |
7800 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 |
7801 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 |
7802 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 |
7803 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a |
7804 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b |
7805 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c |
7806 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d |
7807 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e |
7808 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f |
7809 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 |
7810 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 |
7811 | #define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL 0x1032 |
7812 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 |
7813 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 |
7814 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 |
7815 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 |
7816 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 |
7817 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 |
7818 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 |
7819 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 |
7820 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 |
7821 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 |
7822 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a |
7823 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b |
7824 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c |
7825 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d |
7826 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e |
7827 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f |
7828 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 |
7829 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 |
7830 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 |
7831 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 |
7832 | #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 |
7833 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 |
7834 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 |
7835 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 |
7836 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 |
7837 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 |
7838 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 |
7839 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 |
7840 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 |
7841 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 |
7842 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0 0x10bb |
7843 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 |
7844 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 |
7845 | #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 |
7846 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS 0x10e0 |
7847 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD 0x10e1 |
7848 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS 0x10e2 |
7849 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1 0x10e3 |
7850 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2 0x10e4 |
7851 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC 0x10e5 |
7852 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1 0x10e6 |
7853 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE 0x10e7 |
7854 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 |
7855 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK 0x10e9 |
7856 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1 0x10ea |
7857 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2 0x10eb |
7858 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3 0x10ec |
7859 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2 0x10ed |
7860 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3 0x10ee |
7861 | #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4 0x10ef |
7862 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 |
7863 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 |
7864 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 |
7865 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 |
7866 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 |
7867 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 |
7868 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 |
7869 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 |
7870 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 |
7871 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 |
7872 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a |
7873 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b |
7874 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c |
7875 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d |
7876 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e |
7877 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f |
7878 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 |
7879 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 |
7880 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 |
7881 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 |
7882 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 |
7883 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 |
7884 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 |
7885 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 |
7886 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 |
7887 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 |
7888 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a |
7889 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b |
7890 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c |
7891 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d |
7892 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e |
7893 | #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA 0x111f |
7894 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 |
7895 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 |
7896 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 |
7897 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 |
7898 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 |
7899 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 |
7900 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 |
7901 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 |
7902 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 |
7903 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 |
7904 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a |
7905 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b |
7906 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c |
7907 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d |
7908 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e |
7909 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f |
7910 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 |
7911 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 |
7912 | #define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL 0x1132 |
7913 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 |
7914 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 |
7915 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 |
7916 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 |
7917 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 |
7918 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 |
7919 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 |
7920 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 |
7921 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 |
7922 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a |
7923 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b |
7924 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c |
7925 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d |
7926 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e |
7927 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f |
7928 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 |
7929 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL 0x1151 |
7930 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR 0x1152 |
7931 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 |
7932 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 |
7933 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 |
7934 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 |
7935 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 |
7936 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT 0x1158 |
7937 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ 0x1159 |
7938 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a |
7939 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b |
7940 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 |
7941 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 |
7942 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 |
7943 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 |
7944 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 |
7945 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 |
7946 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 |
7947 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 |
7948 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 |
7949 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 |
7950 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a |
7951 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b |
7952 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c |
7953 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d |
7954 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e |
7955 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f |
7956 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 |
7957 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 |
7958 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 |
7959 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 |
7960 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 |
7961 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 |
7962 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 |
7963 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 |
7964 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 |
7965 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 |
7966 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a |
7967 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b |
7968 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c |
7969 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d |
7970 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e |
7971 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f |
7972 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 |
7973 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 |
7974 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 |
7975 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 |
7976 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 |
7977 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 |
7978 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 |
7979 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 |
7980 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 |
7981 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 |
7982 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a |
7983 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b |
7984 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c |
7985 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d |
7986 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e |
7987 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f |
7988 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 |
7989 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 |
7990 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 |
7991 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 |
7992 | #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 |
7993 | #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 |
7994 | #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 |
7995 | #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 |
7996 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 |
7997 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 |
7998 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 |
7999 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 |
8000 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 |
8001 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 |
8002 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 |
8003 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 |
8004 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 |
8005 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 |
8006 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa |
8007 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab |
8008 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac |
8009 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad |
8010 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL 0x11ae |
8011 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af |
8012 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 |
8013 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 |
8014 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 |
8015 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 |
8016 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE 0x11b4 |
8017 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 |
8018 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 |
8019 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 |
8020 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 |
8021 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 |
8022 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba |
8023 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0 0x11bb |
8024 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1 0x11bc |
8025 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd |
8026 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be |
8027 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf |
8028 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 |
8029 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 |
8030 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 |
8031 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 |
8032 | #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 |
8033 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS 0x11e0 |
8034 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD 0x11e1 |
8035 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS 0x11e2 |
8036 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1 0x11e3 |
8037 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2 0x11e4 |
8038 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC 0x11e5 |
8039 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1 0x11e6 |
8040 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE 0x11e7 |
8041 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 |
8042 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK 0x11e9 |
8043 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1 0x11ea |
8044 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2 0x11eb |
8045 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3 0x11ec |
8046 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2 0x11ed |
8047 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3 0x11ee |
8048 | #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4 0x11ef |
8049 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1 0x11f0 |
8050 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2 0x11f1 |
8051 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES 0x11f2 |
8052 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL 0x11f3 |
8053 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1 0x11f4 |
8054 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2 0x11f5 |
8055 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ 0x11f6 |
8056 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1 0x11f7 |
8057 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2 0x11f8 |
8058 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF 0x11f9 |
8059 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1 0x11fa |
8060 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2 0x11fb |
8061 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3 0x11fc |
8062 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4 0x11fd |
8063 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC 0x11fe |
8064 | #define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1 0x11ff |
8065 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 |
8066 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 |
8067 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 |
8068 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 |
8069 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 |
8070 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 |
8071 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 |
8072 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 |
8073 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 |
8074 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 |
8075 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a |
8076 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b |
8077 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c |
8078 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d |
8079 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e |
8080 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f |
8081 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 |
8082 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 |
8083 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 |
8084 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 |
8085 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 |
8086 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 |
8087 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 |
8088 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 |
8089 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 |
8090 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 |
8091 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a |
8092 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b |
8093 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c |
8094 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d |
8095 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e |
8096 | #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA 0x121f |
8097 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 |
8098 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 |
8099 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 |
8100 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 |
8101 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 |
8102 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 |
8103 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 |
8104 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 |
8105 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 |
8106 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 |
8107 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a |
8108 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b |
8109 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c |
8110 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d |
8111 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e |
8112 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f |
8113 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 |
8114 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 |
8115 | #define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL 0x1232 |
8116 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 |
8117 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 |
8118 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 |
8119 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 |
8120 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 |
8121 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 |
8122 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 |
8123 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 |
8124 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 |
8125 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a |
8126 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b |
8127 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c |
8128 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d |
8129 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e |
8130 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f |
8131 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 |
8132 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL 0x1251 |
8133 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR 0x1252 |
8134 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 |
8135 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 |
8136 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 |
8137 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 |
8138 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 |
8139 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT 0x1258 |
8140 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ 0x1259 |
8141 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a |
8142 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b |
8143 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 |
8144 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 |
8145 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 |
8146 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 |
8147 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 |
8148 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 |
8149 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 |
8150 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 |
8151 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 |
8152 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 |
8153 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a |
8154 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b |
8155 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c |
8156 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d |
8157 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e |
8158 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f |
8159 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 |
8160 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 |
8161 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 |
8162 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 |
8163 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 |
8164 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 |
8165 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 |
8166 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 |
8167 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 |
8168 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 |
8169 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a |
8170 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b |
8171 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c |
8172 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d |
8173 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e |
8174 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f |
8175 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 |
8176 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 |
8177 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 |
8178 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 |
8179 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 |
8180 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 |
8181 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 |
8182 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 |
8183 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 |
8184 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 |
8185 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a |
8186 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b |
8187 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c |
8188 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d |
8189 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e |
8190 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f |
8191 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 |
8192 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 |
8193 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 |
8194 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 |
8195 | #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 |
8196 | #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 |
8197 | #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 |
8198 | #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 |
8199 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 |
8200 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 |
8201 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 |
8202 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 |
8203 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 |
8204 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 |
8205 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 |
8206 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 |
8207 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 |
8208 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 |
8209 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa |
8210 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab |
8211 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac |
8212 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad |
8213 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL 0x12ae |
8214 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af |
8215 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 |
8216 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 |
8217 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 |
8218 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 |
8219 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE 0x12b4 |
8220 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 |
8221 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 |
8222 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 |
8223 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 |
8224 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 |
8225 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba |
8226 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0 0x12bb |
8227 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1 0x12bc |
8228 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd |
8229 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be |
8230 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf |
8231 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 |
8232 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 |
8233 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 |
8234 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 |
8235 | #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 |
8236 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS 0x12e0 |
8237 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD 0x12e1 |
8238 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS 0x12e2 |
8239 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1 0x12e3 |
8240 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2 0x12e4 |
8241 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC 0x12e5 |
8242 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1 0x12e6 |
8243 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE 0x12e7 |
8244 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 |
8245 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK 0x12e9 |
8246 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1 0x12ea |
8247 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2 0x12eb |
8248 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3 0x12ec |
8249 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2 0x12ed |
8250 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3 0x12ee |
8251 | #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4 0x12ef |
8252 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1 0x12f0 |
8253 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2 0x12f1 |
8254 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES 0x12f2 |
8255 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL 0x12f3 |
8256 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1 0x12f4 |
8257 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2 0x12f5 |
8258 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ 0x12f6 |
8259 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1 0x12f7 |
8260 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2 0x12f8 |
8261 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF 0x12f9 |
8262 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1 0x12fa |
8263 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2 0x12fb |
8264 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3 0x12fc |
8265 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4 0x12fd |
8266 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC 0x12fe |
8267 | #define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1 0x12ff |
8268 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 |
8269 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 |
8270 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 |
8271 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 |
8272 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 |
8273 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 |
8274 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 |
8275 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f |
8276 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 |
8277 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 |
8278 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 |
8279 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 |
8280 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 |
8281 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b |
8282 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d |
8283 | #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e |
8284 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 |
8285 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 |
8286 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 |
8287 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 |
8288 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 |
8289 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 |
8290 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 |
8291 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 |
8292 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 |
8293 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 |
8294 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a |
8295 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b |
8296 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c |
8297 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d |
8298 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e |
8299 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f |
8300 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 |
8301 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 |
8302 | #define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL 0x1332 |
8303 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 |
8304 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 |
8305 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 |
8306 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 |
8307 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 |
8308 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 |
8309 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 |
8310 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 |
8311 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 |
8312 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 |
8313 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a |
8314 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b |
8315 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c |
8316 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d |
8317 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e |
8318 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f |
8319 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 |
8320 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 |
8321 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 |
8322 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 |
8323 | #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 |
8324 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 |
8325 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 |
8326 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 |
8327 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 |
8328 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 |
8329 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 |
8330 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 |
8331 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 |
8332 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 |
8333 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0 0x13bb |
8334 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 |
8335 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 |
8336 | #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 |
8337 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS 0x13e0 |
8338 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD 0x13e1 |
8339 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS 0x13e2 |
8340 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1 0x13e3 |
8341 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2 0x13e4 |
8342 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC 0x13e5 |
8343 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1 0x13e6 |
8344 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE 0x13e7 |
8345 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 |
8346 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK 0x13e9 |
8347 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1 0x13ea |
8348 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2 0x13eb |
8349 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3 0x13ec |
8350 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2 0x13ed |
8351 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3 0x13ee |
8352 | #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4 0x13ef |
8353 | #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL 0x2000 |
8354 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 |
8355 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 |
8356 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 |
8357 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 |
8358 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 |
8359 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 |
8360 | #define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 |
8361 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 |
8362 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 |
8363 | #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1 0x200a |
8364 | #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL 0x200b |
8365 | #define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE 0x200c |
8366 | #define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE 0x200d |
8367 | #define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA 0x200e |
8368 | #define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD 0x200f |
8369 | #define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 |
8370 | #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1 0x2011 |
8371 | #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2 0x2012 |
8372 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 |
8373 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 |
8374 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 |
8375 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 |
8376 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 |
8377 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 |
8378 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 |
8379 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 |
8380 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 |
8381 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 |
8382 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a |
8383 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b |
8384 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c |
8385 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d |
8386 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e |
8387 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f |
8388 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 |
8389 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 |
8390 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 |
8391 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 |
8392 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 |
8393 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 |
8394 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 |
8395 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 |
8396 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 |
8397 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 |
8398 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a |
8399 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b |
8400 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c |
8401 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d |
8402 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e |
8403 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f |
8404 | #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 |
8405 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 |
8406 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 |
8407 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 |
8408 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 |
8409 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 |
8410 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 |
8411 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 |
8412 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 |
8413 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 |
8414 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 |
8415 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a |
8416 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b |
8417 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c |
8418 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d |
8419 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e |
8420 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f |
8421 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 |
8422 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 |
8423 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 |
8424 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 |
8425 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 |
8426 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 |
8427 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 |
8428 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 |
8429 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 |
8430 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 |
8431 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a |
8432 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b |
8433 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c |
8434 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d |
8435 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e |
8436 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f |
8437 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 |
8438 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 |
8439 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 |
8440 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 |
8441 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 |
8442 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 |
8443 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 |
8444 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 |
8445 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 |
8446 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 |
8447 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a |
8448 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b |
8449 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP 0x302c |
8450 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d |
8451 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e |
8452 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f |
8453 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 |
8454 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 |
8455 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 |
8456 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 |
8457 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 |
8458 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 |
8459 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 |
8460 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 |
8461 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 |
8462 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 |
8463 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a |
8464 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b |
8465 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA 0x303c |
8466 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d |
8467 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e |
8468 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f |
8469 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 |
8470 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 |
8471 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 |
8472 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 |
8473 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 |
8474 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 |
8475 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 |
8476 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 |
8477 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 |
8478 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 |
8479 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a |
8480 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b |
8481 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c |
8482 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d |
8483 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e |
8484 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f |
8485 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 |
8486 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 |
8487 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 |
8488 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 |
8489 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 |
8490 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 |
8491 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 |
8492 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 |
8493 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 |
8494 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 |
8495 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a |
8496 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b |
8497 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 |
8498 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 |
8499 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 |
8500 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 |
8501 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 |
8502 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 |
8503 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 |
8504 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 |
8505 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 |
8506 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 |
8507 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a |
8508 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b |
8509 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c |
8510 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 |
8511 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 |
8512 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 |
8513 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 |
8514 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 |
8515 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 |
8516 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 |
8517 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 |
8518 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 |
8519 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 |
8520 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 |
8521 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 |
8522 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 |
8523 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 |
8524 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 |
8525 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 |
8526 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 |
8527 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 |
8528 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 |
8529 | #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 |
8530 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 |
8531 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 |
8532 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 |
8533 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 |
8534 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 |
8535 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 |
8536 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 |
8537 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 |
8538 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 |
8539 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 |
8540 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a |
8541 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b |
8542 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c |
8543 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d |
8544 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e |
8545 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f |
8546 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 |
8547 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 |
8548 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 |
8549 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 |
8550 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 |
8551 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 |
8552 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 |
8553 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 |
8554 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 |
8555 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 |
8556 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a |
8557 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b |
8558 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c |
8559 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d |
8560 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e |
8561 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f |
8562 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 |
8563 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 |
8564 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 |
8565 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 |
8566 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 |
8567 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 |
8568 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 |
8569 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 |
8570 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 |
8571 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 |
8572 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a |
8573 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b |
8574 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP 0x312c |
8575 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d |
8576 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e |
8577 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f |
8578 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 |
8579 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 |
8580 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 |
8581 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 |
8582 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 |
8583 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 |
8584 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 |
8585 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 |
8586 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 |
8587 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 |
8588 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a |
8589 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b |
8590 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA 0x313c |
8591 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d |
8592 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e |
8593 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f |
8594 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 |
8595 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 |
8596 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 |
8597 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 |
8598 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 |
8599 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 |
8600 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 |
8601 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 |
8602 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 |
8603 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 |
8604 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a |
8605 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b |
8606 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c |
8607 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d |
8608 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e |
8609 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f |
8610 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 |
8611 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 |
8612 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 |
8613 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 |
8614 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 |
8615 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 |
8616 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 |
8617 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 |
8618 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 |
8619 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 |
8620 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a |
8621 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b |
8622 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 |
8623 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 |
8624 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 |
8625 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 |
8626 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 |
8627 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 |
8628 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 |
8629 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 |
8630 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 |
8631 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 |
8632 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a |
8633 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b |
8634 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c |
8635 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 |
8636 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 |
8637 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 |
8638 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 |
8639 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 |
8640 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 |
8641 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 |
8642 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 |
8643 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 |
8644 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 |
8645 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 |
8646 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 |
8647 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 |
8648 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 |
8649 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 |
8650 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 |
8651 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 |
8652 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 |
8653 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 |
8654 | #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 |
8655 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 |
8656 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 |
8657 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 |
8658 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 |
8659 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 |
8660 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 |
8661 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 |
8662 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 |
8663 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 |
8664 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 |
8665 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a |
8666 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b |
8667 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c |
8668 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d |
8669 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e |
8670 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f |
8671 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 |
8672 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 |
8673 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 |
8674 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 |
8675 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 |
8676 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 |
8677 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 |
8678 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 |
8679 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 |
8680 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 |
8681 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a |
8682 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b |
8683 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c |
8684 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d |
8685 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e |
8686 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f |
8687 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 |
8688 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 |
8689 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 |
8690 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 |
8691 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 |
8692 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 |
8693 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 |
8694 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 |
8695 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 |
8696 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 |
8697 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a |
8698 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b |
8699 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP 0x322c |
8700 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d |
8701 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e |
8702 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f |
8703 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 |
8704 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 |
8705 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 |
8706 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 |
8707 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 |
8708 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 |
8709 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 |
8710 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 |
8711 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 |
8712 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 |
8713 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a |
8714 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b |
8715 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA 0x323c |
8716 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d |
8717 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e |
8718 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f |
8719 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 |
8720 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 |
8721 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 |
8722 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 |
8723 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 |
8724 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 |
8725 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 |
8726 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 |
8727 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 |
8728 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 |
8729 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a |
8730 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b |
8731 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c |
8732 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d |
8733 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e |
8734 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f |
8735 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 |
8736 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 |
8737 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 |
8738 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 |
8739 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 |
8740 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 |
8741 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 |
8742 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 |
8743 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 |
8744 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 |
8745 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a |
8746 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b |
8747 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 |
8748 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 |
8749 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 |
8750 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 |
8751 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 |
8752 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 |
8753 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 |
8754 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 |
8755 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 |
8756 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 |
8757 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a |
8758 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b |
8759 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c |
8760 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 |
8761 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 |
8762 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 |
8763 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 |
8764 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 |
8765 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 |
8766 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 |
8767 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 |
8768 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 |
8769 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 |
8770 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 |
8771 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 |
8772 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 |
8773 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 |
8774 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 |
8775 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 |
8776 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 |
8777 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 |
8778 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 |
8779 | #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 |
8780 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 |
8781 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 |
8782 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 |
8783 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 |
8784 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 |
8785 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 |
8786 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 |
8787 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 |
8788 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 |
8789 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 |
8790 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a |
8791 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b |
8792 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c |
8793 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d |
8794 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e |
8795 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f |
8796 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 |
8797 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 |
8798 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 |
8799 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 |
8800 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 |
8801 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 |
8802 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 |
8803 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 |
8804 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 |
8805 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 |
8806 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a |
8807 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b |
8808 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c |
8809 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d |
8810 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e |
8811 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f |
8812 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 |
8813 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 |
8814 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 |
8815 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 |
8816 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 |
8817 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 |
8818 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 |
8819 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 |
8820 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 |
8821 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 |
8822 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a |
8823 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b |
8824 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP 0x332c |
8825 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d |
8826 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e |
8827 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f |
8828 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 |
8829 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 |
8830 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 |
8831 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 |
8832 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 |
8833 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 |
8834 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 |
8835 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 |
8836 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 |
8837 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 |
8838 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a |
8839 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b |
8840 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA 0x333c |
8841 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d |
8842 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e |
8843 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f |
8844 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 |
8845 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 |
8846 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 |
8847 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 |
8848 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 |
8849 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 |
8850 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 |
8851 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 |
8852 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 |
8853 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 |
8854 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a |
8855 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b |
8856 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c |
8857 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d |
8858 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e |
8859 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f |
8860 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 |
8861 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 |
8862 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 |
8863 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 |
8864 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 |
8865 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 |
8866 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 |
8867 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 |
8868 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 |
8869 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 |
8870 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a |
8871 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b |
8872 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 |
8873 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 |
8874 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 |
8875 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 |
8876 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 |
8877 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 |
8878 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 |
8879 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 |
8880 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 |
8881 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 |
8882 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a |
8883 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b |
8884 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c |
8885 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 |
8886 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 |
8887 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 |
8888 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 |
8889 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 |
8890 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 |
8891 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 |
8892 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 |
8893 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 |
8894 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 |
8895 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 |
8896 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 |
8897 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 |
8898 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 |
8899 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 |
8900 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 |
8901 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 |
8902 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 |
8903 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 |
8904 | #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 |
8905 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 |
8906 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 |
8907 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 |
8908 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 |
8909 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 |
8910 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 |
8911 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 |
8912 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 |
8913 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 |
8914 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 |
8915 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a |
8916 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b |
8917 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c |
8918 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d |
8919 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e |
8920 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f |
8921 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 |
8922 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 |
8923 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 |
8924 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 |
8925 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 |
8926 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 |
8927 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 |
8928 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 |
8929 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 |
8930 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 |
8931 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a |
8932 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b |
8933 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS 0x401c |
8934 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d |
8935 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e |
8936 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f |
8937 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 |
8938 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 |
8939 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 |
8940 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 |
8941 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 |
8942 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 |
8943 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 |
8944 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 |
8945 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 |
8946 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 |
8947 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a |
8948 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b |
8949 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c |
8950 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d |
8951 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e |
8952 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f |
8953 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 |
8954 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 |
8955 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS 0x4032 |
8956 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 |
8957 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 |
8958 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 |
8959 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 |
8960 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 |
8961 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 |
8962 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 |
8963 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a |
8964 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b |
8965 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c |
8966 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d |
8967 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e |
8968 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f |
8969 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 |
8970 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 |
8971 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 |
8972 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 |
8973 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 |
8974 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 |
8975 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 |
8976 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 |
8977 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 |
8978 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 |
8979 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a |
8980 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b |
8981 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c |
8982 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d |
8983 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e |
8984 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f |
8985 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 |
8986 | #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 |
8987 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 |
8988 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 |
8989 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 |
8990 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 |
8991 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 |
8992 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 |
8993 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 |
8994 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 |
8995 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 |
8996 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 |
8997 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a |
8998 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b |
8999 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c |
9000 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d |
9001 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e |
9002 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f |
9003 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 |
9004 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 |
9005 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 |
9006 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 |
9007 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 |
9008 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 |
9009 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 |
9010 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 |
9011 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 |
9012 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 |
9013 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a |
9014 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b |
9015 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS 0x411c |
9016 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d |
9017 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e |
9018 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f |
9019 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 |
9020 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 |
9021 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 |
9022 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 |
9023 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 |
9024 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 |
9025 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 |
9026 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 |
9027 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 |
9028 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 |
9029 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a |
9030 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b |
9031 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c |
9032 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d |
9033 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e |
9034 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f |
9035 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 |
9036 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 |
9037 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS 0x4132 |
9038 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 |
9039 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 |
9040 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 |
9041 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 |
9042 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 |
9043 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 |
9044 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 |
9045 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a |
9046 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b |
9047 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c |
9048 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d |
9049 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e |
9050 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f |
9051 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 |
9052 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 |
9053 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 |
9054 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 |
9055 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 |
9056 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 |
9057 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 |
9058 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 |
9059 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 |
9060 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 |
9061 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a |
9062 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b |
9063 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c |
9064 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d |
9065 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e |
9066 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f |
9067 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 |
9068 | #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 |
9069 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 |
9070 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 |
9071 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 |
9072 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 |
9073 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 |
9074 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 |
9075 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 |
9076 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 |
9077 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 |
9078 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 |
9079 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a |
9080 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b |
9081 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c |
9082 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d |
9083 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e |
9084 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f |
9085 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 |
9086 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 |
9087 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 |
9088 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 |
9089 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 |
9090 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 |
9091 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 |
9092 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 |
9093 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 |
9094 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 |
9095 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a |
9096 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b |
9097 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS 0x421c |
9098 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d |
9099 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e |
9100 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f |
9101 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 |
9102 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 |
9103 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 |
9104 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 |
9105 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 |
9106 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 |
9107 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 |
9108 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 |
9109 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 |
9110 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 |
9111 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a |
9112 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b |
9113 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c |
9114 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d |
9115 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e |
9116 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f |
9117 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 |
9118 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 |
9119 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS 0x4232 |
9120 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 |
9121 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 |
9122 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 |
9123 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 |
9124 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 |
9125 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 |
9126 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 |
9127 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a |
9128 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b |
9129 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c |
9130 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d |
9131 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e |
9132 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f |
9133 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 |
9134 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 |
9135 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 |
9136 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 |
9137 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 |
9138 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 |
9139 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 |
9140 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 |
9141 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 |
9142 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 |
9143 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a |
9144 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b |
9145 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c |
9146 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d |
9147 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e |
9148 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f |
9149 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 |
9150 | #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 |
9151 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 |
9152 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 |
9153 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 |
9154 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 |
9155 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 |
9156 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 |
9157 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 |
9158 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 |
9159 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 |
9160 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 |
9161 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a |
9162 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b |
9163 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c |
9164 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d |
9165 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e |
9166 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f |
9167 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 |
9168 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 |
9169 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 |
9170 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 |
9171 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 |
9172 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 |
9173 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 |
9174 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 |
9175 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 |
9176 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 |
9177 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a |
9178 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b |
9179 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS 0x431c |
9180 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d |
9181 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e |
9182 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f |
9183 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 |
9184 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 |
9185 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 |
9186 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 |
9187 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 |
9188 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 |
9189 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 |
9190 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 |
9191 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 |
9192 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 |
9193 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a |
9194 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b |
9195 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c |
9196 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d |
9197 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e |
9198 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f |
9199 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 |
9200 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 |
9201 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS 0x4332 |
9202 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 |
9203 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 |
9204 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 |
9205 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 |
9206 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 |
9207 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 |
9208 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 |
9209 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a |
9210 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b |
9211 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c |
9212 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d |
9213 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e |
9214 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f |
9215 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 |
9216 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 |
9217 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 |
9218 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 |
9219 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 |
9220 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 |
9221 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 |
9222 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 |
9223 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 |
9224 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 |
9225 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a |
9226 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b |
9227 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c |
9228 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d |
9229 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e |
9230 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f |
9231 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 |
9232 | #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 |
9233 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 |
9234 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 |
9235 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 |
9236 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 |
9237 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 |
9238 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 |
9239 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 |
9240 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 |
9241 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 |
9242 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 |
9243 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a |
9244 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b |
9245 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c |
9246 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d |
9247 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e |
9248 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f |
9249 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 |
9250 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 |
9251 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 |
9252 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 |
9253 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 |
9254 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 |
9255 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 |
9256 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 |
9257 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 |
9258 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 |
9259 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a |
9260 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b |
9261 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS 0x701c |
9262 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d |
9263 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e |
9264 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f |
9265 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 |
9266 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 |
9267 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 |
9268 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 |
9269 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 |
9270 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 |
9271 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 |
9272 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 |
9273 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 |
9274 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 |
9275 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a |
9276 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b |
9277 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c |
9278 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d |
9279 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e |
9280 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f |
9281 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 |
9282 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 |
9283 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS 0x7032 |
9284 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 |
9285 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 |
9286 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 |
9287 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 |
9288 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 |
9289 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 |
9290 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 |
9291 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a |
9292 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b |
9293 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c |
9294 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d |
9295 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e |
9296 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f |
9297 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 |
9298 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 |
9299 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 |
9300 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 |
9301 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 |
9302 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 |
9303 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 |
9304 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 |
9305 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 |
9306 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 |
9307 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a |
9308 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b |
9309 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c |
9310 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d |
9311 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e |
9312 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f |
9313 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 |
9314 | #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 |
9315 | #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO 0x8000 |
9316 | #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI 0x8001 |
9317 | #define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN 0x8002 |
9318 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 |
9319 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 |
9320 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 |
9321 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 |
9322 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 |
9323 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 |
9324 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 |
9325 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a |
9326 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b |
9327 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c |
9328 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d |
9329 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e |
9330 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f |
9331 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 |
9332 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 |
9333 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 |
9334 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 |
9335 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 |
9336 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 |
9337 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 |
9338 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 |
9339 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 |
9340 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 |
9341 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a |
9342 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b |
9343 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c |
9344 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d |
9345 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e |
9346 | #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN 0x801f |
9347 | #define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 |
9348 | #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT 0x8021 |
9349 | #define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN 0x8022 |
9350 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 |
9351 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 |
9352 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 |
9353 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 |
9354 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 |
9355 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 |
9356 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a |
9357 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b |
9358 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c |
9359 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d |
9360 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e |
9361 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f |
9362 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 |
9363 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 |
9364 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 |
9365 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 |
9366 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 |
9367 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 |
9368 | #define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN 0x8036 |
9369 | #define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN 0x8037 |
9370 | #define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 |
9371 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 |
9372 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a |
9373 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b |
9374 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c |
9375 | #define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL 0x8040 |
9376 | #define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL 0x8041 |
9377 | #define ixDPCSSYS_CR3_SUPX_ANA_BG1 0x8042 |
9378 | #define ixDPCSSYS_CR3_SUPX_ANA_BG2 0x8043 |
9379 | #define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 |
9380 | #define ixDPCSSYS_CR3_SUPX_ANA_BG3 0x8045 |
9381 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1 0x8046 |
9382 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2 0x8047 |
9383 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD 0x8048 |
9384 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1 0x8049 |
9385 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2 0x804a |
9386 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3 0x804b |
9387 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1 0x804c |
9388 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2 0x804d |
9389 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3 0x804e |
9390 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4 0x804f |
9391 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5 0x8050 |
9392 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1 0x8051 |
9393 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2 0x8052 |
9394 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1 0x8053 |
9395 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2 0x8054 |
9396 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD 0x8055 |
9397 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1 0x8056 |
9398 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2 0x8057 |
9399 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3 0x8058 |
9400 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1 0x8059 |
9401 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2 0x805a |
9402 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3 0x805b |
9403 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4 0x805c |
9404 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5 0x805d |
9405 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1 0x805e |
9406 | #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2 0x805f |
9407 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 |
9408 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 |
9409 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 |
9410 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 |
9411 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 |
9412 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 |
9413 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 |
9414 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 |
9415 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 |
9416 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b |
9417 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d |
9418 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e |
9419 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f |
9420 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 |
9421 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 |
9422 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 |
9423 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 |
9424 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 |
9425 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 |
9426 | #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 |
9427 | #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 |
9428 | #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 |
9429 | #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a |
9430 | #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b |
9431 | #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c |
9432 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG 0x8081 |
9433 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT 0x8082 |
9434 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 |
9435 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 |
9436 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 |
9437 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT 0x8086 |
9438 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 |
9439 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 |
9440 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 |
9441 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a |
9442 | #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b |
9443 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c |
9444 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d |
9445 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e |
9446 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f |
9447 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 |
9448 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 |
9449 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 |
9450 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT 0x8093 |
9451 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 |
9452 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 |
9453 | #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 |
9454 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 |
9455 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 |
9456 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 |
9457 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 |
9458 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 |
9459 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 |
9460 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 |
9461 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 |
9462 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 |
9463 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 |
9464 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a |
9465 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b |
9466 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c |
9467 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d |
9468 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e |
9469 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f |
9470 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 |
9471 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 |
9472 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 |
9473 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 |
9474 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 |
9475 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 |
9476 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 |
9477 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 |
9478 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 |
9479 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 |
9480 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a |
9481 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b |
9482 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c |
9483 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d |
9484 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e |
9485 | #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA 0x901f |
9486 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 |
9487 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 |
9488 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 |
9489 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 |
9490 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 |
9491 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 |
9492 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 |
9493 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 |
9494 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 |
9495 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 |
9496 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a |
9497 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b |
9498 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c |
9499 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d |
9500 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e |
9501 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f |
9502 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 |
9503 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 |
9504 | #define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL 0x9032 |
9505 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 |
9506 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 |
9507 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 |
9508 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 |
9509 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 |
9510 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 |
9511 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 |
9512 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 |
9513 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 |
9514 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a |
9515 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b |
9516 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c |
9517 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d |
9518 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e |
9519 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f |
9520 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 |
9521 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL 0x9051 |
9522 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR 0x9052 |
9523 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 |
9524 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 |
9525 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 |
9526 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 |
9527 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 |
9528 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT 0x9058 |
9529 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ 0x9059 |
9530 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a |
9531 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b |
9532 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 |
9533 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 |
9534 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 |
9535 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 |
9536 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 |
9537 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 |
9538 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 |
9539 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 |
9540 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 |
9541 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 |
9542 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a |
9543 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b |
9544 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c |
9545 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d |
9546 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e |
9547 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f |
9548 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 |
9549 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 |
9550 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 |
9551 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 |
9552 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 |
9553 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 |
9554 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 |
9555 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 |
9556 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 |
9557 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 |
9558 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a |
9559 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b |
9560 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c |
9561 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d |
9562 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e |
9563 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f |
9564 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 |
9565 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 |
9566 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 |
9567 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 |
9568 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 |
9569 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 |
9570 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 |
9571 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 |
9572 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 |
9573 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 |
9574 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a |
9575 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b |
9576 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c |
9577 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d |
9578 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e |
9579 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f |
9580 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 |
9581 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 |
9582 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 |
9583 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 |
9584 | #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 |
9585 | #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 |
9586 | #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 |
9587 | #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 |
9588 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 |
9589 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 |
9590 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 |
9591 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 |
9592 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 |
9593 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 |
9594 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 |
9595 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 |
9596 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 |
9597 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 |
9598 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa |
9599 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab |
9600 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac |
9601 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad |
9602 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL 0x90ae |
9603 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af |
9604 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 |
9605 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 |
9606 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 |
9607 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 |
9608 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE 0x90b4 |
9609 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 |
9610 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 |
9611 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 |
9612 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 |
9613 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 |
9614 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba |
9615 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0 0x90bb |
9616 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1 0x90bc |
9617 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd |
9618 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be |
9619 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf |
9620 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 |
9621 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 |
9622 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 |
9623 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 |
9624 | #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 |
9625 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS 0x90e0 |
9626 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD 0x90e1 |
9627 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS 0x90e2 |
9628 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1 0x90e3 |
9629 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2 0x90e4 |
9630 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC 0x90e5 |
9631 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1 0x90e6 |
9632 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE 0x90e7 |
9633 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 |
9634 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK 0x90e9 |
9635 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1 0x90ea |
9636 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2 0x90eb |
9637 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3 0x90ec |
9638 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2 0x90ed |
9639 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3 0x90ee |
9640 | #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4 0x90ef |
9641 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1 0x90f0 |
9642 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2 0x90f1 |
9643 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES 0x90f2 |
9644 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL 0x90f3 |
9645 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1 0x90f4 |
9646 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2 0x90f5 |
9647 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ 0x90f6 |
9648 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1 0x90f7 |
9649 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2 0x90f8 |
9650 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF 0x90f9 |
9651 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1 0x90fa |
9652 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2 0x90fb |
9653 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3 0x90fc |
9654 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4 0x90fd |
9655 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC 0x90fe |
9656 | #define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1 0x90ff |
9657 | #define ixDPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 |
9658 | #define ixDPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 |
9659 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 |
9660 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 |
9661 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 |
9662 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 |
9663 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 |
9664 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 |
9665 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 |
9666 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 |
9667 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 |
9668 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 |
9669 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a |
9670 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b |
9671 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c |
9672 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d |
9673 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e |
9674 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f |
9675 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 |
9676 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 |
9677 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 |
9678 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 |
9679 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 |
9680 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 |
9681 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 |
9682 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 |
9683 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 |
9684 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 |
9685 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a |
9686 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b |
9687 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c |
9688 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d |
9689 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e |
9690 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f |
9691 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 |
9692 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 |
9693 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 |
9694 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 |
9695 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 |
9696 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 |
9697 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 |
9698 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 |
9699 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 |
9700 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 |
9701 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a |
9702 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b |
9703 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c |
9704 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d |
9705 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e |
9706 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f |
9707 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 |
9708 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 |
9709 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 |
9710 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 |
9711 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 |
9712 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 |
9713 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 |
9714 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 |
9715 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 |
9716 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 |
9717 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a |
9718 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b |
9719 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA 0xe03c |
9720 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d |
9721 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e |
9722 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f |
9723 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 |
9724 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 |
9725 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 |
9726 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 |
9727 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 |
9728 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 |
9729 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 |
9730 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 |
9731 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 |
9732 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 |
9733 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a |
9734 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b |
9735 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c |
9736 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d |
9737 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e |
9738 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f |
9739 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 |
9740 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 |
9741 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 |
9742 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 |
9743 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 |
9744 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 |
9745 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 |
9746 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 |
9747 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 |
9748 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 |
9749 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a |
9750 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b |
9751 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 |
9752 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 |
9753 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 |
9754 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 |
9755 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 |
9756 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 |
9757 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 |
9758 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 |
9759 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 |
9760 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 |
9761 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a |
9762 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b |
9763 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c |
9764 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 |
9765 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 |
9766 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 |
9767 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 |
9768 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 |
9769 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 |
9770 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 |
9771 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 |
9772 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 |
9773 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 |
9774 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 |
9775 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 |
9776 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 |
9777 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 |
9778 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 |
9779 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 |
9780 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 |
9781 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 |
9782 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 |
9783 | #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 |
9784 | |
9785 | |
9786 | // addressBlock: dpcssys_cr4_rdpcstxcrind |
9787 | // base address: 0x0 |
9788 | #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO 0x0000 |
9789 | #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI 0x0001 |
9790 | #define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN 0x0002 |
9791 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 |
9792 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 |
9793 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 |
9794 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 |
9795 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 |
9796 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 |
9797 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 |
9798 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a |
9799 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b |
9800 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c |
9801 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d |
9802 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3 0x000e |
9803 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4 0x000f |
9804 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 |
9805 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 |
9806 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 |
9807 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 |
9808 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 |
9809 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 |
9810 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 |
9811 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 |
9812 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 |
9813 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 |
9814 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3 0x001a |
9815 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4 0x001b |
9816 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5 0x001c |
9817 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d |
9818 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e |
9819 | #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN 0x001f |
9820 | #define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN 0x0020 |
9821 | #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT 0x0021 |
9822 | #define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN 0x0022 |
9823 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 |
9824 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 |
9825 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 |
9826 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 |
9827 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 |
9828 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 |
9829 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6 0x002a |
9830 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0 0x002b |
9831 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1 0x002c |
9832 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2 0x002d |
9833 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3 0x002e |
9834 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4 0x002f |
9835 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 |
9836 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 |
9837 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 |
9838 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 |
9839 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 |
9840 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 |
9841 | #define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN 0x0036 |
9842 | #define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN 0x0037 |
9843 | #define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN 0x0038 |
9844 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 |
9845 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a |
9846 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b |
9847 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c |
9848 | #define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL 0x0040 |
9849 | #define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL 0x0041 |
9850 | #define ixDPCSSYS_CR4_SUP_ANA_BG1 0x0042 |
9851 | #define ixDPCSSYS_CR4_SUP_ANA_BG2 0x0043 |
9852 | #define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS 0x0044 |
9853 | #define ixDPCSSYS_CR4_SUP_ANA_BG3 0x0045 |
9854 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1 0x0046 |
9855 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2 0x0047 |
9856 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD 0x0048 |
9857 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1 0x0049 |
9858 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2 0x004a |
9859 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3 0x004b |
9860 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1 0x004c |
9861 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2 0x004d |
9862 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3 0x004e |
9863 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4 0x004f |
9864 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5 0x0050 |
9865 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1 0x0051 |
9866 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2 0x0052 |
9867 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1 0x0053 |
9868 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2 0x0054 |
9869 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD 0x0055 |
9870 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1 0x0056 |
9871 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2 0x0057 |
9872 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3 0x0058 |
9873 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1 0x0059 |
9874 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2 0x005a |
9875 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3 0x005b |
9876 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4 0x005c |
9877 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5 0x005d |
9878 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1 0x005e |
9879 | #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2 0x005f |
9880 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 |
9881 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 |
9882 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 |
9883 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 |
9884 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 |
9885 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 |
9886 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 |
9887 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 |
9888 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 |
9889 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b |
9890 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d |
9891 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e |
9892 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f |
9893 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 |
9894 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 |
9895 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 |
9896 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 |
9897 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 |
9898 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 |
9899 | #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 |
9900 | #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 |
9901 | #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 |
9902 | #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a |
9903 | #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b |
9904 | #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD 0x007c |
9905 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG 0x0081 |
9906 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT 0x0082 |
9907 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 |
9908 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 |
9909 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 |
9910 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT 0x0086 |
9911 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT 0x0087 |
9912 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT 0x0088 |
9913 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 |
9914 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a |
9915 | #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b |
9916 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c |
9917 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d |
9918 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e |
9919 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f |
9920 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 |
9921 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 |
9922 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 |
9923 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT 0x0093 |
9924 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 |
9925 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 |
9926 | #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 |
9927 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 |
9928 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 |
9929 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 |
9930 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 |
9931 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 |
9932 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 |
9933 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 |
9934 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f |
9935 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 |
9936 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 |
9937 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 |
9938 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 |
9939 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 |
9940 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b |
9941 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d |
9942 | #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e |
9943 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 |
9944 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 |
9945 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 |
9946 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 |
9947 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 |
9948 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 |
9949 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 |
9950 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 |
9951 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 |
9952 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 |
9953 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a |
9954 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b |
9955 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c |
9956 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d |
9957 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e |
9958 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f |
9959 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 |
9960 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 |
9961 | #define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL 0x1032 |
9962 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 |
9963 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 |
9964 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 |
9965 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 |
9966 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 |
9967 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 |
9968 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 |
9969 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 |
9970 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 |
9971 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 |
9972 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a |
9973 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b |
9974 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c |
9975 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d |
9976 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e |
9977 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f |
9978 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 |
9979 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 |
9980 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 |
9981 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 |
9982 | #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 |
9983 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 |
9984 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 |
9985 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 |
9986 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 |
9987 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 |
9988 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 |
9989 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 |
9990 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 |
9991 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 |
9992 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0 0x10bb |
9993 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 |
9994 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 |
9995 | #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 |
9996 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS 0x10e0 |
9997 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD 0x10e1 |
9998 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS 0x10e2 |
9999 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1 0x10e3 |
10000 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2 0x10e4 |
10001 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC 0x10e5 |
10002 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1 0x10e6 |
10003 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE 0x10e7 |
10004 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 |
10005 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK 0x10e9 |
10006 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1 0x10ea |
10007 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2 0x10eb |
10008 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3 0x10ec |
10009 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2 0x10ed |
10010 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3 0x10ee |
10011 | #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4 0x10ef |
10012 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 |
10013 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 |
10014 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 |
10015 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 |
10016 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 |
10017 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 |
10018 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 |
10019 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 |
10020 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 |
10021 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 |
10022 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a |
10023 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b |
10024 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c |
10025 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d |
10026 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e |
10027 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f |
10028 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 |
10029 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 |
10030 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 |
10031 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 |
10032 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 |
10033 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 |
10034 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 |
10035 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 |
10036 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 |
10037 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 |
10038 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a |
10039 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b |
10040 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c |
10041 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d |
10042 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e |
10043 | #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA 0x111f |
10044 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 |
10045 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 |
10046 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 |
10047 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 |
10048 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 |
10049 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 |
10050 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 |
10051 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 |
10052 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 |
10053 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 |
10054 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a |
10055 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b |
10056 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c |
10057 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d |
10058 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e |
10059 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f |
10060 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 |
10061 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 |
10062 | #define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL 0x1132 |
10063 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 |
10064 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 |
10065 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 |
10066 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 |
10067 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 |
10068 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 |
10069 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 |
10070 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 |
10071 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 |
10072 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a |
10073 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b |
10074 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c |
10075 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d |
10076 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e |
10077 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f |
10078 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 |
10079 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL 0x1151 |
10080 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR 0x1152 |
10081 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 |
10082 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 |
10083 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 |
10084 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 |
10085 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 |
10086 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT 0x1158 |
10087 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ 0x1159 |
10088 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a |
10089 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b |
10090 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 |
10091 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 |
10092 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 |
10093 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 |
10094 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 |
10095 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 |
10096 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 |
10097 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 |
10098 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 |
10099 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 |
10100 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a |
10101 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b |
10102 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c |
10103 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d |
10104 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e |
10105 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f |
10106 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 |
10107 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 |
10108 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 |
10109 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 |
10110 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 |
10111 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 |
10112 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 |
10113 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 |
10114 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 |
10115 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 |
10116 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a |
10117 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b |
10118 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c |
10119 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d |
10120 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e |
10121 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f |
10122 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 |
10123 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 |
10124 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 |
10125 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 |
10126 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 |
10127 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 |
10128 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 |
10129 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 |
10130 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 |
10131 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 |
10132 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a |
10133 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b |
10134 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c |
10135 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d |
10136 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e |
10137 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f |
10138 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 |
10139 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 |
10140 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 |
10141 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 |
10142 | #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 |
10143 | #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 |
10144 | #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 |
10145 | #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 |
10146 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 |
10147 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 |
10148 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 |
10149 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 |
10150 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 |
10151 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 |
10152 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 |
10153 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 |
10154 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 |
10155 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 |
10156 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa |
10157 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab |
10158 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac |
10159 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad |
10160 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL 0x11ae |
10161 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af |
10162 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 |
10163 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 |
10164 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 |
10165 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 |
10166 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE 0x11b4 |
10167 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 |
10168 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 |
10169 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 |
10170 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 |
10171 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 |
10172 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba |
10173 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0 0x11bb |
10174 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1 0x11bc |
10175 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd |
10176 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be |
10177 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf |
10178 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 |
10179 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 |
10180 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 |
10181 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 |
10182 | #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 |
10183 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS 0x11e0 |
10184 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD 0x11e1 |
10185 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS 0x11e2 |
10186 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1 0x11e3 |
10187 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2 0x11e4 |
10188 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC 0x11e5 |
10189 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1 0x11e6 |
10190 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE 0x11e7 |
10191 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 |
10192 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK 0x11e9 |
10193 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1 0x11ea |
10194 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2 0x11eb |
10195 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3 0x11ec |
10196 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2 0x11ed |
10197 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3 0x11ee |
10198 | #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4 0x11ef |
10199 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1 0x11f0 |
10200 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2 0x11f1 |
10201 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES 0x11f2 |
10202 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL 0x11f3 |
10203 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1 0x11f4 |
10204 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2 0x11f5 |
10205 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ 0x11f6 |
10206 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1 0x11f7 |
10207 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2 0x11f8 |
10208 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF 0x11f9 |
10209 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1 0x11fa |
10210 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2 0x11fb |
10211 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3 0x11fc |
10212 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4 0x11fd |
10213 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC 0x11fe |
10214 | #define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1 0x11ff |
10215 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 |
10216 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 |
10217 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 |
10218 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 |
10219 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 |
10220 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 |
10221 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 |
10222 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 |
10223 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 |
10224 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 |
10225 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a |
10226 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b |
10227 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c |
10228 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d |
10229 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e |
10230 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f |
10231 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 |
10232 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 |
10233 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 |
10234 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 |
10235 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 |
10236 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 |
10237 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 |
10238 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 |
10239 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 |
10240 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 |
10241 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a |
10242 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b |
10243 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c |
10244 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d |
10245 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e |
10246 | #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA 0x121f |
10247 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 |
10248 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 |
10249 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 |
10250 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 |
10251 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 |
10252 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 |
10253 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 |
10254 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 |
10255 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 |
10256 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 |
10257 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a |
10258 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b |
10259 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c |
10260 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d |
10261 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e |
10262 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f |
10263 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 |
10264 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 |
10265 | #define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL 0x1232 |
10266 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 |
10267 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 |
10268 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 |
10269 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 |
10270 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 |
10271 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 |
10272 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 |
10273 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 |
10274 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 |
10275 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a |
10276 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b |
10277 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c |
10278 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d |
10279 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e |
10280 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f |
10281 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 |
10282 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL 0x1251 |
10283 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR 0x1252 |
10284 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 |
10285 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 |
10286 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 |
10287 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 |
10288 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 |
10289 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT 0x1258 |
10290 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ 0x1259 |
10291 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a |
10292 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b |
10293 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 |
10294 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 |
10295 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 |
10296 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 |
10297 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 |
10298 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 |
10299 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 |
10300 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 |
10301 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 |
10302 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 |
10303 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a |
10304 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b |
10305 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c |
10306 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d |
10307 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e |
10308 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f |
10309 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 |
10310 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 |
10311 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 |
10312 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 |
10313 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 |
10314 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 |
10315 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 |
10316 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 |
10317 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 |
10318 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 |
10319 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a |
10320 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b |
10321 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c |
10322 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d |
10323 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e |
10324 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f |
10325 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 |
10326 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 |
10327 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 |
10328 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 |
10329 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 |
10330 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 |
10331 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 |
10332 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 |
10333 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 |
10334 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 |
10335 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a |
10336 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b |
10337 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c |
10338 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d |
10339 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e |
10340 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f |
10341 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 |
10342 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 |
10343 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 |
10344 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 |
10345 | #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 |
10346 | #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 |
10347 | #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 |
10348 | #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 |
10349 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 |
10350 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 |
10351 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 |
10352 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 |
10353 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 |
10354 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 |
10355 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 |
10356 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 |
10357 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 |
10358 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 |
10359 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa |
10360 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab |
10361 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac |
10362 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad |
10363 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL 0x12ae |
10364 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af |
10365 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 |
10366 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 |
10367 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 |
10368 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 |
10369 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE 0x12b4 |
10370 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 |
10371 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 |
10372 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 |
10373 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 |
10374 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 |
10375 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba |
10376 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0 0x12bb |
10377 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1 0x12bc |
10378 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd |
10379 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be |
10380 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf |
10381 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 |
10382 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 |
10383 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 |
10384 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 |
10385 | #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 |
10386 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS 0x12e0 |
10387 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD 0x12e1 |
10388 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS 0x12e2 |
10389 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1 0x12e3 |
10390 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2 0x12e4 |
10391 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC 0x12e5 |
10392 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1 0x12e6 |
10393 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE 0x12e7 |
10394 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 |
10395 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK 0x12e9 |
10396 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1 0x12ea |
10397 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2 0x12eb |
10398 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3 0x12ec |
10399 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2 0x12ed |
10400 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3 0x12ee |
10401 | #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4 0x12ef |
10402 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1 0x12f0 |
10403 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2 0x12f1 |
10404 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES 0x12f2 |
10405 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL 0x12f3 |
10406 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1 0x12f4 |
10407 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2 0x12f5 |
10408 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ 0x12f6 |
10409 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1 0x12f7 |
10410 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2 0x12f8 |
10411 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF 0x12f9 |
10412 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1 0x12fa |
10413 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2 0x12fb |
10414 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3 0x12fc |
10415 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4 0x12fd |
10416 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC 0x12fe |
10417 | #define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1 0x12ff |
10418 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 |
10419 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 |
10420 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 |
10421 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 |
10422 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 |
10423 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 |
10424 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 |
10425 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f |
10426 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 |
10427 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 |
10428 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 |
10429 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 |
10430 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 |
10431 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b |
10432 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d |
10433 | #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e |
10434 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 |
10435 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 |
10436 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 |
10437 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 |
10438 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 |
10439 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 |
10440 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 |
10441 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 |
10442 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 |
10443 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 |
10444 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a |
10445 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b |
10446 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c |
10447 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d |
10448 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e |
10449 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f |
10450 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 |
10451 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 |
10452 | #define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL 0x1332 |
10453 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 |
10454 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 |
10455 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 |
10456 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 |
10457 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 |
10458 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 |
10459 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 |
10460 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 |
10461 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 |
10462 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 |
10463 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a |
10464 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b |
10465 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c |
10466 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d |
10467 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e |
10468 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f |
10469 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 |
10470 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 |
10471 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 |
10472 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 |
10473 | #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 |
10474 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 |
10475 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 |
10476 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 |
10477 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 |
10478 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 |
10479 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 |
10480 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 |
10481 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 |
10482 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 |
10483 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0 0x13bb |
10484 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 |
10485 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 |
10486 | #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 |
10487 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS 0x13e0 |
10488 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD 0x13e1 |
10489 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS 0x13e2 |
10490 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1 0x13e3 |
10491 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2 0x13e4 |
10492 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC 0x13e5 |
10493 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1 0x13e6 |
10494 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE 0x13e7 |
10495 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 |
10496 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK 0x13e9 |
10497 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1 0x13ea |
10498 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2 0x13eb |
10499 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3 0x13ec |
10500 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2 0x13ed |
10501 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3 0x13ee |
10502 | #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4 0x13ef |
10503 | #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL 0x2000 |
10504 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 |
10505 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 |
10506 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 |
10507 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 |
10508 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 |
10509 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 |
10510 | #define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 |
10511 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 |
10512 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 |
10513 | #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1 0x200a |
10514 | #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL 0x200b |
10515 | #define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE 0x200c |
10516 | #define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE 0x200d |
10517 | #define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA 0x200e |
10518 | #define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD 0x200f |
10519 | #define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 |
10520 | #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1 0x2011 |
10521 | #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2 0x2012 |
10522 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 |
10523 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 |
10524 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 |
10525 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 |
10526 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 |
10527 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 |
10528 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 |
10529 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 |
10530 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 |
10531 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 |
10532 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a |
10533 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b |
10534 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c |
10535 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d |
10536 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e |
10537 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f |
10538 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 |
10539 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 |
10540 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 |
10541 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 |
10542 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 |
10543 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 |
10544 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 |
10545 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 |
10546 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 |
10547 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 |
10548 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a |
10549 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b |
10550 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c |
10551 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d |
10552 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e |
10553 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f |
10554 | #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 |
10555 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 |
10556 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 |
10557 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 |
10558 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 |
10559 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 |
10560 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 |
10561 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 |
10562 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 |
10563 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 |
10564 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 |
10565 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a |
10566 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b |
10567 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c |
10568 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d |
10569 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e |
10570 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f |
10571 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 |
10572 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 |
10573 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 |
10574 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 |
10575 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 |
10576 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 |
10577 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 |
10578 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 |
10579 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 |
10580 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 |
10581 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a |
10582 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b |
10583 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c |
10584 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d |
10585 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e |
10586 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f |
10587 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 |
10588 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 |
10589 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 |
10590 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 |
10591 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 |
10592 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 |
10593 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 |
10594 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 |
10595 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 |
10596 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 |
10597 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a |
10598 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b |
10599 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP 0x302c |
10600 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d |
10601 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e |
10602 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f |
10603 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 |
10604 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 |
10605 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 |
10606 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 |
10607 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 |
10608 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 |
10609 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 |
10610 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 |
10611 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 |
10612 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 |
10613 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a |
10614 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b |
10615 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA 0x303c |
10616 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d |
10617 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e |
10618 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f |
10619 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 |
10620 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 |
10621 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 |
10622 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 |
10623 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 |
10624 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 |
10625 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 |
10626 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 |
10627 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 |
10628 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 |
10629 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a |
10630 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b |
10631 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c |
10632 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d |
10633 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e |
10634 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f |
10635 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 |
10636 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 |
10637 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 |
10638 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 |
10639 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 |
10640 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 |
10641 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 |
10642 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 |
10643 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 |
10644 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 |
10645 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a |
10646 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b |
10647 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 |
10648 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 |
10649 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 |
10650 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 |
10651 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 |
10652 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 |
10653 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 |
10654 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 |
10655 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 |
10656 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 |
10657 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a |
10658 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b |
10659 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c |
10660 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 |
10661 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 |
10662 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 |
10663 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 |
10664 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 |
10665 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 |
10666 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 |
10667 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 |
10668 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 |
10669 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 |
10670 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 |
10671 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 |
10672 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 |
10673 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 |
10674 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 |
10675 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 |
10676 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 |
10677 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 |
10678 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 |
10679 | #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 |
10680 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 |
10681 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 |
10682 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 |
10683 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 |
10684 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 |
10685 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 |
10686 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 |
10687 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 |
10688 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 |
10689 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 |
10690 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a |
10691 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b |
10692 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c |
10693 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d |
10694 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e |
10695 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f |
10696 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 |
10697 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 |
10698 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 |
10699 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 |
10700 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 |
10701 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 |
10702 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 |
10703 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 |
10704 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 |
10705 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 |
10706 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a |
10707 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b |
10708 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c |
10709 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d |
10710 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e |
10711 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f |
10712 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 |
10713 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 |
10714 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 |
10715 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 |
10716 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 |
10717 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 |
10718 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 |
10719 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 |
10720 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 |
10721 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 |
10722 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a |
10723 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b |
10724 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP 0x312c |
10725 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d |
10726 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e |
10727 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f |
10728 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 |
10729 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 |
10730 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 |
10731 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 |
10732 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 |
10733 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 |
10734 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 |
10735 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 |
10736 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 |
10737 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 |
10738 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a |
10739 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b |
10740 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA 0x313c |
10741 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d |
10742 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e |
10743 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f |
10744 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 |
10745 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 |
10746 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 |
10747 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 |
10748 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 |
10749 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 |
10750 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 |
10751 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 |
10752 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 |
10753 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 |
10754 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a |
10755 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b |
10756 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c |
10757 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d |
10758 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e |
10759 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f |
10760 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 |
10761 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 |
10762 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 |
10763 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 |
10764 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 |
10765 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 |
10766 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 |
10767 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 |
10768 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 |
10769 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 |
10770 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a |
10771 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b |
10772 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 |
10773 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 |
10774 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 |
10775 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 |
10776 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 |
10777 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 |
10778 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 |
10779 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 |
10780 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 |
10781 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 |
10782 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a |
10783 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b |
10784 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c |
10785 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 |
10786 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 |
10787 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 |
10788 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 |
10789 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 |
10790 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 |
10791 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 |
10792 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 |
10793 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 |
10794 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 |
10795 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 |
10796 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 |
10797 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 |
10798 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 |
10799 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 |
10800 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 |
10801 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 |
10802 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 |
10803 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 |
10804 | #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 |
10805 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 |
10806 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 |
10807 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 |
10808 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 |
10809 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 |
10810 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 |
10811 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 |
10812 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 |
10813 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 |
10814 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 |
10815 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a |
10816 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b |
10817 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c |
10818 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d |
10819 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e |
10820 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f |
10821 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 |
10822 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 |
10823 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 |
10824 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 |
10825 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 |
10826 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 |
10827 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 |
10828 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 |
10829 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 |
10830 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 |
10831 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a |
10832 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b |
10833 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c |
10834 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d |
10835 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e |
10836 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f |
10837 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 |
10838 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 |
10839 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 |
10840 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 |
10841 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 |
10842 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 |
10843 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 |
10844 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 |
10845 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 |
10846 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 |
10847 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a |
10848 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b |
10849 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP 0x322c |
10850 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d |
10851 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e |
10852 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f |
10853 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 |
10854 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 |
10855 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 |
10856 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 |
10857 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 |
10858 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 |
10859 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 |
10860 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 |
10861 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 |
10862 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 |
10863 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a |
10864 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b |
10865 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA 0x323c |
10866 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d |
10867 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e |
10868 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f |
10869 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 |
10870 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 |
10871 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 |
10872 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 |
10873 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 |
10874 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 |
10875 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 |
10876 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 |
10877 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 |
10878 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 |
10879 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a |
10880 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b |
10881 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c |
10882 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d |
10883 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e |
10884 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f |
10885 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 |
10886 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 |
10887 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 |
10888 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 |
10889 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 |
10890 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 |
10891 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 |
10892 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 |
10893 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 |
10894 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 |
10895 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a |
10896 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b |
10897 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 |
10898 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 |
10899 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 |
10900 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 |
10901 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 |
10902 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 |
10903 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 |
10904 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 |
10905 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 |
10906 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 |
10907 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a |
10908 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b |
10909 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c |
10910 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 |
10911 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 |
10912 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 |
10913 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 |
10914 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 |
10915 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 |
10916 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 |
10917 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 |
10918 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 |
10919 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 |
10920 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 |
10921 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 |
10922 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 |
10923 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 |
10924 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 |
10925 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 |
10926 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 |
10927 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 |
10928 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 |
10929 | #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 |
10930 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 |
10931 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 |
10932 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 |
10933 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 |
10934 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 |
10935 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 |
10936 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 |
10937 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 |
10938 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 |
10939 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 |
10940 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a |
10941 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b |
10942 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c |
10943 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d |
10944 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e |
10945 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f |
10946 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 |
10947 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 |
10948 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 |
10949 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 |
10950 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 |
10951 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 |
10952 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 |
10953 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 |
10954 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 |
10955 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 |
10956 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a |
10957 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b |
10958 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c |
10959 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d |
10960 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e |
10961 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f |
10962 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 |
10963 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 |
10964 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 |
10965 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 |
10966 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 |
10967 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 |
10968 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 |
10969 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 |
10970 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 |
10971 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 |
10972 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a |
10973 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b |
10974 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP 0x332c |
10975 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d |
10976 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e |
10977 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f |
10978 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 |
10979 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 |
10980 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 |
10981 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 |
10982 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 |
10983 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 |
10984 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 |
10985 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 |
10986 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 |
10987 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 |
10988 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a |
10989 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b |
10990 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA 0x333c |
10991 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d |
10992 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e |
10993 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f |
10994 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 |
10995 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 |
10996 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 |
10997 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 |
10998 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 |
10999 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 |
11000 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 |
11001 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 |
11002 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 |
11003 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 |
11004 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a |
11005 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b |
11006 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c |
11007 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d |
11008 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e |
11009 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f |
11010 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 |
11011 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 |
11012 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 |
11013 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 |
11014 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 |
11015 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 |
11016 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 |
11017 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 |
11018 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 |
11019 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 |
11020 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a |
11021 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b |
11022 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 |
11023 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 |
11024 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 |
11025 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 |
11026 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 |
11027 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 |
11028 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 |
11029 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 |
11030 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 |
11031 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 |
11032 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a |
11033 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b |
11034 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c |
11035 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 |
11036 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 |
11037 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 |
11038 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 |
11039 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 |
11040 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 |
11041 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 |
11042 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 |
11043 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 |
11044 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 |
11045 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 |
11046 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 |
11047 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 |
11048 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 |
11049 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 |
11050 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 |
11051 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 |
11052 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 |
11053 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 |
11054 | #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 |
11055 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 |
11056 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 |
11057 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 |
11058 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 |
11059 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 |
11060 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 |
11061 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 |
11062 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 |
11063 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 |
11064 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 |
11065 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a |
11066 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b |
11067 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c |
11068 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d |
11069 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e |
11070 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f |
11071 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 |
11072 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 |
11073 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 |
11074 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 |
11075 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 |
11076 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 |
11077 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 |
11078 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 |
11079 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 |
11080 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 |
11081 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a |
11082 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b |
11083 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS 0x401c |
11084 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d |
11085 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e |
11086 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f |
11087 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 |
11088 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 |
11089 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 |
11090 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 |
11091 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 |
11092 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 |
11093 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 |
11094 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 |
11095 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 |
11096 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 |
11097 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a |
11098 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b |
11099 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c |
11100 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d |
11101 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e |
11102 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f |
11103 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 |
11104 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 |
11105 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS 0x4032 |
11106 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 |
11107 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 |
11108 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 |
11109 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 |
11110 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 |
11111 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 |
11112 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 |
11113 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a |
11114 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b |
11115 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c |
11116 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d |
11117 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e |
11118 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f |
11119 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 |
11120 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 |
11121 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 |
11122 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 |
11123 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 |
11124 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 |
11125 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 |
11126 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 |
11127 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 |
11128 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 |
11129 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a |
11130 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b |
11131 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c |
11132 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d |
11133 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e |
11134 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f |
11135 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 |
11136 | #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 |
11137 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 |
11138 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 |
11139 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 |
11140 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 |
11141 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 |
11142 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 |
11143 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 |
11144 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 |
11145 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 |
11146 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 |
11147 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a |
11148 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b |
11149 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c |
11150 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d |
11151 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e |
11152 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f |
11153 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 |
11154 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 |
11155 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 |
11156 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 |
11157 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 |
11158 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 |
11159 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 |
11160 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 |
11161 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 |
11162 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 |
11163 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a |
11164 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b |
11165 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS 0x411c |
11166 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d |
11167 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e |
11168 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f |
11169 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 |
11170 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 |
11171 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 |
11172 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 |
11173 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 |
11174 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 |
11175 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 |
11176 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 |
11177 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 |
11178 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 |
11179 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a |
11180 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b |
11181 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c |
11182 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d |
11183 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e |
11184 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f |
11185 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 |
11186 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 |
11187 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS 0x4132 |
11188 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 |
11189 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 |
11190 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 |
11191 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 |
11192 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 |
11193 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 |
11194 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 |
11195 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a |
11196 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b |
11197 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c |
11198 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d |
11199 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e |
11200 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f |
11201 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 |
11202 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 |
11203 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 |
11204 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 |
11205 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 |
11206 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 |
11207 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 |
11208 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 |
11209 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 |
11210 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 |
11211 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a |
11212 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b |
11213 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c |
11214 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d |
11215 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e |
11216 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f |
11217 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 |
11218 | #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 |
11219 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 |
11220 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 |
11221 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 |
11222 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 |
11223 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 |
11224 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 |
11225 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 |
11226 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 |
11227 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 |
11228 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 |
11229 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a |
11230 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b |
11231 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c |
11232 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d |
11233 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e |
11234 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f |
11235 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 |
11236 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 |
11237 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 |
11238 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 |
11239 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 |
11240 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 |
11241 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 |
11242 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 |
11243 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 |
11244 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 |
11245 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a |
11246 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b |
11247 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS 0x421c |
11248 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d |
11249 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e |
11250 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f |
11251 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 |
11252 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 |
11253 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 |
11254 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 |
11255 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 |
11256 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 |
11257 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 |
11258 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 |
11259 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 |
11260 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 |
11261 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a |
11262 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b |
11263 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c |
11264 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d |
11265 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e |
11266 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f |
11267 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 |
11268 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 |
11269 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS 0x4232 |
11270 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 |
11271 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 |
11272 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 |
11273 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 |
11274 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 |
11275 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 |
11276 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 |
11277 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a |
11278 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b |
11279 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c |
11280 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d |
11281 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e |
11282 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f |
11283 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 |
11284 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 |
11285 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 |
11286 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 |
11287 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 |
11288 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 |
11289 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 |
11290 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 |
11291 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 |
11292 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 |
11293 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a |
11294 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b |
11295 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c |
11296 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d |
11297 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e |
11298 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f |
11299 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 |
11300 | #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 |
11301 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 |
11302 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 |
11303 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 |
11304 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 |
11305 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 |
11306 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 |
11307 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 |
11308 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 |
11309 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 |
11310 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 |
11311 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a |
11312 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b |
11313 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c |
11314 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d |
11315 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e |
11316 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f |
11317 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 |
11318 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 |
11319 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 |
11320 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 |
11321 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 |
11322 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 |
11323 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 |
11324 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 |
11325 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 |
11326 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 |
11327 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a |
11328 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b |
11329 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS 0x431c |
11330 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d |
11331 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e |
11332 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f |
11333 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 |
11334 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 |
11335 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 |
11336 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 |
11337 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 |
11338 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 |
11339 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 |
11340 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 |
11341 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 |
11342 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 |
11343 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a |
11344 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b |
11345 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c |
11346 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d |
11347 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e |
11348 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f |
11349 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 |
11350 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 |
11351 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS 0x4332 |
11352 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 |
11353 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 |
11354 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 |
11355 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 |
11356 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 |
11357 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 |
11358 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 |
11359 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a |
11360 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b |
11361 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c |
11362 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d |
11363 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e |
11364 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f |
11365 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 |
11366 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 |
11367 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 |
11368 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 |
11369 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 |
11370 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 |
11371 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 |
11372 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 |
11373 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 |
11374 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 |
11375 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a |
11376 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b |
11377 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c |
11378 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d |
11379 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e |
11380 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f |
11381 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 |
11382 | #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 |
11383 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 |
11384 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 |
11385 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 |
11386 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 |
11387 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 |
11388 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 |
11389 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 |
11390 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 |
11391 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 |
11392 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 |
11393 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a |
11394 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b |
11395 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c |
11396 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d |
11397 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e |
11398 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f |
11399 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 |
11400 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 |
11401 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 |
11402 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 |
11403 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 |
11404 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 |
11405 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 |
11406 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 |
11407 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 |
11408 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 |
11409 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a |
11410 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b |
11411 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS 0x701c |
11412 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d |
11413 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e |
11414 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f |
11415 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 |
11416 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 |
11417 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 |
11418 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 |
11419 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 |
11420 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 |
11421 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 |
11422 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 |
11423 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 |
11424 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 |
11425 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a |
11426 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b |
11427 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c |
11428 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d |
11429 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e |
11430 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f |
11431 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 |
11432 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 |
11433 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS 0x7032 |
11434 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 |
11435 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 |
11436 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 |
11437 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 |
11438 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 |
11439 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 |
11440 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 |
11441 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a |
11442 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b |
11443 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c |
11444 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d |
11445 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e |
11446 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f |
11447 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 |
11448 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 |
11449 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 |
11450 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 |
11451 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 |
11452 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 |
11453 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 |
11454 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 |
11455 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 |
11456 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 |
11457 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a |
11458 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b |
11459 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c |
11460 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d |
11461 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e |
11462 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f |
11463 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 |
11464 | #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 |
11465 | #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO 0x8000 |
11466 | #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI 0x8001 |
11467 | #define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN 0x8002 |
11468 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 |
11469 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 |
11470 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 |
11471 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 |
11472 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 |
11473 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 |
11474 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 |
11475 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a |
11476 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b |
11477 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c |
11478 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d |
11479 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e |
11480 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f |
11481 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 |
11482 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 |
11483 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 |
11484 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 |
11485 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 |
11486 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 |
11487 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 |
11488 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 |
11489 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 |
11490 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 |
11491 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a |
11492 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b |
11493 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c |
11494 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d |
11495 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e |
11496 | #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN 0x801f |
11497 | #define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 |
11498 | #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT 0x8021 |
11499 | #define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN 0x8022 |
11500 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 |
11501 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 |
11502 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 |
11503 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 |
11504 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 |
11505 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 |
11506 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a |
11507 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b |
11508 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c |
11509 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d |
11510 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e |
11511 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f |
11512 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 |
11513 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 |
11514 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 |
11515 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 |
11516 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 |
11517 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 |
11518 | #define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN 0x8036 |
11519 | #define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN 0x8037 |
11520 | #define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 |
11521 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 |
11522 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a |
11523 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b |
11524 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c |
11525 | #define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL 0x8040 |
11526 | #define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL 0x8041 |
11527 | #define ixDPCSSYS_CR4_SUPX_ANA_BG1 0x8042 |
11528 | #define ixDPCSSYS_CR4_SUPX_ANA_BG2 0x8043 |
11529 | #define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 |
11530 | #define ixDPCSSYS_CR4_SUPX_ANA_BG3 0x8045 |
11531 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1 0x8046 |
11532 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2 0x8047 |
11533 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD 0x8048 |
11534 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1 0x8049 |
11535 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2 0x804a |
11536 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3 0x804b |
11537 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1 0x804c |
11538 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2 0x804d |
11539 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3 0x804e |
11540 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4 0x804f |
11541 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5 0x8050 |
11542 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1 0x8051 |
11543 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2 0x8052 |
11544 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1 0x8053 |
11545 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2 0x8054 |
11546 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD 0x8055 |
11547 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1 0x8056 |
11548 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2 0x8057 |
11549 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3 0x8058 |
11550 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1 0x8059 |
11551 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2 0x805a |
11552 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3 0x805b |
11553 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4 0x805c |
11554 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5 0x805d |
11555 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1 0x805e |
11556 | #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2 0x805f |
11557 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 |
11558 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 |
11559 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 |
11560 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 |
11561 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 |
11562 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 |
11563 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 |
11564 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 |
11565 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 |
11566 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b |
11567 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d |
11568 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e |
11569 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f |
11570 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 |
11571 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 |
11572 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 |
11573 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 |
11574 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 |
11575 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 |
11576 | #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 |
11577 | #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 |
11578 | #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 |
11579 | #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a |
11580 | #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b |
11581 | #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c |
11582 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG 0x8081 |
11583 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT 0x8082 |
11584 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 |
11585 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 |
11586 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 |
11587 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT 0x8086 |
11588 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 |
11589 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 |
11590 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 |
11591 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a |
11592 | #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b |
11593 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c |
11594 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d |
11595 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e |
11596 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f |
11597 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 |
11598 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 |
11599 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 |
11600 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT 0x8093 |
11601 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 |
11602 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 |
11603 | #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 |
11604 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 |
11605 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 |
11606 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 |
11607 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 |
11608 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 |
11609 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 |
11610 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 |
11611 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 |
11612 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 |
11613 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 |
11614 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a |
11615 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b |
11616 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c |
11617 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d |
11618 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e |
11619 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f |
11620 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 |
11621 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 |
11622 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 |
11623 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 |
11624 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 |
11625 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 |
11626 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 |
11627 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 |
11628 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 |
11629 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 |
11630 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a |
11631 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b |
11632 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c |
11633 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d |
11634 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e |
11635 | #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA 0x901f |
11636 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 |
11637 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 |
11638 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 |
11639 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 |
11640 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 |
11641 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 |
11642 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 |
11643 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 |
11644 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 |
11645 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 |
11646 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a |
11647 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b |
11648 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c |
11649 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d |
11650 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e |
11651 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f |
11652 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 |
11653 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 |
11654 | #define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL 0x9032 |
11655 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 |
11656 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 |
11657 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 |
11658 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 |
11659 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 |
11660 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 |
11661 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 |
11662 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 |
11663 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 |
11664 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a |
11665 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b |
11666 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c |
11667 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d |
11668 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e |
11669 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f |
11670 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 |
11671 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL 0x9051 |
11672 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR 0x9052 |
11673 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 |
11674 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 |
11675 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 |
11676 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 |
11677 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 |
11678 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT 0x9058 |
11679 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ 0x9059 |
11680 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a |
11681 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b |
11682 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 |
11683 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 |
11684 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 |
11685 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 |
11686 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 |
11687 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 |
11688 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 |
11689 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 |
11690 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 |
11691 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 |
11692 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a |
11693 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b |
11694 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c |
11695 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d |
11696 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e |
11697 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f |
11698 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 |
11699 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 |
11700 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 |
11701 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 |
11702 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 |
11703 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 |
11704 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 |
11705 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 |
11706 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 |
11707 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 |
11708 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a |
11709 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b |
11710 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c |
11711 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d |
11712 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e |
11713 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f |
11714 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 |
11715 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 |
11716 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 |
11717 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 |
11718 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 |
11719 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 |
11720 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 |
11721 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 |
11722 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 |
11723 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 |
11724 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a |
11725 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b |
11726 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c |
11727 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d |
11728 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e |
11729 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f |
11730 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 |
11731 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 |
11732 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 |
11733 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 |
11734 | #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 |
11735 | #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 |
11736 | #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 |
11737 | #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 |
11738 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 |
11739 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 |
11740 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 |
11741 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 |
11742 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 |
11743 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 |
11744 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 |
11745 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 |
11746 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 |
11747 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 |
11748 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa |
11749 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab |
11750 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac |
11751 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad |
11752 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL 0x90ae |
11753 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af |
11754 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 |
11755 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 |
11756 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 |
11757 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 |
11758 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE 0x90b4 |
11759 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 |
11760 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 |
11761 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 |
11762 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 |
11763 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 |
11764 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba |
11765 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0 0x90bb |
11766 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1 0x90bc |
11767 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd |
11768 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be |
11769 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf |
11770 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 |
11771 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 |
11772 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 |
11773 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 |
11774 | #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 |
11775 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS 0x90e0 |
11776 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD 0x90e1 |
11777 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS 0x90e2 |
11778 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1 0x90e3 |
11779 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2 0x90e4 |
11780 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC 0x90e5 |
11781 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1 0x90e6 |
11782 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE 0x90e7 |
11783 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 |
11784 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK 0x90e9 |
11785 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1 0x90ea |
11786 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2 0x90eb |
11787 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3 0x90ec |
11788 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2 0x90ed |
11789 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3 0x90ee |
11790 | #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4 0x90ef |
11791 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1 0x90f0 |
11792 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2 0x90f1 |
11793 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES 0x90f2 |
11794 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL 0x90f3 |
11795 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1 0x90f4 |
11796 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2 0x90f5 |
11797 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ 0x90f6 |
11798 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1 0x90f7 |
11799 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2 0x90f8 |
11800 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF 0x90f9 |
11801 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1 0x90fa |
11802 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2 0x90fb |
11803 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3 0x90fc |
11804 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4 0x90fd |
11805 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC 0x90fe |
11806 | #define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1 0x90ff |
11807 | #define ixDPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 |
11808 | #define ixDPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 |
11809 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 |
11810 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 |
11811 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 |
11812 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 |
11813 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 |
11814 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 |
11815 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 |
11816 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 |
11817 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 |
11818 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 |
11819 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a |
11820 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b |
11821 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c |
11822 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d |
11823 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e |
11824 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f |
11825 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 |
11826 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 |
11827 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 |
11828 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 |
11829 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 |
11830 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 |
11831 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 |
11832 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 |
11833 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 |
11834 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 |
11835 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a |
11836 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b |
11837 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c |
11838 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d |
11839 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e |
11840 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f |
11841 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 |
11842 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 |
11843 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 |
11844 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 |
11845 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 |
11846 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 |
11847 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 |
11848 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 |
11849 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 |
11850 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 |
11851 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a |
11852 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b |
11853 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c |
11854 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d |
11855 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e |
11856 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f |
11857 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 |
11858 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 |
11859 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 |
11860 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 |
11861 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 |
11862 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 |
11863 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 |
11864 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 |
11865 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 |
11866 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 |
11867 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a |
11868 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b |
11869 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA 0xe03c |
11870 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d |
11871 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e |
11872 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f |
11873 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 |
11874 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 |
11875 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 |
11876 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 |
11877 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 |
11878 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 |
11879 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 |
11880 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 |
11881 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 |
11882 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 |
11883 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a |
11884 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b |
11885 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c |
11886 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d |
11887 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e |
11888 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f |
11889 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 |
11890 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 |
11891 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 |
11892 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 |
11893 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 |
11894 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 |
11895 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 |
11896 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 |
11897 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 |
11898 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 |
11899 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a |
11900 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b |
11901 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 |
11902 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 |
11903 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 |
11904 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 |
11905 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 |
11906 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 |
11907 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 |
11908 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 |
11909 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 |
11910 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 |
11911 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a |
11912 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b |
11913 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c |
11914 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 |
11915 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 |
11916 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 |
11917 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 |
11918 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 |
11919 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 |
11920 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 |
11921 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 |
11922 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 |
11923 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 |
11924 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 |
11925 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 |
11926 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 |
11927 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 |
11928 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 |
11929 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 |
11930 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 |
11931 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 |
11932 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 |
11933 | #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 |
11934 | |
11935 | //RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 |
11936 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 |
11937 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 |
11938 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 |
11939 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L |
11940 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L |
11941 | #define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L |
11942 | |
11943 | //RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 |
11944 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 |
11945 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 |
11946 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 |
11947 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L |
11948 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L |
11949 | #define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L |
11950 | |
11951 | //[Note] Hack. RDPCSPIPE only has 2 instances. |
11952 | #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0x2d73 |
11953 | #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 |
11954 | #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0x2e4b |
11955 | #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 |
11956 | #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0x2d73 |
11957 | #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 |
11958 | #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0x2e4b |
11959 | #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 |
11960 | #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0x2d73 |
11961 | #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 |
11962 | |
11963 | #endif |
11964 | |