1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _gc_9_1_OFFSET_HEADER
22#define _gc_9_1_OFFSET_HEADER
23
24
25
26// addressBlock: gc_grbmdec
27// base address: 0x8000
28#define mmGRBM_CNTL 0x0000
29#define mmGRBM_CNTL_BASE_IDX 0
30#define mmGRBM_SKEW_CNTL 0x0001
31#define mmGRBM_SKEW_CNTL_BASE_IDX 0
32#define mmGRBM_STATUS2 0x0002
33#define mmGRBM_STATUS2_BASE_IDX 0
34#define mmGRBM_PWR_CNTL 0x0003
35#define mmGRBM_PWR_CNTL_BASE_IDX 0
36#define mmGRBM_STATUS 0x0004
37#define mmGRBM_STATUS_BASE_IDX 0
38#define mmGRBM_STATUS_SE0 0x0005
39#define mmGRBM_STATUS_SE0_BASE_IDX 0
40#define mmGRBM_STATUS_SE1 0x0006
41#define mmGRBM_STATUS_SE1_BASE_IDX 0
42#define mmGRBM_SOFT_RESET 0x0008
43#define mmGRBM_SOFT_RESET_BASE_IDX 0
44#define mmGRBM_CGTT_CLK_CNTL 0x000b
45#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0
46#define mmGRBM_GFX_CLKEN_CNTL 0x000c
47#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
48#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d
49#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
50#define mmGRBM_STATUS_SE2 0x000e
51#define mmGRBM_STATUS_SE2_BASE_IDX 0
52#define mmGRBM_STATUS_SE3 0x000f
53#define mmGRBM_STATUS_SE3_BASE_IDX 0
54#define mmGRBM_READ_ERROR 0x0016
55#define mmGRBM_READ_ERROR_BASE_IDX 0
56#define mmGRBM_READ_ERROR2 0x0017
57#define mmGRBM_READ_ERROR2_BASE_IDX 0
58#define mmGRBM_INT_CNTL 0x0018
59#define mmGRBM_INT_CNTL_BASE_IDX 0
60#define mmGRBM_TRAP_OP 0x0019
61#define mmGRBM_TRAP_OP_BASE_IDX 0
62#define mmGRBM_TRAP_ADDR 0x001a
63#define mmGRBM_TRAP_ADDR_BASE_IDX 0
64#define mmGRBM_TRAP_ADDR_MSK 0x001b
65#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0
66#define mmGRBM_TRAP_WD 0x001c
67#define mmGRBM_TRAP_WD_BASE_IDX 0
68#define mmGRBM_TRAP_WD_MSK 0x001d
69#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0
70#define mmGRBM_DSM_BYPASS 0x001e
71#define mmGRBM_DSM_BYPASS_BASE_IDX 0
72#define mmGRBM_WRITE_ERROR 0x001f
73#define mmGRBM_WRITE_ERROR_BASE_IDX 0
74#define mmGRBM_IOV_ERROR 0x0020
75#define mmGRBM_IOV_ERROR_BASE_IDX 0
76#define mmGRBM_CHIP_REVISION 0x0021
77#define mmGRBM_CHIP_REVISION_BASE_IDX 0
78#define mmGRBM_GFX_CNTL 0x0022
79#define mmGRBM_GFX_CNTL_BASE_IDX 0
80#define mmGRBM_RSMU_CFG 0x0023
81#define mmGRBM_RSMU_CFG_BASE_IDX 0
82#define mmGRBM_IH_CREDIT 0x0024
83#define mmGRBM_IH_CREDIT_BASE_IDX 0
84#define mmGRBM_PWR_CNTL2 0x0025
85#define mmGRBM_PWR_CNTL2_BASE_IDX 0
86#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026
87#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
88#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027
89#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
90#define mmGRBM_RSMU_READ_ERROR 0x0028
91#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0
92#define mmGRBM_CHICKEN_BITS 0x0029
93#define mmGRBM_CHICKEN_BITS_BASE_IDX 0
94#define mmGRBM_NOWHERE 0x003f
95#define mmGRBM_NOWHERE_BASE_IDX 0
96#define mmGRBM_SCRATCH_REG0 0x0040
97#define mmGRBM_SCRATCH_REG0_BASE_IDX 0
98#define mmGRBM_SCRATCH_REG1 0x0041
99#define mmGRBM_SCRATCH_REG1_BASE_IDX 0
100#define mmGRBM_SCRATCH_REG2 0x0042
101#define mmGRBM_SCRATCH_REG2_BASE_IDX 0
102#define mmGRBM_SCRATCH_REG3 0x0043
103#define mmGRBM_SCRATCH_REG3_BASE_IDX 0
104#define mmGRBM_SCRATCH_REG4 0x0044
105#define mmGRBM_SCRATCH_REG4_BASE_IDX 0
106#define mmGRBM_SCRATCH_REG5 0x0045
107#define mmGRBM_SCRATCH_REG5_BASE_IDX 0
108#define mmGRBM_SCRATCH_REG6 0x0046
109#define mmGRBM_SCRATCH_REG6_BASE_IDX 0
110#define mmGRBM_SCRATCH_REG7 0x0047
111#define mmGRBM_SCRATCH_REG7_BASE_IDX 0
112
113
114// addressBlock: gc_cpdec
115// base address: 0x8200
116#define mmCP_CPC_STATUS 0x0084
117#define mmCP_CPC_STATUS_BASE_IDX 0
118#define mmCP_CPC_BUSY_STAT 0x0085
119#define mmCP_CPC_BUSY_STAT_BASE_IDX 0
120#define mmCP_CPC_STALLED_STAT1 0x0086
121#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0
122#define mmCP_CPF_STATUS 0x0087
123#define mmCP_CPF_STATUS_BASE_IDX 0
124#define mmCP_CPF_BUSY_STAT 0x0088
125#define mmCP_CPF_BUSY_STAT_BASE_IDX 0
126#define mmCP_CPF_STALLED_STAT1 0x0089
127#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0
128#define mmCP_CPC_GRBM_FREE_COUNT 0x008b
129#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
130#define mmCP_MEC_CNTL 0x008d
131#define mmCP_MEC_CNTL_BASE_IDX 0
132#define mmCP_MEC_ME1_HEADER_DUMP 0x008e
133#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
134#define mmCP_MEC_ME2_HEADER_DUMP 0x008f
135#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
136#define mmCP_CPC_SCRATCH_INDEX 0x0090
137#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0
138#define mmCP_CPC_SCRATCH_DATA 0x0091
139#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0
140#define mmCP_CPF_GRBM_FREE_COUNT 0x0092
141#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
142#define mmCP_CPC_HALT_HYST_COUNT 0x00a7
143#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
144#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad
145#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0
146#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae
147#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0
148#define mmCP_PRT_LOD_STATS_CNTL2 0x00af
149#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0
150#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0
151#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0
152#define mmCP_CE_COMPARE_COUNT 0x00c0
153#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0
154#define mmCP_CE_DE_COUNT 0x00c1
155#define mmCP_CE_DE_COUNT_BASE_IDX 0
156#define mmCP_DE_CE_COUNT 0x00c2
157#define mmCP_DE_CE_COUNT_BASE_IDX 0
158#define mmCP_DE_LAST_INVAL_COUNT 0x00c3
159#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
160#define mmCP_DE_DE_COUNT 0x00c4
161#define mmCP_DE_DE_COUNT_BASE_IDX 0
162#define mmCP_STALLED_STAT3 0x019c
163#define mmCP_STALLED_STAT3_BASE_IDX 0
164#define mmCP_STALLED_STAT1 0x019d
165#define mmCP_STALLED_STAT1_BASE_IDX 0
166#define mmCP_STALLED_STAT2 0x019e
167#define mmCP_STALLED_STAT2_BASE_IDX 0
168#define mmCP_BUSY_STAT 0x019f
169#define mmCP_BUSY_STAT_BASE_IDX 0
170#define mmCP_STAT 0x01a0
171#define mmCP_STAT_BASE_IDX 0
172#define mmCP_ME_HEADER_DUMP 0x01a1
173#define mmCP_ME_HEADER_DUMP_BASE_IDX 0
174#define mmCP_PFP_HEADER_DUMP 0x01a2
175#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0
176#define mmCP_GRBM_FREE_COUNT 0x01a3
177#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0
178#define mmCP_CE_HEADER_DUMP 0x01a4
179#define mmCP_CE_HEADER_DUMP_BASE_IDX 0
180#define mmCP_PFP_INSTR_PNTR 0x01a5
181#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0
182#define mmCP_ME_INSTR_PNTR 0x01a6
183#define mmCP_ME_INSTR_PNTR_BASE_IDX 0
184#define mmCP_CE_INSTR_PNTR 0x01a7
185#define mmCP_CE_INSTR_PNTR_BASE_IDX 0
186#define mmCP_MEC1_INSTR_PNTR 0x01a8
187#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0
188#define mmCP_MEC2_INSTR_PNTR 0x01a9
189#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0
190#define mmCP_CSF_STAT 0x01b4
191#define mmCP_CSF_STAT_BASE_IDX 0
192#define mmCP_ME_CNTL 0x01b6
193#define mmCP_ME_CNTL_BASE_IDX 0
194#define mmCP_CNTX_STAT 0x01b8
195#define mmCP_CNTX_STAT_BASE_IDX 0
196#define mmCP_ME_PREEMPTION 0x01b9
197#define mmCP_ME_PREEMPTION_BASE_IDX 0
198#define mmCP_ROQ_THRESHOLDS 0x01bc
199#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0
200#define mmCP_MEQ_STQ_THRESHOLD 0x01bd
201#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
202#define mmCP_RB2_RPTR 0x01be
203#define mmCP_RB2_RPTR_BASE_IDX 0
204#define mmCP_RB1_RPTR 0x01bf
205#define mmCP_RB1_RPTR_BASE_IDX 0
206#define mmCP_RB0_RPTR 0x01c0
207#define mmCP_RB0_RPTR_BASE_IDX 0
208#define mmCP_RB_RPTR 0x01c0
209#define mmCP_RB_RPTR_BASE_IDX 0
210#define mmCP_RB_WPTR_DELAY 0x01c1
211#define mmCP_RB_WPTR_DELAY_BASE_IDX 0
212#define mmCP_RB_WPTR_POLL_CNTL 0x01c2
213#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
214#define mmCP_ROQ1_THRESHOLDS 0x01d5
215#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0
216#define mmCP_ROQ2_THRESHOLDS 0x01d6
217#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0
218#define mmCP_STQ_THRESHOLDS 0x01d7
219#define mmCP_STQ_THRESHOLDS_BASE_IDX 0
220#define mmCP_QUEUE_THRESHOLDS 0x01d8
221#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0
222#define mmCP_MEQ_THRESHOLDS 0x01d9
223#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0
224#define mmCP_ROQ_AVAIL 0x01da
225#define mmCP_ROQ_AVAIL_BASE_IDX 0
226#define mmCP_STQ_AVAIL 0x01db
227#define mmCP_STQ_AVAIL_BASE_IDX 0
228#define mmCP_ROQ2_AVAIL 0x01dc
229#define mmCP_ROQ2_AVAIL_BASE_IDX 0
230#define mmCP_MEQ_AVAIL 0x01dd
231#define mmCP_MEQ_AVAIL_BASE_IDX 0
232#define mmCP_CMD_INDEX 0x01de
233#define mmCP_CMD_INDEX_BASE_IDX 0
234#define mmCP_CMD_DATA 0x01df
235#define mmCP_CMD_DATA_BASE_IDX 0
236#define mmCP_ROQ_RB_STAT 0x01e0
237#define mmCP_ROQ_RB_STAT_BASE_IDX 0
238#define mmCP_ROQ_IB1_STAT 0x01e1
239#define mmCP_ROQ_IB1_STAT_BASE_IDX 0
240#define mmCP_ROQ_IB2_STAT 0x01e2
241#define mmCP_ROQ_IB2_STAT_BASE_IDX 0
242#define mmCP_STQ_STAT 0x01e3
243#define mmCP_STQ_STAT_BASE_IDX 0
244#define mmCP_STQ_WR_STAT 0x01e4
245#define mmCP_STQ_WR_STAT_BASE_IDX 0
246#define mmCP_MEQ_STAT 0x01e5
247#define mmCP_MEQ_STAT_BASE_IDX 0
248#define mmCP_CEQ1_AVAIL 0x01e6
249#define mmCP_CEQ1_AVAIL_BASE_IDX 0
250#define mmCP_CEQ2_AVAIL 0x01e7
251#define mmCP_CEQ2_AVAIL_BASE_IDX 0
252#define mmCP_CE_ROQ_RB_STAT 0x01e8
253#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0
254#define mmCP_CE_ROQ_IB1_STAT 0x01e9
255#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0
256#define mmCP_CE_ROQ_IB2_STAT 0x01ea
257#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0
258
259
260// addressBlock: gc_padec
261// base address: 0x8800
262#define mmVGT_VTX_VECT_EJECT_REG 0x022c
263#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
264#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d
265#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
266#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e
267#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
268#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f
269#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
270#define mmVGT_LAST_COPY_STATE 0x0230
271#define mmVGT_LAST_COPY_STATE_BASE_IDX 0
272#define mmVGT_CACHE_INVALIDATION 0x0231
273#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0
274#define mmVGT_STRMOUT_DELAY 0x0233
275#define mmVGT_STRMOUT_DELAY_BASE_IDX 0
276#define mmVGT_FIFO_DEPTHS 0x0234
277#define mmVGT_FIFO_DEPTHS_BASE_IDX 0
278#define mmVGT_GS_VERTEX_REUSE 0x0235
279#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0
280#define mmVGT_MC_LAT_CNTL 0x0236
281#define mmVGT_MC_LAT_CNTL_BASE_IDX 0
282#define mmIA_CNTL_STATUS 0x0237
283#define mmIA_CNTL_STATUS_BASE_IDX 0
284#define mmVGT_CNTL_STATUS 0x023c
285#define mmVGT_CNTL_STATUS_BASE_IDX 0
286#define mmWD_CNTL_STATUS 0x023f
287#define mmWD_CNTL_STATUS_BASE_IDX 0
288#define mmCC_GC_PRIM_CONFIG 0x0240
289#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0
290#define mmGC_USER_PRIM_CONFIG 0x0241
291#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0
292#define mmWD_QOS 0x0242
293#define mmWD_QOS_BASE_IDX 0
294#define mmWD_UTCL1_CNTL 0x0243
295#define mmWD_UTCL1_CNTL_BASE_IDX 0
296#define mmWD_UTCL1_STATUS 0x0244
297#define mmWD_UTCL1_STATUS_BASE_IDX 0
298#define mmIA_UTCL1_CNTL 0x0246
299#define mmIA_UTCL1_CNTL_BASE_IDX 0
300#define mmIA_UTCL1_STATUS 0x0247
301#define mmIA_UTCL1_STATUS_BASE_IDX 0
302#define mmVGT_SYS_CONFIG 0x0263
303#define mmVGT_SYS_CONFIG_BASE_IDX 0
304#define mmVGT_VS_MAX_WAVE_ID 0x0268
305#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0
306#define mmVGT_GS_MAX_WAVE_ID 0x0269
307#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0
308#define mmGFX_PIPE_CONTROL 0x026d
309#define mmGFX_PIPE_CONTROL_BASE_IDX 0
310#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f
311#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
312#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270
313#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
314#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271
315#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
316#define mmVGT_DMA_CONTROL 0x0272
317#define mmVGT_DMA_CONTROL_BASE_IDX 0
318#define mmVGT_DMA_LS_HS_CONFIG 0x0273
319#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
320#define mmWD_BUF_RESOURCE_1 0x0276
321#define mmWD_BUF_RESOURCE_1_BASE_IDX 0
322#define mmWD_BUF_RESOURCE_2 0x0277
323#define mmWD_BUF_RESOURCE_2_BASE_IDX 0
324#define mmPA_CL_CNTL_STATUS 0x0284
325#define mmPA_CL_CNTL_STATUS_BASE_IDX 0
326#define mmPA_CL_ENHANCE 0x0285
327#define mmPA_CL_ENHANCE_BASE_IDX 0
328#define mmPA_SU_CNTL_STATUS 0x0294
329#define mmPA_SU_CNTL_STATUS_BASE_IDX 0
330#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295
331#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
332#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0
333#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
334#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1
335#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
336#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2
337#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
338#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9
339#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
340#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc
341#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
342#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd
343#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
344#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce
345#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
346#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf
347#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
348#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0
349#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
350#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1
351#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
352#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2
353#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
354#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3
355#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
356#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4
357#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
358#define mmPA_SC_FIFO_SIZE 0x02f3
359#define mmPA_SC_FIFO_SIZE_BASE_IDX 0
360#define mmPA_SC_IF_FIFO_SIZE 0x02f5
361#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0
362#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8
363#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
364#define mmPA_UTCL1_CNTL1 0x02f9
365#define mmPA_UTCL1_CNTL1_BASE_IDX 0
366#define mmPA_UTCL1_CNTL2 0x02fa
367#define mmPA_UTCL1_CNTL2_BASE_IDX 0
368#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb
369#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
370#define mmPA_SC_ENHANCE 0x02fc
371#define mmPA_SC_ENHANCE_BASE_IDX 0
372#define mmPA_SC_ENHANCE_1 0x02fd
373#define mmPA_SC_ENHANCE_1_BASE_IDX 0
374#define mmPA_SC_DSM_CNTL 0x02fe
375#define mmPA_SC_DSM_CNTL_BASE_IDX 0
376#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff
377#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
378
379
380// addressBlock: gc_sqdec
381// base address: 0x8c00
382#define mmSQ_CONFIG 0x0300
383#define mmSQ_CONFIG_BASE_IDX 0
384#define mmSQC_CONFIG 0x0301
385#define mmSQC_CONFIG_BASE_IDX 0
386#define mmLDS_CONFIG 0x0302
387#define mmLDS_CONFIG_BASE_IDX 0
388#define mmSQ_RANDOM_WAVE_PRI 0x0303
389#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0
390#define mmSQ_REG_CREDITS 0x0304
391#define mmSQ_REG_CREDITS_BASE_IDX 0
392#define mmSQ_FIFO_SIZES 0x0305
393#define mmSQ_FIFO_SIZES_BASE_IDX 0
394#define mmSQ_DSM_CNTL 0x0306
395#define mmSQ_DSM_CNTL_BASE_IDX 0
396#define mmSQ_DSM_CNTL2 0x0307
397#define mmSQ_DSM_CNTL2_BASE_IDX 0
398#define mmSQ_RUNTIME_CONFIG 0x0308
399#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0
400#define mmSH_MEM_BASES 0x030a
401#define mmSH_MEM_BASES_BASE_IDX 0
402#define mmSH_MEM_CONFIG 0x030d
403#define mmSH_MEM_CONFIG_BASE_IDX 0
404#define mmCC_GC_SHADER_RATE_CONFIG 0x0312
405#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
406#define mmGC_USER_SHADER_RATE_CONFIG 0x0313
407#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
408#define mmSQ_INTERRUPT_AUTO_MASK 0x0314
409#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
410#define mmSQ_INTERRUPT_MSG_CTRL 0x0315
411#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
412#define mmSQ_UTCL1_CNTL1 0x0317
413#define mmSQ_UTCL1_CNTL1_BASE_IDX 0
414#define mmSQ_UTCL1_CNTL2 0x0318
415#define mmSQ_UTCL1_CNTL2_BASE_IDX 0
416#define mmSQ_UTCL1_STATUS 0x0319
417#define mmSQ_UTCL1_STATUS_BASE_IDX 0
418#define mmSQ_SHADER_TBA_LO 0x031c
419#define mmSQ_SHADER_TBA_LO_BASE_IDX 0
420#define mmSQ_SHADER_TBA_HI 0x031d
421#define mmSQ_SHADER_TBA_HI_BASE_IDX 0
422#define mmSQ_SHADER_TMA_LO 0x031e
423#define mmSQ_SHADER_TMA_LO_BASE_IDX 0
424#define mmSQ_SHADER_TMA_HI 0x031f
425#define mmSQ_SHADER_TMA_HI_BASE_IDX 0
426#define mmSQC_DSM_CNTL 0x0320
427#define mmSQC_DSM_CNTL_BASE_IDX 0
428#define mmSQC_DSM_CNTLA 0x0321
429#define mmSQC_DSM_CNTLA_BASE_IDX 0
430#define mmSQC_DSM_CNTLB 0x0322
431#define mmSQC_DSM_CNTLB_BASE_IDX 0
432#define mmSQC_DSM_CNTL2 0x0325
433#define mmSQC_DSM_CNTL2_BASE_IDX 0
434#define mmSQC_DSM_CNTL2A 0x0326
435#define mmSQC_DSM_CNTL2A_BASE_IDX 0
436#define mmSQC_DSM_CNTL2B 0x0327
437#define mmSQC_DSM_CNTL2B_BASE_IDX 0
438#define mmSQC_EDC_FUE_CNTL 0x032b
439#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0
440#define mmSQC_EDC_CNT2 0x032c
441#define mmSQC_EDC_CNT2_BASE_IDX 0
442#define mmSQC_EDC_CNT3 0x032d
443#define mmSQC_EDC_CNT3_BASE_IDX 0
444#define mmSQ_REG_TIMESTAMP 0x0374
445#define mmSQ_REG_TIMESTAMP_BASE_IDX 0
446#define mmSQ_CMD_TIMESTAMP 0x0375
447#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0
448#define mmSQ_IND_INDEX 0x0378
449#define mmSQ_IND_INDEX_BASE_IDX 0
450#define mmSQ_IND_DATA 0x0379
451#define mmSQ_IND_DATA_BASE_IDX 0
452#define mmSQ_CMD 0x037b
453#define mmSQ_CMD_BASE_IDX 0
454#define mmSQ_TIME_HI 0x037c
455#define mmSQ_TIME_HI_BASE_IDX 0
456#define mmSQ_TIME_LO 0x037d
457#define mmSQ_TIME_LO_BASE_IDX 0
458#define mmSQ_DS_0 0x037f
459#define mmSQ_DS_0_BASE_IDX 0
460#define mmSQ_DS_1 0x037f
461#define mmSQ_DS_1_BASE_IDX 0
462#define mmSQ_EXP_0 0x037f
463#define mmSQ_EXP_0_BASE_IDX 0
464#define mmSQ_EXP_1 0x037f
465#define mmSQ_EXP_1_BASE_IDX 0
466#define mmSQ_FLAT_0 0x037f
467#define mmSQ_FLAT_0_BASE_IDX 0
468#define mmSQ_FLAT_1 0x037f
469#define mmSQ_FLAT_1_BASE_IDX 0
470#define mmSQ_GLBL_0 0x037f
471#define mmSQ_GLBL_0_BASE_IDX 0
472#define mmSQ_GLBL_1 0x037f
473#define mmSQ_GLBL_1_BASE_IDX 0
474#define mmSQ_INST 0x037f
475#define mmSQ_INST_BASE_IDX 0
476#define mmSQ_MIMG_0 0x037f
477#define mmSQ_MIMG_0_BASE_IDX 0
478#define mmSQ_MIMG_1 0x037f
479#define mmSQ_MIMG_1_BASE_IDX 0
480#define mmSQ_MTBUF_0 0x037f
481#define mmSQ_MTBUF_0_BASE_IDX 0
482#define mmSQ_MTBUF_1 0x037f
483#define mmSQ_MTBUF_1_BASE_IDX 0
484#define mmSQ_MUBUF_0 0x037f
485#define mmSQ_MUBUF_0_BASE_IDX 0
486#define mmSQ_MUBUF_1 0x037f
487#define mmSQ_MUBUF_1_BASE_IDX 0
488#define mmSQ_SCRATCH_0 0x037f
489#define mmSQ_SCRATCH_0_BASE_IDX 0
490#define mmSQ_SCRATCH_1 0x037f
491#define mmSQ_SCRATCH_1_BASE_IDX 0
492#define mmSQ_SMEM_0 0x037f
493#define mmSQ_SMEM_0_BASE_IDX 0
494#define mmSQ_SMEM_1 0x037f
495#define mmSQ_SMEM_1_BASE_IDX 0
496#define mmSQ_SOP1 0x037f
497#define mmSQ_SOP1_BASE_IDX 0
498#define mmSQ_SOP2 0x037f
499#define mmSQ_SOP2_BASE_IDX 0
500#define mmSQ_SOPC 0x037f
501#define mmSQ_SOPC_BASE_IDX 0
502#define mmSQ_SOPK 0x037f
503#define mmSQ_SOPK_BASE_IDX 0
504#define mmSQ_SOPP 0x037f
505#define mmSQ_SOPP_BASE_IDX 0
506#define mmSQ_VINTRP 0x037f
507#define mmSQ_VINTRP_BASE_IDX 0
508#define mmSQ_VOP1 0x037f
509#define mmSQ_VOP1_BASE_IDX 0
510#define mmSQ_VOP2 0x037f
511#define mmSQ_VOP2_BASE_IDX 0
512#define mmSQ_VOP3P_0 0x037f
513#define mmSQ_VOP3P_0_BASE_IDX 0
514#define mmSQ_VOP3P_1 0x037f
515#define mmSQ_VOP3P_1_BASE_IDX 0
516#define mmSQ_VOP3_0 0x037f
517#define mmSQ_VOP3_0_BASE_IDX 0
518#define mmSQ_VOP3_0_SDST_ENC 0x037f
519#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0
520#define mmSQ_VOP3_1 0x037f
521#define mmSQ_VOP3_1_BASE_IDX 0
522#define mmSQ_VOPC 0x037f
523#define mmSQ_VOPC_BASE_IDX 0
524#define mmSQ_VOP_DPP 0x037f
525#define mmSQ_VOP_DPP_BASE_IDX 0
526#define mmSQ_VOP_SDWA 0x037f
527#define mmSQ_VOP_SDWA_BASE_IDX 0
528#define mmSQ_VOP_SDWA_SDST_ENC 0x037f
529#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0
530#define mmSQ_LB_CTR_CTRL 0x0398
531#define mmSQ_LB_CTR_CTRL_BASE_IDX 0
532#define mmSQ_LB_DATA0 0x0399
533#define mmSQ_LB_DATA0_BASE_IDX 0
534#define mmSQ_LB_DATA1 0x039a
535#define mmSQ_LB_DATA1_BASE_IDX 0
536#define mmSQ_LB_DATA2 0x039b
537#define mmSQ_LB_DATA2_BASE_IDX 0
538#define mmSQ_LB_DATA3 0x039c
539#define mmSQ_LB_DATA3_BASE_IDX 0
540#define mmSQ_LB_CTR_SEL 0x039d
541#define mmSQ_LB_CTR_SEL_BASE_IDX 0
542#define mmSQ_LB_CTR0_CU 0x039e
543#define mmSQ_LB_CTR0_CU_BASE_IDX 0
544#define mmSQ_LB_CTR1_CU 0x039f
545#define mmSQ_LB_CTR1_CU_BASE_IDX 0
546#define mmSQ_LB_CTR2_CU 0x03a0
547#define mmSQ_LB_CTR2_CU_BASE_IDX 0
548#define mmSQ_LB_CTR3_CU 0x03a1
549#define mmSQ_LB_CTR3_CU_BASE_IDX 0
550#define mmSQC_EDC_CNT 0x03a2
551#define mmSQC_EDC_CNT_BASE_IDX 0
552#define mmSQ_EDC_SEC_CNT 0x03a3
553#define mmSQ_EDC_SEC_CNT_BASE_IDX 0
554#define mmSQ_EDC_DED_CNT 0x03a4
555#define mmSQ_EDC_DED_CNT_BASE_IDX 0
556#define mmSQ_EDC_INFO 0x03a5
557#define mmSQ_EDC_INFO_BASE_IDX 0
558#define mmSQ_EDC_CNT 0x03a6
559#define mmSQ_EDC_CNT_BASE_IDX 0
560#define mmSQ_EDC_FUE_CNTL 0x03a7
561#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0
562#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0
563#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0
564#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0
565#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0
566#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0
567#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0
568#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0
569#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0
570#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0
571#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0
572#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0
573#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0
574#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0
575#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0
576#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0
577#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0
578#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0
579#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0
580#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0
581#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0
582#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0
583#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0
584#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0
585#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0
586#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0
587#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0
588#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0
589#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0
590#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0
591#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0
592#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1
593#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0
594#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1
595#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0
596#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1
597#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0
598#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1
599#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0
600#define mmSQ_WREXEC_EXEC_HI 0x03b1
601#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0
602#define mmSQ_WREXEC_EXEC_LO 0x03b1
603#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0
604#define mmSQ_BUF_RSRC_WORD0 0x03c0
605#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0
606#define mmSQ_BUF_RSRC_WORD1 0x03c1
607#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0
608#define mmSQ_BUF_RSRC_WORD2 0x03c2
609#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0
610#define mmSQ_BUF_RSRC_WORD3 0x03c3
611#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0
612#define mmSQ_IMG_RSRC_WORD0 0x03c4
613#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0
614#define mmSQ_IMG_RSRC_WORD1 0x03c5
615#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0
616#define mmSQ_IMG_RSRC_WORD2 0x03c6
617#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0
618#define mmSQ_IMG_RSRC_WORD3 0x03c7
619#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0
620#define mmSQ_IMG_RSRC_WORD4 0x03c8
621#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0
622#define mmSQ_IMG_RSRC_WORD5 0x03c9
623#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0
624#define mmSQ_IMG_RSRC_WORD6 0x03ca
625#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0
626#define mmSQ_IMG_RSRC_WORD7 0x03cb
627#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0
628#define mmSQ_IMG_SAMP_WORD0 0x03cc
629#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0
630#define mmSQ_IMG_SAMP_WORD1 0x03cd
631#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0
632#define mmSQ_IMG_SAMP_WORD2 0x03ce
633#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0
634#define mmSQ_IMG_SAMP_WORD3 0x03cf
635#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0
636#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0
637#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0
638#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1
639#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0
640#define mmSQ_M0_GPR_IDX_WORD 0x03d2
641#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0
642#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3
643#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0
644#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4
645#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0
646#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5
647#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0
648#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6
649#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0
650#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7
651#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
652#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8
653#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0
654
655
656// addressBlock: gc_shsdec
657// base address: 0x9000
658#define mmSX_DEBUG_1 0x0419
659#define mmSX_DEBUG_1_BASE_IDX 0
660#define mmSPI_PS_MAX_WAVE_ID 0x043a
661#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0
662#define mmSPI_START_PHASE 0x043b
663#define mmSPI_START_PHASE_BASE_IDX 0
664#define mmSPI_GFX_CNTL 0x043c
665#define mmSPI_GFX_CNTL_BASE_IDX 0
666#define mmSPI_DSM_CNTL 0x0443
667#define mmSPI_DSM_CNTL_BASE_IDX 0
668#define mmSPI_DSM_CNTL2 0x0444
669#define mmSPI_DSM_CNTL2_BASE_IDX 0
670#define mmSPI_EDC_CNT 0x0445
671#define mmSPI_EDC_CNT_BASE_IDX 0
672#define mmSPI_CONFIG_PS_CU_EN 0x0452
673#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0
674#define mmSPI_WF_LIFETIME_CNTL 0x04aa
675#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0
676#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab
677#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0
678#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac
679#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0
680#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad
681#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0
682#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae
683#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0
684#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af
685#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0
686#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0
687#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0
688#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1
689#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0
690#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2
691#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0
692#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3
693#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0
694#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4
695#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0
696#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5
697#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0
698#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6
699#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0
700#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7
701#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0
702#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8
703#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0
704#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9
705#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0
706#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba
707#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0
708#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb
709#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0
710#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc
711#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0
712#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd
713#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0
714#define mmSPI_WF_LIFETIME_STATUS_9 0x04be
715#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0
716#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf
717#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0
718#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0
719#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0
720#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1
721#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0
722#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2
723#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0
724#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3
725#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0
726#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4
727#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0
728#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5
729#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0
730#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6
731#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0
732#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7
733#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0
734#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8
735#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0
736#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9
737#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0
738#define mmSPI_LB_CTR_CTRL 0x04d4
739#define mmSPI_LB_CTR_CTRL_BASE_IDX 0
740#define mmSPI_LB_CU_MASK 0x04d5
741#define mmSPI_LB_CU_MASK_BASE_IDX 0
742#define mmSPI_LB_DATA_REG 0x04d6
743#define mmSPI_LB_DATA_REG_BASE_IDX 0
744#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7
745#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0
746#define mmSPI_GDS_CREDITS 0x04d8
747#define mmSPI_GDS_CREDITS_BASE_IDX 0
748#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9
749#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0
750#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da
751#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0
752#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db
753#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0
754#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc
755#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0
756#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd
757#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0
758#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de
759#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0
760#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df
761#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0
762#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0
763#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0
764#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1
765#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0
766#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2
767#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0
768#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3
769#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0
770#define mmSPI_LB_DATA_WAVES 0x04e4
771#define mmSPI_LB_DATA_WAVES_BASE_IDX 0
772#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5
773#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0
774#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6
775#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0
776#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7
777#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0
778#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec
779#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
780#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed
781#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
782#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee
783#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
784#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef
785#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
786#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0
787#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
788#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1
789#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
790#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2
791#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
792#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3
793#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
794#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4
795#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
796#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5
797#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
798
799
800// addressBlock: gc_tpdec
801// base address: 0x9400
802#define mmTD_CNTL 0x0525
803#define mmTD_CNTL_BASE_IDX 0
804#define mmTD_STATUS 0x0526
805#define mmTD_STATUS_BASE_IDX 0
806#define mmTD_DSM_CNTL 0x052f
807#define mmTD_DSM_CNTL_BASE_IDX 0
808#define mmTD_DSM_CNTL2 0x0530
809#define mmTD_DSM_CNTL2_BASE_IDX 0
810#define mmTD_SCRATCH 0x0533
811#define mmTD_SCRATCH_BASE_IDX 0
812#define mmTA_CNTL 0x0541
813#define mmTA_CNTL_BASE_IDX 0
814#define mmTA_CNTL_AUX 0x0542
815#define mmTA_CNTL_AUX_BASE_IDX 0
816#define mmTA_RESERVED_010C 0x0543
817#define mmTA_RESERVED_010C_BASE_IDX 0
818#define mmTA_STATUS 0x0548
819#define mmTA_STATUS_BASE_IDX 0
820#define mmTA_SCRATCH 0x0564
821#define mmTA_SCRATCH_BASE_IDX 0
822
823
824// addressBlock: gc_gdsdec
825// base address: 0x9700
826#define mmGDS_CONFIG 0x05c0
827#define mmGDS_CONFIG_BASE_IDX 0
828#define mmGDS_CNTL_STATUS 0x05c1
829#define mmGDS_CNTL_STATUS_BASE_IDX 0
830#define mmGDS_ENHANCE2 0x05c2
831#define mmGDS_ENHANCE2_BASE_IDX 0
832#define mmGDS_PROTECTION_FAULT 0x05c3
833#define mmGDS_PROTECTION_FAULT_BASE_IDX 0
834#define mmGDS_VM_PROTECTION_FAULT 0x05c4
835#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0
836#define mmGDS_EDC_CNT 0x05c5
837#define mmGDS_EDC_CNT_BASE_IDX 0
838#define mmGDS_EDC_GRBM_CNT 0x05c6
839#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0
840#define mmGDS_EDC_OA_DED 0x05c7
841#define mmGDS_EDC_OA_DED_BASE_IDX 0
842#define mmGDS_DSM_CNTL 0x05ca
843#define mmGDS_DSM_CNTL_BASE_IDX 0
844#define mmGDS_EDC_OA_PHY_CNT 0x05cb
845#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0
846#define mmGDS_EDC_OA_PIPE_CNT 0x05cc
847#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0
848#define mmGDS_DSM_CNTL2 0x05cd
849#define mmGDS_DSM_CNTL2_BASE_IDX 0
850#define mmGDS_WD_GDS_CSB 0x05ce
851#define mmGDS_WD_GDS_CSB_BASE_IDX 0
852
853
854// addressBlock: gc_rbdec
855// base address: 0x9800
856#define mmDB_DEBUG 0x060c
857#define mmDB_DEBUG_BASE_IDX 0
858#define mmDB_DEBUG2 0x060d
859#define mmDB_DEBUG2_BASE_IDX 0
860#define mmDB_DEBUG3 0x060e
861#define mmDB_DEBUG3_BASE_IDX 0
862#define mmDB_DEBUG4 0x060f
863#define mmDB_DEBUG4_BASE_IDX 0
864#define mmDB_CREDIT_LIMIT 0x0614
865#define mmDB_CREDIT_LIMIT_BASE_IDX 0
866#define mmDB_WATERMARKS 0x0615
867#define mmDB_WATERMARKS_BASE_IDX 0
868#define mmDB_SUBTILE_CONTROL 0x0616
869#define mmDB_SUBTILE_CONTROL_BASE_IDX 0
870#define mmDB_FREE_CACHELINES 0x0617
871#define mmDB_FREE_CACHELINES_BASE_IDX 0
872#define mmDB_FIFO_DEPTH1 0x0618
873#define mmDB_FIFO_DEPTH1_BASE_IDX 0
874#define mmDB_FIFO_DEPTH2 0x0619
875#define mmDB_FIFO_DEPTH2_BASE_IDX 0
876#define mmDB_EXCEPTION_CONTROL 0x061a
877#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0
878#define mmDB_RING_CONTROL 0x061b
879#define mmDB_RING_CONTROL_BASE_IDX 0
880#define mmDB_MEM_ARB_WATERMARKS 0x061c
881#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0
882#define mmDB_RMI_CACHE_POLICY 0x061e
883#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0
884#define mmDB_DFSM_CONFIG 0x0630
885#define mmDB_DFSM_CONFIG_BASE_IDX 0
886#define mmDB_DFSM_WATERMARK 0x0631
887#define mmDB_DFSM_WATERMARK_BASE_IDX 0
888#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632
889#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0
890#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633
891#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0
892#define mmDB_DFSM_WATCHDOG 0x0634
893#define mmDB_DFSM_WATCHDOG_BASE_IDX 0
894#define mmDB_DFSM_FLUSH_ENABLE 0x0635
895#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0
896#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636
897#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0
898#define mmCC_RB_REDUNDANCY 0x063c
899#define mmCC_RB_REDUNDANCY_BASE_IDX 0
900#define mmCC_RB_BACKEND_DISABLE 0x063d
901#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0
902#define mmGB_ADDR_CONFIG 0x063e
903#define mmGB_ADDR_CONFIG_BASE_IDX 0
904#define mmGB_BACKEND_MAP 0x063f
905#define mmGB_BACKEND_MAP_BASE_IDX 0
906#define mmGB_GPU_ID 0x0640
907#define mmGB_GPU_ID_BASE_IDX 0
908#define mmCC_RB_DAISY_CHAIN 0x0641
909#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0
910#define mmGB_ADDR_CONFIG_READ 0x0642
911#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0
912#define mmGB_TILE_MODE0 0x0644
913#define mmGB_TILE_MODE0_BASE_IDX 0
914#define mmGB_TILE_MODE1 0x0645
915#define mmGB_TILE_MODE1_BASE_IDX 0
916#define mmGB_TILE_MODE2 0x0646
917#define mmGB_TILE_MODE2_BASE_IDX 0
918#define mmGB_TILE_MODE3 0x0647
919#define mmGB_TILE_MODE3_BASE_IDX 0
920#define mmGB_TILE_MODE4 0x0648
921#define mmGB_TILE_MODE4_BASE_IDX 0
922#define mmGB_TILE_MODE5 0x0649
923#define mmGB_TILE_MODE5_BASE_IDX 0
924#define mmGB_TILE_MODE6 0x064a
925#define mmGB_TILE_MODE6_BASE_IDX 0
926#define mmGB_TILE_MODE7 0x064b
927#define mmGB_TILE_MODE7_BASE_IDX 0
928#define mmGB_TILE_MODE8 0x064c
929#define mmGB_TILE_MODE8_BASE_IDX 0
930#define mmGB_TILE_MODE9 0x064d
931#define mmGB_TILE_MODE9_BASE_IDX 0
932#define mmGB_TILE_MODE10 0x064e
933#define mmGB_TILE_MODE10_BASE_IDX 0
934#define mmGB_TILE_MODE11 0x064f
935#define mmGB_TILE_MODE11_BASE_IDX 0
936#define mmGB_TILE_MODE12 0x0650
937#define mmGB_TILE_MODE12_BASE_IDX 0
938#define mmGB_TILE_MODE13 0x0651
939#define mmGB_TILE_MODE13_BASE_IDX 0
940#define mmGB_TILE_MODE14 0x0652
941#define mmGB_TILE_MODE14_BASE_IDX 0
942#define mmGB_TILE_MODE15 0x0653
943#define mmGB_TILE_MODE15_BASE_IDX 0
944#define mmGB_TILE_MODE16 0x0654
945#define mmGB_TILE_MODE16_BASE_IDX 0
946#define mmGB_TILE_MODE17 0x0655
947#define mmGB_TILE_MODE17_BASE_IDX 0
948#define mmGB_TILE_MODE18 0x0656
949#define mmGB_TILE_MODE18_BASE_IDX 0
950#define mmGB_TILE_MODE19 0x0657
951#define mmGB_TILE_MODE19_BASE_IDX 0
952#define mmGB_TILE_MODE20 0x0658
953#define mmGB_TILE_MODE20_BASE_IDX 0
954#define mmGB_TILE_MODE21 0x0659
955#define mmGB_TILE_MODE21_BASE_IDX 0
956#define mmGB_TILE_MODE22 0x065a
957#define mmGB_TILE_MODE22_BASE_IDX 0
958#define mmGB_TILE_MODE23 0x065b
959#define mmGB_TILE_MODE23_BASE_IDX 0
960#define mmGB_TILE_MODE24 0x065c
961#define mmGB_TILE_MODE24_BASE_IDX 0
962#define mmGB_TILE_MODE25 0x065d
963#define mmGB_TILE_MODE25_BASE_IDX 0
964#define mmGB_TILE_MODE26 0x065e
965#define mmGB_TILE_MODE26_BASE_IDX 0
966#define mmGB_TILE_MODE27 0x065f
967#define mmGB_TILE_MODE27_BASE_IDX 0
968#define mmGB_TILE_MODE28 0x0660
969#define mmGB_TILE_MODE28_BASE_IDX 0
970#define mmGB_TILE_MODE29 0x0661
971#define mmGB_TILE_MODE29_BASE_IDX 0
972#define mmGB_TILE_MODE30 0x0662
973#define mmGB_TILE_MODE30_BASE_IDX 0
974#define mmGB_TILE_MODE31 0x0663
975#define mmGB_TILE_MODE31_BASE_IDX 0
976#define mmGB_MACROTILE_MODE0 0x0664
977#define mmGB_MACROTILE_MODE0_BASE_IDX 0
978#define mmGB_MACROTILE_MODE1 0x0665
979#define mmGB_MACROTILE_MODE1_BASE_IDX 0
980#define mmGB_MACROTILE_MODE2 0x0666
981#define mmGB_MACROTILE_MODE2_BASE_IDX 0
982#define mmGB_MACROTILE_MODE3 0x0667
983#define mmGB_MACROTILE_MODE3_BASE_IDX 0
984#define mmGB_MACROTILE_MODE4 0x0668
985#define mmGB_MACROTILE_MODE4_BASE_IDX 0
986#define mmGB_MACROTILE_MODE5 0x0669
987#define mmGB_MACROTILE_MODE5_BASE_IDX 0
988#define mmGB_MACROTILE_MODE6 0x066a
989#define mmGB_MACROTILE_MODE6_BASE_IDX 0
990#define mmGB_MACROTILE_MODE7 0x066b
991#define mmGB_MACROTILE_MODE7_BASE_IDX 0
992#define mmGB_MACROTILE_MODE8 0x066c
993#define mmGB_MACROTILE_MODE8_BASE_IDX 0
994#define mmGB_MACROTILE_MODE9 0x066d
995#define mmGB_MACROTILE_MODE9_BASE_IDX 0
996#define mmGB_MACROTILE_MODE10 0x066e
997#define mmGB_MACROTILE_MODE10_BASE_IDX 0
998#define mmGB_MACROTILE_MODE11 0x066f
999#define mmGB_MACROTILE_MODE11_BASE_IDX 0
1000#define mmGB_MACROTILE_MODE12 0x0670
1001#define mmGB_MACROTILE_MODE12_BASE_IDX 0
1002#define mmGB_MACROTILE_MODE13 0x0671
1003#define mmGB_MACROTILE_MODE13_BASE_IDX 0
1004#define mmGB_MACROTILE_MODE14 0x0672
1005#define mmGB_MACROTILE_MODE14_BASE_IDX 0
1006#define mmGB_MACROTILE_MODE15 0x0673
1007#define mmGB_MACROTILE_MODE15_BASE_IDX 0
1008#define mmCB_HW_CONTROL 0x0680
1009#define mmCB_HW_CONTROL_BASE_IDX 0
1010#define mmCB_HW_CONTROL_1 0x0681
1011#define mmCB_HW_CONTROL_1_BASE_IDX 0
1012#define mmCB_HW_CONTROL_2 0x0682
1013#define mmCB_HW_CONTROL_2_BASE_IDX 0
1014#define mmCB_HW_CONTROL_3 0x0683
1015#define mmCB_HW_CONTROL_3_BASE_IDX 0
1016#define mmCB_HW_MEM_ARBITER_RD 0x0686
1017#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0
1018#define mmCB_HW_MEM_ARBITER_WR 0x0687
1019#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0
1020#define mmCB_DCC_CONFIG 0x0688
1021#define mmCB_DCC_CONFIG_BASE_IDX 0
1022#define mmGC_USER_RB_REDUNDANCY 0x06de
1023#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0
1024#define mmGC_USER_RB_BACKEND_DISABLE 0x06df
1025#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
1026
1027
1028// addressBlock: gc_ea_gceadec2
1029// base address: 0x9c00
1030#define mmGCEA_EDC_CNT 0x0701
1031#define mmGCEA_EDC_CNT_BASE_IDX 0
1032#define mmGCEA_EDC_CNT2 0x0702
1033#define mmGCEA_EDC_CNT2_BASE_IDX 0
1034#define mmGCEA_DSM_CNTL 0x0703
1035#define mmGCEA_DSM_CNTL_BASE_IDX 0
1036#define mmGCEA_DSM_CNTLA 0x0704
1037#define mmGCEA_DSM_CNTLA_BASE_IDX 0
1038#define mmGCEA_DSM_CNTLB 0x0705
1039#define mmGCEA_DSM_CNTLB_BASE_IDX 0
1040#define mmGCEA_DSM_CNTL2 0x0706
1041#define mmGCEA_DSM_CNTL2_BASE_IDX 0
1042#define mmGCEA_DSM_CNTL2A 0x0707
1043#define mmGCEA_DSM_CNTL2A_BASE_IDX 0
1044#define mmGCEA_DSM_CNTL2B 0x0708
1045#define mmGCEA_DSM_CNTL2B_BASE_IDX 0
1046#define mmGCEA_TCC_XBR_CREDITS 0x0709
1047#define mmGCEA_TCC_XBR_CREDITS_BASE_IDX 0
1048#define mmGCEA_TCC_XBR_MAXBURST 0x070a
1049#define mmGCEA_TCC_XBR_MAXBURST_BASE_IDX 0
1050#define mmGCEA_PROBE_CNTL 0x070b
1051#define mmGCEA_PROBE_CNTL_BASE_IDX 0
1052#define mmGCEA_PROBE_MAP 0x070c
1053#define mmGCEA_PROBE_MAP_BASE_IDX 0
1054#define mmGCEA_ERR_STATUS 0x070d
1055#define mmGCEA_ERR_STATUS_BASE_IDX 0
1056#define mmGCEA_MISC2 0x070e
1057#define mmGCEA_MISC2_BASE_IDX 0
1058#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0 0x070f
1059#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0
1060#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1 0x0710
1061#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0
1062#define mmGCEA_SDP_BACKDOOR_DATACREDITS0 0x0711
1063#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0
1064#define mmGCEA_SDP_BACKDOOR_DATACREDITS1 0x0712
1065#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0
1066#define mmGCEA_SDP_BACKDOOR_MISCCREDITS 0x0713
1067#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0
1068#define mmGCEA_SDP_ENABLE 0x0714
1069#define mmGCEA_SDP_ENABLE_BASE_IDX 0
1070
1071
1072// addressBlock: gc_rmi_rmidec
1073// base address: 0x9e00
1074#define mmRMI_GENERAL_CNTL 0x0780
1075#define mmRMI_GENERAL_CNTL_BASE_IDX 0
1076#define mmRMI_GENERAL_CNTL1 0x0781
1077#define mmRMI_GENERAL_CNTL1_BASE_IDX 0
1078#define mmRMI_GENERAL_STATUS 0x0782
1079#define mmRMI_GENERAL_STATUS_BASE_IDX 0
1080#define mmRMI_SUBBLOCK_STATUS0 0x0783
1081#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0
1082#define mmRMI_SUBBLOCK_STATUS1 0x0784
1083#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0
1084#define mmRMI_SUBBLOCK_STATUS2 0x0785
1085#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0
1086#define mmRMI_SUBBLOCK_STATUS3 0x0786
1087#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0
1088#define mmRMI_XBAR_CONFIG 0x0787
1089#define mmRMI_XBAR_CONFIG_BASE_IDX 0
1090#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788
1091#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0
1092#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789
1093#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0
1094#define mmRMI_DEMUX_CNTL 0x078a
1095#define mmRMI_DEMUX_CNTL_BASE_IDX 0
1096#define mmRMI_UTCL1_CNTL1 0x078b
1097#define mmRMI_UTCL1_CNTL1_BASE_IDX 0
1098#define mmRMI_UTCL1_CNTL2 0x078c
1099#define mmRMI_UTCL1_CNTL2_BASE_IDX 0
1100#define mmRMI_UTC_UNIT_CONFIG 0x078d
1101#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0
1102#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e
1103#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0
1104#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f
1105#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0
1106#define mmRMI_SCOREBOARD_CNTL 0x0790
1107#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0
1108#define mmRMI_SCOREBOARD_STATUS0 0x0791
1109#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0
1110#define mmRMI_SCOREBOARD_STATUS1 0x0792
1111#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0
1112#define mmRMI_SCOREBOARD_STATUS2 0x0793
1113#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0
1114#define mmRMI_XBAR_ARBITER_CONFIG 0x0794
1115#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0
1116#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795
1117#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0
1118#define mmRMI_CLOCK_CNTRL 0x0796
1119#define mmRMI_CLOCK_CNTRL_BASE_IDX 0
1120#define mmRMI_UTCL1_STATUS 0x0797
1121#define mmRMI_UTCL1_STATUS_BASE_IDX 0
1122#define mmRMI_SPARE 0x079e
1123#define mmRMI_SPARE_BASE_IDX 0
1124#define mmRMI_SPARE_1 0x079f
1125#define mmRMI_SPARE_1_BASE_IDX 0
1126#define mmRMI_SPARE_2 0x07a0
1127#define mmRMI_SPARE_2_BASE_IDX 0
1128
1129
1130// addressBlock: gc_dbgu_gfx_dbgudec
1131// base address: 0x9f00
1132#define mmport_a_addr 0x07c0
1133#define mmport_a_addr_BASE_IDX 0
1134#define mmport_a_data_lo 0x07c1
1135#define mmport_a_data_lo_BASE_IDX 0
1136#define mmport_a_data_hi 0x07c2
1137#define mmport_a_data_hi_BASE_IDX 0
1138#define mmport_b_addr 0x07c3
1139#define mmport_b_addr_BASE_IDX 0
1140#define mmport_b_data_lo 0x07c4
1141#define mmport_b_data_lo_BASE_IDX 0
1142#define mmport_b_data_hi 0x07c5
1143#define mmport_b_data_hi_BASE_IDX 0
1144#define mmport_c_addr 0x07c6
1145#define mmport_c_addr_BASE_IDX 0
1146#define mmport_c_data_lo 0x07c7
1147#define mmport_c_data_lo_BASE_IDX 0
1148#define mmport_c_data_hi 0x07c8
1149#define mmport_c_data_hi_BASE_IDX 0
1150#define mmport_d_addr 0x07c9
1151#define mmport_d_addr_BASE_IDX 0
1152#define mmport_d_data_lo 0x07ca
1153#define mmport_d_data_lo_BASE_IDX 0
1154#define mmport_d_data_hi 0x07cb
1155#define mmport_d_data_hi_BASE_IDX 0
1156
1157
1158// addressBlock: gc_utcl2_atcl2dec
1159// base address: 0xa000
1160#define mmATC_L2_CNTL 0x0800
1161#define mmATC_L2_CNTL_BASE_IDX 0
1162#define mmATC_L2_CNTL2 0x0801
1163#define mmATC_L2_CNTL2_BASE_IDX 0
1164#define mmATC_L2_CACHE_DATA0 0x0804
1165#define mmATC_L2_CACHE_DATA0_BASE_IDX 0
1166#define mmATC_L2_CACHE_DATA1 0x0805
1167#define mmATC_L2_CACHE_DATA1_BASE_IDX 0
1168#define mmATC_L2_CACHE_DATA2 0x0806
1169#define mmATC_L2_CACHE_DATA2_BASE_IDX 0
1170#define mmATC_L2_CNTL3 0x0807
1171#define mmATC_L2_CNTL3_BASE_IDX 0
1172#define mmATC_L2_STATUS 0x0808
1173#define mmATC_L2_STATUS_BASE_IDX 0
1174#define mmATC_L2_STATUS2 0x0809
1175#define mmATC_L2_STATUS2_BASE_IDX 0
1176#define mmATC_L2_MISC_CG 0x080a
1177#define mmATC_L2_MISC_CG_BASE_IDX 0
1178#define mmATC_L2_MEM_POWER_LS 0x080b
1179#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
1180#define mmATC_L2_CGTT_CLK_CTRL 0x080c
1181#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
1182
1183
1184// addressBlock: gc_utcl2_vml2pfdec
1185// base address: 0xa100
1186#define mmVM_L2_CNTL 0x0840
1187#define mmVM_L2_CNTL_BASE_IDX 0
1188#define mmVM_L2_CNTL2 0x0841
1189#define mmVM_L2_CNTL2_BASE_IDX 0
1190#define mmVM_L2_CNTL3 0x0842
1191#define mmVM_L2_CNTL3_BASE_IDX 0
1192#define mmVM_L2_STATUS 0x0843
1193#define mmVM_L2_STATUS_BASE_IDX 0
1194#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844
1195#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
1196#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845
1197#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
1198#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846
1199#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
1200#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847
1201#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
1202#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848
1203#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
1204#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849
1205#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
1206#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a
1207#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
1208#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b
1209#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
1210#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c
1211#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
1212#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d
1213#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
1214#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e
1215#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
1216#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f
1217#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
1218#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851
1219#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
1220#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852
1221#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
1222#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853
1223#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
1224#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854
1225#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
1226#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855
1227#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
1228#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856
1229#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
1230#define mmVM_L2_CNTL4 0x0857
1231#define mmVM_L2_CNTL4_BASE_IDX 0
1232#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858
1233#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
1234#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859
1235#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
1236#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a
1237#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
1238#define mmVM_L2_CACHE_PARITY_CNTL 0x085b
1239#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
1240#define mmVM_L2_CGTT_CLK_CTRL 0x085e
1241#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
1242
1243
1244// addressBlock: gc_utcl2_vml2vcdec
1245// base address: 0xa200
1246#define mmVM_CONTEXT0_CNTL 0x0880
1247#define mmVM_CONTEXT0_CNTL_BASE_IDX 0
1248#define mmVM_CONTEXT1_CNTL 0x0881
1249#define mmVM_CONTEXT1_CNTL_BASE_IDX 0
1250#define mmVM_CONTEXT2_CNTL 0x0882
1251#define mmVM_CONTEXT2_CNTL_BASE_IDX 0
1252#define mmVM_CONTEXT3_CNTL 0x0883
1253#define mmVM_CONTEXT3_CNTL_BASE_IDX 0
1254#define mmVM_CONTEXT4_CNTL 0x0884
1255#define mmVM_CONTEXT4_CNTL_BASE_IDX 0
1256#define mmVM_CONTEXT5_CNTL 0x0885
1257#define mmVM_CONTEXT5_CNTL_BASE_IDX 0
1258#define mmVM_CONTEXT6_CNTL 0x0886
1259#define mmVM_CONTEXT6_CNTL_BASE_IDX 0
1260#define mmVM_CONTEXT7_CNTL 0x0887
1261#define mmVM_CONTEXT7_CNTL_BASE_IDX 0
1262#define mmVM_CONTEXT8_CNTL 0x0888
1263#define mmVM_CONTEXT8_CNTL_BASE_IDX 0
1264#define mmVM_CONTEXT9_CNTL 0x0889
1265#define mmVM_CONTEXT9_CNTL_BASE_IDX 0
1266#define mmVM_CONTEXT10_CNTL 0x088a
1267#define mmVM_CONTEXT10_CNTL_BASE_IDX 0
1268#define mmVM_CONTEXT11_CNTL 0x088b
1269#define mmVM_CONTEXT11_CNTL_BASE_IDX 0
1270#define mmVM_CONTEXT12_CNTL 0x088c
1271#define mmVM_CONTEXT12_CNTL_BASE_IDX 0
1272#define mmVM_CONTEXT13_CNTL 0x088d
1273#define mmVM_CONTEXT13_CNTL_BASE_IDX 0
1274#define mmVM_CONTEXT14_CNTL 0x088e
1275#define mmVM_CONTEXT14_CNTL_BASE_IDX 0
1276#define mmVM_CONTEXT15_CNTL 0x088f
1277#define mmVM_CONTEXT15_CNTL_BASE_IDX 0
1278#define mmVM_CONTEXTS_DISABLE 0x0890
1279#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0
1280#define mmVM_INVALIDATE_ENG0_SEM 0x0891
1281#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
1282#define mmVM_INVALIDATE_ENG1_SEM 0x0892
1283#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
1284#define mmVM_INVALIDATE_ENG2_SEM 0x0893
1285#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
1286#define mmVM_INVALIDATE_ENG3_SEM 0x0894
1287#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
1288#define mmVM_INVALIDATE_ENG4_SEM 0x0895
1289#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
1290#define mmVM_INVALIDATE_ENG5_SEM 0x0896
1291#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
1292#define mmVM_INVALIDATE_ENG6_SEM 0x0897
1293#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
1294#define mmVM_INVALIDATE_ENG7_SEM 0x0898
1295#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
1296#define mmVM_INVALIDATE_ENG8_SEM 0x0899
1297#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
1298#define mmVM_INVALIDATE_ENG9_SEM 0x089a
1299#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
1300#define mmVM_INVALIDATE_ENG10_SEM 0x089b
1301#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
1302#define mmVM_INVALIDATE_ENG11_SEM 0x089c
1303#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
1304#define mmVM_INVALIDATE_ENG12_SEM 0x089d
1305#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
1306#define mmVM_INVALIDATE_ENG13_SEM 0x089e
1307#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
1308#define mmVM_INVALIDATE_ENG14_SEM 0x089f
1309#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
1310#define mmVM_INVALIDATE_ENG15_SEM 0x08a0
1311#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
1312#define mmVM_INVALIDATE_ENG16_SEM 0x08a1
1313#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
1314#define mmVM_INVALIDATE_ENG17_SEM 0x08a2
1315#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
1316#define mmVM_INVALIDATE_ENG0_REQ 0x08a3
1317#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
1318#define mmVM_INVALIDATE_ENG1_REQ 0x08a4
1319#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
1320#define mmVM_INVALIDATE_ENG2_REQ 0x08a5
1321#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
1322#define mmVM_INVALIDATE_ENG3_REQ 0x08a6
1323#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
1324#define mmVM_INVALIDATE_ENG4_REQ 0x08a7
1325#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
1326#define mmVM_INVALIDATE_ENG5_REQ 0x08a8
1327#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
1328#define mmVM_INVALIDATE_ENG6_REQ 0x08a9
1329#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
1330#define mmVM_INVALIDATE_ENG7_REQ 0x08aa
1331#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
1332#define mmVM_INVALIDATE_ENG8_REQ 0x08ab
1333#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
1334#define mmVM_INVALIDATE_ENG9_REQ 0x08ac
1335#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
1336#define mmVM_INVALIDATE_ENG10_REQ 0x08ad
1337#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
1338#define mmVM_INVALIDATE_ENG11_REQ 0x08ae
1339#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
1340#define mmVM_INVALIDATE_ENG12_REQ 0x08af
1341#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
1342#define mmVM_INVALIDATE_ENG13_REQ 0x08b0
1343#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
1344#define mmVM_INVALIDATE_ENG14_REQ 0x08b1
1345#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
1346#define mmVM_INVALIDATE_ENG15_REQ 0x08b2
1347#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
1348#define mmVM_INVALIDATE_ENG16_REQ 0x08b3
1349#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
1350#define mmVM_INVALIDATE_ENG17_REQ 0x08b4
1351#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
1352#define mmVM_INVALIDATE_ENG0_ACK 0x08b5
1353#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
1354#define mmVM_INVALIDATE_ENG1_ACK 0x08b6
1355#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
1356#define mmVM_INVALIDATE_ENG2_ACK 0x08b7
1357#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
1358#define mmVM_INVALIDATE_ENG3_ACK 0x08b8
1359#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
1360#define mmVM_INVALIDATE_ENG4_ACK 0x08b9
1361#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
1362#define mmVM_INVALIDATE_ENG5_ACK 0x08ba
1363#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
1364#define mmVM_INVALIDATE_ENG6_ACK 0x08bb
1365#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
1366#define mmVM_INVALIDATE_ENG7_ACK 0x08bc
1367#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
1368#define mmVM_INVALIDATE_ENG8_ACK 0x08bd
1369#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
1370#define mmVM_INVALIDATE_ENG9_ACK 0x08be
1371#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
1372#define mmVM_INVALIDATE_ENG10_ACK 0x08bf
1373#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
1374#define mmVM_INVALIDATE_ENG11_ACK 0x08c0
1375#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
1376#define mmVM_INVALIDATE_ENG12_ACK 0x08c1
1377#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
1378#define mmVM_INVALIDATE_ENG13_ACK 0x08c2
1379#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
1380#define mmVM_INVALIDATE_ENG14_ACK 0x08c3
1381#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
1382#define mmVM_INVALIDATE_ENG15_ACK 0x08c4
1383#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
1384#define mmVM_INVALIDATE_ENG16_ACK 0x08c5
1385#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
1386#define mmVM_INVALIDATE_ENG17_ACK 0x08c6
1387#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
1388#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7
1389#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
1390#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8
1391#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
1392#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9
1393#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
1394#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca
1395#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
1396#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb
1397#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
1398#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc
1399#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
1400#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd
1401#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
1402#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce
1403#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
1404#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf
1405#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
1406#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0
1407#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
1408#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1
1409#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
1410#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2
1411#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
1412#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3
1413#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
1414#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4
1415#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
1416#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5
1417#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
1418#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6
1419#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
1420#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7
1421#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
1422#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8
1423#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
1424#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9
1425#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
1426#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da
1427#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
1428#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db
1429#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
1430#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc
1431#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
1432#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd
1433#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
1434#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de
1435#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
1436#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df
1437#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
1438#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0
1439#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
1440#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1
1441#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
1442#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2
1443#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
1444#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3
1445#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
1446#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4
1447#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
1448#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5
1449#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
1450#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6
1451#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
1452#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7
1453#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
1454#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8
1455#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
1456#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9
1457#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
1458#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea
1459#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
1460#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb
1461#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1462#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec
1463#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1464#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed
1465#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1466#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee
1467#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1468#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef
1469#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1470#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0
1471#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1472#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1
1473#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1474#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2
1475#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1476#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3
1477#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1478#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4
1479#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1480#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5
1481#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1482#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6
1483#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1484#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7
1485#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1486#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8
1487#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1488#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9
1489#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1490#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa
1491#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1492#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb
1493#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1494#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc
1495#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1496#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd
1497#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1498#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe
1499#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1500#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff
1501#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1502#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900
1503#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1504#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901
1505#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1506#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902
1507#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1508#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903
1509#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1510#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904
1511#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1512#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905
1513#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1514#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906
1515#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1516#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907
1517#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1518#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908
1519#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1520#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909
1521#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1522#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a
1523#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1524#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b
1525#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1526#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c
1527#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1528#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d
1529#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1530#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e
1531#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1532#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f
1533#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1534#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910
1535#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1536#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911
1537#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1538#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912
1539#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1540#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913
1541#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1542#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914
1543#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1544#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915
1545#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1546#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916
1547#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1548#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917
1549#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1550#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918
1551#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1552#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919
1553#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1554#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a
1555#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1556#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b
1557#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1558#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c
1559#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1560#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d
1561#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1562#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e
1563#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1564#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f
1565#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1566#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920
1567#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1568#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921
1569#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1570#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922
1571#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1572#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923
1573#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1574#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924
1575#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1576#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925
1577#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1578#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926
1579#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1580#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927
1581#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1582#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928
1583#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1584#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929
1585#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1586#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a
1587#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1588#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b
1589#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1590#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c
1591#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1592#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d
1593#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1594#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e
1595#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1596#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f
1597#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1598#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930
1599#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1600#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931
1601#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1602#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932
1603#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1604#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933
1605#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1606#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934
1607#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1608#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935
1609#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1610#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936
1611#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1612#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937
1613#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1614#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938
1615#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1616#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939
1617#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1618#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a
1619#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1620#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b
1621#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1622#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c
1623#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1624#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d
1625#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1626#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e
1627#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1628#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f
1629#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1630#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940
1631#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1632#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941
1633#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1634#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942
1635#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1636#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943
1637#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1638#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944
1639#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1640#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945
1641#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1642#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946
1643#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1644#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947
1645#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1646#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948
1647#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1648#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949
1649#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1650#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a
1651#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1652
1653
1654// addressBlock: gc_utcl2_vmsharedpfdec
1655// base address: 0xa590
1656#define mmMC_VM_NB_MMIOBASE 0x0964
1657#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0
1658#define mmMC_VM_NB_MMIOLIMIT 0x0965
1659#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0
1660#define mmMC_VM_NB_PCI_CTRL 0x0966
1661#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0
1662#define mmMC_VM_NB_PCI_ARB 0x0967
1663#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0
1664#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968
1665#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
1666#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969
1667#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
1668#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a
1669#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
1670#define mmMC_VM_FB_OFFSET 0x096b
1671#define mmMC_VM_FB_OFFSET_BASE_IDX 0
1672#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c
1673#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
1674#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d
1675#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
1676#define mmMC_VM_STEERING 0x096e
1677#define mmMC_VM_STEERING_BASE_IDX 0
1678#define mmMC_SHARED_VIRT_RESET_REQ 0x096f
1679#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
1680#define mmMC_MEM_POWER_LS 0x0970
1681#define mmMC_MEM_POWER_LS_BASE_IDX 0
1682#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971
1683#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
1684#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972
1685#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
1686#define mmMC_VM_APT_CNTL 0x0973
1687#define mmMC_VM_APT_CNTL_BASE_IDX 0
1688#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974
1689#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
1690#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975
1691#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
1692#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976
1693#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
1694
1695
1696// addressBlock: gc_utcl2_vmsharedvcdec
1697// base address: 0xa600
1698#define mmMC_VM_FB_LOCATION_BASE 0x0980
1699#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0
1700#define mmMC_VM_FB_LOCATION_TOP 0x0981
1701#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0
1702#define mmMC_VM_AGP_TOP 0x0982
1703#define mmMC_VM_AGP_TOP_BASE_IDX 0
1704#define mmMC_VM_AGP_BOT 0x0983
1705#define mmMC_VM_AGP_BOT_BASE_IDX 0
1706#define mmMC_VM_AGP_BASE 0x0984
1707#define mmMC_VM_AGP_BASE_BASE_IDX 0
1708#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985
1709#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
1710#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986
1711#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
1712#define mmMC_VM_MX_L1_TLB_CNTL 0x0987
1713#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
1714
1715
1716// addressBlock: gc_ea_gceadec
1717// base address: 0xa800
1718#define mmGCEA_DRAM_RD_CLI2GRP_MAP0 0x0a00
1719#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0
1720#define mmGCEA_DRAM_RD_CLI2GRP_MAP1 0x0a01
1721#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0
1722#define mmGCEA_DRAM_WR_CLI2GRP_MAP0 0x0a02
1723#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0
1724#define mmGCEA_DRAM_WR_CLI2GRP_MAP1 0x0a03
1725#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0
1726#define mmGCEA_DRAM_RD_GRP2VC_MAP 0x0a04
1727#define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0
1728#define mmGCEA_DRAM_WR_GRP2VC_MAP 0x0a05
1729#define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0
1730#define mmGCEA_DRAM_RD_LAZY 0x0a06
1731#define mmGCEA_DRAM_RD_LAZY_BASE_IDX 0
1732#define mmGCEA_DRAM_WR_LAZY 0x0a07
1733#define mmGCEA_DRAM_WR_LAZY_BASE_IDX 0
1734#define mmGCEA_DRAM_RD_CAM_CNTL 0x0a08
1735#define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0
1736#define mmGCEA_DRAM_WR_CAM_CNTL 0x0a09
1737#define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0
1738#define mmGCEA_DRAM_PAGE_BURST 0x0a0a
1739#define mmGCEA_DRAM_PAGE_BURST_BASE_IDX 0
1740#define mmGCEA_DRAM_RD_PRI_AGE 0x0a0b
1741#define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0
1742#define mmGCEA_DRAM_WR_PRI_AGE 0x0a0c
1743#define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0
1744#define mmGCEA_DRAM_RD_PRI_QUEUING 0x0a0d
1745#define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0
1746#define mmGCEA_DRAM_WR_PRI_QUEUING 0x0a0e
1747#define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0
1748#define mmGCEA_DRAM_RD_PRI_FIXED 0x0a0f
1749#define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0
1750#define mmGCEA_DRAM_WR_PRI_FIXED 0x0a10
1751#define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0
1752#define mmGCEA_DRAM_RD_PRI_URGENCY 0x0a11
1753#define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0
1754#define mmGCEA_DRAM_WR_PRI_URGENCY 0x0a12
1755#define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0
1756#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0x0a13
1757#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0
1758#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0x0a14
1759#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0
1760#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0x0a15
1761#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0
1762#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0x0a16
1763#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0
1764#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0x0a17
1765#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0
1766#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0x0a18
1767#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0
1768#define mmGCEA_ADDRNORM_BASE_ADDR0 0x0a32
1769#define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0
1770#define mmGCEA_ADDRNORM_LIMIT_ADDR0 0x0a33
1771#define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0
1772#define mmGCEA_ADDRNORM_BASE_ADDR1 0x0a34
1773#define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0
1774#define mmGCEA_ADDRNORM_LIMIT_ADDR1 0x0a35
1775#define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0
1776#define mmGCEA_ADDRNORM_OFFSET_ADDR1 0x0a36
1777#define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0
1778#define mmGCEA_ADDRNORM_HOLE_CNTL 0x0a41
1779#define mmGCEA_ADDRNORM_HOLE_CNTL_BASE_IDX 0
1780#define mmGCEA_ADDRDEC_BANK_CFG 0x0a42
1781#define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0
1782#define mmGCEA_ADDRDEC_MISC_CFG 0x0a43
1783#define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0
1784#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0 0x0a44
1785#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0
1786#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1 0x0a45
1787#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0
1788#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2 0x0a46
1789#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0
1790#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3 0x0a47
1791#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0
1792#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4 0x0a48
1793#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0
1794#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC 0x0a49
1795#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0
1796#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2 0x0a4a
1797#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0
1798#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0 0x0a4b
1799#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0
1800#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1 0x0a4c
1801#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0
1802#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE 0x0a4d
1803#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0
1804#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0 0x0a58
1805#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0
1806#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1 0x0a59
1807#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0
1808#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2 0x0a5a
1809#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0
1810#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3 0x0a5b
1811#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0
1812#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0x0a5c
1813#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0
1814#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0x0a5d
1815#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0
1816#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0x0a5e
1817#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0
1818#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0x0a5f
1819#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0
1820#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01 0x0a60
1821#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0
1822#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23 0x0a61
1823#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0
1824#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0x0a62
1825#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0
1826#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0x0a63
1827#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0
1828#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01 0x0a64
1829#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0
1830#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23 0x0a65
1831#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0
1832#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01 0x0a66
1833#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0
1834#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23 0x0a67
1835#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0
1836#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01 0x0a68
1837#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0
1838#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23 0x0a69
1839#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0
1840#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01 0x0a6a
1841#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0
1842#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23 0x0a6b
1843#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0
1844#define mmGCEA_ADDRDEC0_RM_SEL_CS01 0x0a6c
1845#define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0
1846#define mmGCEA_ADDRDEC0_RM_SEL_CS23 0x0a6d
1847#define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0
1848#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01 0x0a6e
1849#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0
1850#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23 0x0a6f
1851#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0
1852#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0 0x0a70
1853#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0
1854#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1 0x0a71
1855#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0
1856#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2 0x0a72
1857#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0
1858#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3 0x0a73
1859#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0
1860#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0x0a74
1861#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0
1862#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0x0a75
1863#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0
1864#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0x0a76
1865#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0
1866#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0x0a77
1867#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0
1868#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01 0x0a78
1869#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0
1870#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23 0x0a79
1871#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0
1872#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0x0a7a
1873#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0
1874#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0x0a7b
1875#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0
1876#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01 0x0a7c
1877#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0
1878#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23 0x0a7d
1879#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0
1880#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01 0x0a7e
1881#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0
1882#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23 0x0a7f
1883#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0
1884#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01 0x0a80
1885#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0
1886#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23 0x0a81
1887#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0
1888#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01 0x0a82
1889#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0
1890#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23 0x0a83
1891#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0
1892#define mmGCEA_ADDRDEC1_RM_SEL_CS01 0x0a84
1893#define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0
1894#define mmGCEA_ADDRDEC1_RM_SEL_CS23 0x0a85
1895#define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0
1896#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01 0x0a86
1897#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0
1898#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23 0x0a87
1899#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0
1900#define mmGCEA_IO_RD_CLI2GRP_MAP0 0x0ad0
1901#define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0
1902#define mmGCEA_IO_RD_CLI2GRP_MAP1 0x0ad1
1903#define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0
1904#define mmGCEA_IO_WR_CLI2GRP_MAP0 0x0ad2
1905#define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0
1906#define mmGCEA_IO_WR_CLI2GRP_MAP1 0x0ad3
1907#define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0
1908#define mmGCEA_IO_RD_COMBINE_FLUSH 0x0ad4
1909#define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0
1910#define mmGCEA_IO_WR_COMBINE_FLUSH 0x0ad5
1911#define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0
1912#define mmGCEA_IO_GROUP_BURST 0x0ad6
1913#define mmGCEA_IO_GROUP_BURST_BASE_IDX 0
1914#define mmGCEA_IO_RD_PRI_AGE 0x0ad7
1915#define mmGCEA_IO_RD_PRI_AGE_BASE_IDX 0
1916#define mmGCEA_IO_WR_PRI_AGE 0x0ad8
1917#define mmGCEA_IO_WR_PRI_AGE_BASE_IDX 0
1918#define mmGCEA_IO_RD_PRI_QUEUING 0x0ad9
1919#define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0
1920#define mmGCEA_IO_WR_PRI_QUEUING 0x0ada
1921#define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0
1922#define mmGCEA_IO_RD_PRI_FIXED 0x0adb
1923#define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX 0
1924#define mmGCEA_IO_WR_PRI_FIXED 0x0adc
1925#define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX 0
1926#define mmGCEA_IO_RD_PRI_URGENCY 0x0add
1927#define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0
1928#define mmGCEA_IO_WR_PRI_URGENCY 0x0ade
1929#define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0
1930#define mmGCEA_IO_RD_PRI_URGENCY_MASK 0x0adf
1931#define mmGCEA_IO_RD_PRI_URGENCY_MASK_BASE_IDX 0
1932#define mmGCEA_IO_WR_PRI_URGENCY_MASK 0x0ae0
1933#define mmGCEA_IO_WR_PRI_URGENCY_MASK_BASE_IDX 0
1934#define mmGCEA_IO_RD_PRI_QUANT_PRI1 0x0ae1
1935#define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0
1936#define mmGCEA_IO_RD_PRI_QUANT_PRI2 0x0ae2
1937#define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0
1938#define mmGCEA_IO_RD_PRI_QUANT_PRI3 0x0ae3
1939#define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0
1940#define mmGCEA_IO_WR_PRI_QUANT_PRI1 0x0ae4
1941#define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0
1942#define mmGCEA_IO_WR_PRI_QUANT_PRI2 0x0ae5
1943#define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0
1944#define mmGCEA_IO_WR_PRI_QUANT_PRI3 0x0ae6
1945#define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0
1946#define mmGCEA_SDP_ARB_DRAM 0x0ae7
1947#define mmGCEA_SDP_ARB_DRAM_BASE_IDX 0
1948#define mmGCEA_SDP_ARB_FINAL 0x0ae9
1949#define mmGCEA_SDP_ARB_FINAL_BASE_IDX 0
1950#define mmGCEA_SDP_DRAM_PRIORITY 0x0aea
1951#define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX 0
1952#define mmGCEA_SDP_IO_PRIORITY 0x0aec
1953#define mmGCEA_SDP_IO_PRIORITY_BASE_IDX 0
1954#define mmGCEA_SDP_CREDITS 0x0aed
1955#define mmGCEA_SDP_CREDITS_BASE_IDX 0
1956#define mmGCEA_SDP_TAG_RESERVE0 0x0aee
1957#define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX 0
1958#define mmGCEA_SDP_TAG_RESERVE1 0x0aef
1959#define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX 0
1960#define mmGCEA_SDP_VCC_RESERVE0 0x0af0
1961#define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX 0
1962#define mmGCEA_SDP_VCC_RESERVE1 0x0af1
1963#define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX 0
1964#define mmGCEA_SDP_VCD_RESERVE0 0x0af2
1965#define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX 0
1966#define mmGCEA_SDP_VCD_RESERVE1 0x0af3
1967#define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX 0
1968#define mmGCEA_SDP_REQ_CNTL 0x0af4
1969#define mmGCEA_SDP_REQ_CNTL_BASE_IDX 0
1970#define mmGCEA_MISC 0x0af5
1971#define mmGCEA_MISC_BASE_IDX 0
1972#define mmGCEA_LATENCY_SAMPLING 0x0af6
1973#define mmGCEA_LATENCY_SAMPLING_BASE_IDX 0
1974#define mmGCEA_PERFCOUNTER_LO 0x0af7
1975#define mmGCEA_PERFCOUNTER_LO_BASE_IDX 0
1976#define mmGCEA_PERFCOUNTER_HI 0x0af8
1977#define mmGCEA_PERFCOUNTER_HI_BASE_IDX 0
1978#define mmGCEA_PERFCOUNTER0_CFG 0x0af9
1979#define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX 0
1980#define mmGCEA_PERFCOUNTER1_CFG 0x0afa
1981#define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX 0
1982#define mmGCEA_PERFCOUNTER_RSLT_CNTL 0x0afb
1983#define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
1984
1985
1986// addressBlock: gc_tcdec
1987// base address: 0xac00
1988#define mmTCP_INVALIDATE 0x0b00
1989#define mmTCP_INVALIDATE_BASE_IDX 0
1990#define mmTCP_STATUS 0x0b01
1991#define mmTCP_STATUS_BASE_IDX 0
1992#define mmTCP_CNTL 0x0b02
1993#define mmTCP_CNTL_BASE_IDX 0
1994#define mmTCP_CHAN_STEER_LO 0x0b03
1995#define mmTCP_CHAN_STEER_LO_BASE_IDX 0
1996#define mmTCP_CHAN_STEER_HI 0x0b04
1997#define mmTCP_CHAN_STEER_HI_BASE_IDX 0
1998#define mmTCP_ADDR_CONFIG 0x0b05
1999#define mmTCP_ADDR_CONFIG_BASE_IDX 0
2000#define mmTCP_CREDIT 0x0b06
2001#define mmTCP_CREDIT_BASE_IDX 0
2002#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16
2003#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0
2004#define mmTCP_EDC_CNT 0x0b17
2005#define mmTCP_EDC_CNT_BASE_IDX 0
2006#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a
2007#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0
2008#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b
2009#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0
2010#define mmTC_CFG_L1_STORE_POLICY 0x0b1c
2011#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0
2012#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d
2013#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0
2014#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e
2015#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0
2016#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f
2017#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0
2018#define mmTC_CFG_L2_STORE_POLICY1 0x0b20
2019#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0
2020#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21
2021#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0
2022#define mmTC_CFG_L1_VOLATILE 0x0b22
2023#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0
2024#define mmTC_CFG_L2_VOLATILE 0x0b23
2025#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0
2026#define mmTCI_STATUS 0x0b61
2027#define mmTCI_STATUS_BASE_IDX 0
2028#define mmTCI_CNTL_1 0x0b62
2029#define mmTCI_CNTL_1_BASE_IDX 0
2030#define mmTCI_CNTL_2 0x0b63
2031#define mmTCI_CNTL_2_BASE_IDX 0
2032#define mmTCC_CTRL 0x0b80
2033#define mmTCC_CTRL_BASE_IDX 0
2034#define mmTCC_CTRL2 0x0b81
2035#define mmTCC_CTRL2_BASE_IDX 0
2036#define mmTCC_EDC_CNT 0x0b82
2037#define mmTCC_EDC_CNT_BASE_IDX 0
2038#define mmTCC_EDC_CNT2 0x0b83
2039#define mmTCC_EDC_CNT2_BASE_IDX 0
2040#define mmTCC_REDUNDANCY 0x0b84
2041#define mmTCC_REDUNDANCY_BASE_IDX 0
2042#define mmTCC_EXE_DISABLE 0x0b85
2043#define mmTCC_EXE_DISABLE_BASE_IDX 0
2044#define mmTCC_DSM_CNTL 0x0b86
2045#define mmTCC_DSM_CNTL_BASE_IDX 0
2046#define mmTCC_DSM_CNTLA 0x0b87
2047#define mmTCC_DSM_CNTLA_BASE_IDX 0
2048#define mmTCC_DSM_CNTL2 0x0b88
2049#define mmTCC_DSM_CNTL2_BASE_IDX 0
2050#define mmTCC_DSM_CNTL2A 0x0b89
2051#define mmTCC_DSM_CNTL2A_BASE_IDX 0
2052#define mmTCC_DSM_CNTL2B 0x0b8a
2053#define mmTCC_DSM_CNTL2B_BASE_IDX 0
2054#define mmTCC_WBINVL2 0x0b8b
2055#define mmTCC_WBINVL2_BASE_IDX 0
2056#define mmTCC_SOFT_RESET 0x0b8c
2057#define mmTCC_SOFT_RESET_BASE_IDX 0
2058#define mmTCA_CTRL 0x0bc0
2059#define mmTCA_CTRL_BASE_IDX 0
2060#define mmTCA_BURST_MASK 0x0bc1
2061#define mmTCA_BURST_MASK_BASE_IDX 0
2062#define mmTCA_BURST_CTRL 0x0bc2
2063#define mmTCA_BURST_CTRL_BASE_IDX 0
2064#define mmTCA_DSM_CNTL 0x0bc3
2065#define mmTCA_DSM_CNTL_BASE_IDX 0
2066#define mmTCA_DSM_CNTL2 0x0bc4
2067#define mmTCA_DSM_CNTL2_BASE_IDX 0
2068#define mmTCA_EDC_CNT 0x0bc5
2069#define mmTCA_EDC_CNT_BASE_IDX 0
2070
2071
2072// addressBlock: gc_shdec
2073// base address: 0xb000
2074#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07
2075#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0
2076#define mmSPI_SHADER_PGM_LO_PS 0x0c08
2077#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0
2078#define mmSPI_SHADER_PGM_HI_PS 0x0c09
2079#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0
2080#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a
2081#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0
2082#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b
2083#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0
2084#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c
2085#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0
2086#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d
2087#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0
2088#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e
2089#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0
2090#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f
2091#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0
2092#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10
2093#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0
2094#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11
2095#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0
2096#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12
2097#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0
2098#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13
2099#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0
2100#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14
2101#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0
2102#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15
2103#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0
2104#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16
2105#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0
2106#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17
2107#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0
2108#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18
2109#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0
2110#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19
2111#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0
2112#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a
2113#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0
2114#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b
2115#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0
2116#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c
2117#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0
2118#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d
2119#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0
2120#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e
2121#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0
2122#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f
2123#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0
2124#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20
2125#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0
2126#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21
2127#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0
2128#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22
2129#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0
2130#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23
2131#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0
2132#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24
2133#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0
2134#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25
2135#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0
2136#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26
2137#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0
2138#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27
2139#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0
2140#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28
2141#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0
2142#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29
2143#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0
2144#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a
2145#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0
2146#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b
2147#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0
2148#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46
2149#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0
2150#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47
2151#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0
2152#define mmSPI_SHADER_PGM_LO_VS 0x0c48
2153#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0
2154#define mmSPI_SHADER_PGM_HI_VS 0x0c49
2155#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0
2156#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a
2157#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0
2158#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b
2159#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0
2160#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c
2161#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0
2162#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d
2163#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0
2164#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e
2165#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0
2166#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f
2167#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0
2168#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50
2169#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0
2170#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51
2171#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0
2172#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52
2173#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0
2174#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53
2175#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0
2176#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54
2177#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0
2178#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55
2179#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0
2180#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56
2181#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0
2182#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57
2183#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0
2184#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58
2185#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0
2186#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59
2187#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0
2188#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a
2189#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0
2190#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b
2191#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0
2192#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c
2193#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0
2194#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d
2195#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0
2196#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e
2197#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0
2198#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f
2199#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0
2200#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60
2201#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0
2202#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61
2203#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0
2204#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62
2205#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0
2206#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63
2207#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0
2208#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64
2209#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0
2210#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65
2211#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0
2212#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66
2213#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0
2214#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67
2215#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0
2216#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68
2217#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0
2218#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69
2219#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0
2220#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a
2221#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0
2222#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b
2223#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0
2224#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c
2225#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0
2226#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81
2227#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0
2228#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82
2229#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0
2230#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83
2231#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0
2232#define mmSPI_SHADER_PGM_LO_ES 0x0c84
2233#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0
2234#define mmSPI_SHADER_PGM_HI_ES 0x0c85
2235#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0
2236#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87
2237#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0
2238#define mmSPI_SHADER_PGM_LO_GS 0x0c88
2239#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0
2240#define mmSPI_SHADER_PGM_HI_GS 0x0c89
2241#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0
2242#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a
2243#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0
2244#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b
2245#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0
2246#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc
2247#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0
2248#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd
2249#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0
2250#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce
2251#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0
2252#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf
2253#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0
2254#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0
2255#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0
2256#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1
2257#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0
2258#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2
2259#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0
2260#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3
2261#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0
2262#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4
2263#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0
2264#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5
2265#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0
2266#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6
2267#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0
2268#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7
2269#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0
2270#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8
2271#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0
2272#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9
2273#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0
2274#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda
2275#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0
2276#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb
2277#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0
2278#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc
2279#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0
2280#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd
2281#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0
2282#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde
2283#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0
2284#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf
2285#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0
2286#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0
2287#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0
2288#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1
2289#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0
2290#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2
2291#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0
2292#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3
2293#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0
2294#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4
2295#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0
2296#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5
2297#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0
2298#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6
2299#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0
2300#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7
2301#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0
2302#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8
2303#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0
2304#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9
2305#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0
2306#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea
2307#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0
2308#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb
2309#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0
2310#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01
2311#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0
2312#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02
2313#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0
2314#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03
2315#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0
2316#define mmSPI_SHADER_PGM_LO_LS 0x0d04
2317#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0
2318#define mmSPI_SHADER_PGM_HI_LS 0x0d05
2319#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0
2320#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07
2321#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0
2322#define mmSPI_SHADER_PGM_LO_HS 0x0d08
2323#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0
2324#define mmSPI_SHADER_PGM_HI_HS 0x0d09
2325#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0
2326#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a
2327#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0
2328#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b
2329#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0
2330#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c
2331#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0
2332#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d
2333#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0
2334#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e
2335#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0
2336#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f
2337#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0
2338#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10
2339#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0
2340#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11
2341#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0
2342#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12
2343#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0
2344#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13
2345#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0
2346#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14
2347#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0
2348#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15
2349#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0
2350#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16
2351#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0
2352#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17
2353#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0
2354#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18
2355#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0
2356#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19
2357#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0
2358#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a
2359#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0
2360#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b
2361#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0
2362#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c
2363#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0
2364#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d
2365#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0
2366#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e
2367#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0
2368#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f
2369#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0
2370#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20
2371#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0
2372#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21
2373#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0
2374#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22
2375#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0
2376#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23
2377#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0
2378#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24
2379#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0
2380#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25
2381#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0
2382#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26
2383#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0
2384#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27
2385#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0
2386#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28
2387#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0
2388#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29
2389#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0
2390#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a
2391#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0
2392#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b
2393#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0
2394#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c
2395#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0
2396#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d
2397#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0
2398#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e
2399#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0
2400#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f
2401#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0
2402#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50
2403#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0
2404#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51
2405#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0
2406#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52
2407#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0
2408#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53
2409#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0
2410#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54
2411#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0
2412#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55
2413#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0
2414#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56
2415#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0
2416#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57
2417#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0
2418#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58
2419#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0
2420#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59
2421#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0
2422#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a
2423#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0
2424#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b
2425#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0
2426#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c
2427#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0
2428#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d
2429#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0
2430#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e
2431#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0
2432#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f
2433#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0
2434#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60
2435#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0
2436#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61
2437#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0
2438#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62
2439#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0
2440#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63
2441#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0
2442#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64
2443#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0
2444#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65
2445#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0
2446#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66
2447#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0
2448#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67
2449#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0
2450#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68
2451#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0
2452#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69
2453#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0
2454#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a
2455#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0
2456#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b
2457#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0
2458#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00
2459#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0
2460#define mmCOMPUTE_DIM_X 0x0e01
2461#define mmCOMPUTE_DIM_X_BASE_IDX 0
2462#define mmCOMPUTE_DIM_Y 0x0e02
2463#define mmCOMPUTE_DIM_Y_BASE_IDX 0
2464#define mmCOMPUTE_DIM_Z 0x0e03
2465#define mmCOMPUTE_DIM_Z_BASE_IDX 0
2466#define mmCOMPUTE_START_X 0x0e04
2467#define mmCOMPUTE_START_X_BASE_IDX 0
2468#define mmCOMPUTE_START_Y 0x0e05
2469#define mmCOMPUTE_START_Y_BASE_IDX 0
2470#define mmCOMPUTE_START_Z 0x0e06
2471#define mmCOMPUTE_START_Z_BASE_IDX 0
2472#define mmCOMPUTE_NUM_THREAD_X 0x0e07
2473#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0
2474#define mmCOMPUTE_NUM_THREAD_Y 0x0e08
2475#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0
2476#define mmCOMPUTE_NUM_THREAD_Z 0x0e09
2477#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0
2478#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a
2479#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0
2480#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b
2481#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0
2482#define mmCOMPUTE_PGM_LO 0x0e0c
2483#define mmCOMPUTE_PGM_LO_BASE_IDX 0
2484#define mmCOMPUTE_PGM_HI 0x0e0d
2485#define mmCOMPUTE_PGM_HI_BASE_IDX 0
2486#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e
2487#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0
2488#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f
2489#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0
2490#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10
2491#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0
2492#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11
2493#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0
2494#define mmCOMPUTE_PGM_RSRC1 0x0e12
2495#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0
2496#define mmCOMPUTE_PGM_RSRC2 0x0e13
2497#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0
2498#define mmCOMPUTE_VMID 0x0e14
2499#define mmCOMPUTE_VMID_BASE_IDX 0
2500#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15
2501#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0
2502#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16
2503#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0
2504#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17
2505#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0
2506#define mmCOMPUTE_TMPRING_SIZE 0x0e18
2507#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0
2508#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19
2509#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
2510#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a
2511#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
2512#define mmCOMPUTE_RESTART_X 0x0e1b
2513#define mmCOMPUTE_RESTART_X_BASE_IDX 0
2514#define mmCOMPUTE_RESTART_Y 0x0e1c
2515#define mmCOMPUTE_RESTART_Y_BASE_IDX 0
2516#define mmCOMPUTE_RESTART_Z 0x0e1d
2517#define mmCOMPUTE_RESTART_Z_BASE_IDX 0
2518#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e
2519#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0
2520#define mmCOMPUTE_MISC_RESERVED 0x0e1f
2521#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0
2522#define mmCOMPUTE_DISPATCH_ID 0x0e20
2523#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0
2524#define mmCOMPUTE_THREADGROUP_ID 0x0e21
2525#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0
2526#define mmCOMPUTE_RELAUNCH 0x0e22
2527#define mmCOMPUTE_RELAUNCH_BASE_IDX 0
2528#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23
2529#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0
2530#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24
2531#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0
2532#define mmCOMPUTE_USER_DATA_0 0x0e40
2533#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0
2534#define mmCOMPUTE_USER_DATA_1 0x0e41
2535#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0
2536#define mmCOMPUTE_USER_DATA_2 0x0e42
2537#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0
2538#define mmCOMPUTE_USER_DATA_3 0x0e43
2539#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0
2540#define mmCOMPUTE_USER_DATA_4 0x0e44
2541#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0
2542#define mmCOMPUTE_USER_DATA_5 0x0e45
2543#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0
2544#define mmCOMPUTE_USER_DATA_6 0x0e46
2545#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0
2546#define mmCOMPUTE_USER_DATA_7 0x0e47
2547#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0
2548#define mmCOMPUTE_USER_DATA_8 0x0e48
2549#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0
2550#define mmCOMPUTE_USER_DATA_9 0x0e49
2551#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0
2552#define mmCOMPUTE_USER_DATA_10 0x0e4a
2553#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0
2554#define mmCOMPUTE_USER_DATA_11 0x0e4b
2555#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0
2556#define mmCOMPUTE_USER_DATA_12 0x0e4c
2557#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0
2558#define mmCOMPUTE_USER_DATA_13 0x0e4d
2559#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0
2560#define mmCOMPUTE_USER_DATA_14 0x0e4e
2561#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0
2562#define mmCOMPUTE_USER_DATA_15 0x0e4f
2563#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0
2564#define mmCOMPUTE_NOWHERE 0x0e7f
2565#define mmCOMPUTE_NOWHERE_BASE_IDX 0
2566
2567
2568// addressBlock: gc_cppdec
2569// base address: 0xc080
2570#define mmCP_DFY_CNTL 0x1020
2571#define mmCP_DFY_CNTL_BASE_IDX 0
2572#define mmCP_DFY_STAT 0x1021
2573#define mmCP_DFY_STAT_BASE_IDX 0
2574#define mmCP_DFY_ADDR_HI 0x1022
2575#define mmCP_DFY_ADDR_HI_BASE_IDX 0
2576#define mmCP_DFY_ADDR_LO 0x1023
2577#define mmCP_DFY_ADDR_LO_BASE_IDX 0
2578#define mmCP_DFY_DATA_0 0x1024
2579#define mmCP_DFY_DATA_0_BASE_IDX 0
2580#define mmCP_DFY_DATA_1 0x1025
2581#define mmCP_DFY_DATA_1_BASE_IDX 0
2582#define mmCP_DFY_DATA_2 0x1026
2583#define mmCP_DFY_DATA_2_BASE_IDX 0
2584#define mmCP_DFY_DATA_3 0x1027
2585#define mmCP_DFY_DATA_3_BASE_IDX 0
2586#define mmCP_DFY_DATA_4 0x1028
2587#define mmCP_DFY_DATA_4_BASE_IDX 0
2588#define mmCP_DFY_DATA_5 0x1029
2589#define mmCP_DFY_DATA_5_BASE_IDX 0
2590#define mmCP_DFY_DATA_6 0x102a
2591#define mmCP_DFY_DATA_6_BASE_IDX 0
2592#define mmCP_DFY_DATA_7 0x102b
2593#define mmCP_DFY_DATA_7_BASE_IDX 0
2594#define mmCP_DFY_DATA_8 0x102c
2595#define mmCP_DFY_DATA_8_BASE_IDX 0
2596#define mmCP_DFY_DATA_9 0x102d
2597#define mmCP_DFY_DATA_9_BASE_IDX 0
2598#define mmCP_DFY_DATA_10 0x102e
2599#define mmCP_DFY_DATA_10_BASE_IDX 0
2600#define mmCP_DFY_DATA_11 0x102f
2601#define mmCP_DFY_DATA_11_BASE_IDX 0
2602#define mmCP_DFY_DATA_12 0x1030
2603#define mmCP_DFY_DATA_12_BASE_IDX 0
2604#define mmCP_DFY_DATA_13 0x1031
2605#define mmCP_DFY_DATA_13_BASE_IDX 0
2606#define mmCP_DFY_DATA_14 0x1032
2607#define mmCP_DFY_DATA_14_BASE_IDX 0
2608#define mmCP_DFY_DATA_15 0x1033
2609#define mmCP_DFY_DATA_15_BASE_IDX 0
2610#define mmCP_DFY_CMD 0x1034
2611#define mmCP_DFY_CMD_BASE_IDX 0
2612#define mmCP_EOPQ_WAIT_TIME 0x1035
2613#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0
2614#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036
2615#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0
2616#define mmCPC_INT_INFO 0x1037
2617#define mmCPC_INT_INFO_BASE_IDX 0
2618#define mmCP_VIRT_STATUS 0x1038
2619#define mmCP_VIRT_STATUS_BASE_IDX 0
2620#define mmCPC_INT_ADDR 0x1039
2621#define mmCPC_INT_ADDR_BASE_IDX 0
2622#define mmCPC_INT_PASID 0x103a
2623#define mmCPC_INT_PASID_BASE_IDX 0
2624#define mmCP_GFX_ERROR 0x103b
2625#define mmCP_GFX_ERROR_BASE_IDX 0
2626#define mmCPG_UTCL1_CNTL 0x103c
2627#define mmCPG_UTCL1_CNTL_BASE_IDX 0
2628#define mmCPC_UTCL1_CNTL 0x103d
2629#define mmCPC_UTCL1_CNTL_BASE_IDX 0
2630#define mmCPF_UTCL1_CNTL 0x103e
2631#define mmCPF_UTCL1_CNTL_BASE_IDX 0
2632#define mmCP_AQL_SMM_STATUS 0x103f
2633#define mmCP_AQL_SMM_STATUS_BASE_IDX 0
2634#define mmCP_RB0_BASE 0x1040
2635#define mmCP_RB0_BASE_BASE_IDX 0
2636#define mmCP_RB_BASE 0x1040
2637#define mmCP_RB_BASE_BASE_IDX 0
2638#define mmCP_RB0_CNTL 0x1041
2639#define mmCP_RB0_CNTL_BASE_IDX 0
2640#define mmCP_RB_CNTL 0x1041
2641#define mmCP_RB_CNTL_BASE_IDX 0
2642#define mmCP_RB_RPTR_WR 0x1042
2643#define mmCP_RB_RPTR_WR_BASE_IDX 0
2644#define mmCP_RB0_RPTR_ADDR 0x1043
2645#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0
2646#define mmCP_RB_RPTR_ADDR 0x1043
2647#define mmCP_RB_RPTR_ADDR_BASE_IDX 0
2648#define mmCP_RB0_RPTR_ADDR_HI 0x1044
2649#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0
2650#define mmCP_RB_RPTR_ADDR_HI 0x1044
2651#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0
2652#define mmCP_RB0_BUFSZ_MASK 0x1045
2653#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0
2654#define mmCP_RB_BUFSZ_MASK 0x1045
2655#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0
2656#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046
2657#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
2658#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047
2659#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
2660#define mmGC_PRIV_MODE 0x1048
2661#define mmGC_PRIV_MODE_BASE_IDX 0
2662#define mmCP_INT_CNTL 0x1049
2663#define mmCP_INT_CNTL_BASE_IDX 0
2664#define mmCP_INT_STATUS 0x104a
2665#define mmCP_INT_STATUS_BASE_IDX 0
2666#define mmCP_DEVICE_ID 0x104b
2667#define mmCP_DEVICE_ID_BASE_IDX 0
2668#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c
2669#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0
2670#define mmCP_RING_PRIORITY_CNTS 0x104c
2671#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0
2672#define mmCP_ME0_PIPE0_PRIORITY 0x104d
2673#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0
2674#define mmCP_RING0_PRIORITY 0x104d
2675#define mmCP_RING0_PRIORITY_BASE_IDX 0
2676#define mmCP_ME0_PIPE1_PRIORITY 0x104e
2677#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0
2678#define mmCP_RING1_PRIORITY 0x104e
2679#define mmCP_RING1_PRIORITY_BASE_IDX 0
2680#define mmCP_ME0_PIPE2_PRIORITY 0x104f
2681#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0
2682#define mmCP_RING2_PRIORITY 0x104f
2683#define mmCP_RING2_PRIORITY_BASE_IDX 0
2684#define mmCP_FATAL_ERROR 0x1050
2685#define mmCP_FATAL_ERROR_BASE_IDX 0
2686#define mmCP_RB_VMID 0x1051
2687#define mmCP_RB_VMID_BASE_IDX 0
2688#define mmCP_ME0_PIPE0_VMID 0x1052
2689#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0
2690#define mmCP_ME0_PIPE1_VMID 0x1053
2691#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0
2692#define mmCP_RB0_WPTR 0x1054
2693#define mmCP_RB0_WPTR_BASE_IDX 0
2694#define mmCP_RB_WPTR 0x1054
2695#define mmCP_RB_WPTR_BASE_IDX 0
2696#define mmCP_RB0_WPTR_HI 0x1055
2697#define mmCP_RB0_WPTR_HI_BASE_IDX 0
2698#define mmCP_RB_WPTR_HI 0x1055
2699#define mmCP_RB_WPTR_HI_BASE_IDX 0
2700#define mmCP_RB1_WPTR 0x1056
2701#define mmCP_RB1_WPTR_BASE_IDX 0
2702#define mmCP_RB1_WPTR_HI 0x1057
2703#define mmCP_RB1_WPTR_HI_BASE_IDX 0
2704#define mmCP_RB2_WPTR 0x1058
2705#define mmCP_RB2_WPTR_BASE_IDX 0
2706#define mmCP_RB_DOORBELL_CONTROL 0x1059
2707#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0
2708#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a
2709#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0
2710#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b
2711#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0
2712#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c
2713#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0
2714#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d
2715#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0
2716#define mmCPG_UTCL1_ERROR 0x105e
2717#define mmCPG_UTCL1_ERROR_BASE_IDX 0
2718#define mmCPC_UTCL1_ERROR 0x105f
2719#define mmCPC_UTCL1_ERROR_BASE_IDX 0
2720#define mmCP_RB1_BASE 0x1060
2721#define mmCP_RB1_BASE_BASE_IDX 0
2722#define mmCP_RB1_CNTL 0x1061
2723#define mmCP_RB1_CNTL_BASE_IDX 0
2724#define mmCP_RB1_RPTR_ADDR 0x1062
2725#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0
2726#define mmCP_RB1_RPTR_ADDR_HI 0x1063
2727#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0
2728#define mmCP_RB2_BASE 0x1065
2729#define mmCP_RB2_BASE_BASE_IDX 0
2730#define mmCP_RB2_CNTL 0x1066
2731#define mmCP_RB2_CNTL_BASE_IDX 0
2732#define mmCP_RB2_RPTR_ADDR 0x1067
2733#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0
2734#define mmCP_RB2_RPTR_ADDR_HI 0x1068
2735#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0
2736#define mmCP_RB0_ACTIVE 0x1069
2737#define mmCP_RB0_ACTIVE_BASE_IDX 0
2738#define mmCP_RB_ACTIVE 0x1069
2739#define mmCP_RB_ACTIVE_BASE_IDX 0
2740#define mmCP_INT_CNTL_RING0 0x106a
2741#define mmCP_INT_CNTL_RING0_BASE_IDX 0
2742#define mmCP_INT_CNTL_RING1 0x106b
2743#define mmCP_INT_CNTL_RING1_BASE_IDX 0
2744#define mmCP_INT_CNTL_RING2 0x106c
2745#define mmCP_INT_CNTL_RING2_BASE_IDX 0
2746#define mmCP_INT_STATUS_RING0 0x106d
2747#define mmCP_INT_STATUS_RING0_BASE_IDX 0
2748#define mmCP_INT_STATUS_RING1 0x106e
2749#define mmCP_INT_STATUS_RING1_BASE_IDX 0
2750#define mmCP_INT_STATUS_RING2 0x106f
2751#define mmCP_INT_STATUS_RING2_BASE_IDX 0
2752#define mmCP_PWR_CNTL 0x1078
2753#define mmCP_PWR_CNTL_BASE_IDX 0
2754#define mmCP_MEM_SLP_CNTL 0x1079
2755#define mmCP_MEM_SLP_CNTL_BASE_IDX 0
2756#define mmCP_ECC_FIRSTOCCURRENCE 0x107a
2757#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0
2758#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b
2759#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0
2760#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c
2761#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
2762#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d
2763#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
2764#define mmGB_EDC_MODE 0x107e
2765#define mmGB_EDC_MODE_BASE_IDX 0
2766#define mmCP_PQ_WPTR_POLL_CNTL 0x1083
2767#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
2768#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084
2769#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0
2770#define mmCP_ME1_PIPE0_INT_CNTL 0x1085
2771#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0
2772#define mmCP_ME1_PIPE1_INT_CNTL 0x1086
2773#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0
2774#define mmCP_ME1_PIPE2_INT_CNTL 0x1087
2775#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0
2776#define mmCP_ME1_PIPE3_INT_CNTL 0x1088
2777#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0
2778#define mmCP_ME2_PIPE0_INT_CNTL 0x1089
2779#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0
2780#define mmCP_ME2_PIPE1_INT_CNTL 0x108a
2781#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0
2782#define mmCP_ME2_PIPE2_INT_CNTL 0x108b
2783#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0
2784#define mmCP_ME2_PIPE3_INT_CNTL 0x108c
2785#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0
2786#define mmCP_ME1_PIPE0_INT_STATUS 0x108d
2787#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0
2788#define mmCP_ME1_PIPE1_INT_STATUS 0x108e
2789#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0
2790#define mmCP_ME1_PIPE2_INT_STATUS 0x108f
2791#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0
2792#define mmCP_ME1_PIPE3_INT_STATUS 0x1090
2793#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0
2794#define mmCP_ME2_PIPE0_INT_STATUS 0x1091
2795#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0
2796#define mmCP_ME2_PIPE1_INT_STATUS 0x1092
2797#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0
2798#define mmCP_ME2_PIPE2_INT_STATUS 0x1093
2799#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0
2800#define mmCP_ME2_PIPE3_INT_STATUS 0x1094
2801#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0
2802#define mmCC_GC_EDC_CONFIG 0x1098
2803#define mmCC_GC_EDC_CONFIG_BASE_IDX 0
2804#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099
2805#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0
2806#define mmCP_ME1_PIPE0_PRIORITY 0x109a
2807#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0
2808#define mmCP_ME1_PIPE1_PRIORITY 0x109b
2809#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0
2810#define mmCP_ME1_PIPE2_PRIORITY 0x109c
2811#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0
2812#define mmCP_ME1_PIPE3_PRIORITY 0x109d
2813#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0
2814#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e
2815#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0
2816#define mmCP_ME2_PIPE0_PRIORITY 0x109f
2817#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0
2818#define mmCP_ME2_PIPE1_PRIORITY 0x10a0
2819#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0
2820#define mmCP_ME2_PIPE2_PRIORITY 0x10a1
2821#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0
2822#define mmCP_ME2_PIPE3_PRIORITY 0x10a2
2823#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0
2824#define mmCP_CE_PRGRM_CNTR_START 0x10a3
2825#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0
2826#define mmCP_PFP_PRGRM_CNTR_START 0x10a4
2827#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0
2828#define mmCP_ME_PRGRM_CNTR_START 0x10a5
2829#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0
2830#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6
2831#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0
2832#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7
2833#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0
2834#define mmCP_CE_INTR_ROUTINE_START 0x10a8
2835#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0
2836#define mmCP_PFP_INTR_ROUTINE_START 0x10a9
2837#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0
2838#define mmCP_ME_INTR_ROUTINE_START 0x10aa
2839#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0
2840#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab
2841#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0
2842#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac
2843#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0
2844#define mmCP_CONTEXT_CNTL 0x10ad
2845#define mmCP_CONTEXT_CNTL_BASE_IDX 0
2846#define mmCP_MAX_CONTEXT 0x10ae
2847#define mmCP_MAX_CONTEXT_BASE_IDX 0
2848#define mmCP_IQ_WAIT_TIME1 0x10af
2849#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0
2850#define mmCP_IQ_WAIT_TIME2 0x10b0
2851#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0
2852#define mmCP_RB0_BASE_HI 0x10b1
2853#define mmCP_RB0_BASE_HI_BASE_IDX 0
2854#define mmCP_RB1_BASE_HI 0x10b2
2855#define mmCP_RB1_BASE_HI_BASE_IDX 0
2856#define mmCP_VMID_RESET 0x10b3
2857#define mmCP_VMID_RESET_BASE_IDX 0
2858#define mmCPC_INT_CNTL 0x10b4
2859#define mmCPC_INT_CNTL_BASE_IDX 0
2860#define mmCPC_INT_STATUS 0x10b5
2861#define mmCPC_INT_STATUS_BASE_IDX 0
2862#define mmCP_VMID_PREEMPT 0x10b6
2863#define mmCP_VMID_PREEMPT_BASE_IDX 0
2864#define mmCPC_INT_CNTX_ID 0x10b7
2865#define mmCPC_INT_CNTX_ID_BASE_IDX 0
2866#define mmCP_PQ_STATUS 0x10b8
2867#define mmCP_PQ_STATUS_BASE_IDX 0
2868#define mmCP_CPC_IC_BASE_LO 0x10b9
2869#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0
2870#define mmCP_CPC_IC_BASE_HI 0x10ba
2871#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0
2872#define mmCP_CPC_IC_BASE_CNTL 0x10bb
2873#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0
2874#define mmCP_CPC_IC_OP_CNTL 0x10bc
2875#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0
2876#define mmCP_MEC1_F32_INT_DIS 0x10bd
2877#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0
2878#define mmCP_MEC2_F32_INT_DIS 0x10be
2879#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0
2880#define mmCP_VMID_STATUS 0x10bf
2881#define mmCP_VMID_STATUS_BASE_IDX 0
2882
2883
2884// addressBlock: gc_cppdec2
2885// base address: 0xc600
2886#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180
2887#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0
2888#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181
2889#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0
2890#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182
2891#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0
2892#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183
2893#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0
2894#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184
2895#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0
2896#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185
2897#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0
2898#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186
2899#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0
2900#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187
2901#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
2902#define mmCP_RB_DOORBELL_CLEAR 0x1188
2903#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
2904#define mmCP_GFX_MQD_CONTROL 0x11a0
2905#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
2906#define mmCP_GFX_MQD_BASE_ADDR 0x11a1
2907#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0
2908#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2
2909#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0
2910#define mmCP_RB_STATUS 0x11a3
2911#define mmCP_RB_STATUS_BASE_IDX 0
2912#define mmCPG_UTCL1_STATUS 0x11b4
2913#define mmCPG_UTCL1_STATUS_BASE_IDX 0
2914#define mmCPC_UTCL1_STATUS 0x11b5
2915#define mmCPC_UTCL1_STATUS_BASE_IDX 0
2916#define mmCPF_UTCL1_STATUS 0x11b6
2917#define mmCPF_UTCL1_STATUS_BASE_IDX 0
2918#define mmCP_SD_CNTL 0x11b7
2919#define mmCP_SD_CNTL_BASE_IDX 0
2920#define mmCP_SOFT_RESET_CNTL 0x11b9
2921#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0
2922#define mmCP_CPC_GFX_CNTL 0x11ba
2923#define mmCP_CPC_GFX_CNTL_BASE_IDX 0
2924
2925
2926// addressBlock: gc_spipdec
2927// base address: 0xc700
2928#define mmSPI_ARB_PRIORITY 0x11c0
2929#define mmSPI_ARB_PRIORITY_BASE_IDX 0
2930#define mmSPI_ARB_CYCLES_0 0x11c1
2931#define mmSPI_ARB_CYCLES_0_BASE_IDX 0
2932#define mmSPI_ARB_CYCLES_1 0x11c2
2933#define mmSPI_ARB_CYCLES_1_BASE_IDX 0
2934#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7
2935#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0
2936#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8
2937#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0
2938#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9
2939#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0
2940#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca
2941#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0
2942#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb
2943#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0
2944#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc
2945#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0
2946#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd
2947#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0
2948#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce
2949#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0
2950#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf
2951#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
2952#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0
2953#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
2954#define mmSPI_COMPUTE_QUEUE_RESET 0x11db
2955#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
2956#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc
2957#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0
2958#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd
2959#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0
2960#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de
2961#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0
2962#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df
2963#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0
2964#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0
2965#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0
2966#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1
2967#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0
2968#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2
2969#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0
2970#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3
2971#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0
2972#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4
2973#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0
2974#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5
2975#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0
2976#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6
2977#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0
2978#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7
2979#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0
2980#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8
2981#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0
2982#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9
2983#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0
2984#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea
2985#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0
2986#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb
2987#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0
2988#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec
2989#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0
2990#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed
2991#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0
2992#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee
2993#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0
2994#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef
2995#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
2996#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0
2997#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0
2998#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1
2999#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0
3000#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2
3001#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0
3002#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3
3003#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0
3004#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4
3005#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0
3006#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5
3007#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0
3008#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6
3009#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0
3010#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7
3011#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0
3012#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8
3013#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0
3014#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9
3015#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0
3016#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa
3017#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0
3018#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb
3019#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0
3020#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc
3021#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0
3022#define mmSPI_ARB_CNTL_0 0x11fd
3023#define mmSPI_ARB_CNTL_0_BASE_IDX 0
3024
3025
3026// addressBlock: gc_cpphqddec
3027// base address: 0xc800
3028#define mmCP_HQD_GFX_CONTROL 0x123e
3029#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0
3030#define mmCP_HQD_GFX_STATUS 0x123f
3031#define mmCP_HQD_GFX_STATUS_BASE_IDX 0
3032#define mmCP_HPD_ROQ_OFFSETS 0x1240
3033#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0
3034#define mmCP_HPD_STATUS0 0x1241
3035#define mmCP_HPD_STATUS0_BASE_IDX 0
3036#define mmCP_HPD_UTCL1_CNTL 0x1242
3037#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0
3038#define mmCP_HPD_UTCL1_ERROR 0x1243
3039#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0
3040#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244
3041#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0
3042#define mmCP_MQD_BASE_ADDR 0x1245
3043#define mmCP_MQD_BASE_ADDR_BASE_IDX 0
3044#define mmCP_MQD_BASE_ADDR_HI 0x1246
3045#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0
3046#define mmCP_HQD_ACTIVE 0x1247
3047#define mmCP_HQD_ACTIVE_BASE_IDX 0
3048#define mmCP_HQD_VMID 0x1248
3049#define mmCP_HQD_VMID_BASE_IDX 0
3050#define mmCP_HQD_PERSISTENT_STATE 0x1249
3051#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0
3052#define mmCP_HQD_PIPE_PRIORITY 0x124a
3053#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0
3054#define mmCP_HQD_QUEUE_PRIORITY 0x124b
3055#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0
3056#define mmCP_HQD_QUANTUM 0x124c
3057#define mmCP_HQD_QUANTUM_BASE_IDX 0
3058#define mmCP_HQD_PQ_BASE 0x124d
3059#define mmCP_HQD_PQ_BASE_BASE_IDX 0
3060#define mmCP_HQD_PQ_BASE_HI 0x124e
3061#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0
3062#define mmCP_HQD_PQ_RPTR 0x124f
3063#define mmCP_HQD_PQ_RPTR_BASE_IDX 0
3064#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
3065#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0
3066#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
3067#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0
3068#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
3069#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0
3070#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
3071#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0
3072#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254
3073#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0
3074#define mmCP_HQD_PQ_CONTROL 0x1256
3075#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0
3076#define mmCP_HQD_IB_BASE_ADDR 0x1257
3077#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0
3078#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258
3079#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0
3080#define mmCP_HQD_IB_RPTR 0x1259
3081#define mmCP_HQD_IB_RPTR_BASE_IDX 0
3082#define mmCP_HQD_IB_CONTROL 0x125a
3083#define mmCP_HQD_IB_CONTROL_BASE_IDX 0
3084#define mmCP_HQD_IQ_TIMER 0x125b
3085#define mmCP_HQD_IQ_TIMER_BASE_IDX 0
3086#define mmCP_HQD_IQ_RPTR 0x125c
3087#define mmCP_HQD_IQ_RPTR_BASE_IDX 0
3088#define mmCP_HQD_DEQUEUE_REQUEST 0x125d
3089#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0
3090#define mmCP_HQD_DMA_OFFLOAD 0x125e
3091#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0
3092#define mmCP_HQD_OFFLOAD 0x125e
3093#define mmCP_HQD_OFFLOAD_BASE_IDX 0
3094#define mmCP_HQD_SEMA_CMD 0x125f
3095#define mmCP_HQD_SEMA_CMD_BASE_IDX 0
3096#define mmCP_HQD_MSG_TYPE 0x1260
3097#define mmCP_HQD_MSG_TYPE_BASE_IDX 0
3098#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261
3099#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0
3100#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262
3101#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0
3102#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263
3103#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0
3104#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264
3105#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0
3106#define mmCP_HQD_HQ_SCHEDULER0 0x1265
3107#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0
3108#define mmCP_HQD_HQ_STATUS0 0x1265
3109#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0
3110#define mmCP_HQD_HQ_CONTROL0 0x1266
3111#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0
3112#define mmCP_HQD_HQ_SCHEDULER1 0x1266
3113#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0
3114#define mmCP_MQD_CONTROL 0x1267
3115#define mmCP_MQD_CONTROL_BASE_IDX 0
3116#define mmCP_HQD_HQ_STATUS1 0x1268
3117#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0
3118#define mmCP_HQD_HQ_CONTROL1 0x1269
3119#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0
3120#define mmCP_HQD_EOP_BASE_ADDR 0x126a
3121#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0
3122#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b
3123#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0
3124#define mmCP_HQD_EOP_CONTROL 0x126c
3125#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
3126#define mmCP_HQD_EOP_RPTR 0x126d
3127#define mmCP_HQD_EOP_RPTR_BASE_IDX 0
3128#define mmCP_HQD_EOP_WPTR 0x126e
3129#define mmCP_HQD_EOP_WPTR_BASE_IDX 0
3130#define mmCP_HQD_EOP_EVENTS 0x126f
3131#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0
3132#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270
3133#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
3134#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271
3135#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
3136#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272
3137#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0
3138#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273
3139#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0
3140#define mmCP_HQD_CNTL_STACK_SIZE 0x1274
3141#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0
3142#define mmCP_HQD_WG_STATE_OFFSET 0x1275
3143#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0
3144#define mmCP_HQD_CTX_SAVE_SIZE 0x1276
3145#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0
3146#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277
3147#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0
3148#define mmCP_HQD_ERROR 0x1278
3149#define mmCP_HQD_ERROR_BASE_IDX 0
3150#define mmCP_HQD_EOP_WPTR_MEM 0x1279
3151#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0
3152#define mmCP_HQD_AQL_CONTROL 0x127a
3153#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0
3154#define mmCP_HQD_PQ_WPTR_LO 0x127b
3155#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0
3156#define mmCP_HQD_PQ_WPTR_HI 0x127c
3157#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0
3158
3159
3160// addressBlock: gc_didtdec
3161// base address: 0xca00
3162#define mmDIDT_IND_INDEX 0x1280
3163#define mmDIDT_IND_INDEX_BASE_IDX 0
3164#define mmDIDT_IND_DATA 0x1281
3165#define mmDIDT_IND_DATA_BASE_IDX 0
3166
3167
3168// addressBlock: gc_gccacdec
3169// base address: 0xca10
3170#define mmGC_CAC_CTRL_1 0x1284
3171#define mmGC_CAC_CTRL_1_BASE_IDX 0
3172#define mmGC_CAC_CTRL_2 0x1285
3173#define mmGC_CAC_CTRL_2_BASE_IDX 0
3174#define mmGC_CAC_CGTT_CLK_CTRL 0x1286
3175#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0
3176#define mmGC_CAC_AGGR_LOWER 0x1287
3177#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0
3178#define mmGC_CAC_AGGR_UPPER 0x1288
3179#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0
3180#define mmGC_CAC_PG_AGGR_LOWER 0x128b
3181#define mmGC_CAC_PG_AGGR_LOWER_BASE_IDX 0
3182#define mmGC_CAC_PG_AGGR_UPPER 0x128c
3183#define mmGC_CAC_PG_AGGR_UPPER_BASE_IDX 0
3184#define mmGC_CAC_SOFT_CTRL 0x128d
3185#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0
3186#define mmGC_DIDT_CTRL0 0x128e
3187#define mmGC_DIDT_CTRL0_BASE_IDX 0
3188#define mmGC_DIDT_CTRL1 0x128f
3189#define mmGC_DIDT_CTRL1_BASE_IDX 0
3190#define mmGC_DIDT_CTRL2 0x1290
3191#define mmGC_DIDT_CTRL2_BASE_IDX 0
3192#define mmGC_DIDT_WEIGHT 0x1291
3193#define mmGC_DIDT_WEIGHT_BASE_IDX 0
3194#define mmGC_EDC_CTRL 0x1293
3195#define mmGC_EDC_CTRL_BASE_IDX 0
3196#define mmGC_EDC_THRESHOLD 0x1294
3197#define mmGC_EDC_THRESHOLD_BASE_IDX 0
3198#define mmGC_EDC_STATUS 0x1295
3199#define mmGC_EDC_STATUS_BASE_IDX 0
3200#define mmGC_EDC_OVERFLOW 0x1296
3201#define mmGC_EDC_OVERFLOW_BASE_IDX 0
3202#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297
3203#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0
3204#define mmGC_DIDT_DROOP_CTRL 0x1298
3205#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0
3206#define mmGC_EDC_DROOP_CTRL 0x1299
3207#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0
3208#define mmGC_CAC_IND_INDEX 0x129a
3209#define mmGC_CAC_IND_INDEX_BASE_IDX 0
3210#define mmGC_CAC_IND_DATA 0x129b
3211#define mmGC_CAC_IND_DATA_BASE_IDX 0
3212#define mmSE_CAC_CGTT_CLK_CTRL 0x129c
3213#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0
3214#define mmSE_CAC_IND_INDEX 0x129d
3215#define mmSE_CAC_IND_INDEX_BASE_IDX 0
3216#define mmSE_CAC_IND_DATA 0x129e
3217#define mmSE_CAC_IND_DATA_BASE_IDX 0
3218
3219
3220// addressBlock: gc_tcpdec
3221// base address: 0xca80
3222#define mmTCP_WATCH0_ADDR_H 0x12a0
3223#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0
3224#define mmTCP_WATCH0_ADDR_L 0x12a1
3225#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0
3226#define mmTCP_WATCH0_CNTL 0x12a2
3227#define mmTCP_WATCH0_CNTL_BASE_IDX 0
3228#define mmTCP_WATCH1_ADDR_H 0x12a3
3229#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0
3230#define mmTCP_WATCH1_ADDR_L 0x12a4
3231#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0
3232#define mmTCP_WATCH1_CNTL 0x12a5
3233#define mmTCP_WATCH1_CNTL_BASE_IDX 0
3234#define mmTCP_WATCH2_ADDR_H 0x12a6
3235#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0
3236#define mmTCP_WATCH2_ADDR_L 0x12a7
3237#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0
3238#define mmTCP_WATCH2_CNTL 0x12a8
3239#define mmTCP_WATCH2_CNTL_BASE_IDX 0
3240#define mmTCP_WATCH3_ADDR_H 0x12a9
3241#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0
3242#define mmTCP_WATCH3_ADDR_L 0x12aa
3243#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0
3244#define mmTCP_WATCH3_CNTL 0x12ab
3245#define mmTCP_WATCH3_CNTL_BASE_IDX 0
3246#define mmTCP_GATCL1_CNTL 0x12b0
3247#define mmTCP_GATCL1_CNTL_BASE_IDX 0
3248#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1
3249#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0
3250#define mmTCP_GATCL1_DSM_CNTL 0x12b2
3251#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0
3252#define mmTCP_CNTL2 0x12b4
3253#define mmTCP_CNTL2_BASE_IDX 0
3254#define mmTCP_UTCL1_CNTL1 0x12b5
3255#define mmTCP_UTCL1_CNTL1_BASE_IDX 0
3256#define mmTCP_UTCL1_CNTL2 0x12b6
3257#define mmTCP_UTCL1_CNTL2_BASE_IDX 0
3258#define mmTCP_UTCL1_STATUS 0x12b7
3259#define mmTCP_UTCL1_STATUS_BASE_IDX 0
3260#define mmTCP_PERFCOUNTER_FILTER 0x12b9
3261#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0
3262#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba
3263#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0
3264
3265
3266// addressBlock: gc_gdspdec
3267// base address: 0xcc00
3268#define mmGDS_VMID0_BASE 0x1300
3269#define mmGDS_VMID0_BASE_BASE_IDX 0
3270#define mmGDS_VMID0_SIZE 0x1301
3271#define mmGDS_VMID0_SIZE_BASE_IDX 0
3272#define mmGDS_VMID1_BASE 0x1302
3273#define mmGDS_VMID1_BASE_BASE_IDX 0
3274#define mmGDS_VMID1_SIZE 0x1303
3275#define mmGDS_VMID1_SIZE_BASE_IDX 0
3276#define mmGDS_VMID2_BASE 0x1304
3277#define mmGDS_VMID2_BASE_BASE_IDX 0
3278#define mmGDS_VMID2_SIZE 0x1305
3279#define mmGDS_VMID2_SIZE_BASE_IDX 0
3280#define mmGDS_VMID3_BASE 0x1306
3281#define mmGDS_VMID3_BASE_BASE_IDX 0
3282#define mmGDS_VMID3_SIZE 0x1307
3283#define mmGDS_VMID3_SIZE_BASE_IDX 0
3284#define mmGDS_VMID4_BASE 0x1308
3285#define mmGDS_VMID4_BASE_BASE_IDX 0
3286#define mmGDS_VMID4_SIZE 0x1309
3287#define mmGDS_VMID4_SIZE_BASE_IDX 0
3288#define mmGDS_VMID5_BASE 0x130a
3289#define mmGDS_VMID5_BASE_BASE_IDX 0
3290#define mmGDS_VMID5_SIZE 0x130b
3291#define mmGDS_VMID5_SIZE_BASE_IDX 0
3292#define mmGDS_VMID6_BASE 0x130c
3293#define mmGDS_VMID6_BASE_BASE_IDX 0
3294#define mmGDS_VMID6_SIZE 0x130d
3295#define mmGDS_VMID6_SIZE_BASE_IDX 0
3296#define mmGDS_VMID7_BASE 0x130e
3297#define mmGDS_VMID7_BASE_BASE_IDX 0
3298#define mmGDS_VMID7_SIZE 0x130f
3299#define mmGDS_VMID7_SIZE_BASE_IDX 0
3300#define mmGDS_VMID8_BASE 0x1310
3301#define mmGDS_VMID8_BASE_BASE_IDX 0
3302#define mmGDS_VMID8_SIZE 0x1311
3303#define mmGDS_VMID8_SIZE_BASE_IDX 0
3304#define mmGDS_VMID9_BASE 0x1312
3305#define mmGDS_VMID9_BASE_BASE_IDX 0
3306#define mmGDS_VMID9_SIZE 0x1313
3307#define mmGDS_VMID9_SIZE_BASE_IDX 0
3308#define mmGDS_VMID10_BASE 0x1314
3309#define mmGDS_VMID10_BASE_BASE_IDX 0
3310#define mmGDS_VMID10_SIZE 0x1315
3311#define mmGDS_VMID10_SIZE_BASE_IDX 0
3312#define mmGDS_VMID11_BASE 0x1316
3313#define mmGDS_VMID11_BASE_BASE_IDX 0
3314#define mmGDS_VMID11_SIZE 0x1317
3315#define mmGDS_VMID11_SIZE_BASE_IDX 0
3316#define mmGDS_VMID12_BASE 0x1318
3317#define mmGDS_VMID12_BASE_BASE_IDX 0
3318#define mmGDS_VMID12_SIZE 0x1319
3319#define mmGDS_VMID12_SIZE_BASE_IDX 0
3320#define mmGDS_VMID13_BASE 0x131a
3321#define mmGDS_VMID13_BASE_BASE_IDX 0
3322#define mmGDS_VMID13_SIZE 0x131b
3323#define mmGDS_VMID13_SIZE_BASE_IDX 0
3324#define mmGDS_VMID14_BASE 0x131c
3325#define mmGDS_VMID14_BASE_BASE_IDX 0
3326#define mmGDS_VMID14_SIZE 0x131d
3327#define mmGDS_VMID14_SIZE_BASE_IDX 0
3328#define mmGDS_VMID15_BASE 0x131e
3329#define mmGDS_VMID15_BASE_BASE_IDX 0
3330#define mmGDS_VMID15_SIZE 0x131f
3331#define mmGDS_VMID15_SIZE_BASE_IDX 0
3332#define mmGDS_GWS_VMID0 0x1320
3333#define mmGDS_GWS_VMID0_BASE_IDX 0
3334#define mmGDS_GWS_VMID1 0x1321
3335#define mmGDS_GWS_VMID1_BASE_IDX 0
3336#define mmGDS_GWS_VMID2 0x1322
3337#define mmGDS_GWS_VMID2_BASE_IDX 0
3338#define mmGDS_GWS_VMID3 0x1323
3339#define mmGDS_GWS_VMID3_BASE_IDX 0
3340#define mmGDS_GWS_VMID4 0x1324
3341#define mmGDS_GWS_VMID4_BASE_IDX 0
3342#define mmGDS_GWS_VMID5 0x1325
3343#define mmGDS_GWS_VMID5_BASE_IDX 0
3344#define mmGDS_GWS_VMID6 0x1326
3345#define mmGDS_GWS_VMID6_BASE_IDX 0
3346#define mmGDS_GWS_VMID7 0x1327
3347#define mmGDS_GWS_VMID7_BASE_IDX 0
3348#define mmGDS_GWS_VMID8 0x1328
3349#define mmGDS_GWS_VMID8_BASE_IDX 0
3350#define mmGDS_GWS_VMID9 0x1329
3351#define mmGDS_GWS_VMID9_BASE_IDX 0
3352#define mmGDS_GWS_VMID10 0x132a
3353#define mmGDS_GWS_VMID10_BASE_IDX 0
3354#define mmGDS_GWS_VMID11 0x132b
3355#define mmGDS_GWS_VMID11_BASE_IDX 0
3356#define mmGDS_GWS_VMID12 0x132c
3357#define mmGDS_GWS_VMID12_BASE_IDX 0
3358#define mmGDS_GWS_VMID13 0x132d
3359#define mmGDS_GWS_VMID13_BASE_IDX 0
3360#define mmGDS_GWS_VMID14 0x132e
3361#define mmGDS_GWS_VMID14_BASE_IDX 0
3362#define mmGDS_GWS_VMID15 0x132f
3363#define mmGDS_GWS_VMID15_BASE_IDX 0
3364#define mmGDS_OA_VMID0 0x1330
3365#define mmGDS_OA_VMID0_BASE_IDX 0
3366#define mmGDS_OA_VMID1 0x1331
3367#define mmGDS_OA_VMID1_BASE_IDX 0
3368#define mmGDS_OA_VMID2 0x1332
3369#define mmGDS_OA_VMID2_BASE_IDX 0
3370#define mmGDS_OA_VMID3 0x1333
3371#define mmGDS_OA_VMID3_BASE_IDX 0
3372#define mmGDS_OA_VMID4 0x1334
3373#define mmGDS_OA_VMID4_BASE_IDX 0
3374#define mmGDS_OA_VMID5 0x1335
3375#define mmGDS_OA_VMID5_BASE_IDX 0
3376#define mmGDS_OA_VMID6 0x1336
3377#define mmGDS_OA_VMID6_BASE_IDX 0
3378#define mmGDS_OA_VMID7 0x1337
3379#define mmGDS_OA_VMID7_BASE_IDX 0
3380#define mmGDS_OA_VMID8 0x1338
3381#define mmGDS_OA_VMID8_BASE_IDX 0
3382#define mmGDS_OA_VMID9 0x1339
3383#define mmGDS_OA_VMID9_BASE_IDX 0
3384#define mmGDS_OA_VMID10 0x133a
3385#define mmGDS_OA_VMID10_BASE_IDX 0
3386#define mmGDS_OA_VMID11 0x133b
3387#define mmGDS_OA_VMID11_BASE_IDX 0
3388#define mmGDS_OA_VMID12 0x133c
3389#define mmGDS_OA_VMID12_BASE_IDX 0
3390#define mmGDS_OA_VMID13 0x133d
3391#define mmGDS_OA_VMID13_BASE_IDX 0
3392#define mmGDS_OA_VMID14 0x133e
3393#define mmGDS_OA_VMID14_BASE_IDX 0
3394#define mmGDS_OA_VMID15 0x133f
3395#define mmGDS_OA_VMID15_BASE_IDX 0
3396#define mmGDS_GWS_RESET0 0x1344
3397#define mmGDS_GWS_RESET0_BASE_IDX 0
3398#define mmGDS_GWS_RESET1 0x1345
3399#define mmGDS_GWS_RESET1_BASE_IDX 0
3400#define mmGDS_GWS_RESOURCE_RESET 0x1346
3401#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0
3402#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348
3403#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0
3404#define mmGDS_OA_RESET_MASK 0x1349
3405#define mmGDS_OA_RESET_MASK_BASE_IDX 0
3406#define mmGDS_OA_RESET 0x134a
3407#define mmGDS_OA_RESET_BASE_IDX 0
3408#define mmGDS_ENHANCE 0x134b
3409#define mmGDS_ENHANCE_BASE_IDX 0
3410#define mmGDS_OA_CGPG_RESTORE 0x134c
3411#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0
3412#define mmGDS_CS_CTXSW_STATUS 0x134d
3413#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0
3414#define mmGDS_CS_CTXSW_CNT0 0x134e
3415#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0
3416#define mmGDS_CS_CTXSW_CNT1 0x134f
3417#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0
3418#define mmGDS_CS_CTXSW_CNT2 0x1350
3419#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0
3420#define mmGDS_CS_CTXSW_CNT3 0x1351
3421#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0
3422#define mmGDS_GFX_CTXSW_STATUS 0x1352
3423#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0
3424#define mmGDS_VS_CTXSW_CNT0 0x1353
3425#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0
3426#define mmGDS_VS_CTXSW_CNT1 0x1354
3427#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0
3428#define mmGDS_VS_CTXSW_CNT2 0x1355
3429#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0
3430#define mmGDS_VS_CTXSW_CNT3 0x1356
3431#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0
3432#define mmGDS_PS0_CTXSW_CNT0 0x1357
3433#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0
3434#define mmGDS_PS0_CTXSW_CNT1 0x1358
3435#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0
3436#define mmGDS_PS0_CTXSW_CNT2 0x1359
3437#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0
3438#define mmGDS_PS0_CTXSW_CNT3 0x135a
3439#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0
3440#define mmGDS_PS1_CTXSW_CNT0 0x135b
3441#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0
3442#define mmGDS_PS1_CTXSW_CNT1 0x135c
3443#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0
3444#define mmGDS_PS1_CTXSW_CNT2 0x135d
3445#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0
3446#define mmGDS_PS1_CTXSW_CNT3 0x135e
3447#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0
3448#define mmGDS_PS2_CTXSW_CNT0 0x135f
3449#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0
3450#define mmGDS_PS2_CTXSW_CNT1 0x1360
3451#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0
3452#define mmGDS_PS2_CTXSW_CNT2 0x1361
3453#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0
3454#define mmGDS_PS2_CTXSW_CNT3 0x1362
3455#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0
3456#define mmGDS_PS3_CTXSW_CNT0 0x1363
3457#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0
3458#define mmGDS_PS3_CTXSW_CNT1 0x1364
3459#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0
3460#define mmGDS_PS3_CTXSW_CNT2 0x1365
3461#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0
3462#define mmGDS_PS3_CTXSW_CNT3 0x1366
3463#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0
3464#define mmGDS_PS4_CTXSW_CNT0 0x1367
3465#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0
3466#define mmGDS_PS4_CTXSW_CNT1 0x1368
3467#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0
3468#define mmGDS_PS4_CTXSW_CNT2 0x1369
3469#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0
3470#define mmGDS_PS4_CTXSW_CNT3 0x136a
3471#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0
3472#define mmGDS_PS5_CTXSW_CNT0 0x136b
3473#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0
3474#define mmGDS_PS5_CTXSW_CNT1 0x136c
3475#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0
3476#define mmGDS_PS5_CTXSW_CNT2 0x136d
3477#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0
3478#define mmGDS_PS5_CTXSW_CNT3 0x136e
3479#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0
3480#define mmGDS_PS6_CTXSW_CNT0 0x136f
3481#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0
3482#define mmGDS_PS6_CTXSW_CNT1 0x1370
3483#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0
3484#define mmGDS_PS6_CTXSW_CNT2 0x1371
3485#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0
3486#define mmGDS_PS6_CTXSW_CNT3 0x1372
3487#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0
3488#define mmGDS_PS7_CTXSW_CNT0 0x1373
3489#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0
3490#define mmGDS_PS7_CTXSW_CNT1 0x1374
3491#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0
3492#define mmGDS_PS7_CTXSW_CNT2 0x1375
3493#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0
3494#define mmGDS_PS7_CTXSW_CNT3 0x1376
3495#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0
3496#define mmGDS_GS_CTXSW_CNT0 0x1377
3497#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0
3498#define mmGDS_GS_CTXSW_CNT1 0x1378
3499#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0
3500#define mmGDS_GS_CTXSW_CNT2 0x1379
3501#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0
3502#define mmGDS_GS_CTXSW_CNT3 0x137a
3503#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0
3504
3505
3506// addressBlock: gc_rasdec
3507// base address: 0xce00
3508#define mmRAS_SIGNATURE_CONTROL 0x1380
3509#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0
3510#define mmRAS_SIGNATURE_MASK 0x1381
3511#define mmRAS_SIGNATURE_MASK_BASE_IDX 0
3512#define mmRAS_SX_SIGNATURE0 0x1382
3513#define mmRAS_SX_SIGNATURE0_BASE_IDX 0
3514#define mmRAS_SX_SIGNATURE1 0x1383
3515#define mmRAS_SX_SIGNATURE1_BASE_IDX 0
3516#define mmRAS_SX_SIGNATURE2 0x1384
3517#define mmRAS_SX_SIGNATURE2_BASE_IDX 0
3518#define mmRAS_SX_SIGNATURE3 0x1385
3519#define mmRAS_SX_SIGNATURE3_BASE_IDX 0
3520#define mmRAS_DB_SIGNATURE0 0x138b
3521#define mmRAS_DB_SIGNATURE0_BASE_IDX 0
3522#define mmRAS_PA_SIGNATURE0 0x138c
3523#define mmRAS_PA_SIGNATURE0_BASE_IDX 0
3524#define mmRAS_VGT_SIGNATURE0 0x138d
3525#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0
3526#define mmRAS_SQ_SIGNATURE0 0x138e
3527#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0
3528#define mmRAS_SC_SIGNATURE0 0x138f
3529#define mmRAS_SC_SIGNATURE0_BASE_IDX 0
3530#define mmRAS_SC_SIGNATURE1 0x1390
3531#define mmRAS_SC_SIGNATURE1_BASE_IDX 0
3532#define mmRAS_SC_SIGNATURE2 0x1391
3533#define mmRAS_SC_SIGNATURE2_BASE_IDX 0
3534#define mmRAS_SC_SIGNATURE3 0x1392
3535#define mmRAS_SC_SIGNATURE3_BASE_IDX 0
3536#define mmRAS_SC_SIGNATURE4 0x1393
3537#define mmRAS_SC_SIGNATURE4_BASE_IDX 0
3538#define mmRAS_SC_SIGNATURE5 0x1394
3539#define mmRAS_SC_SIGNATURE5_BASE_IDX 0
3540#define mmRAS_SC_SIGNATURE6 0x1395
3541#define mmRAS_SC_SIGNATURE6_BASE_IDX 0
3542#define mmRAS_SC_SIGNATURE7 0x1396
3543#define mmRAS_SC_SIGNATURE7_BASE_IDX 0
3544#define mmRAS_IA_SIGNATURE0 0x1397
3545#define mmRAS_IA_SIGNATURE0_BASE_IDX 0
3546#define mmRAS_IA_SIGNATURE1 0x1398
3547#define mmRAS_IA_SIGNATURE1_BASE_IDX 0
3548#define mmRAS_SPI_SIGNATURE0 0x1399
3549#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0
3550#define mmRAS_SPI_SIGNATURE1 0x139a
3551#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0
3552#define mmRAS_TA_SIGNATURE0 0x139b
3553#define mmRAS_TA_SIGNATURE0_BASE_IDX 0
3554#define mmRAS_TD_SIGNATURE0 0x139c
3555#define mmRAS_TD_SIGNATURE0_BASE_IDX 0
3556#define mmRAS_CB_SIGNATURE0 0x139d
3557#define mmRAS_CB_SIGNATURE0_BASE_IDX 0
3558#define mmRAS_BCI_SIGNATURE0 0x139e
3559#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0
3560#define mmRAS_BCI_SIGNATURE1 0x139f
3561#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0
3562#define mmRAS_TA_SIGNATURE1 0x13a0
3563#define mmRAS_TA_SIGNATURE1_BASE_IDX 0
3564
3565
3566// addressBlock: gc_gfxdec0
3567// base address: 0x28000
3568#define mmDB_RENDER_CONTROL 0x0000
3569#define mmDB_RENDER_CONTROL_BASE_IDX 1
3570#define mmDB_COUNT_CONTROL 0x0001
3571#define mmDB_COUNT_CONTROL_BASE_IDX 1
3572#define mmDB_DEPTH_VIEW 0x0002
3573#define mmDB_DEPTH_VIEW_BASE_IDX 1
3574#define mmDB_RENDER_OVERRIDE 0x0003
3575#define mmDB_RENDER_OVERRIDE_BASE_IDX 1
3576#define mmDB_RENDER_OVERRIDE2 0x0004
3577#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1
3578#define mmDB_HTILE_DATA_BASE 0x0005
3579#define mmDB_HTILE_DATA_BASE_BASE_IDX 1
3580#define mmDB_HTILE_DATA_BASE_HI 0x0006
3581#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1
3582#define mmDB_DEPTH_SIZE 0x0007
3583#define mmDB_DEPTH_SIZE_BASE_IDX 1
3584#define mmDB_DEPTH_BOUNDS_MIN 0x0008
3585#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
3586#define mmDB_DEPTH_BOUNDS_MAX 0x0009
3587#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1
3588#define mmDB_STENCIL_CLEAR 0x000a
3589#define mmDB_STENCIL_CLEAR_BASE_IDX 1
3590#define mmDB_DEPTH_CLEAR 0x000b
3591#define mmDB_DEPTH_CLEAR_BASE_IDX 1
3592#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c
3593#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1
3594#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d
3595#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1
3596#define mmDB_Z_INFO 0x000e
3597#define mmDB_Z_INFO_BASE_IDX 1
3598#define mmDB_STENCIL_INFO 0x000f
3599#define mmDB_STENCIL_INFO_BASE_IDX 1
3600#define mmDB_Z_READ_BASE 0x0010
3601#define mmDB_Z_READ_BASE_BASE_IDX 1
3602#define mmDB_Z_READ_BASE_HI 0x0011
3603#define mmDB_Z_READ_BASE_HI_BASE_IDX 1
3604#define mmDB_STENCIL_READ_BASE 0x0012
3605#define mmDB_STENCIL_READ_BASE_BASE_IDX 1
3606#define mmDB_STENCIL_READ_BASE_HI 0x0013
3607#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1
3608#define mmDB_Z_WRITE_BASE 0x0014
3609#define mmDB_Z_WRITE_BASE_BASE_IDX 1
3610#define mmDB_Z_WRITE_BASE_HI 0x0015
3611#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1
3612#define mmDB_STENCIL_WRITE_BASE 0x0016
3613#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1
3614#define mmDB_STENCIL_WRITE_BASE_HI 0x0017
3615#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
3616#define mmDB_DFSM_CONTROL 0x0018
3617#define mmDB_DFSM_CONTROL_BASE_IDX 1
3618#define mmDB_Z_INFO2 0x001a
3619#define mmDB_Z_INFO2_BASE_IDX 1
3620#define mmDB_STENCIL_INFO2 0x001b
3621#define mmDB_STENCIL_INFO2_BASE_IDX 1
3622#define mmTA_BC_BASE_ADDR 0x0020
3623#define mmTA_BC_BASE_ADDR_BASE_IDX 1
3624#define mmTA_BC_BASE_ADDR_HI 0x0021
3625#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1
3626#define mmCOHER_DEST_BASE_HI_0 0x007a
3627#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1
3628#define mmCOHER_DEST_BASE_HI_1 0x007b
3629#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1
3630#define mmCOHER_DEST_BASE_HI_2 0x007c
3631#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1
3632#define mmCOHER_DEST_BASE_HI_3 0x007d
3633#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1
3634#define mmCOHER_DEST_BASE_2 0x007e
3635#define mmCOHER_DEST_BASE_2_BASE_IDX 1
3636#define mmCOHER_DEST_BASE_3 0x007f
3637#define mmCOHER_DEST_BASE_3_BASE_IDX 1
3638#define mmPA_SC_WINDOW_OFFSET 0x0080
3639#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1
3640#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081
3641#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1
3642#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082
3643#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1
3644#define mmPA_SC_CLIPRECT_RULE 0x0083
3645#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1
3646#define mmPA_SC_CLIPRECT_0_TL 0x0084
3647#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1
3648#define mmPA_SC_CLIPRECT_0_BR 0x0085
3649#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1
3650#define mmPA_SC_CLIPRECT_1_TL 0x0086
3651#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1
3652#define mmPA_SC_CLIPRECT_1_BR 0x0087
3653#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1
3654#define mmPA_SC_CLIPRECT_2_TL 0x0088
3655#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1
3656#define mmPA_SC_CLIPRECT_2_BR 0x0089
3657#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1
3658#define mmPA_SC_CLIPRECT_3_TL 0x008a
3659#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1
3660#define mmPA_SC_CLIPRECT_3_BR 0x008b
3661#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1
3662#define mmPA_SC_EDGERULE 0x008c
3663#define mmPA_SC_EDGERULE_BASE_IDX 1
3664#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d
3665#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1
3666#define mmCB_TARGET_MASK 0x008e
3667#define mmCB_TARGET_MASK_BASE_IDX 1
3668#define mmCB_SHADER_MASK 0x008f
3669#define mmCB_SHADER_MASK_BASE_IDX 1
3670#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090
3671#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1
3672#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091
3673#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1
3674#define mmCOHER_DEST_BASE_0 0x0092
3675#define mmCOHER_DEST_BASE_0_BASE_IDX 1
3676#define mmCOHER_DEST_BASE_1 0x0093
3677#define mmCOHER_DEST_BASE_1_BASE_IDX 1
3678#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094
3679#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1
3680#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095
3681#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1
3682#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096
3683#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1
3684#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097
3685#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1
3686#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098
3687#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1
3688#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099
3689#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1
3690#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a
3691#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1
3692#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b
3693#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1
3694#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c
3695#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1
3696#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d
3697#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1
3698#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e
3699#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1
3700#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f
3701#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1
3702#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0
3703#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1
3704#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1
3705#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1
3706#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2
3707#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1
3708#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3
3709#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1
3710#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4
3711#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1
3712#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5
3713#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1
3714#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6
3715#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1
3716#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7
3717#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1
3718#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8
3719#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1
3720#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9
3721#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1
3722#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa
3723#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1
3724#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab
3725#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1
3726#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac
3727#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1
3728#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad
3729#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1
3730#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae
3731#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1
3732#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af
3733#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1
3734#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0
3735#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1
3736#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1
3737#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1
3738#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2
3739#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1
3740#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3
3741#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1
3742#define mmPA_SC_VPORT_ZMIN_0 0x00b4
3743#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1
3744#define mmPA_SC_VPORT_ZMAX_0 0x00b5
3745#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1
3746#define mmPA_SC_VPORT_ZMIN_1 0x00b6
3747#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1
3748#define mmPA_SC_VPORT_ZMAX_1 0x00b7
3749#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1
3750#define mmPA_SC_VPORT_ZMIN_2 0x00b8
3751#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1
3752#define mmPA_SC_VPORT_ZMAX_2 0x00b9
3753#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1
3754#define mmPA_SC_VPORT_ZMIN_3 0x00ba
3755#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1
3756#define mmPA_SC_VPORT_ZMAX_3 0x00bb
3757#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1
3758#define mmPA_SC_VPORT_ZMIN_4 0x00bc
3759#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1
3760#define mmPA_SC_VPORT_ZMAX_4 0x00bd
3761#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1
3762#define mmPA_SC_VPORT_ZMIN_5 0x00be
3763#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1
3764#define mmPA_SC_VPORT_ZMAX_5 0x00bf
3765#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1
3766#define mmPA_SC_VPORT_ZMIN_6 0x00c0
3767#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1
3768#define mmPA_SC_VPORT_ZMAX_6 0x00c1
3769#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1
3770#define mmPA_SC_VPORT_ZMIN_7 0x00c2
3771#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1
3772#define mmPA_SC_VPORT_ZMAX_7 0x00c3
3773#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1
3774#define mmPA_SC_VPORT_ZMIN_8 0x00c4
3775#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1
3776#define mmPA_SC_VPORT_ZMAX_8 0x00c5
3777#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1
3778#define mmPA_SC_VPORT_ZMIN_9 0x00c6
3779#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1
3780#define mmPA_SC_VPORT_ZMAX_9 0x00c7
3781#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1
3782#define mmPA_SC_VPORT_ZMIN_10 0x00c8
3783#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1
3784#define mmPA_SC_VPORT_ZMAX_10 0x00c9
3785#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1
3786#define mmPA_SC_VPORT_ZMIN_11 0x00ca
3787#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1
3788#define mmPA_SC_VPORT_ZMAX_11 0x00cb
3789#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1
3790#define mmPA_SC_VPORT_ZMIN_12 0x00cc
3791#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1
3792#define mmPA_SC_VPORT_ZMAX_12 0x00cd
3793#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1
3794#define mmPA_SC_VPORT_ZMIN_13 0x00ce
3795#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1
3796#define mmPA_SC_VPORT_ZMAX_13 0x00cf
3797#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1
3798#define mmPA_SC_VPORT_ZMIN_14 0x00d0
3799#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1
3800#define mmPA_SC_VPORT_ZMAX_14 0x00d1
3801#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1
3802#define mmPA_SC_VPORT_ZMIN_15 0x00d2
3803#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1
3804#define mmPA_SC_VPORT_ZMAX_15 0x00d3
3805#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1
3806#define mmPA_SC_RASTER_CONFIG 0x00d4
3807#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1
3808#define mmPA_SC_RASTER_CONFIG_1 0x00d5
3809#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1
3810#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6
3811#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1
3812#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7
3813#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1
3814#define mmCP_PERFMON_CNTX_CNTL 0x00d8
3815#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1
3816#define mmCP_PIPEID 0x00d9
3817#define mmCP_PIPEID_BASE_IDX 1
3818#define mmCP_RINGID 0x00d9
3819#define mmCP_RINGID_BASE_IDX 1
3820#define mmCP_VMID 0x00da
3821#define mmCP_VMID_BASE_IDX 1
3822#define mmPA_SC_RIGHT_VERT_GRID 0x00e8
3823#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1
3824#define mmPA_SC_LEFT_VERT_GRID 0x00e9
3825#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
3826#define mmPA_SC_HORIZ_GRID 0x00ea
3827#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
3828#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
3829#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
3830#define mmCB_BLEND_RED 0x0105
3831#define mmCB_BLEND_RED_BASE_IDX 1
3832#define mmCB_BLEND_GREEN 0x0106
3833#define mmCB_BLEND_GREEN_BASE_IDX 1
3834#define mmCB_BLEND_BLUE 0x0107
3835#define mmCB_BLEND_BLUE_BASE_IDX 1
3836#define mmCB_BLEND_ALPHA 0x0108
3837#define mmCB_BLEND_ALPHA_BASE_IDX 1
3838#define mmCB_DCC_CONTROL 0x0109
3839#define mmCB_DCC_CONTROL_BASE_IDX 1
3840#define mmDB_STENCIL_CONTROL 0x010b
3841#define mmDB_STENCIL_CONTROL_BASE_IDX 1
3842#define mmDB_STENCILREFMASK 0x010c
3843#define mmDB_STENCILREFMASK_BASE_IDX 1
3844#define mmDB_STENCILREFMASK_BF 0x010d
3845#define mmDB_STENCILREFMASK_BF_BASE_IDX 1
3846#define mmPA_CL_VPORT_XSCALE 0x010f
3847#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1
3848#define mmPA_CL_VPORT_XOFFSET 0x0110
3849#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1
3850#define mmPA_CL_VPORT_YSCALE 0x0111
3851#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1
3852#define mmPA_CL_VPORT_YOFFSET 0x0112
3853#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1
3854#define mmPA_CL_VPORT_ZSCALE 0x0113
3855#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1
3856#define mmPA_CL_VPORT_ZOFFSET 0x0114
3857#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1
3858#define mmPA_CL_VPORT_XSCALE_1 0x0115
3859#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1
3860#define mmPA_CL_VPORT_XOFFSET_1 0x0116
3861#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1
3862#define mmPA_CL_VPORT_YSCALE_1 0x0117
3863#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1
3864#define mmPA_CL_VPORT_YOFFSET_1 0x0118
3865#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1
3866#define mmPA_CL_VPORT_ZSCALE_1 0x0119
3867#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1
3868#define mmPA_CL_VPORT_ZOFFSET_1 0x011a
3869#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1
3870#define mmPA_CL_VPORT_XSCALE_2 0x011b
3871#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1
3872#define mmPA_CL_VPORT_XOFFSET_2 0x011c
3873#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1
3874#define mmPA_CL_VPORT_YSCALE_2 0x011d
3875#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1
3876#define mmPA_CL_VPORT_YOFFSET_2 0x011e
3877#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1
3878#define mmPA_CL_VPORT_ZSCALE_2 0x011f
3879#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1
3880#define mmPA_CL_VPORT_ZOFFSET_2 0x0120
3881#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1
3882#define mmPA_CL_VPORT_XSCALE_3 0x0121
3883#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1
3884#define mmPA_CL_VPORT_XOFFSET_3 0x0122
3885#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1
3886#define mmPA_CL_VPORT_YSCALE_3 0x0123
3887#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1
3888#define mmPA_CL_VPORT_YOFFSET_3 0x0124
3889#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1
3890#define mmPA_CL_VPORT_ZSCALE_3 0x0125
3891#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1
3892#define mmPA_CL_VPORT_ZOFFSET_3 0x0126
3893#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1
3894#define mmPA_CL_VPORT_XSCALE_4 0x0127
3895#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1
3896#define mmPA_CL_VPORT_XOFFSET_4 0x0128
3897#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1
3898#define mmPA_CL_VPORT_YSCALE_4 0x0129
3899#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1
3900#define mmPA_CL_VPORT_YOFFSET_4 0x012a
3901#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1
3902#define mmPA_CL_VPORT_ZSCALE_4 0x012b
3903#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1
3904#define mmPA_CL_VPORT_ZOFFSET_4 0x012c
3905#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1
3906#define mmPA_CL_VPORT_XSCALE_5 0x012d
3907#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1
3908#define mmPA_CL_VPORT_XOFFSET_5 0x012e
3909#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1
3910#define mmPA_CL_VPORT_YSCALE_5 0x012f
3911#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1
3912#define mmPA_CL_VPORT_YOFFSET_5 0x0130
3913#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1
3914#define mmPA_CL_VPORT_ZSCALE_5 0x0131
3915#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1
3916#define mmPA_CL_VPORT_ZOFFSET_5 0x0132
3917#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1
3918#define mmPA_CL_VPORT_XSCALE_6 0x0133
3919#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1
3920#define mmPA_CL_VPORT_XOFFSET_6 0x0134
3921#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1
3922#define mmPA_CL_VPORT_YSCALE_6 0x0135
3923#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1
3924#define mmPA_CL_VPORT_YOFFSET_6 0x0136
3925#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1
3926#define mmPA_CL_VPORT_ZSCALE_6 0x0137
3927#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1
3928#define mmPA_CL_VPORT_ZOFFSET_6 0x0138
3929#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1
3930#define mmPA_CL_VPORT_XSCALE_7 0x0139
3931#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1
3932#define mmPA_CL_VPORT_XOFFSET_7 0x013a
3933#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1
3934#define mmPA_CL_VPORT_YSCALE_7 0x013b
3935#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1
3936#define mmPA_CL_VPORT_YOFFSET_7 0x013c
3937#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1
3938#define mmPA_CL_VPORT_ZSCALE_7 0x013d
3939#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1
3940#define mmPA_CL_VPORT_ZOFFSET_7 0x013e
3941#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1
3942#define mmPA_CL_VPORT_XSCALE_8 0x013f
3943#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1
3944#define mmPA_CL_VPORT_XOFFSET_8 0x0140
3945#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1
3946#define mmPA_CL_VPORT_YSCALE_8 0x0141
3947#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1
3948#define mmPA_CL_VPORT_YOFFSET_8 0x0142
3949#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1
3950#define mmPA_CL_VPORT_ZSCALE_8 0x0143
3951#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1
3952#define mmPA_CL_VPORT_ZOFFSET_8 0x0144
3953#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1
3954#define mmPA_CL_VPORT_XSCALE_9 0x0145
3955#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1
3956#define mmPA_CL_VPORT_XOFFSET_9 0x0146
3957#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1
3958#define mmPA_CL_VPORT_YSCALE_9 0x0147
3959#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1
3960#define mmPA_CL_VPORT_YOFFSET_9 0x0148
3961#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1
3962#define mmPA_CL_VPORT_ZSCALE_9 0x0149
3963#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1
3964#define mmPA_CL_VPORT_ZOFFSET_9 0x014a
3965#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1
3966#define mmPA_CL_VPORT_XSCALE_10 0x014b
3967#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1
3968#define mmPA_CL_VPORT_XOFFSET_10 0x014c
3969#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1
3970#define mmPA_CL_VPORT_YSCALE_10 0x014d
3971#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1
3972#define mmPA_CL_VPORT_YOFFSET_10 0x014e
3973#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1
3974#define mmPA_CL_VPORT_ZSCALE_10 0x014f
3975#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1
3976#define mmPA_CL_VPORT_ZOFFSET_10 0x0150
3977#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1
3978#define mmPA_CL_VPORT_XSCALE_11 0x0151
3979#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1
3980#define mmPA_CL_VPORT_XOFFSET_11 0x0152
3981#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1
3982#define mmPA_CL_VPORT_YSCALE_11 0x0153
3983#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1
3984#define mmPA_CL_VPORT_YOFFSET_11 0x0154
3985#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1
3986#define mmPA_CL_VPORT_ZSCALE_11 0x0155
3987#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1
3988#define mmPA_CL_VPORT_ZOFFSET_11 0x0156
3989#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1
3990#define mmPA_CL_VPORT_XSCALE_12 0x0157
3991#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1
3992#define mmPA_CL_VPORT_XOFFSET_12 0x0158
3993#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1
3994#define mmPA_CL_VPORT_YSCALE_12 0x0159
3995#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1
3996#define mmPA_CL_VPORT_YOFFSET_12 0x015a
3997#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1
3998#define mmPA_CL_VPORT_ZSCALE_12 0x015b
3999#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1
4000#define mmPA_CL_VPORT_ZOFFSET_12 0x015c
4001#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1
4002#define mmPA_CL_VPORT_XSCALE_13 0x015d
4003#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1
4004#define mmPA_CL_VPORT_XOFFSET_13 0x015e
4005#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1
4006#define mmPA_CL_VPORT_YSCALE_13 0x015f
4007#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1
4008#define mmPA_CL_VPORT_YOFFSET_13 0x0160
4009#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1
4010#define mmPA_CL_VPORT_ZSCALE_13 0x0161
4011#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1
4012#define mmPA_CL_VPORT_ZOFFSET_13 0x0162
4013#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1
4014#define mmPA_CL_VPORT_XSCALE_14 0x0163
4015#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1
4016#define mmPA_CL_VPORT_XOFFSET_14 0x0164
4017#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1
4018#define mmPA_CL_VPORT_YSCALE_14 0x0165
4019#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1
4020#define mmPA_CL_VPORT_YOFFSET_14 0x0166
4021#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1
4022#define mmPA_CL_VPORT_ZSCALE_14 0x0167
4023#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1
4024#define mmPA_CL_VPORT_ZOFFSET_14 0x0168
4025#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1
4026#define mmPA_CL_VPORT_XSCALE_15 0x0169
4027#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1
4028#define mmPA_CL_VPORT_XOFFSET_15 0x016a
4029#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1
4030#define mmPA_CL_VPORT_YSCALE_15 0x016b
4031#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1
4032#define mmPA_CL_VPORT_YOFFSET_15 0x016c
4033#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1
4034#define mmPA_CL_VPORT_ZSCALE_15 0x016d
4035#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1
4036#define mmPA_CL_VPORT_ZOFFSET_15 0x016e
4037#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1
4038#define mmPA_CL_UCP_0_X 0x016f
4039#define mmPA_CL_UCP_0_X_BASE_IDX 1
4040#define mmPA_CL_UCP_0_Y 0x0170
4041#define mmPA_CL_UCP_0_Y_BASE_IDX 1
4042#define mmPA_CL_UCP_0_Z 0x0171
4043#define mmPA_CL_UCP_0_Z_BASE_IDX 1
4044#define mmPA_CL_UCP_0_W 0x0172
4045#define mmPA_CL_UCP_0_W_BASE_IDX 1
4046#define mmPA_CL_UCP_1_X 0x0173
4047#define mmPA_CL_UCP_1_X_BASE_IDX 1
4048#define mmPA_CL_UCP_1_Y 0x0174
4049#define mmPA_CL_UCP_1_Y_BASE_IDX 1
4050#define mmPA_CL_UCP_1_Z 0x0175
4051#define mmPA_CL_UCP_1_Z_BASE_IDX 1
4052#define mmPA_CL_UCP_1_W 0x0176
4053#define mmPA_CL_UCP_1_W_BASE_IDX 1
4054#define mmPA_CL_UCP_2_X 0x0177
4055#define mmPA_CL_UCP_2_X_BASE_IDX 1
4056#define mmPA_CL_UCP_2_Y 0x0178
4057#define mmPA_CL_UCP_2_Y_BASE_IDX 1
4058#define mmPA_CL_UCP_2_Z 0x0179
4059#define mmPA_CL_UCP_2_Z_BASE_IDX 1
4060#define mmPA_CL_UCP_2_W 0x017a
4061#define mmPA_CL_UCP_2_W_BASE_IDX 1
4062#define mmPA_CL_UCP_3_X 0x017b
4063#define mmPA_CL_UCP_3_X_BASE_IDX 1
4064#define mmPA_CL_UCP_3_Y 0x017c
4065#define mmPA_CL_UCP_3_Y_BASE_IDX 1
4066#define mmPA_CL_UCP_3_Z 0x017d
4067#define mmPA_CL_UCP_3_Z_BASE_IDX 1
4068#define mmPA_CL_UCP_3_W 0x017e
4069#define mmPA_CL_UCP_3_W_BASE_IDX 1
4070#define mmPA_CL_UCP_4_X 0x017f
4071#define mmPA_CL_UCP_4_X_BASE_IDX 1
4072#define mmPA_CL_UCP_4_Y 0x0180
4073#define mmPA_CL_UCP_4_Y_BASE_IDX 1
4074#define mmPA_CL_UCP_4_Z 0x0181
4075#define mmPA_CL_UCP_4_Z_BASE_IDX 1
4076#define mmPA_CL_UCP_4_W 0x0182
4077#define mmPA_CL_UCP_4_W_BASE_IDX 1
4078#define mmPA_CL_UCP_5_X 0x0183
4079#define mmPA_CL_UCP_5_X_BASE_IDX 1
4080#define mmPA_CL_UCP_5_Y 0x0184
4081#define mmPA_CL_UCP_5_Y_BASE_IDX 1
4082#define mmPA_CL_UCP_5_Z 0x0185
4083#define mmPA_CL_UCP_5_Z_BASE_IDX 1
4084#define mmPA_CL_UCP_5_W 0x0186
4085#define mmPA_CL_UCP_5_W_BASE_IDX 1
4086#define mmSPI_PS_INPUT_CNTL_0 0x0191
4087#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1
4088#define mmSPI_PS_INPUT_CNTL_1 0x0192
4089#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1
4090#define mmSPI_PS_INPUT_CNTL_2 0x0193
4091#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1
4092#define mmSPI_PS_INPUT_CNTL_3 0x0194
4093#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1
4094#define mmSPI_PS_INPUT_CNTL_4 0x0195
4095#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1
4096#define mmSPI_PS_INPUT_CNTL_5 0x0196
4097#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1
4098#define mmSPI_PS_INPUT_CNTL_6 0x0197
4099#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1
4100#define mmSPI_PS_INPUT_CNTL_7 0x0198
4101#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1
4102#define mmSPI_PS_INPUT_CNTL_8 0x0199
4103#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1
4104#define mmSPI_PS_INPUT_CNTL_9 0x019a
4105#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1
4106#define mmSPI_PS_INPUT_CNTL_10 0x019b
4107#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1
4108#define mmSPI_PS_INPUT_CNTL_11 0x019c
4109#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1
4110#define mmSPI_PS_INPUT_CNTL_12 0x019d
4111#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1
4112#define mmSPI_PS_INPUT_CNTL_13 0x019e
4113#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1
4114#define mmSPI_PS_INPUT_CNTL_14 0x019f
4115#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1
4116#define mmSPI_PS_INPUT_CNTL_15 0x01a0
4117#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1
4118#define mmSPI_PS_INPUT_CNTL_16 0x01a1
4119#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1
4120#define mmSPI_PS_INPUT_CNTL_17 0x01a2
4121#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1
4122#define mmSPI_PS_INPUT_CNTL_18 0x01a3
4123#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1
4124#define mmSPI_PS_INPUT_CNTL_19 0x01a4
4125#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1
4126#define mmSPI_PS_INPUT_CNTL_20 0x01a5
4127#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1
4128#define mmSPI_PS_INPUT_CNTL_21 0x01a6
4129#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1
4130#define mmSPI_PS_INPUT_CNTL_22 0x01a7
4131#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1
4132#define mmSPI_PS_INPUT_CNTL_23 0x01a8
4133#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1
4134#define mmSPI_PS_INPUT_CNTL_24 0x01a9
4135#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1
4136#define mmSPI_PS_INPUT_CNTL_25 0x01aa
4137#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1
4138#define mmSPI_PS_INPUT_CNTL_26 0x01ab
4139#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1
4140#define mmSPI_PS_INPUT_CNTL_27 0x01ac
4141#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1
4142#define mmSPI_PS_INPUT_CNTL_28 0x01ad
4143#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1
4144#define mmSPI_PS_INPUT_CNTL_29 0x01ae
4145#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1
4146#define mmSPI_PS_INPUT_CNTL_30 0x01af
4147#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1
4148#define mmSPI_PS_INPUT_CNTL_31 0x01b0
4149#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1
4150#define mmSPI_VS_OUT_CONFIG 0x01b1
4151#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1
4152#define mmSPI_PS_INPUT_ENA 0x01b3
4153#define mmSPI_PS_INPUT_ENA_BASE_IDX 1
4154#define mmSPI_PS_INPUT_ADDR 0x01b4
4155#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1