| 1 | /* |
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| 2 | * Copyright (C) 2020 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _gc_9_4_1_OFFSET_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | // addressBlock: gc_grbmdec |
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| 25 | // base address: 0x8000 |
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| 26 | #define mmGRBM_CNTL 0x0000 |
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| 27 | #define mmGRBM_CNTL_BASE_IDX 0 |
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| 28 | #define mmGRBM_SKEW_CNTL 0x0001 |
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| 29 | #define mmGRBM_SKEW_CNTL_BASE_IDX 0 |
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| 30 | #define mmGRBM_STATUS2 0x0002 |
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| 31 | #define mmGRBM_STATUS2_BASE_IDX 0 |
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| 32 | #define mmGRBM_PWR_CNTL 0x0003 |
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| 33 | #define mmGRBM_PWR_CNTL_BASE_IDX 0 |
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| 34 | #define mmGRBM_STATUS 0x0004 |
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| 35 | #define mmGRBM_STATUS_BASE_IDX 0 |
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| 36 | #define mmGRBM_STATUS_SE0 0x0005 |
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| 37 | #define mmGRBM_STATUS_SE0_BASE_IDX 0 |
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| 38 | #define mmGRBM_STATUS_SE1 0x0006 |
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| 39 | #define mmGRBM_STATUS_SE1_BASE_IDX 0 |
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| 40 | #define mmGRBM_SOFT_RESET 0x0008 |
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| 41 | #define mmGRBM_SOFT_RESET_BASE_IDX 0 |
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| 42 | #define mmGRBM_GFX_CLKEN_CNTL 0x000c |
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| 43 | #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 |
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| 44 | #define mmGRBM_WAIT_IDLE_CLOCKS 0x000d |
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| 45 | #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 |
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| 46 | #define mmGRBM_STATUS_SE2 0x000e |
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| 47 | #define mmGRBM_STATUS_SE2_BASE_IDX 0 |
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| 48 | #define mmGRBM_STATUS_SE3 0x000f |
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| 49 | #define mmGRBM_STATUS_SE3_BASE_IDX 0 |
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| 50 | #define mmGRBM_READ_ERROR 0x0016 |
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| 51 | #define mmGRBM_READ_ERROR_BASE_IDX 0 |
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| 52 | #define mmGRBM_READ_ERROR2 0x0017 |
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| 53 | #define mmGRBM_READ_ERROR2_BASE_IDX 0 |
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| 54 | #define mmGRBM_INT_CNTL 0x0018 |
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| 55 | #define mmGRBM_INT_CNTL_BASE_IDX 0 |
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| 56 | #define mmGRBM_TRAP_OP 0x0019 |
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| 57 | #define mmGRBM_TRAP_OP_BASE_IDX 0 |
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| 58 | #define mmGRBM_TRAP_ADDR 0x001a |
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| 59 | #define mmGRBM_TRAP_ADDR_BASE_IDX 0 |
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| 60 | #define mmGRBM_TRAP_ADDR_MSK 0x001b |
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| 61 | #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0 |
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| 62 | #define mmGRBM_TRAP_WD 0x001c |
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| 63 | #define mmGRBM_TRAP_WD_BASE_IDX 0 |
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| 64 | #define mmGRBM_TRAP_WD_MSK 0x001d |
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| 65 | #define mmGRBM_TRAP_WD_MSK_BASE_IDX 0 |
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| 66 | #define mmGRBM_DSM_BYPASS 0x001e |
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| 67 | #define mmGRBM_DSM_BYPASS_BASE_IDX 0 |
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| 68 | #define mmGRBM_WRITE_ERROR 0x001f |
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| 69 | #define mmGRBM_WRITE_ERROR_BASE_IDX 0 |
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| 70 | #define mmGRBM_IOV_ERROR 0x0020 |
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| 71 | #define mmGRBM_IOV_ERROR_BASE_IDX 0 |
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| 72 | #define mmGRBM_CHIP_REVISION 0x0021 |
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| 73 | #define mmGRBM_CHIP_REVISION_BASE_IDX 0 |
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| 74 | #define mmGRBM_GFX_CNTL 0x0022 |
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| 75 | #define mmGRBM_GFX_CNTL_BASE_IDX 0 |
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| 76 | #define mmGRBM_RSMU_CFG 0x0023 |
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| 77 | #define mmGRBM_RSMU_CFG_BASE_IDX 0 |
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| 78 | #define mmGRBM_IH_CREDIT 0x0024 |
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| 79 | #define mmGRBM_IH_CREDIT_BASE_IDX 0 |
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| 80 | #define mmGRBM_PWR_CNTL2 0x0025 |
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| 81 | #define mmGRBM_PWR_CNTL2_BASE_IDX 0 |
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| 82 | #define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026 |
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| 83 | #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 |
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| 84 | #define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027 |
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| 85 | #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 |
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| 86 | #define mmGRBM_RSMU_READ_ERROR 0x0028 |
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| 87 | #define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0 |
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| 88 | #define mmGRBM_CHICKEN_BITS 0x0029 |
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| 89 | #define mmGRBM_CHICKEN_BITS_BASE_IDX 0 |
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| 90 | #define mmGRBM_FENCE_RANGE0 0x002a |
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| 91 | #define mmGRBM_FENCE_RANGE0_BASE_IDX 0 |
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| 92 | #define mmGRBM_FENCE_RANGE1 0x002b |
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| 93 | #define mmGRBM_FENCE_RANGE1_BASE_IDX 0 |
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| 94 | #define mmGRBM_NOWHERE 0x003f |
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| 95 | #define mmGRBM_NOWHERE_BASE_IDX 0 |
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| 96 | #define mmGRBM_SCRATCH_REG0 0x0040 |
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| 97 | #define mmGRBM_SCRATCH_REG0_BASE_IDX 0 |
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| 98 | #define mmGRBM_SCRATCH_REG1 0x0041 |
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| 99 | #define mmGRBM_SCRATCH_REG1_BASE_IDX 0 |
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| 100 | #define mmGRBM_SCRATCH_REG2 0x0042 |
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| 101 | #define mmGRBM_SCRATCH_REG2_BASE_IDX 0 |
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| 102 | #define mmGRBM_SCRATCH_REG3 0x0043 |
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| 103 | #define mmGRBM_SCRATCH_REG3_BASE_IDX 0 |
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| 104 | #define mmGRBM_SCRATCH_REG4 0x0044 |
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| 105 | #define mmGRBM_SCRATCH_REG4_BASE_IDX 0 |
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| 106 | #define mmGRBM_SCRATCH_REG5 0x0045 |
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| 107 | #define mmGRBM_SCRATCH_REG5_BASE_IDX 0 |
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| 108 | #define mmGRBM_SCRATCH_REG6 0x0046 |
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| 109 | #define mmGRBM_SCRATCH_REG6_BASE_IDX 0 |
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| 110 | #define mmGRBM_SCRATCH_REG7 0x0047 |
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| 111 | #define mmGRBM_SCRATCH_REG7_BASE_IDX 0 |
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| 112 | |
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| 113 | // addressBlock: gc_cppdec2 |
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| 114 | // base address: 0xc600 |
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| 115 | #define mmCPF_EDC_TAG_CNT 0x1189 |
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| 116 | #define mmCPF_EDC_TAG_CNT_BASE_IDX 0 |
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| 117 | #define mmCPF_EDC_ROQ_CNT 0x118a |
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| 118 | #define mmCPF_EDC_ROQ_CNT_BASE_IDX 0 |
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| 119 | #define mmCPG_EDC_TAG_CNT 0x118b |
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| 120 | #define mmCPG_EDC_TAG_CNT_BASE_IDX 0 |
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| 121 | #define mmCPG_EDC_DMA_CNT 0x118d |
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| 122 | #define mmCPG_EDC_DMA_CNT_BASE_IDX 0 |
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| 123 | #define mmCPC_EDC_SCRATCH_CNT 0x118e |
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| 124 | #define mmCPC_EDC_SCRATCH_CNT_BASE_IDX 0 |
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| 125 | #define mmCPC_EDC_UCODE_CNT 0x118f |
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| 126 | #define mmCPC_EDC_UCODE_CNT_BASE_IDX 0 |
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| 127 | #define mmDC_EDC_STATE_CNT 0x1191 |
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| 128 | #define mmDC_EDC_STATE_CNT_BASE_IDX 0 |
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| 129 | #define mmDC_EDC_CSINVOC_CNT 0x1192 |
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| 130 | #define mmDC_EDC_CSINVOC_CNT_BASE_IDX 0 |
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| 131 | #define mmDC_EDC_RESTORE_CNT 0x1193 |
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| 132 | #define mmDC_EDC_RESTORE_CNT_BASE_IDX 0 |
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| 133 | |
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| 134 | // addressBlock: gc_gdsdec |
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| 135 | // base address: 0x9700 |
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| 136 | #define mmGDS_EDC_CNT 0x05c5 |
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| 137 | #define mmGDS_EDC_CNT_BASE_IDX 0 |
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| 138 | #define mmGDS_EDC_GRBM_CNT 0x05c6 |
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| 139 | #define mmGDS_EDC_GRBM_CNT_BASE_IDX 0 |
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| 140 | #define mmGDS_EDC_OA_DED 0x05c7 |
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| 141 | #define mmGDS_EDC_OA_DED_BASE_IDX 0 |
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| 142 | #define mmGDS_EDC_OA_PHY_CNT 0x05cb |
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| 143 | #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0 |
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| 144 | #define mmGDS_EDC_OA_PIPE_CNT 0x05cc |
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| 145 | #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 |
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| 146 | |
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| 147 | // addressBlock: gc_shsdec |
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| 148 | // base address: 0x9000 |
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| 149 | #define mmSPI_EDC_CNT 0x0445 |
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| 150 | #define mmSPI_EDC_CNT_BASE_IDX 0 |
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| 151 | |
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| 152 | // addressBlock: gc_sqdec |
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| 153 | // base address: 0x8c00 |
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| 154 | #define mmSQC_EDC_CNT2 0x032c |
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| 155 | #define mmSQC_EDC_CNT2_BASE_IDX 0 |
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| 156 | #define mmSQC_EDC_CNT3 0x032d |
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| 157 | #define mmSQC_EDC_CNT3_BASE_IDX 0 |
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| 158 | #define mmSQC_EDC_PARITY_CNT3 0x032e |
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| 159 | #define mmSQC_EDC_PARITY_CNT3_BASE_IDX 0 |
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| 160 | #define mmSQC_EDC_CNT 0x03a2 |
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| 161 | #define mmSQC_EDC_CNT_BASE_IDX 0 |
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| 162 | #define mmSQ_EDC_SEC_CNT 0x03a3 |
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| 163 | #define mmSQ_EDC_SEC_CNT_BASE_IDX 0 |
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| 164 | #define mmSQ_EDC_DED_CNT 0x03a4 |
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| 165 | #define mmSQ_EDC_DED_CNT_BASE_IDX 0 |
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| 166 | #define mmSQ_EDC_INFO 0x03a5 |
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| 167 | #define mmSQ_EDC_INFO_BASE_IDX 0 |
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| 168 | #define mmSQ_EDC_CNT 0x03a6 |
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| 169 | #define mmSQ_EDC_CNT_BASE_IDX 0 |
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| 170 | |
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| 171 | // addressBlock: gc_tpdec |
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| 172 | // base address: 0x9400 |
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| 173 | #define mmTA_EDC_CNT 0x0586 |
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| 174 | #define mmTA_EDC_CNT_BASE_IDX 0 |
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| 175 | |
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| 176 | // addressBlock: gc_tcdec |
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| 177 | // base address: 0xac00 |
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| 178 | #define mmTCP_EDC_CNT 0x0b17 |
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| 179 | #define mmTCP_EDC_CNT_BASE_IDX 0 |
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| 180 | #define mmTCP_EDC_CNT_NEW 0x0b18 |
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| 181 | #define mmTCP_EDC_CNT_NEW_BASE_IDX 0 |
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| 182 | #define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1 |
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| 183 | #define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0 |
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| 184 | #define mmTCI_EDC_CNT 0x0b60 |
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| 185 | #define mmTCI_EDC_CNT_BASE_IDX 0 |
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| 186 | #define mmTCC_EDC_CNT 0x0b82 |
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| 187 | #define mmTCC_EDC_CNT_BASE_IDX 0 |
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| 188 | #define mmTCC_EDC_CNT2 0x0b83 |
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| 189 | #define mmTCC_EDC_CNT2_BASE_IDX 0 |
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| 190 | #define mmTCA_EDC_CNT 0x0bc5 |
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| 191 | #define mmTCA_EDC_CNT_BASE_IDX 0 |
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| 192 | |
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| 193 | // addressBlock: gc_tpdec |
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| 194 | // base address: 0x9400 |
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| 195 | #define mmTD_EDC_CNT 0x052e |
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| 196 | #define mmTD_EDC_CNT_BASE_IDX 0 |
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| 197 | #define mmTA_EDC_CNT 0x0586 |
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| 198 | #define mmTA_EDC_CNT_BASE_IDX 0 |
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| 199 | |
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| 200 | // addressBlock: gc_ea_gceadec2 |
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| 201 | // base address: 0x9c00 |
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| 202 | #define mmGCEA_EDC_CNT 0x0706 |
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| 203 | #define mmGCEA_EDC_CNT_BASE_IDX 0 |
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| 204 | #define mmGCEA_EDC_CNT2 0x0707 |
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| 205 | #define mmGCEA_EDC_CNT2_BASE_IDX 0 |
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| 206 | #define mmGCEA_EDC_CNT3 0x071b |
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| 207 | #define mmGCEA_EDC_CNT3_BASE_IDX 0 |
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| 208 | #define mmGCEA_ERR_STATUS 0x0712 |
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| 209 | #define mmGCEA_ERR_STATUS_BASE_IDX 0 |
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| 210 | |
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| 211 | // addressBlock: gc_gfxudec |
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| 212 | // base address: 0x30000 |
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| 213 | #define mmSCRATCH_REG0 0x2040 |
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| 214 | #define mmSCRATCH_REG0_BASE_IDX 1 |
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| 215 | #define mmSCRATCH_REG1 0x2041 |
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| 216 | #define mmSCRATCH_REG1_BASE_IDX 1 |
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| 217 | #define mmSCRATCH_REG2 0x2042 |
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| 218 | #define mmSCRATCH_REG2_BASE_IDX 1 |
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| 219 | #define mmSCRATCH_REG3 0x2043 |
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| 220 | #define mmSCRATCH_REG3_BASE_IDX 1 |
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| 221 | #define mmSCRATCH_REG4 0x2044 |
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| 222 | #define mmSCRATCH_REG4_BASE_IDX 1 |
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| 223 | #define mmSCRATCH_REG5 0x2045 |
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| 224 | #define mmSCRATCH_REG5_BASE_IDX 1 |
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| 225 | #define mmSCRATCH_REG6 0x2046 |
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| 226 | #define mmSCRATCH_REG6_BASE_IDX 1 |
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| 227 | #define mmSCRATCH_REG7 0x2047 |
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| 228 | #define mmSCRATCH_REG7_BASE_IDX 1 |
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| 229 | #define mmGRBM_GFX_INDEX 0x2200 |
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| 230 | #define mmGRBM_GFX_INDEX_BASE_IDX 1 |
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| 231 | |
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| 232 | // addressBlock: gc_utcl2_atcl2dec |
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| 233 | // base address: 0xa000 |
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| 234 | #define mmATC_L2_CACHE_4K_DSM_INDEX 0x080e |
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| 235 | #define mmATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 |
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| 236 | #define mmATC_L2_CACHE_2M_DSM_INDEX 0x080f |
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| 237 | #define mmATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 |
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| 238 | #define mmATC_L2_CACHE_4K_DSM_CNTL 0x0810 |
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| 239 | #define mmATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 |
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| 240 | #define mmATC_L2_CACHE_2M_DSM_CNTL 0x0811 |
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| 241 | #define mmATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 |
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| 242 | |
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| 243 | // addressBlock: gc_utcl2_vml2pfdec |
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| 244 | // base address: 0xa100 |
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| 245 | #define mmVML2_MEM_ECC_INDEX 0x0860 |
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| 246 | #define mmVML2_MEM_ECC_INDEX_BASE_IDX 0 |
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| 247 | #define mmVML2_WALKER_MEM_ECC_INDEX 0x0861 |
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| 248 | #define mmVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 |
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| 249 | #define mmUTCL2_MEM_ECC_INDEX 0x0862 |
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| 250 | #define mmUTCL2_MEM_ECC_INDEX_BASE_IDX 0 |
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| 251 | |
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| 252 | #define mmVML2_MEM_ECC_CNTL 0x0863 |
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| 253 | #define mmVML2_MEM_ECC_CNTL_BASE_IDX 0 |
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| 254 | #define mmVML2_WALKER_MEM_ECC_CNTL 0x0864 |
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| 255 | #define mmVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 |
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| 256 | #define mmUTCL2_MEM_ECC_CNTL 0x0865 |
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| 257 | #define mmUTCL2_MEM_ECC_CNTL_BASE_IDX 0 |
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| 258 | |
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| 259 | // addressBlock: gc_rlcpdec |
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| 260 | // base address: 0x3b000 |
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| 261 | #define mmRLC_EDC_CNT 0x4d40 |
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| 262 | #define mmRLC_EDC_CNT_BASE_IDX 1 |
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| 263 | #define mmRLC_EDC_CNT2 0x4d41 |
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| 264 | #define mmRLC_EDC_CNT2_BASE_IDX 1 |
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| 265 | |
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| 266 | #endif |
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| 267 | |
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