1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _gc_9_4_2_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: didtind |
28 | //DIDT_SQ_CTRL0 |
29 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
30 | #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
31 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
32 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
33 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
34 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
35 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
36 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
37 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
38 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
39 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
40 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
41 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
42 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
43 | #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
44 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
45 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
46 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
47 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
48 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
49 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
50 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
51 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
52 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
53 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
54 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
55 | //DIDT_SQ_CTRL2 |
56 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
57 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
58 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
59 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
60 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
61 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
62 | //DIDT_SQ_STALL_CTRL |
63 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
64 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
65 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
66 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
67 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
68 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
69 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
70 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
71 | //DIDT_SQ_TUNING_CTRL |
72 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
73 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
74 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
75 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
76 | //DIDT_SQ_STALL_AUTO_RELEASE_CTRL |
77 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
78 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
79 | //DIDT_SQ_CTRL3 |
80 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
81 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
82 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
83 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
84 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
85 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
86 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
87 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
88 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
89 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
90 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
91 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
92 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
93 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
94 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
95 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
96 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
97 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
98 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
99 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
100 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
101 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
102 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
103 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
104 | //DIDT_SQ_STALL_PATTERN_1_2 |
105 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
106 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
107 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
108 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
109 | //DIDT_SQ_STALL_PATTERN_3_4 |
110 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
111 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
112 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
113 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
114 | //DIDT_SQ_STALL_PATTERN_5_6 |
115 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
116 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
117 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
118 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
119 | //DIDT_SQ_STALL_PATTERN_7 |
120 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
121 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
122 | //DIDT_SQ_MPD_SCALE_FACTOR |
123 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
124 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
125 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
126 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
127 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
128 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
129 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
130 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
131 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
132 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
133 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
134 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
135 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
136 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
137 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
138 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
139 | //DIDT_SQ_THROTTLE_CNTL0 |
140 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 |
141 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
142 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
143 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
144 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L |
145 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
146 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
147 | #define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
148 | //DIDT_SQ_THROTTLE_CNTL1 |
149 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
150 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
151 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
152 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
153 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
154 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
155 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
156 | #define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
157 | //DIDT_SQ_THROTTLE_CNTL_STATUS |
158 | #define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 |
159 | #define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L |
160 | //DIDT_SQ_WEIGHT0_3 |
161 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
162 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
163 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
164 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
165 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
166 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
167 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
168 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
169 | //DIDT_SQ_WEIGHT4_7 |
170 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
171 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
172 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
173 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
174 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
175 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
176 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
177 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
178 | //DIDT_SQ_WEIGHT8_11 |
179 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
180 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
181 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
182 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
183 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
184 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
185 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
186 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
187 | //DIDT_SQ_EDC_CTRL |
188 | #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 |
189 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
190 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
191 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
192 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
193 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
194 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
195 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
196 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
197 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
198 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
199 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
200 | #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L |
201 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
202 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
203 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
204 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
205 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
206 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
207 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
208 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
209 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
210 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
211 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
212 | //DIDT_SQ_THROTTLE_CTRL |
213 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
214 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
215 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
216 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
217 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
218 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
219 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
220 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
221 | //DIDT_SQ_EDC_STALL_PATTERN_1_2 |
222 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
223 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
224 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
225 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
226 | //DIDT_SQ_EDC_STALL_PATTERN_3_4 |
227 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
228 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
229 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
230 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
231 | //DIDT_SQ_EDC_STALL_PATTERN_5_6 |
232 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
233 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
234 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
235 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
236 | //DIDT_SQ_EDC_STALL_PATTERN_7 |
237 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
238 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
239 | //DIDT_SQ_EDC_STATUS |
240 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
241 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
242 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
243 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
244 | //DIDT_SQ_EDC_STALL_DELAY_1 |
245 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 |
246 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x8 |
247 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0x10 |
248 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x18 |
249 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x000000FFL |
250 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x0000FF00L |
251 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x00FF0000L |
252 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0xFF000000L |
253 | //DIDT_SQ_EDC_STALL_DELAY_2 |
254 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 |
255 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x8 |
256 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0x10 |
257 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x18 |
258 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x000000FFL |
259 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x0000FF00L |
260 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x00FF0000L |
261 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0xFF000000L |
262 | //DIDT_SQ_EDC_STALL_DELAY_3 |
263 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 |
264 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x8 |
265 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0x10 |
266 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT 0x18 |
267 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x000000FFL |
268 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x0000FF00L |
269 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x00FF0000L |
270 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK 0xFF000000L |
271 | //DIDT_SQ_EDC_STALL_DELAY_4 |
272 | #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT 0x0 |
273 | #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT 0x8 |
274 | #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK 0x000000FFL |
275 | #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK 0x0000FF00L |
276 | //DIDT_SQ_EDC_OVERFLOW |
277 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
278 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
279 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
280 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
281 | //DIDT_SQ_EDC_ROLLING_POWER_DELTA |
282 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
283 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
284 | //DIDT_DB_CTRL0 |
285 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
286 | #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
287 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
288 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
289 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
290 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
291 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
292 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
293 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
294 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
295 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
296 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
297 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
298 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
299 | #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
300 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
301 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
302 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
303 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
304 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
305 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
306 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
307 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
308 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
309 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
310 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
311 | //DIDT_DB_CTRL2 |
312 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
313 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
314 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
315 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
316 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
317 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
318 | //DIDT_DB_STALL_CTRL |
319 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
320 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
321 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
322 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
323 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
324 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
325 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
326 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
327 | //DIDT_DB_TUNING_CTRL |
328 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
329 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
330 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
331 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
332 | //DIDT_DB_STALL_AUTO_RELEASE_CTRL |
333 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
334 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
335 | //DIDT_DB_CTRL3 |
336 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
337 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
338 | #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
339 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
340 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
341 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
342 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
343 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
344 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
345 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
346 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
347 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
348 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
349 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
350 | #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
351 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
352 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
353 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
354 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
355 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
356 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
357 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
358 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
359 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
360 | //DIDT_DB_STALL_PATTERN_1_2 |
361 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
362 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
363 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
364 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
365 | //DIDT_DB_STALL_PATTERN_3_4 |
366 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
367 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
368 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
369 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
370 | //DIDT_DB_STALL_PATTERN_5_6 |
371 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
372 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
373 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
374 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
375 | //DIDT_DB_STALL_PATTERN_7 |
376 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
377 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
378 | //DIDT_DB_MPD_SCALE_FACTOR |
379 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
380 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
381 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
382 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
383 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
384 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
385 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
386 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
387 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
388 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
389 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
390 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
391 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
392 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
393 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
394 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
395 | //DIDT_DB_THROTTLE_CNTL0 |
396 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 |
397 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
398 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
399 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
400 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L |
401 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
402 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
403 | #define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
404 | //DIDT_DB_THROTTLE_CNTL1 |
405 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
406 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
407 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
408 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
409 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
410 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
411 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
412 | #define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
413 | //DIDT_DB_THROTTLE_CNTL_STATUS |
414 | #define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 |
415 | #define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L |
416 | //DIDT_DB_WEIGHT0_3 |
417 | #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
418 | #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
419 | #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
420 | #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
421 | #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
422 | #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
423 | #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
424 | #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
425 | //DIDT_DB_WEIGHT4_7 |
426 | #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
427 | #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
428 | #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
429 | #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
430 | #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
431 | #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
432 | #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
433 | #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
434 | //DIDT_DB_WEIGHT8_11 |
435 | #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
436 | #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
437 | #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
438 | #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
439 | #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
440 | #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
441 | #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
442 | #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
443 | //DIDT_DB_EDC_CTRL |
444 | #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 |
445 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
446 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
447 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
448 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
449 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
450 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
451 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
452 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
453 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
454 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
455 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
456 | #define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L |
457 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
458 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
459 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
460 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
461 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
462 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
463 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
464 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
465 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
466 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
467 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
468 | //DIDT_DB_THROTTLE_CTRL |
469 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
470 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
471 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
472 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
473 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
474 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
475 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
476 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
477 | //DIDT_DB_EDC_STALL_PATTERN_1_2 |
478 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
479 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
480 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
481 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
482 | //DIDT_DB_EDC_STALL_PATTERN_3_4 |
483 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
484 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
485 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
486 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
487 | //DIDT_DB_EDC_STALL_PATTERN_5_6 |
488 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
489 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
490 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
491 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
492 | //DIDT_DB_EDC_STALL_PATTERN_7 |
493 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
494 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
495 | //DIDT_DB_EDC_STATUS |
496 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
497 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
498 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
499 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
500 | //DIDT_DB_EDC_STALL_DELAY_1 |
501 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 |
502 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x6 |
503 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xc |
504 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0x12 |
505 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000003FL |
506 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000FC0L |
507 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x0003F000L |
508 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x00FC0000L |
509 | //DIDT_DB_EDC_OVERFLOW |
510 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
511 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
512 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
513 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
514 | //DIDT_DB_EDC_ROLLING_POWER_DELTA |
515 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
516 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
517 | //DIDT_TD_CTRL0 |
518 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
519 | #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
520 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
521 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
522 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
523 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
524 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
525 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
526 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
527 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
528 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
529 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
530 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
531 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
532 | #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
533 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
534 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
535 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
536 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
537 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
538 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
539 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
540 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
541 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
542 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
543 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
544 | //DIDT_TD_CTRL2 |
545 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
546 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
547 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
548 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
549 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
550 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
551 | //DIDT_TD_STALL_CTRL |
552 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
553 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
554 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
555 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
556 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
557 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
558 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
559 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
560 | //DIDT_TD_TUNING_CTRL |
561 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
562 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
563 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
564 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
565 | //DIDT_TD_STALL_AUTO_RELEASE_CTRL |
566 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
567 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
568 | //DIDT_TD_CTRL3 |
569 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
570 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
571 | #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
572 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
573 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
574 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
575 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
576 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
577 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
578 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
579 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
580 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
581 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
582 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
583 | #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
584 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
585 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
586 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
587 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
588 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
589 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
590 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
591 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
592 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
593 | //DIDT_TD_STALL_PATTERN_1_2 |
594 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
595 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
596 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
597 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
598 | //DIDT_TD_STALL_PATTERN_3_4 |
599 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
600 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
601 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
602 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
603 | //DIDT_TD_STALL_PATTERN_5_6 |
604 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
605 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
606 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
607 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
608 | //DIDT_TD_STALL_PATTERN_7 |
609 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
610 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
611 | //DIDT_TD_MPD_SCALE_FACTOR |
612 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
613 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
614 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
615 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
616 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
617 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
618 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
619 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
620 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
621 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
622 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
623 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
624 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
625 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
626 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
627 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
628 | //DIDT_TD_THROTTLE_CNTL0 |
629 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 |
630 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
631 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
632 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
633 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L |
634 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
635 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
636 | #define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
637 | //DIDT_TD_THROTTLE_CNTL1 |
638 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
639 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
640 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
641 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
642 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
643 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
644 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
645 | #define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
646 | //DIDT_TD_THROTTLE_CNTL_STATUS |
647 | #define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 |
648 | #define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L |
649 | //DIDT_TD_WEIGHT0_3 |
650 | #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
651 | #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
652 | #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
653 | #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
654 | #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
655 | #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
656 | #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
657 | #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
658 | //DIDT_TD_WEIGHT4_7 |
659 | #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
660 | #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
661 | #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
662 | #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
663 | #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
664 | #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
665 | #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
666 | #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
667 | //DIDT_TD_WEIGHT8_11 |
668 | #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
669 | #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
670 | #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
671 | #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
672 | #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
673 | #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
674 | #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
675 | #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
676 | //DIDT_TD_EDC_CTRL |
677 | #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 |
678 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
679 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
680 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
681 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
682 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
683 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
684 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
685 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
686 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
687 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
688 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
689 | #define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L |
690 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
691 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
692 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
693 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
694 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
695 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
696 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
697 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
698 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
699 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
700 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
701 | //DIDT_TD_THROTTLE_CTRL |
702 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
703 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
704 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
705 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
706 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
707 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
708 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
709 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
710 | //DIDT_TD_EDC_STALL_PATTERN_1_2 |
711 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
712 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
713 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
714 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
715 | //DIDT_TD_EDC_STALL_PATTERN_3_4 |
716 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
717 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
718 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
719 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
720 | //DIDT_TD_EDC_STALL_PATTERN_5_6 |
721 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
722 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
723 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
724 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
725 | //DIDT_TD_EDC_STALL_PATTERN_7 |
726 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
727 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
728 | //DIDT_TD_EDC_STATUS |
729 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
730 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
731 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
732 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
733 | //DIDT_TD_EDC_STALL_DELAY_1 |
734 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 |
735 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x8 |
736 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0x10 |
737 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x18 |
738 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x000000FFL |
739 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x0000FF00L |
740 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x00FF0000L |
741 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0xFF000000L |
742 | //DIDT_TD_EDC_STALL_DELAY_2 |
743 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 |
744 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x8 |
745 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0x10 |
746 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x18 |
747 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x000000FFL |
748 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x0000FF00L |
749 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x00FF0000L |
750 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0xFF000000L |
751 | //DIDT_TD_EDC_STALL_DELAY_3 |
752 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 |
753 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x8 |
754 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0x10 |
755 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT 0x18 |
756 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x000000FFL |
757 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x0000FF00L |
758 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x00FF0000L |
759 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK 0xFF000000L |
760 | //DIDT_TD_EDC_STALL_DELAY_4 |
761 | #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT 0x0 |
762 | #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT 0x8 |
763 | #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK 0x000000FFL |
764 | #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK 0x0000FF00L |
765 | //DIDT_TD_EDC_OVERFLOW |
766 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
767 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
768 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
769 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
770 | //DIDT_TD_EDC_ROLLING_POWER_DELTA |
771 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
772 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
773 | //DIDT_TCP_CTRL0 |
774 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
775 | #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
776 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
777 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
778 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
779 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
780 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
781 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
782 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
783 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
784 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
785 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
786 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
787 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
788 | #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
789 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
790 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
791 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
792 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
793 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
794 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
795 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
796 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
797 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
798 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
799 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
800 | //DIDT_TCP_CTRL2 |
801 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
802 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
803 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
804 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
805 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
806 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
807 | //DIDT_TCP_STALL_CTRL |
808 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
809 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
810 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
811 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
812 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
813 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
814 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
815 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
816 | //DIDT_TCP_TUNING_CTRL |
817 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
818 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
819 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
820 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
821 | //DIDT_TCP_STALL_AUTO_RELEASE_CTRL |
822 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
823 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
824 | //DIDT_TCP_CTRL3 |
825 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
826 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
827 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
828 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
829 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
830 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
831 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
832 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
833 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
834 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
835 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
836 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
837 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
838 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
839 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
840 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
841 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
842 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
843 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
844 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
845 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
846 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
847 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
848 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
849 | //DIDT_TCP_STALL_PATTERN_1_2 |
850 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
851 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
852 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
853 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
854 | //DIDT_TCP_STALL_PATTERN_3_4 |
855 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
856 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
857 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
858 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
859 | //DIDT_TCP_STALL_PATTERN_5_6 |
860 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
861 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
862 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
863 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
864 | //DIDT_TCP_STALL_PATTERN_7 |
865 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
866 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
867 | //DIDT_TCP_MPD_SCALE_FACTOR |
868 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
869 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
870 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
871 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
872 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
873 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
874 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
875 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
876 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
877 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
878 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
879 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
880 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
881 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
882 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
883 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
884 | //DIDT_TCP_THROTTLE_CNTL0 |
885 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0 |
886 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
887 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
888 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
889 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L |
890 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
891 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
892 | #define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
893 | //DIDT_TCP_THROTTLE_CNTL1 |
894 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
895 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
896 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
897 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
898 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
899 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
900 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
901 | #define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
902 | //DIDT_TCP_THROTTLE_CNTL_STATUS |
903 | #define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0 |
904 | #define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L |
905 | //DIDT_TCP_WEIGHT0_3 |
906 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
907 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
908 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
909 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
910 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
911 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
912 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
913 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
914 | //DIDT_TCP_WEIGHT4_7 |
915 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
916 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
917 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
918 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
919 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
920 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
921 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
922 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
923 | //DIDT_TCP_WEIGHT8_11 |
924 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
925 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
926 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
927 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
928 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
929 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
930 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
931 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
932 | //DIDT_TCP_EDC_CTRL |
933 | #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 |
934 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
935 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
936 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
937 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
938 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
939 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
940 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
941 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
942 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
943 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
944 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
945 | #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L |
946 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
947 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
948 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
949 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
950 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
951 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
952 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
953 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
954 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
955 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
956 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
957 | //DIDT_TCP_THROTTLE_CTRL |
958 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
959 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
960 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
961 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
962 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
963 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
964 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
965 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
966 | //DIDT_TCP_EDC_STALL_PATTERN_1_2 |
967 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
968 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
969 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
970 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
971 | //DIDT_TCP_EDC_STALL_PATTERN_3_4 |
972 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
973 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
974 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
975 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
976 | //DIDT_TCP_EDC_STALL_PATTERN_5_6 |
977 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
978 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
979 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
980 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
981 | //DIDT_TCP_EDC_STALL_PATTERN_7 |
982 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
983 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
984 | //DIDT_TCP_EDC_STATUS |
985 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
986 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
987 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
988 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
989 | //DIDT_TCP_EDC_STALL_DELAY_1 |
990 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 |
991 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x8 |
992 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0x10 |
993 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x18 |
994 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x000000FFL |
995 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x0000FF00L |
996 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x00FF0000L |
997 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0xFF000000L |
998 | //DIDT_TCP_EDC_STALL_DELAY_2 |
999 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 |
1000 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x8 |
1001 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0x10 |
1002 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x18 |
1003 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x000000FFL |
1004 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x0000FF00L |
1005 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x00FF0000L |
1006 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0xFF000000L |
1007 | //DIDT_TCP_EDC_STALL_DELAY_3 |
1008 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 |
1009 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x8 |
1010 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0x10 |
1011 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT 0x18 |
1012 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x000000FFL |
1013 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x0000FF00L |
1014 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x00FF0000L |
1015 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK 0xFF000000L |
1016 | //DIDT_TCP_EDC_STALL_DELAY_4 |
1017 | #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT 0x0 |
1018 | #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT 0x8 |
1019 | #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK 0x000000FFL |
1020 | #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK 0x0000FF00L |
1021 | //DIDT_TCP_EDC_OVERFLOW |
1022 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
1023 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
1024 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
1025 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
1026 | //DIDT_TCP_EDC_ROLLING_POWER_DELTA |
1027 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
1028 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
1029 | //DIDT_SQ_STALL_EVENT_COUNTER |
1030 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
1031 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
1032 | //DIDT_DB_STALL_EVENT_COUNTER |
1033 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
1034 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
1035 | //DIDT_TD_STALL_EVENT_COUNTER |
1036 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
1037 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
1038 | //DIDT_TCP_STALL_EVENT_COUNTER |
1039 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
1040 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
1041 | //DIDT_DBR_STALL_EVENT_COUNTER |
1042 | #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
1043 | #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
1044 | //DIDT_SQ_EDC_PCC_PERF_COUNTER |
1045 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 |
1046 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL |
1047 | //DIDT_TD_EDC_PCC_PERF_COUNTER |
1048 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 |
1049 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL |
1050 | //DIDT_TCP_EDC_PCC_PERF_COUNTER |
1051 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 |
1052 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL |
1053 | //DIDT_DB_EDC_PCC_PERF_COUNTER |
1054 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 |
1055 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL |
1056 | //DIDT_DBR_EDC_PCC_PERF_COUNTER |
1057 | #define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER__SHIFT 0x0 |
1058 | #define DIDT_DBR_EDC_PCC_PERF_COUNTER__PERF_COUNTER_MASK 0xFFFFFFFFL |
1059 | //DIDT_SQ_CTRL1 |
1060 | #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 |
1061 | #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 |
1062 | #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
1063 | #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
1064 | //DIDT_SQ_EDC_THRESHOLD |
1065 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
1066 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
1067 | //DIDT_DB_CTRL1 |
1068 | #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 |
1069 | #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 |
1070 | #define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
1071 | #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
1072 | //DIDT_DB_EDC_THRESHOLD |
1073 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
1074 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
1075 | //DIDT_TD_CTRL1 |
1076 | #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 |
1077 | #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 |
1078 | #define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
1079 | #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
1080 | //DIDT_TD_EDC_THRESHOLD |
1081 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
1082 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
1083 | //DIDT_TCP_CTRL1 |
1084 | #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 |
1085 | #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 |
1086 | #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
1087 | #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
1088 | //DIDT_TCP_EDC_THRESHOLD |
1089 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
1090 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
1091 | |
1092 | |
1093 | // addressBlock: gc_cpdec |
1094 | //CP_CPC_STATUS |
1095 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 |
1096 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 |
1097 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 |
1098 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 |
1099 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 |
1100 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 |
1101 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 |
1102 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 |
1103 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa |
1104 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb |
1105 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc |
1106 | #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd |
1107 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe |
1108 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d |
1109 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e |
1110 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f |
1111 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L |
1112 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L |
1113 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L |
1114 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L |
1115 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L |
1116 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L |
1117 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L |
1118 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L |
1119 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L |
1120 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L |
1121 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L |
1122 | #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L |
1123 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L |
1124 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L |
1125 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L |
1126 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L |
1127 | //CP_CPC_BUSY_STAT |
1128 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 |
1129 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 |
1130 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 |
1131 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 |
1132 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 |
1133 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 |
1134 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 |
1135 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 |
1136 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 |
1137 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 |
1138 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa |
1139 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb |
1140 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc |
1141 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd |
1142 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 |
1143 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 |
1144 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 |
1145 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 |
1146 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 |
1147 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 |
1148 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 |
1149 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 |
1150 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 |
1151 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 |
1152 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a |
1153 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b |
1154 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c |
1155 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d |
1156 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L |
1157 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L |
1158 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L |
1159 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L |
1160 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L |
1161 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L |
1162 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L |
1163 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L |
1164 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L |
1165 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L |
1166 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L |
1167 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L |
1168 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L |
1169 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L |
1170 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L |
1171 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L |
1172 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L |
1173 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L |
1174 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L |
1175 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L |
1176 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L |
1177 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L |
1178 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L |
1179 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L |
1180 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L |
1181 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L |
1182 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L |
1183 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L |
1184 | //CP_CPC_STALLED_STAT1 |
1185 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 |
1186 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 |
1187 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 |
1188 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 |
1189 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 |
1190 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa |
1191 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd |
1192 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 |
1193 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 |
1194 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 |
1195 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 |
1196 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 |
1197 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 |
1198 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 |
1199 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L |
1200 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L |
1201 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L |
1202 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L |
1203 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L |
1204 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L |
1205 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L |
1206 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L |
1207 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L |
1208 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L |
1209 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L |
1210 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L |
1211 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L |
1212 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L |
1213 | //CP_CPF_STATUS |
1214 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 |
1215 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 |
1216 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 |
1217 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 |
1218 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 |
1219 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 |
1220 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 |
1221 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 |
1222 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa |
1223 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb |
1224 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc |
1225 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd |
1226 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe |
1227 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf |
1228 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 |
1229 | #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 |
1230 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a |
1231 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b |
1232 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c |
1233 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e |
1234 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f |
1235 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L |
1236 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L |
1237 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L |
1238 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L |
1239 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L |
1240 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L |
1241 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L |
1242 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L |
1243 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L |
1244 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L |
1245 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L |
1246 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L |
1247 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L |
1248 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L |
1249 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L |
1250 | #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L |
1251 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L |
1252 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L |
1253 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L |
1254 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L |
1255 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L |
1256 | //CP_CPF_BUSY_STAT |
1257 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
1258 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 |
1259 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 |
1260 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 |
1261 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 |
1262 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 |
1263 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 |
1264 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 |
1265 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 |
1266 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 |
1267 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb |
1268 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc |
1269 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd |
1270 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
1271 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf |
1272 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 |
1273 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 |
1274 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
1275 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 |
1276 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 |
1277 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 |
1278 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
1279 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
1280 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
1281 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 |
1282 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a |
1283 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
1284 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c |
1285 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d |
1286 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e |
1287 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f |
1288 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
1289 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L |
1290 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L |
1291 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L |
1292 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L |
1293 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L |
1294 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L |
1295 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L |
1296 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L |
1297 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L |
1298 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L |
1299 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L |
1300 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L |
1301 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
1302 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L |
1303 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L |
1304 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L |
1305 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
1306 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L |
1307 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L |
1308 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L |
1309 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
1310 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
1311 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
1312 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L |
1313 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L |
1314 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
1315 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L |
1316 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L |
1317 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L |
1318 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L |
1319 | //CP_CPF_STALLED_STAT1 |
1320 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 |
1321 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 |
1322 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 |
1323 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 |
1324 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 |
1325 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 |
1326 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 |
1327 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 |
1328 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 |
1329 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa |
1330 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb |
1331 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L |
1332 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L |
1333 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L |
1334 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L |
1335 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L |
1336 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L |
1337 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L |
1338 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L |
1339 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L |
1340 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L |
1341 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L |
1342 | //CP_CPC_GRBM_FREE_COUNT |
1343 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
1344 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
1345 | //CP_CPC_PRIV_VIOLATION_ADDR |
1346 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
1347 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL |
1348 | //CP_MEC_CNTL |
1349 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 |
1350 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 |
1351 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 |
1352 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 |
1353 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 |
1354 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 |
1355 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 |
1356 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c |
1357 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d |
1358 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e |
1359 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f |
1360 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L |
1361 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L |
1362 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L |
1363 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L |
1364 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L |
1365 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L |
1366 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L |
1367 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L |
1368 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L |
1369 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L |
1370 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L |
1371 | //CP_MEC_ME1_HEADER_DUMP |
1372 | #define 0x0 |
1373 | #define 0xFFFFFFFFL |
1374 | //CP_MEC_ME2_HEADER_DUMP |
1375 | #define 0x0 |
1376 | #define 0xFFFFFFFFL |
1377 | //CP_CPC_SCRATCH_INDEX |
1378 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
1379 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
1380 | //CP_CPC_SCRATCH_DATA |
1381 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
1382 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
1383 | //CP_CPF_GRBM_FREE_COUNT |
1384 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
1385 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L |
1386 | //CP_CPC_HALT_HYST_COUNT |
1387 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 |
1388 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL |
1389 | //CP_CE_COMPARE_COUNT |
1390 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 |
1391 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL |
1392 | //CP_CE_DE_COUNT |
1393 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
1394 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
1395 | //CP_DE_CE_COUNT |
1396 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 |
1397 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
1398 | //CP_DE_LAST_INVAL_COUNT |
1399 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 |
1400 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL |
1401 | //CP_DE_DE_COUNT |
1402 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
1403 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
1404 | //CP_STALLED_STAT3 |
1405 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
1406 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 |
1407 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 |
1408 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 |
1409 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 |
1410 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 |
1411 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 |
1412 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 |
1413 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa |
1414 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb |
1415 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc |
1416 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd |
1417 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe |
1418 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf |
1419 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 |
1420 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 |
1421 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 |
1422 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 |
1423 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 |
1424 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
1425 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L |
1426 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L |
1427 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L |
1428 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L |
1429 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L |
1430 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L |
1431 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L |
1432 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L |
1433 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L |
1434 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L |
1435 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L |
1436 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L |
1437 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L |
1438 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L |
1439 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L |
1440 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L |
1441 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L |
1442 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L |
1443 | //CP_STALLED_STAT1 |
1444 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 |
1445 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 |
1446 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 |
1447 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa |
1448 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb |
1449 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc |
1450 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd |
1451 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe |
1452 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf |
1453 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 |
1454 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 |
1455 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 |
1456 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a |
1457 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b |
1458 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c |
1459 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d |
1460 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L |
1461 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L |
1462 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L |
1463 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L |
1464 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L |
1465 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L |
1466 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L |
1467 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L |
1468 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L |
1469 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L |
1470 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L |
1471 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L |
1472 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L |
1473 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L |
1474 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L |
1475 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L |
1476 | //CP_STALLED_STAT2 |
1477 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
1478 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 |
1479 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 |
1480 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 |
1481 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 |
1482 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 |
1483 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 |
1484 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa |
1485 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb |
1486 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc |
1487 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd |
1488 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe |
1489 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf |
1490 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 |
1491 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 |
1492 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 |
1493 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 |
1494 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 |
1495 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 |
1496 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 |
1497 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 |
1498 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 |
1499 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 |
1500 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a |
1501 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b |
1502 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c |
1503 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d |
1504 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e |
1505 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f |
1506 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
1507 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L |
1508 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L |
1509 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L |
1510 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L |
1511 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L |
1512 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L |
1513 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L |
1514 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L |
1515 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L |
1516 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L |
1517 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L |
1518 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L |
1519 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L |
1520 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L |
1521 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L |
1522 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L |
1523 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L |
1524 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L |
1525 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L |
1526 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L |
1527 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L |
1528 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L |
1529 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L |
1530 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L |
1531 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L |
1532 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L |
1533 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L |
1534 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L |
1535 | //CP_BUSY_STAT |
1536 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
1537 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 |
1538 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 |
1539 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 |
1540 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 |
1541 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa |
1542 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc |
1543 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd |
1544 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe |
1545 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf |
1546 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 |
1547 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 |
1548 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 |
1549 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 |
1550 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 |
1551 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 |
1552 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
1553 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L |
1554 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L |
1555 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L |
1556 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L |
1557 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L |
1558 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L |
1559 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L |
1560 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L |
1561 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L |
1562 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L |
1563 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L |
1564 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L |
1565 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L |
1566 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L |
1567 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L |
1568 | //CP_STAT |
1569 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 |
1570 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa |
1571 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb |
1572 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc |
1573 | #define CP_STAT__DC_BUSY__SHIFT 0xd |
1574 | #define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe |
1575 | #define CP_STAT__PFP_BUSY__SHIFT 0xf |
1576 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 |
1577 | #define CP_STAT__ME_BUSY__SHIFT 0x11 |
1578 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 |
1579 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 |
1580 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 |
1581 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 |
1582 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 |
1583 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 |
1584 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 |
1585 | #define CP_STAT__CE_BUSY__SHIFT 0x1a |
1586 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b |
1587 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c |
1588 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d |
1589 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e |
1590 | #define CP_STAT__CP_BUSY__SHIFT 0x1f |
1591 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L |
1592 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L |
1593 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L |
1594 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L |
1595 | #define CP_STAT__DC_BUSY_MASK 0x00002000L |
1596 | #define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L |
1597 | #define CP_STAT__PFP_BUSY_MASK 0x00008000L |
1598 | #define CP_STAT__MEQ_BUSY_MASK 0x00010000L |
1599 | #define CP_STAT__ME_BUSY_MASK 0x00020000L |
1600 | #define CP_STAT__QUERY_BUSY_MASK 0x00040000L |
1601 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L |
1602 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L |
1603 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L |
1604 | #define CP_STAT__DMA_BUSY_MASK 0x00400000L |
1605 | #define CP_STAT__RCIU_BUSY_MASK 0x00800000L |
1606 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L |
1607 | #define CP_STAT__CE_BUSY_MASK 0x04000000L |
1608 | #define CP_STAT__TCIU_BUSY_MASK 0x08000000L |
1609 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L |
1610 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L |
1611 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L |
1612 | #define CP_STAT__CP_BUSY_MASK 0x80000000L |
1613 | //CP_ME_HEADER_DUMP |
1614 | #define 0x0 |
1615 | #define 0xFFFFFFFFL |
1616 | //CP_PFP_HEADER_DUMP |
1617 | #define 0x0 |
1618 | #define 0xFFFFFFFFL |
1619 | //CP_GRBM_FREE_COUNT |
1620 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
1621 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 |
1622 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 |
1623 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
1624 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L |
1625 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L |
1626 | //CP_CE_HEADER_DUMP |
1627 | #define 0x0 |
1628 | #define 0xFFFFFFFFL |
1629 | //CP_PFP_INSTR_PNTR |
1630 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
1631 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
1632 | //CP_ME_INSTR_PNTR |
1633 | #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
1634 | #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
1635 | //CP_CE_INSTR_PNTR |
1636 | #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
1637 | #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
1638 | //CP_MEC1_INSTR_PNTR |
1639 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
1640 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
1641 | //CP_MEC2_INSTR_PNTR |
1642 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
1643 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
1644 | //CP_CSF_STAT |
1645 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 |
1646 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L |
1647 | //CP_ME_CNTL |
1648 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 |
1649 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 |
1650 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 |
1651 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 |
1652 | #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 |
1653 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 |
1654 | #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 |
1655 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 |
1656 | #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 |
1657 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 |
1658 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 |
1659 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a |
1660 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b |
1661 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c |
1662 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d |
1663 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L |
1664 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L |
1665 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L |
1666 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L |
1667 | #define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L |
1668 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L |
1669 | #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L |
1670 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L |
1671 | #define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L |
1672 | #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L |
1673 | #define CP_ME_CNTL__CE_STEP_MASK 0x02000000L |
1674 | #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L |
1675 | #define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L |
1676 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L |
1677 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000L |
1678 | //CP_CNTX_STAT |
1679 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 |
1680 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 |
1681 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 |
1682 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c |
1683 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL |
1684 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L |
1685 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L |
1686 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L |
1687 | //CP_ME_PREEMPTION |
1688 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 |
1689 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L |
1690 | //CP_ROQ_THRESHOLDS |
1691 | #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 |
1692 | #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 |
1693 | #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL |
1694 | #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L |
1695 | //CP_MEQ_STQ_THRESHOLD |
1696 | #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 |
1697 | #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL |
1698 | //CP_RB2_RPTR |
1699 | #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 |
1700 | #define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL |
1701 | //CP_RB1_RPTR |
1702 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 |
1703 | #define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL |
1704 | //CP_RB0_RPTR |
1705 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 |
1706 | #define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL |
1707 | //CP_RB_RPTR |
1708 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 |
1709 | #define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL |
1710 | //CP_RB_WPTR_DELAY |
1711 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 |
1712 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c |
1713 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL |
1714 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L |
1715 | //CP_RB_WPTR_POLL_CNTL |
1716 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 |
1717 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1718 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL |
1719 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1720 | //CP_ROQ1_THRESHOLDS |
1721 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 |
1722 | #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 |
1723 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 |
1724 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 |
1725 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL |
1726 | #define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L |
1727 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L |
1728 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L |
1729 | //CP_ROQ2_THRESHOLDS |
1730 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 |
1731 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 |
1732 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 |
1733 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 |
1734 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL |
1735 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L |
1736 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L |
1737 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L |
1738 | //CP_STQ_THRESHOLDS |
1739 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 |
1740 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 |
1741 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 |
1742 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL |
1743 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L |
1744 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L |
1745 | //CP_QUEUE_THRESHOLDS |
1746 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 |
1747 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 |
1748 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL |
1749 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L |
1750 | //CP_MEQ_THRESHOLDS |
1751 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 |
1752 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 |
1753 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL |
1754 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L |
1755 | //CP_ROQ_AVAIL |
1756 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 |
1757 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 |
1758 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL |
1759 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L |
1760 | //CP_STQ_AVAIL |
1761 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 |
1762 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL |
1763 | //CP_ROQ2_AVAIL |
1764 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 |
1765 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL |
1766 | //CP_MEQ_AVAIL |
1767 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 |
1768 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL |
1769 | //CP_CMD_INDEX |
1770 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 |
1771 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc |
1772 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 |
1773 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL |
1774 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L |
1775 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L |
1776 | //CP_CMD_DATA |
1777 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 |
1778 | #define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL |
1779 | //CP_ROQ_RB_STAT |
1780 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 |
1781 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 |
1782 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL |
1783 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L |
1784 | //CP_ROQ_IB1_STAT |
1785 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 |
1786 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 |
1787 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL |
1788 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L |
1789 | //CP_ROQ_IB2_STAT |
1790 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 |
1791 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 |
1792 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL |
1793 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L |
1794 | //CP_STQ_STAT |
1795 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 |
1796 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL |
1797 | //CP_STQ_WR_STAT |
1798 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 |
1799 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL |
1800 | //CP_MEQ_STAT |
1801 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 |
1802 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 |
1803 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL |
1804 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L |
1805 | //CP_CEQ1_AVAIL |
1806 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 |
1807 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 |
1808 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL |
1809 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L |
1810 | //CP_CEQ2_AVAIL |
1811 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 |
1812 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL |
1813 | //CP_CE_ROQ_RB_STAT |
1814 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 |
1815 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 |
1816 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL |
1817 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L |
1818 | //CP_CE_ROQ_IB1_STAT |
1819 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 |
1820 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 |
1821 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL |
1822 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L |
1823 | //CP_CE_ROQ_IB2_STAT |
1824 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 |
1825 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 |
1826 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL |
1827 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L |
1828 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 |
1829 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
1830 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L |
1831 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
1832 | //CP_PRIV_VIOLATION_ADDR |
1833 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
1834 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL |
1835 | |
1836 | |
1837 | // addressBlock: gc_cppdec |
1838 | //CP_EOPQ_WAIT_TIME |
1839 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 |
1840 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa |
1841 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL |
1842 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L |
1843 | //CP_CPC_MGCG_SYNC_CNTL |
1844 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 |
1845 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 |
1846 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL |
1847 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L |
1848 | //CPC_INT_INFO |
1849 | #define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 |
1850 | #define CPC_INT_INFO__TYPE__SHIFT 0x10 |
1851 | #define CPC_INT_INFO__VMID__SHIFT 0x14 |
1852 | #define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c |
1853 | #define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL |
1854 | #define CPC_INT_INFO__TYPE_MASK 0x00010000L |
1855 | #define CPC_INT_INFO__VMID_MASK 0x00F00000L |
1856 | #define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L |
1857 | //CP_VIRT_STATUS |
1858 | #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 |
1859 | #define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL |
1860 | //CPC_INT_ADDR |
1861 | #define CPC_INT_ADDR__ADDR__SHIFT 0x0 |
1862 | #define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL |
1863 | //CPC_INT_PASID |
1864 | #define CPC_INT_PASID__PASID__SHIFT 0x0 |
1865 | #define CPC_INT_PASID__PASID_MASK 0x0000FFFFL |
1866 | //CP_GFX_ERROR |
1867 | #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
1868 | #define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 |
1869 | #define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 |
1870 | #define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 |
1871 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 |
1872 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 |
1873 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 |
1874 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa |
1875 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb |
1876 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc |
1877 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd |
1878 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe |
1879 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf |
1880 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 |
1881 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 |
1882 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 |
1883 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 |
1884 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 |
1885 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 |
1886 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 |
1887 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 |
1888 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 |
1889 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 |
1890 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a |
1891 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b |
1892 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c |
1893 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d |
1894 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e |
1895 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f |
1896 | #define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
1897 | #define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L |
1898 | #define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L |
1899 | #define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L |
1900 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L |
1901 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L |
1902 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L |
1903 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L |
1904 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L |
1905 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L |
1906 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L |
1907 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L |
1908 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L |
1909 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L |
1910 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L |
1911 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L |
1912 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L |
1913 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L |
1914 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L |
1915 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L |
1916 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L |
1917 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L |
1918 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L |
1919 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L |
1920 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L |
1921 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L |
1922 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L |
1923 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L |
1924 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L |
1925 | //CPG_UTCL1_CNTL |
1926 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
1927 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
1928 | #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
1929 | #define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
1930 | #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
1931 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
1932 | #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
1933 | #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
1934 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
1935 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
1936 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
1937 | #define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
1938 | #define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
1939 | #define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
1940 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
1941 | #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
1942 | #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
1943 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
1944 | //CPC_UTCL1_CNTL |
1945 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
1946 | #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
1947 | #define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
1948 | #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
1949 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
1950 | #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
1951 | #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
1952 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
1953 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
1954 | #define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
1955 | #define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
1956 | #define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
1957 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
1958 | #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
1959 | #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
1960 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
1961 | //CPF_UTCL1_CNTL |
1962 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
1963 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
1964 | #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
1965 | #define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
1966 | #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
1967 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
1968 | #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
1969 | #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
1970 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
1971 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f |
1972 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
1973 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
1974 | #define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
1975 | #define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
1976 | #define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
1977 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
1978 | #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
1979 | #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
1980 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
1981 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L |
1982 | //CP_AQL_SMM_STATUS |
1983 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 |
1984 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL |
1985 | //CP_RB0_BASE |
1986 | #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 |
1987 | #define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL |
1988 | //CP_RB_BASE |
1989 | #define CP_RB_BASE__RB_BASE__SHIFT 0x0 |
1990 | #define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL |
1991 | //CP_RB0_CNTL |
1992 | #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 |
1993 | #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 |
1994 | #define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 |
1995 | #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
1996 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
1997 | #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 |
1998 | #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
1999 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
2000 | #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL |
2001 | #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L |
2002 | #define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L |
2003 | #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
2004 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
2005 | #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L |
2006 | #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
2007 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
2008 | //CP_RB_CNTL |
2009 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
2010 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
2011 | #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
2012 | #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
2013 | #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 |
2014 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
2015 | #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
2016 | #define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL |
2017 | #define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L |
2018 | #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
2019 | #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
2020 | #define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L |
2021 | #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
2022 | #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
2023 | //CP_RB_RPTR_WR |
2024 | #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
2025 | #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
2026 | //CP_RB0_RPTR_ADDR |
2027 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
2028 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
2029 | //CP_RB_RPTR_ADDR |
2030 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
2031 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
2032 | //CP_RB0_RPTR_ADDR_HI |
2033 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
2034 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
2035 | //CP_RB_RPTR_ADDR_HI |
2036 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
2037 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
2038 | //CP_RB0_BUFSZ_MASK |
2039 | #define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 |
2040 | #define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
2041 | //CP_RB_BUFSZ_MASK |
2042 | #define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 |
2043 | #define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
2044 | //CP_RB_WPTR_POLL_ADDR_LO |
2045 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
2046 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
2047 | //CP_RB_WPTR_POLL_ADDR_HI |
2048 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
2049 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
2050 | //CP_INT_CNTL |
2051 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
2052 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2053 | #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2054 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2055 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
2056 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
2057 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
2058 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
2059 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
2060 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2061 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2062 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2063 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2064 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2065 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2066 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2067 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
2068 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2069 | #define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2070 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2071 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
2072 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
2073 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
2074 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
2075 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
2076 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2077 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2078 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2079 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2080 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2081 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2082 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2083 | //CP_INT_STATUS |
2084 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
2085 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
2086 | #define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 |
2087 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
2088 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 |
2089 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
2090 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
2091 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 |
2092 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
2093 | #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 |
2094 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
2095 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a |
2096 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
2097 | #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d |
2098 | #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e |
2099 | #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f |
2100 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
2101 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
2102 | #define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L |
2103 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
2104 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L |
2105 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
2106 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
2107 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L |
2108 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
2109 | #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L |
2110 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
2111 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L |
2112 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
2113 | #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L |
2114 | #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L |
2115 | #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L |
2116 | //CP_DEVICE_ID |
2117 | #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
2118 | #define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL |
2119 | //CP_ME0_PIPE_PRIORITY_CNTS |
2120 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
2121 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
2122 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
2123 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
2124 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
2125 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
2126 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
2127 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
2128 | //CP_RING_PRIORITY_CNTS |
2129 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
2130 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
2131 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
2132 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
2133 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
2134 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
2135 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
2136 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
2137 | //CP_ME0_PIPE0_PRIORITY |
2138 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
2139 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
2140 | //CP_RING0_PRIORITY |
2141 | #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 |
2142 | #define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L |
2143 | //CP_ME0_PIPE1_PRIORITY |
2144 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
2145 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
2146 | //CP_RING1_PRIORITY |
2147 | #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 |
2148 | #define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L |
2149 | //CP_ME0_PIPE2_PRIORITY |
2150 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
2151 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
2152 | //CP_RING2_PRIORITY |
2153 | #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 |
2154 | #define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L |
2155 | //CP_FATAL_ERROR |
2156 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 |
2157 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 |
2158 | #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 |
2159 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 |
2160 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 |
2161 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L |
2162 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L |
2163 | #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L |
2164 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L |
2165 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L |
2166 | //CP_RB_VMID |
2167 | #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 |
2168 | #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 |
2169 | #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 |
2170 | #define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL |
2171 | #define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L |
2172 | #define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L |
2173 | //CP_ME0_PIPE0_VMID |
2174 | #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 |
2175 | #define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL |
2176 | //CP_ME0_PIPE1_VMID |
2177 | #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 |
2178 | #define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL |
2179 | //CP_RB0_WPTR |
2180 | #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 |
2181 | #define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
2182 | //CP_RB_WPTR |
2183 | #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 |
2184 | #define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
2185 | //CP_RB0_WPTR_HI |
2186 | #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 |
2187 | #define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
2188 | //CP_RB_WPTR_HI |
2189 | #define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 |
2190 | #define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
2191 | //CP_RB1_WPTR |
2192 | #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 |
2193 | #define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
2194 | //CP_RB1_WPTR_HI |
2195 | #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 |
2196 | #define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
2197 | //CP_RB2_WPTR |
2198 | #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 |
2199 | #define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL |
2200 | //CP_RB_DOORBELL_CONTROL |
2201 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
2202 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
2203 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
2204 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
2205 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
2206 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
2207 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
2208 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
2209 | //CP_RB_DOORBELL_RANGE_LOWER |
2210 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
2211 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL |
2212 | //CP_RB_DOORBELL_RANGE_UPPER |
2213 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
2214 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL |
2215 | //CP_MEC_DOORBELL_RANGE_LOWER |
2216 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
2217 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL |
2218 | //CP_MEC_DOORBELL_RANGE_UPPER |
2219 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
2220 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL |
2221 | //CPG_UTCL1_ERROR |
2222 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
2223 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
2224 | //CPC_UTCL1_ERROR |
2225 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
2226 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
2227 | //CP_RB1_BASE |
2228 | #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 |
2229 | #define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL |
2230 | //CP_RB1_CNTL |
2231 | #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 |
2232 | #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 |
2233 | #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
2234 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
2235 | #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 |
2236 | #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
2237 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
2238 | #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL |
2239 | #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L |
2240 | #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
2241 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
2242 | #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L |
2243 | #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
2244 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
2245 | //CP_RB1_RPTR_ADDR |
2246 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
2247 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
2248 | //CP_RB1_RPTR_ADDR_HI |
2249 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
2250 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
2251 | //CP_RB2_BASE |
2252 | #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 |
2253 | #define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL |
2254 | //CP_RB2_CNTL |
2255 | #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 |
2256 | #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 |
2257 | #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
2258 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
2259 | #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 |
2260 | #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
2261 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
2262 | #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL |
2263 | #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L |
2264 | #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
2265 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
2266 | #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L |
2267 | #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
2268 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
2269 | //CP_RB2_RPTR_ADDR |
2270 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
2271 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
2272 | //CP_RB2_RPTR_ADDR_HI |
2273 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
2274 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
2275 | //CP_RB0_ACTIVE |
2276 | #define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 |
2277 | #define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L |
2278 | //CP_RB_ACTIVE |
2279 | #define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 |
2280 | #define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L |
2281 | //CP_INT_CNTL_RING0 |
2282 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
2283 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2284 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 |
2285 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2286 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
2287 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
2288 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
2289 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
2290 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
2291 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2292 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2293 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2294 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2295 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2296 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2297 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2298 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
2299 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2300 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L |
2301 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2302 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
2303 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
2304 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
2305 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
2306 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
2307 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2308 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2309 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2310 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2311 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2312 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2313 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2314 | //CP_INT_CNTL_RING1 |
2315 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
2316 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2317 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 |
2318 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2319 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
2320 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
2321 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
2322 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
2323 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
2324 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2325 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2326 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2327 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2328 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2329 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2330 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2331 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
2332 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2333 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L |
2334 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2335 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
2336 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
2337 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
2338 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
2339 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
2340 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2341 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2342 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2343 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2344 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2345 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2346 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2347 | //CP_INT_CNTL_RING2 |
2348 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
2349 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2350 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 |
2351 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2352 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
2353 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
2354 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
2355 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
2356 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
2357 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2358 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2359 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2360 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2361 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2362 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2363 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2364 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
2365 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2366 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L |
2367 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2368 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
2369 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
2370 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
2371 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
2372 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
2373 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2374 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2375 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2376 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2377 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2378 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2379 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2380 | //CP_INT_STATUS_RING0 |
2381 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
2382 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
2383 | #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 |
2384 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
2385 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 |
2386 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 |
2387 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
2388 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 |
2389 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
2390 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 |
2391 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
2392 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a |
2393 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
2394 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d |
2395 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e |
2396 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f |
2397 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
2398 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
2399 | #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L |
2400 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
2401 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L |
2402 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L |
2403 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
2404 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L |
2405 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
2406 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L |
2407 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
2408 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L |
2409 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
2410 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L |
2411 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L |
2412 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L |
2413 | //CP_INT_STATUS_RING1 |
2414 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
2415 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
2416 | #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 |
2417 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
2418 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 |
2419 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
2420 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
2421 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 |
2422 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
2423 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 |
2424 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
2425 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a |
2426 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
2427 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d |
2428 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e |
2429 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f |
2430 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
2431 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
2432 | #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L |
2433 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
2434 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L |
2435 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
2436 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
2437 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L |
2438 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
2439 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L |
2440 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
2441 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L |
2442 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
2443 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L |
2444 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L |
2445 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L |
2446 | //CP_INT_STATUS_RING2 |
2447 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
2448 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
2449 | #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 |
2450 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
2451 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 |
2452 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
2453 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
2454 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 |
2455 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
2456 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 |
2457 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
2458 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a |
2459 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
2460 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d |
2461 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e |
2462 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f |
2463 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
2464 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
2465 | #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L |
2466 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
2467 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L |
2468 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
2469 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
2470 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L |
2471 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
2472 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L |
2473 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
2474 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L |
2475 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
2476 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L |
2477 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L |
2478 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L |
2479 | //CP_ME_F32_INTERRUPT |
2480 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
2481 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 |
2482 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 |
2483 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 |
2484 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
2485 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L |
2486 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L |
2487 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L |
2488 | //CP_PFP_F32_INTERRUPT |
2489 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
2490 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
2491 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
2492 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 |
2493 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
2494 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
2495 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
2496 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L |
2497 | //CP_CE_F32_INTERRUPT |
2498 | #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
2499 | #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x1 |
2500 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x2 |
2501 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x3 |
2502 | #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
2503 | #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L |
2504 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L |
2505 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L |
2506 | //CP_MEC1_F32_INTERRUPT |
2507 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
2508 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
2509 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
2510 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
2511 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
2512 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
2513 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
2514 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
2515 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
2516 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
2517 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
2518 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
2519 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
2520 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
2521 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
2522 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
2523 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
2524 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
2525 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
2526 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
2527 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
2528 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
2529 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
2530 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
2531 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
2532 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
2533 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
2534 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
2535 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
2536 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
2537 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
2538 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
2539 | //CP_MEC2_F32_INTERRUPT |
2540 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
2541 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
2542 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
2543 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
2544 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
2545 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
2546 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
2547 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
2548 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
2549 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
2550 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
2551 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
2552 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
2553 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
2554 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
2555 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
2556 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
2557 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
2558 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
2559 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
2560 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
2561 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
2562 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
2563 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
2564 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
2565 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
2566 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
2567 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
2568 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
2569 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
2570 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
2571 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
2572 | //CP_PWR_CNTL |
2573 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 |
2574 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 |
2575 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 |
2576 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 |
2577 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa |
2578 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb |
2579 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 |
2580 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 |
2581 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 |
2582 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 |
2583 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L |
2584 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L |
2585 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L |
2586 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L |
2587 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L |
2588 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L |
2589 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L |
2590 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L |
2591 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L |
2592 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L |
2593 | //CP_MEM_SLP_CNTL |
2594 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 |
2595 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 |
2596 | #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
2597 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
2598 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 |
2599 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 |
2600 | #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
2601 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L |
2602 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L |
2603 | #define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
2604 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
2605 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
2606 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
2607 | #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
2608 | //CP_ECC_DMA_FIRST_OCCURRENCE |
2609 | #define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE__SHIFT 0x0 |
2610 | #define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT__SHIFT 0x4 |
2611 | #define CP_ECC_DMA_FIRST_OCCURRENCE__ME__SHIFT 0x8 |
2612 | #define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE__SHIFT 0xa |
2613 | #define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE__SHIFT 0xc |
2614 | #define CP_ECC_DMA_FIRST_OCCURRENCE__VMID__SHIFT 0x10 |
2615 | #define CP_ECC_DMA_FIRST_OCCURRENCE__INTERFACE_MASK 0x00000003L |
2616 | #define CP_ECC_DMA_FIRST_OCCURRENCE__CLIENT_MASK 0x000000F0L |
2617 | #define CP_ECC_DMA_FIRST_OCCURRENCE__ME_MASK 0x00000300L |
2618 | #define CP_ECC_DMA_FIRST_OCCURRENCE__PIPE_MASK 0x00000C00L |
2619 | #define CP_ECC_DMA_FIRST_OCCURRENCE__QUEUE_MASK 0x00007000L |
2620 | #define CP_ECC_DMA_FIRST_OCCURRENCE__VMID_MASK 0x000F0000L |
2621 | //CP_ECC_FIRSTOCCURRENCE |
2622 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 |
2623 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 |
2624 | #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 |
2625 | #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa |
2626 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc |
2627 | #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 |
2628 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L |
2629 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L |
2630 | #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L |
2631 | #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L |
2632 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L |
2633 | #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L |
2634 | //CP_ECC_FIRSTOCCURRENCE_RING0 |
2635 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 |
2636 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL |
2637 | //CP_ECC_FIRSTOCCURRENCE_RING1 |
2638 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 |
2639 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL |
2640 | //CP_ECC_FIRSTOCCURRENCE_RING2 |
2641 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 |
2642 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL |
2643 | //GB_EDC_MODE |
2644 | #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
2645 | #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
2646 | #define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 |
2647 | #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 |
2648 | #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d |
2649 | #define GB_EDC_MODE__BYPASS__SHIFT 0x1f |
2650 | #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
2651 | #define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
2652 | #define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L |
2653 | #define GB_EDC_MODE__DED_MODE_MASK 0x00300000L |
2654 | #define GB_EDC_MODE__PROP_FED_MASK 0x20000000L |
2655 | #define GB_EDC_MODE__BYPASS_MASK 0x80000000L |
2656 | //CP_PQ_WPTR_POLL_CNTL |
2657 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 |
2658 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d |
2659 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e |
2660 | #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f |
2661 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL |
2662 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L |
2663 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L |
2664 | #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L |
2665 | //CP_PQ_WPTR_POLL_CNTL1 |
2666 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 |
2667 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL |
2668 | //CP_ME1_PIPE0_INT_CNTL |
2669 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2670 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2671 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2672 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2673 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2674 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2675 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2676 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2677 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2678 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2679 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2680 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2681 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2682 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2683 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2684 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2685 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2686 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2687 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2688 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2689 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2690 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2691 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2692 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2693 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2694 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2695 | //CP_ME1_PIPE1_INT_CNTL |
2696 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2697 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2698 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2699 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2700 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2701 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2702 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2703 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2704 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2705 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2706 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2707 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2708 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2709 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2710 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2711 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2712 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2713 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2714 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2715 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2716 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2717 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2718 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2719 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2720 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2721 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2722 | //CP_ME1_PIPE2_INT_CNTL |
2723 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2724 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2725 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2726 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2727 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2728 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2729 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2730 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2731 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2732 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2733 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2734 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2735 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2736 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2737 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2738 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2739 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2740 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2741 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2742 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2743 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2744 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2745 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2746 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2747 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2748 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2749 | //CP_ME1_PIPE3_INT_CNTL |
2750 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2751 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2752 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2753 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2754 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2755 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2756 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2757 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2758 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2759 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2760 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2761 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2762 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2763 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2764 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2765 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2766 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2767 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2768 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2769 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2770 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2771 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2772 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2773 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2774 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2775 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2776 | //CP_ME2_PIPE0_INT_CNTL |
2777 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2778 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2779 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2780 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2781 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2782 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2783 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2784 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2785 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2786 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2787 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2788 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2789 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2790 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2791 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2792 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2793 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2794 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2795 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2796 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2797 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2798 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2799 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2800 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2801 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2802 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2803 | //CP_ME2_PIPE1_INT_CNTL |
2804 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2805 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2806 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2807 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2808 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2809 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2810 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2811 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2812 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2813 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2814 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2815 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2816 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2817 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2818 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2819 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2820 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2821 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2822 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2823 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2824 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2825 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2826 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2827 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2828 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2829 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2830 | //CP_ME2_PIPE2_INT_CNTL |
2831 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2832 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2833 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2834 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2835 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2836 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2837 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2838 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2839 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2840 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2841 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2842 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2843 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2844 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2845 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2846 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2847 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2848 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2849 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2850 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2851 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2852 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2853 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2854 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2855 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2856 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2857 | //CP_ME2_PIPE3_INT_CNTL |
2858 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
2859 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
2860 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
2861 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
2862 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
2863 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
2864 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
2865 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
2866 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
2867 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
2868 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
2869 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
2870 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
2871 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
2872 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
2873 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
2874 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
2875 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
2876 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
2877 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
2878 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
2879 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
2880 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
2881 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
2882 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
2883 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
2884 | //CP_ME1_PIPE0_INT_STATUS |
2885 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
2886 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
2887 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
2888 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
2889 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
2890 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
2891 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
2892 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
2893 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
2894 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
2895 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
2896 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
2897 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
2898 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
2899 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
2900 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
2901 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
2902 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
2903 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
2904 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
2905 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
2906 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
2907 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
2908 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
2909 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
2910 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
2911 | //CP_ME1_PIPE1_INT_STATUS |
2912 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
2913 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
2914 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
2915 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
2916 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
2917 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
2918 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
2919 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
2920 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
2921 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
2922 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
2923 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
2924 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
2925 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
2926 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
2927 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
2928 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
2929 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
2930 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
2931 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
2932 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
2933 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
2934 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
2935 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
2936 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
2937 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
2938 | //CP_ME1_PIPE2_INT_STATUS |
2939 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
2940 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
2941 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
2942 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
2943 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
2944 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
2945 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
2946 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
2947 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
2948 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
2949 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
2950 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
2951 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
2952 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
2953 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
2954 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
2955 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
2956 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
2957 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
2958 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
2959 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
2960 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
2961 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
2962 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
2963 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
2964 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
2965 | //CP_ME1_PIPE3_INT_STATUS |
2966 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
2967 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
2968 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
2969 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
2970 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
2971 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
2972 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
2973 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
2974 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
2975 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
2976 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
2977 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
2978 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
2979 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
2980 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
2981 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
2982 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
2983 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
2984 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
2985 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
2986 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
2987 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
2988 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
2989 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
2990 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
2991 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
2992 | //CP_ME1_INT_STAT_DEBUG |
2993 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
2994 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
2995 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
2996 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
2997 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
2998 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
2999 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
3000 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
3001 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
3002 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
3003 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
3004 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
3005 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
3006 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
3007 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
3008 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
3009 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3010 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
3011 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
3012 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
3013 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
3014 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
3015 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
3016 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
3017 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
3018 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
3019 | //CP_ME2_INT_STAT_DEBUG |
3020 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
3021 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
3022 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
3023 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3024 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
3025 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
3026 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
3027 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
3028 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
3029 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
3030 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
3031 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
3032 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
3033 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
3034 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
3035 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
3036 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3037 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
3038 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
3039 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
3040 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
3041 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
3042 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
3043 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
3044 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
3045 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
3046 | //CP_ME2_PIPE0_INT_STATUS |
3047 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
3048 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
3049 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
3050 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3051 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
3052 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
3053 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
3054 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
3055 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
3056 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
3057 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
3058 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
3059 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
3060 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
3061 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
3062 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
3063 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3064 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
3065 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
3066 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
3067 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
3068 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
3069 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
3070 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
3071 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
3072 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
3073 | //CP_ME2_PIPE1_INT_STATUS |
3074 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
3075 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
3076 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
3077 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3078 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
3079 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
3080 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
3081 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
3082 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
3083 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
3084 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
3085 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
3086 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
3087 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
3088 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
3089 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
3090 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3091 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
3092 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
3093 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
3094 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
3095 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
3096 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
3097 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
3098 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
3099 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
3100 | //CP_ME2_PIPE2_INT_STATUS |
3101 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
3102 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
3103 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
3104 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3105 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
3106 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
3107 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
3108 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
3109 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
3110 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
3111 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
3112 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
3113 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
3114 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
3115 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
3116 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
3117 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3118 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
3119 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
3120 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
3121 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
3122 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
3123 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
3124 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
3125 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
3126 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
3127 | //CP_ME2_PIPE3_INT_STATUS |
3128 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
3129 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
3130 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
3131 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3132 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
3133 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
3134 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
3135 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
3136 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
3137 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
3138 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
3139 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
3140 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
3141 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
3142 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
3143 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
3144 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3145 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
3146 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
3147 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
3148 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
3149 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
3150 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
3151 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
3152 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
3153 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
3154 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
3155 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
3156 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
3157 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
3158 | //CC_GC_EDC_CONFIG |
3159 | #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
3160 | #define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK__SHIFT 0x2 |
3161 | #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
3162 | #define CC_GC_EDC_CONFIG__ENABLE_IRRITATOR_CLK_MASK 0x00000004L |
3163 | //CP_ME1_PIPE_PRIORITY_CNTS |
3164 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
3165 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
3166 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
3167 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
3168 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
3169 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
3170 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
3171 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
3172 | //CP_ME1_PIPE0_PRIORITY |
3173 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
3174 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
3175 | //CP_ME1_PIPE1_PRIORITY |
3176 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
3177 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
3178 | //CP_ME1_PIPE2_PRIORITY |
3179 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
3180 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
3181 | //CP_ME1_PIPE3_PRIORITY |
3182 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
3183 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
3184 | //CP_ME2_PIPE_PRIORITY_CNTS |
3185 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
3186 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
3187 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
3188 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
3189 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
3190 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
3191 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
3192 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
3193 | //CP_ME2_PIPE0_PRIORITY |
3194 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
3195 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
3196 | //CP_ME2_PIPE1_PRIORITY |
3197 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
3198 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
3199 | //CP_ME2_PIPE2_PRIORITY |
3200 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
3201 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
3202 | //CP_ME2_PIPE3_PRIORITY |
3203 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
3204 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
3205 | //CP_CE_PRGRM_CNTR_START |
3206 | #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
3207 | #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL |
3208 | //CP_PFP_PRGRM_CNTR_START |
3209 | #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
3210 | #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL |
3211 | //CP_ME_PRGRM_CNTR_START |
3212 | #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
3213 | #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL |
3214 | //CP_MEC1_PRGRM_CNTR_START |
3215 | #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
3216 | #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL |
3217 | //CP_MEC2_PRGRM_CNTR_START |
3218 | #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
3219 | #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL |
3220 | //CP_CE_INTR_ROUTINE_START |
3221 | #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
3222 | #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL |
3223 | //CP_PFP_INTR_ROUTINE_START |
3224 | #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
3225 | #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL |
3226 | //CP_ME_INTR_ROUTINE_START |
3227 | #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
3228 | #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL |
3229 | //CP_MEC1_INTR_ROUTINE_START |
3230 | #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
3231 | #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL |
3232 | //CP_MEC2_INTR_ROUTINE_START |
3233 | #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
3234 | #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL |
3235 | //CP_CONTEXT_CNTL |
3236 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 |
3237 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 |
3238 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 |
3239 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 |
3240 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L |
3241 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L |
3242 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L |
3243 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L |
3244 | //CP_MAX_CONTEXT |
3245 | #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 |
3246 | #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L |
3247 | //CP_IQ_WAIT_TIME1 |
3248 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 |
3249 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 |
3250 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 |
3251 | #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 |
3252 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL |
3253 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L |
3254 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L |
3255 | #define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L |
3256 | //CP_IQ_WAIT_TIME2 |
3257 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 |
3258 | #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 |
3259 | #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 |
3260 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 |
3261 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL |
3262 | #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L |
3263 | #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L |
3264 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L |
3265 | //CP_RB0_BASE_HI |
3266 | #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
3267 | #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
3268 | //CP_RB1_BASE_HI |
3269 | #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
3270 | #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
3271 | //CP_VMID_RESET |
3272 | #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 |
3273 | #define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL |
3274 | //CPC_INT_CNTL |
3275 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
3276 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
3277 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
3278 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
3279 | #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
3280 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
3281 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
3282 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
3283 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
3284 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
3285 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
3286 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
3287 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
3288 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
3289 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
3290 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
3291 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
3292 | #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
3293 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
3294 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
3295 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
3296 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
3297 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
3298 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
3299 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
3300 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
3301 | //CPC_INT_STATUS |
3302 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
3303 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
3304 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
3305 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
3306 | #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
3307 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
3308 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
3309 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
3310 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
3311 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
3312 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
3313 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
3314 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
3315 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
3316 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
3317 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
3318 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
3319 | #define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
3320 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
3321 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
3322 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
3323 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
3324 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
3325 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
3326 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
3327 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
3328 | //CP_VMID_PREEMPT |
3329 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 |
3330 | #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 |
3331 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL |
3332 | #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L |
3333 | //CPC_INT_CNTX_ID |
3334 | #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 |
3335 | #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
3336 | //CP_PQ_STATUS |
3337 | #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
3338 | #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
3339 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
3340 | #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
3341 | //CP_CPC_IC_BASE_LO |
3342 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
3343 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
3344 | //CP_CPC_IC_BASE_HI |
3345 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
3346 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
3347 | //CP_CPC_IC_BASE_CNTL |
3348 | #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 |
3349 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
3350 | #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
3351 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L |
3352 | //CP_CPC_IC_OP_CNTL |
3353 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
3354 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
3355 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
3356 | #define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED__SHIFT 0x6 |
3357 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
3358 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
3359 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
3360 | #define CP_CPC_IC_OP_CNTL__ICACHE_INVALIDATED_MASK 0x00000040L |
3361 | //CP_MEC1_F32_INT_DIS |
3362 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
3363 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
3364 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
3365 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
3366 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
3367 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
3368 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
3369 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
3370 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
3371 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
3372 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
3373 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
3374 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
3375 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
3376 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
3377 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
3378 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
3379 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
3380 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
3381 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
3382 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
3383 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
3384 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
3385 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
3386 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
3387 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
3388 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
3389 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
3390 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
3391 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
3392 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
3393 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
3394 | //CP_MEC2_F32_INT_DIS |
3395 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
3396 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
3397 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
3398 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
3399 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
3400 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
3401 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
3402 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
3403 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
3404 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
3405 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
3406 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
3407 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
3408 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
3409 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
3410 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
3411 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
3412 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
3413 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
3414 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
3415 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
3416 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
3417 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
3418 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
3419 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
3420 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
3421 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
3422 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
3423 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
3424 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
3425 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
3426 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
3427 | //CP_VMID_STATUS |
3428 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 |
3429 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 |
3430 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL |
3431 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L |
3432 | |
3433 | |
3434 | // addressBlock: gc_cppdec2 |
3435 | //CP_RB_DOORBELL_CONTROL_SCH_0 |
3436 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 |
3437 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e |
3438 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f |
3439 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3440 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L |
3441 | #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L |
3442 | //CP_RB_DOORBELL_CONTROL_SCH_1 |
3443 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 |
3444 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e |
3445 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f |
3446 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3447 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L |
3448 | #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L |
3449 | //CP_RB_DOORBELL_CONTROL_SCH_2 |
3450 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 |
3451 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e |
3452 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f |
3453 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3454 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L |
3455 | #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L |
3456 | //CP_RB_DOORBELL_CONTROL_SCH_3 |
3457 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 |
3458 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e |
3459 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f |
3460 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3461 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L |
3462 | #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L |
3463 | //CP_RB_DOORBELL_CONTROL_SCH_4 |
3464 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 |
3465 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e |
3466 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f |
3467 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3468 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L |
3469 | #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L |
3470 | //CP_RB_DOORBELL_CONTROL_SCH_5 |
3471 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 |
3472 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e |
3473 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f |
3474 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3475 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L |
3476 | #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L |
3477 | //CP_RB_DOORBELL_CONTROL_SCH_6 |
3478 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 |
3479 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e |
3480 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f |
3481 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3482 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L |
3483 | #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L |
3484 | //CP_RB_DOORBELL_CONTROL_SCH_7 |
3485 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 |
3486 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e |
3487 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f |
3488 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3489 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L |
3490 | #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L |
3491 | //CP_RB_DOORBELL_CLEAR |
3492 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 |
3493 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 |
3494 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 |
3495 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa |
3496 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb |
3497 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc |
3498 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd |
3499 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L |
3500 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L |
3501 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L |
3502 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L |
3503 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L |
3504 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L |
3505 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L |
3506 | //CPF_EDC_TAG_CNT |
3507 | #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 |
3508 | #define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 |
3509 | #define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L |
3510 | #define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL |
3511 | //CPF_EDC_ROQ_CNT |
3512 | #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0 |
3513 | #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2 |
3514 | #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4 |
3515 | #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6 |
3516 | #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L |
3517 | #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL |
3518 | #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L |
3519 | #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L |
3520 | //CPG_EDC_TAG_CNT |
3521 | #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 |
3522 | #define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 |
3523 | #define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L |
3524 | #define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL |
3525 | //CPG_EDC_DMA_CNT |
3526 | #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0 |
3527 | #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2 |
3528 | #define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4 |
3529 | #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6 |
3530 | #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L |
3531 | #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL |
3532 | #define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L |
3533 | #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L |
3534 | //CPC_EDC_SCRATCH_CNT |
3535 | #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0 |
3536 | #define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2 |
3537 | #define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L |
3538 | #define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL |
3539 | //CPC_EDC_UCODE_CNT |
3540 | #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0 |
3541 | #define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2 |
3542 | #define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L |
3543 | #define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL |
3544 | //DC_EDC_STATE_CNT |
3545 | #define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0 |
3546 | #define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2 |
3547 | #define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L |
3548 | #define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL |
3549 | //DC_EDC_CSINVOC_CNT |
3550 | #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0 |
3551 | #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2 |
3552 | #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4 |
3553 | #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6 |
3554 | #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L |
3555 | #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL |
3556 | #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L |
3557 | #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L |
3558 | //DC_EDC_RESTORE_CNT |
3559 | #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0 |
3560 | #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2 |
3561 | #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4 |
3562 | #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6 |
3563 | #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L |
3564 | #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL |
3565 | #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L |
3566 | #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L |
3567 | //CP_CPF_DSM_CNTL |
3568 | #define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA__SHIFT 0x0 |
3569 | #define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
3570 | #define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA__SHIFT 0x3 |
3571 | #define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
3572 | #define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA__SHIFT 0x6 |
3573 | #define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
3574 | #define CP_CPF_DSM_CNTL__CPF0_DSM_IRRITATOR_DATA_MASK 0x00000003L |
3575 | #define CP_CPF_DSM_CNTL__CPF0_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
3576 | #define CP_CPF_DSM_CNTL__CPF1_DSM_IRRITATOR_DATA_MASK 0x00000018L |
3577 | #define CP_CPF_DSM_CNTL__CPF1_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
3578 | #define CP_CPF_DSM_CNTL__CPF2_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
3579 | #define CP_CPF_DSM_CNTL__CPF2_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
3580 | //CP_CPG_DSM_CNTL |
3581 | #define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA__SHIFT 0x0 |
3582 | #define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
3583 | #define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA__SHIFT 0x3 |
3584 | #define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
3585 | #define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA__SHIFT 0x6 |
3586 | #define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
3587 | #define CP_CPG_DSM_CNTL__CPG0_DSM_IRRITATOR_DATA_MASK 0x00000003L |
3588 | #define CP_CPG_DSM_CNTL__CPG0_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
3589 | #define CP_CPG_DSM_CNTL__CPG1_DSM_IRRITATOR_DATA_MASK 0x00000018L |
3590 | #define CP_CPG_DSM_CNTL__CPG1_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
3591 | #define CP_CPG_DSM_CNTL__CPG2_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
3592 | #define CP_CPG_DSM_CNTL__CPG2_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
3593 | //CP_CPC_DSM_CNTL |
3594 | #define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA__SHIFT 0x0 |
3595 | #define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
3596 | #define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA__SHIFT 0x3 |
3597 | #define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
3598 | #define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA__SHIFT 0x6 |
3599 | #define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
3600 | #define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA__SHIFT 0x9 |
3601 | #define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE__SHIFT 0xb |
3602 | #define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA__SHIFT 0xc |
3603 | #define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE__SHIFT 0xe |
3604 | #define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA__SHIFT 0xf |
3605 | #define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
3606 | #define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA__SHIFT 0x12 |
3607 | #define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
3608 | #define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA__SHIFT 0x15 |
3609 | #define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
3610 | #define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA__SHIFT 0x18 |
3611 | #define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
3612 | #define CP_CPC_DSM_CNTL__CPC0_DSM_IRRITATOR_DATA_MASK 0x00000003L |
3613 | #define CP_CPC_DSM_CNTL__CPC0_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
3614 | #define CP_CPC_DSM_CNTL__CPC1_DSM_IRRITATOR_DATA_MASK 0x00000018L |
3615 | #define CP_CPC_DSM_CNTL__CPC1_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
3616 | #define CP_CPC_DSM_CNTL__CPC2_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
3617 | #define CP_CPC_DSM_CNTL__CPC2_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
3618 | #define CP_CPC_DSM_CNTL__CPC3_DSM_IRRITATOR_DATA_MASK 0x00000600L |
3619 | #define CP_CPC_DSM_CNTL__CPC3_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
3620 | #define CP_CPC_DSM_CNTL__CPC4_DSM_IRRITATOR_DATA_MASK 0x00003000L |
3621 | #define CP_CPC_DSM_CNTL__CPC4_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
3622 | #define CP_CPC_DSM_CNTL__CPC5_DSM_IRRITATOR_DATA_MASK 0x00018000L |
3623 | #define CP_CPC_DSM_CNTL__CPC5_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
3624 | #define CP_CPC_DSM_CNTL__CPC6_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
3625 | #define CP_CPC_DSM_CNTL__CPC6_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
3626 | #define CP_CPC_DSM_CNTL__CPC7_DSM_IRRITATOR_DATA_MASK 0x00600000L |
3627 | #define CP_CPC_DSM_CNTL__CPC7_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
3628 | #define CP_CPC_DSM_CNTL__CPC8_DSM_IRRITATOR_DATA_MASK 0x03000000L |
3629 | #define CP_CPC_DSM_CNTL__CPC8_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
3630 | //CP_CPF_DSM_CNTL2 |
3631 | #define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT__SHIFT 0x0 |
3632 | #define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY__SHIFT 0x2 |
3633 | #define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT__SHIFT 0x3 |
3634 | #define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY__SHIFT 0x5 |
3635 | #define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT__SHIFT 0x6 |
3636 | #define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY__SHIFT 0x8 |
3637 | #define CP_CPF_DSM_CNTL2__CPF0_ENABLE_ERROR_INJECT_MASK 0x00000003L |
3638 | #define CP_CPF_DSM_CNTL2__CPF0_SELECT_INJECT_DELAY_MASK 0x00000004L |
3639 | #define CP_CPF_DSM_CNTL2__CPF1_ENABLE_ERROR_INJECT_MASK 0x00000018L |
3640 | #define CP_CPF_DSM_CNTL2__CPF1_SELECT_INJECT_DELAY_MASK 0x00000020L |
3641 | #define CP_CPF_DSM_CNTL2__CPF2_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
3642 | #define CP_CPF_DSM_CNTL2__CPF2_SELECT_INJECT_DELAY_MASK 0x00000100L |
3643 | //CP_CPG_DSM_CNTL2 |
3644 | #define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT__SHIFT 0x0 |
3645 | #define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY__SHIFT 0x2 |
3646 | #define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT__SHIFT 0x3 |
3647 | #define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY__SHIFT 0x5 |
3648 | #define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT__SHIFT 0x6 |
3649 | #define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY__SHIFT 0x8 |
3650 | #define CP_CPG_DSM_CNTL2__CPG0_ENABLE_ERROR_INJECT_MASK 0x00000003L |
3651 | #define CP_CPG_DSM_CNTL2__CPG0_SELECT_INJECT_DELAY_MASK 0x00000004L |
3652 | #define CP_CPG_DSM_CNTL2__CPG1_ENABLE_ERROR_INJECT_MASK 0x00000018L |
3653 | #define CP_CPG_DSM_CNTL2__CPG1_SELECT_INJECT_DELAY_MASK 0x00000020L |
3654 | #define CP_CPG_DSM_CNTL2__CPG2_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
3655 | #define CP_CPG_DSM_CNTL2__CPG2_SELECT_INJECT_DELAY_MASK 0x00000100L |
3656 | //CP_CPC_DSM_CNTL2 |
3657 | #define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT__SHIFT 0x0 |
3658 | #define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY__SHIFT 0x2 |
3659 | #define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT__SHIFT 0x3 |
3660 | #define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY__SHIFT 0x5 |
3661 | #define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT__SHIFT 0x6 |
3662 | #define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY__SHIFT 0x8 |
3663 | #define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT__SHIFT 0x9 |
3664 | #define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY__SHIFT 0xb |
3665 | #define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT__SHIFT 0xc |
3666 | #define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY__SHIFT 0xe |
3667 | #define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT__SHIFT 0xf |
3668 | #define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY__SHIFT 0x11 |
3669 | #define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT__SHIFT 0x12 |
3670 | #define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY__SHIFT 0x14 |
3671 | #define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT__SHIFT 0x15 |
3672 | #define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY__SHIFT 0x17 |
3673 | #define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT__SHIFT 0x18 |
3674 | #define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY__SHIFT 0x1a |
3675 | #define CP_CPC_DSM_CNTL2__CPC0_ENABLE_ERROR_INJECT_MASK 0x00000003L |
3676 | #define CP_CPC_DSM_CNTL2__CPC0_SELECT_INJECT_DELAY_MASK 0x00000004L |
3677 | #define CP_CPC_DSM_CNTL2__CPC1_ENABLE_ERROR_INJECT_MASK 0x00000018L |
3678 | #define CP_CPC_DSM_CNTL2__CPC1_SELECT_INJECT_DELAY_MASK 0x00000020L |
3679 | #define CP_CPC_DSM_CNTL2__CPC2_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
3680 | #define CP_CPC_DSM_CNTL2__CPC2_SELECT_INJECT_DELAY_MASK 0x00000100L |
3681 | #define CP_CPC_DSM_CNTL2__CPC3_ENABLE_ERROR_INJECT_MASK 0x00000600L |
3682 | #define CP_CPC_DSM_CNTL2__CPC3_SELECT_INJECT_DELAY_MASK 0x00000800L |
3683 | #define CP_CPC_DSM_CNTL2__CPC4_ENABLE_ERROR_INJECT_MASK 0x00003000L |
3684 | #define CP_CPC_DSM_CNTL2__CPC4_SELECT_INJECT_DELAY_MASK 0x00004000L |
3685 | #define CP_CPC_DSM_CNTL2__CPC5_ENABLE_ERROR_INJECT_MASK 0x00018000L |
3686 | #define CP_CPC_DSM_CNTL2__CPC5_SELECT_INJECT_DELAY_MASK 0x00020000L |
3687 | #define CP_CPC_DSM_CNTL2__CPC6_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
3688 | #define CP_CPC_DSM_CNTL2__CPC6_SELECT_INJECT_DELAY_MASK 0x00100000L |
3689 | #define CP_CPC_DSM_CNTL2__CPC7_ENABLE_ERROR_INJECT_MASK 0x00600000L |
3690 | #define CP_CPC_DSM_CNTL2__CPC7_SELECT_INJECT_DELAY_MASK 0x00800000L |
3691 | #define CP_CPC_DSM_CNTL2__CPC8_ENABLE_ERROR_INJECT_MASK 0x03000000L |
3692 | #define CP_CPC_DSM_CNTL2__CPC8_SELECT_INJECT_DELAY_MASK 0x04000000L |
3693 | //CP_CPF_DSM_CNTL2A |
3694 | #define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY__SHIFT 0x0 |
3695 | #define CP_CPF_DSM_CNTL2A__CPF_INJECT_DELAY_MASK 0x0000003FL |
3696 | //CP_CPG_DSM_CNTL2A |
3697 | #define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY__SHIFT 0x0 |
3698 | #define CP_CPG_DSM_CNTL2A__CPG_INJECT_DELAY_MASK 0x0000003FL |
3699 | //CP_CPC_DSM_CNTL2A |
3700 | #define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY__SHIFT 0x0 |
3701 | #define CP_CPC_DSM_CNTL2A__CPC_INJECT_DELAY_MASK 0x0000003FL |
3702 | //CP_EDC_FUE_CNTL |
3703 | #define CP_EDC_FUE_CNTL__CP_FUE_MASK__SHIFT 0x0 |
3704 | #define CP_EDC_FUE_CNTL__SPI_FUE_MASK__SHIFT 0x1 |
3705 | #define CP_EDC_FUE_CNTL__GDS_FUE_MASK__SHIFT 0x2 |
3706 | #define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK__SHIFT 0x3 |
3707 | #define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK__SHIFT 0x4 |
3708 | #define CP_EDC_FUE_CNTL__TCA_FUE_MASK__SHIFT 0x5 |
3709 | #define CP_EDC_FUE_CNTL__TCC_FUE_MASK__SHIFT 0x6 |
3710 | #define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK__SHIFT 0x7 |
3711 | #define CP_EDC_FUE_CNTL__CP_FUE_FLAG__SHIFT 0x10 |
3712 | #define CP_EDC_FUE_CNTL__SPI_FUE_FLAG__SHIFT 0x11 |
3713 | #define CP_EDC_FUE_CNTL__GDS_FUE_FLAG__SHIFT 0x12 |
3714 | #define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG__SHIFT 0x13 |
3715 | #define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG__SHIFT 0x14 |
3716 | #define CP_EDC_FUE_CNTL__TCA_FUE_FLAG__SHIFT 0x15 |
3717 | #define CP_EDC_FUE_CNTL__TCC_FUE_FLAG__SHIFT 0x16 |
3718 | #define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG__SHIFT 0x17 |
3719 | #define CP_EDC_FUE_CNTL__CP_FUE_MASK_MASK 0x00000001L |
3720 | #define CP_EDC_FUE_CNTL__SPI_FUE_MASK_MASK 0x00000002L |
3721 | #define CP_EDC_FUE_CNTL__GDS_FUE_MASK_MASK 0x00000004L |
3722 | #define CP_EDC_FUE_CNTL__TC_RLC_FUE_MASK_MASK 0x00000008L |
3723 | #define CP_EDC_FUE_CNTL__TC_CPG_FUE_MASK_MASK 0x00000010L |
3724 | #define CP_EDC_FUE_CNTL__TCA_FUE_MASK_MASK 0x00000020L |
3725 | #define CP_EDC_FUE_CNTL__TCC_FUE_MASK_MASK 0x00000040L |
3726 | #define CP_EDC_FUE_CNTL__UTCL2_FUE_MASK_MASK 0x00000080L |
3727 | #define CP_EDC_FUE_CNTL__CP_FUE_FLAG_MASK 0x00010000L |
3728 | #define CP_EDC_FUE_CNTL__SPI_FUE_FLAG_MASK 0x00020000L |
3729 | #define CP_EDC_FUE_CNTL__GDS_FUE_FLAG_MASK 0x00040000L |
3730 | #define CP_EDC_FUE_CNTL__TC_RLC_FUE_FLAG_MASK 0x00080000L |
3731 | #define CP_EDC_FUE_CNTL__TC_CPG_FUE_FLAG_MASK 0x00100000L |
3732 | #define CP_EDC_FUE_CNTL__TCA_FUE_FLAG_MASK 0x00200000L |
3733 | #define CP_EDC_FUE_CNTL__TCC_FUE_FLAG_MASK 0x00400000L |
3734 | #define CP_EDC_FUE_CNTL__UTCL2_FUE_FLAG_MASK 0x00800000L |
3735 | //CP_GFX_MQD_CONTROL |
3736 | #define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 |
3737 | #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
3738 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
3739 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
3740 | #define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL |
3741 | #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
3742 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
3743 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L |
3744 | //CP_GFX_MQD_BASE_ADDR |
3745 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
3746 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
3747 | //CP_GFX_MQD_BASE_ADDR_HI |
3748 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
3749 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
3750 | //CP_RB_STATUS |
3751 | #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
3752 | #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
3753 | #define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
3754 | #define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
3755 | //CPG_UTCL1_STATUS |
3756 | #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
3757 | #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
3758 | #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
3759 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
3760 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
3761 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
3762 | #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
3763 | #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
3764 | #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
3765 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
3766 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
3767 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
3768 | //CPC_UTCL1_STATUS |
3769 | #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
3770 | #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
3771 | #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
3772 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
3773 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
3774 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
3775 | #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
3776 | #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
3777 | #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
3778 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
3779 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
3780 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
3781 | //CPF_UTCL1_STATUS |
3782 | #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
3783 | #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
3784 | #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
3785 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
3786 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
3787 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
3788 | #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
3789 | #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
3790 | #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
3791 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
3792 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
3793 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
3794 | //CP_SD_CNTL |
3795 | #define CP_SD_CNTL__CPF_EN__SHIFT 0x0 |
3796 | #define CP_SD_CNTL__CPG_EN__SHIFT 0x1 |
3797 | #define CP_SD_CNTL__CPC_EN__SHIFT 0x2 |
3798 | #define CP_SD_CNTL__RLC_EN__SHIFT 0x3 |
3799 | #define CP_SD_CNTL__SPI_EN__SHIFT 0x4 |
3800 | #define CP_SD_CNTL__WD_EN__SHIFT 0x5 |
3801 | #define CP_SD_CNTL__IA_EN__SHIFT 0x6 |
3802 | #define CP_SD_CNTL__PA_EN__SHIFT 0x7 |
3803 | #define CP_SD_CNTL__RMI_EN__SHIFT 0x8 |
3804 | #define CP_SD_CNTL__EA_EN__SHIFT 0x9 |
3805 | #define CP_SD_CNTL__CPF_EN_MASK 0x00000001L |
3806 | #define CP_SD_CNTL__CPG_EN_MASK 0x00000002L |
3807 | #define CP_SD_CNTL__CPC_EN_MASK 0x00000004L |
3808 | #define CP_SD_CNTL__RLC_EN_MASK 0x00000008L |
3809 | #define CP_SD_CNTL__SPI_EN_MASK 0x00000010L |
3810 | #define CP_SD_CNTL__WD_EN_MASK 0x00000020L |
3811 | #define CP_SD_CNTL__IA_EN_MASK 0x00000040L |
3812 | #define CP_SD_CNTL__PA_EN_MASK 0x00000080L |
3813 | #define CP_SD_CNTL__RMI_EN_MASK 0x00000100L |
3814 | #define CP_SD_CNTL__EA_EN_MASK 0x00000200L |
3815 | //CP_SOFT_RESET_CNTL |
3816 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 |
3817 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 |
3818 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 |
3819 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 |
3820 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 |
3821 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 |
3822 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 |
3823 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L |
3824 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L |
3825 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L |
3826 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L |
3827 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L |
3828 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L |
3829 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L |
3830 | //CP_CPC_GFX_CNTL |
3831 | #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 |
3832 | #define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 |
3833 | #define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 |
3834 | #define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 |
3835 | #define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L |
3836 | #define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L |
3837 | #define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L |
3838 | #define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L |
3839 | |
3840 | |
3841 | // addressBlock: gc_cpphqddec |
3842 | //CP_HQD_GFX_CONTROL |
3843 | #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 |
3844 | #define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 |
3845 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf |
3846 | #define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL |
3847 | #define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L |
3848 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L |
3849 | //CP_HQD_GFX_STATUS |
3850 | #define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 |
3851 | #define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL |
3852 | //CP_HPD_ROQ_OFFSETS |
3853 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
3854 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
3855 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
3856 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
3857 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
3858 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L |
3859 | //CP_HPD_STATUS0 |
3860 | #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
3861 | #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
3862 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
3863 | #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 |
3864 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 |
3865 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 |
3866 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
3867 | #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
3868 | #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
3869 | #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
3870 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
3871 | #define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L |
3872 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L |
3873 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L |
3874 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
3875 | #define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
3876 | //CP_HPD_UTCL1_CNTL |
3877 | #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 |
3878 | #define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL |
3879 | //CP_HPD_UTCL1_ERROR |
3880 | #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 |
3881 | #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 |
3882 | #define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 |
3883 | #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL |
3884 | #define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L |
3885 | #define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L |
3886 | //CP_HPD_UTCL1_ERROR_ADDR |
3887 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc |
3888 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L |
3889 | //CP_MQD_BASE_ADDR |
3890 | #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
3891 | #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
3892 | //CP_MQD_BASE_ADDR_HI |
3893 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
3894 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
3895 | //CP_HQD_ACTIVE |
3896 | #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
3897 | #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 |
3898 | #define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
3899 | #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L |
3900 | //CP_HQD_VMID |
3901 | #define CP_HQD_VMID__VMID__SHIFT 0x0 |
3902 | #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 |
3903 | #define CP_HQD_VMID__VQID__SHIFT 0x10 |
3904 | #define CP_HQD_VMID__VMID_MASK 0x0000000FL |
3905 | #define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L |
3906 | #define CP_HQD_VMID__VQID_MASK 0x03FF0000L |
3907 | //CP_HQD_PERSISTENT_STATE |
3908 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 |
3909 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 |
3910 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 |
3911 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 |
3912 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 |
3913 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 |
3914 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 |
3915 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a |
3916 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b |
3917 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c |
3918 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d |
3919 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e |
3920 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f |
3921 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L |
3922 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L |
3923 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L |
3924 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L |
3925 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L |
3926 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L |
3927 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L |
3928 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L |
3929 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L |
3930 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L |
3931 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L |
3932 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L |
3933 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L |
3934 | //CP_HQD_PIPE_PRIORITY |
3935 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 |
3936 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L |
3937 | //CP_HQD_QUEUE_PRIORITY |
3938 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
3939 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
3940 | //CP_HQD_QUANTUM |
3941 | #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
3942 | #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 |
3943 | #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
3944 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
3945 | #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
3946 | #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L |
3947 | #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L |
3948 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
3949 | //CP_HQD_PQ_BASE |
3950 | #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 |
3951 | #define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL |
3952 | //CP_HQD_PQ_BASE_HI |
3953 | #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 |
3954 | #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL |
3955 | //CP_HQD_PQ_RPTR |
3956 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
3957 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL |
3958 | //CP_HQD_PQ_RPTR_REPORT_ADDR |
3959 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 |
3960 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL |
3961 | //CP_HQD_PQ_RPTR_REPORT_ADDR_HI |
3962 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 |
3963 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL |
3964 | //CP_HQD_PQ_WPTR_POLL_ADDR |
3965 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 |
3966 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L |
3967 | //CP_HQD_PQ_WPTR_POLL_ADDR_HI |
3968 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 |
3969 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL |
3970 | //CP_HQD_PQ_DOORBELL_CONTROL |
3971 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 |
3972 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
3973 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
3974 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c |
3975 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d |
3976 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
3977 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
3978 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L |
3979 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
3980 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
3981 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L |
3982 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L |
3983 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
3984 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
3985 | //CP_HQD_PQ_CONTROL |
3986 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 |
3987 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 |
3988 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 |
3989 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 |
3990 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe |
3991 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf |
3992 | #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 |
3993 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 |
3994 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 |
3995 | #define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 |
3996 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 |
3997 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 |
3998 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 |
3999 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b |
4000 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c |
4001 | #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d |
4002 | #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e |
4003 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f |
4004 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL |
4005 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L |
4006 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L |
4007 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L |
4008 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L |
4009 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L |
4010 | #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L |
4011 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L |
4012 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L |
4013 | #define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L |
4014 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L |
4015 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L |
4016 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L |
4017 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L |
4018 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L |
4019 | #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L |
4020 | #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L |
4021 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L |
4022 | //CP_HQD_IB_BASE_ADDR |
4023 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 |
4024 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL |
4025 | //CP_HQD_IB_BASE_ADDR_HI |
4026 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 |
4027 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL |
4028 | //CP_HQD_IB_RPTR |
4029 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
4030 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL |
4031 | //CP_HQD_IB_CONTROL |
4032 | #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 |
4033 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 |
4034 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 |
4035 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 |
4036 | #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f |
4037 | #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL |
4038 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L |
4039 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L |
4040 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L |
4041 | #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L |
4042 | //CP_HQD_IQ_TIMER |
4043 | #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 |
4044 | #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 |
4045 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb |
4046 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc |
4047 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe |
4048 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 |
4049 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 |
4050 | #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 |
4051 | #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 |
4052 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 |
4053 | #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c |
4054 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d |
4055 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e |
4056 | #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f |
4057 | #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL |
4058 | #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L |
4059 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L |
4060 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L |
4061 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L |
4062 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L |
4063 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L |
4064 | #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L |
4065 | #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L |
4066 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L |
4067 | #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L |
4068 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L |
4069 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L |
4070 | #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L |
4071 | //CP_HQD_IQ_RPTR |
4072 | #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 |
4073 | #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL |
4074 | //CP_HQD_DEQUEUE_REQUEST |
4075 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
4076 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
4077 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 |
4078 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
4079 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
4080 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L |
4081 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
4082 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L |
4083 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
4084 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
4085 | //CP_HQD_DMA_OFFLOAD |
4086 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
4087 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
4088 | //CP_HQD_OFFLOAD |
4089 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
4090 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 |
4091 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 |
4092 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 |
4093 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 |
4094 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 |
4095 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
4096 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L |
4097 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L |
4098 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L |
4099 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L |
4100 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L |
4101 | //CP_HQD_SEMA_CMD |
4102 | #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 |
4103 | #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 |
4104 | #define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L |
4105 | #define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L |
4106 | //CP_HQD_MSG_TYPE |
4107 | #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 |
4108 | #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 |
4109 | #define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L |
4110 | #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L |
4111 | //CP_HQD_ATOMIC0_PREOP_LO |
4112 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 |
4113 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
4114 | //CP_HQD_ATOMIC0_PREOP_HI |
4115 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 |
4116 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
4117 | //CP_HQD_ATOMIC1_PREOP_LO |
4118 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 |
4119 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
4120 | //CP_HQD_ATOMIC1_PREOP_HI |
4121 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 |
4122 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
4123 | //CP_HQD_HQ_SCHEDULER0 |
4124 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 |
4125 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL |
4126 | //CP_HQD_HQ_STATUS0 |
4127 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
4128 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 |
4129 | #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 |
4130 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 |
4131 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 |
4132 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 |
4133 | #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa |
4134 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
4135 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f |
4136 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L |
4137 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL |
4138 | #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L |
4139 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L |
4140 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L |
4141 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L |
4142 | #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L |
4143 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
4144 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L |
4145 | //CP_HQD_HQ_CONTROL0 |
4146 | #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 |
4147 | #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL |
4148 | //CP_HQD_HQ_SCHEDULER1 |
4149 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 |
4150 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL |
4151 | //CP_MQD_CONTROL |
4152 | #define CP_MQD_CONTROL__VMID__SHIFT 0x0 |
4153 | #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
4154 | #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
4155 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
4156 | #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
4157 | #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
4158 | #define CP_MQD_CONTROL__VMID_MASK 0x0000000FL |
4159 | #define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
4160 | #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
4161 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
4162 | #define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
4163 | #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L |
4164 | //CP_HQD_HQ_STATUS1 |
4165 | #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 |
4166 | #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL |
4167 | //CP_HQD_HQ_CONTROL1 |
4168 | #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 |
4169 | #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL |
4170 | //CP_HQD_EOP_BASE_ADDR |
4171 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
4172 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
4173 | //CP_HQD_EOP_BASE_ADDR_HI |
4174 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
4175 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL |
4176 | //CP_HQD_EOP_CONTROL |
4177 | #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 |
4178 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 |
4179 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc |
4180 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd |
4181 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe |
4182 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 |
4183 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 |
4184 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 |
4185 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 |
4186 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d |
4187 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f |
4188 | #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL |
4189 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L |
4190 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L |
4191 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L |
4192 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L |
4193 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L |
4194 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L |
4195 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L |
4196 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L |
4197 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L |
4198 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L |
4199 | //CP_HQD_EOP_RPTR |
4200 | #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 |
4201 | #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c |
4202 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d |
4203 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e |
4204 | #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f |
4205 | #define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL |
4206 | #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L |
4207 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L |
4208 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L |
4209 | #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L |
4210 | //CP_HQD_EOP_WPTR |
4211 | #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 |
4212 | #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf |
4213 | #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 |
4214 | #define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL |
4215 | #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L |
4216 | #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L |
4217 | //CP_HQD_EOP_EVENTS |
4218 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 |
4219 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 |
4220 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL |
4221 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L |
4222 | //CP_HQD_CTX_SAVE_BASE_ADDR_LO |
4223 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
4224 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
4225 | //CP_HQD_CTX_SAVE_BASE_ADDR_HI |
4226 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
4227 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
4228 | //CP_HQD_CTX_SAVE_CONTROL |
4229 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
4230 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
4231 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L |
4232 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
4233 | //CP_HQD_CNTL_STACK_OFFSET |
4234 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
4235 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL |
4236 | //CP_HQD_CNTL_STACK_SIZE |
4237 | #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
4238 | #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L |
4239 | //CP_HQD_WG_STATE_OFFSET |
4240 | #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
4241 | #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x07FFFFFCL |
4242 | //CP_HQD_CTX_SAVE_SIZE |
4243 | #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
4244 | #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x07FFF000L |
4245 | //CP_HQD_GDS_RESOURCE_STATE |
4246 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 |
4247 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 |
4248 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 |
4249 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc |
4250 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L |
4251 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L |
4252 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L |
4253 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L |
4254 | //CP_HQD_ERROR |
4255 | #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
4256 | #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 |
4257 | #define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 |
4258 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 |
4259 | #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 |
4260 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa |
4261 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb |
4262 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc |
4263 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd |
4264 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe |
4265 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf |
4266 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 |
4267 | #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 |
4268 | #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 |
4269 | #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 |
4270 | #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
4271 | #define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L |
4272 | #define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L |
4273 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L |
4274 | #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L |
4275 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L |
4276 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L |
4277 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L |
4278 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L |
4279 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L |
4280 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L |
4281 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L |
4282 | #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L |
4283 | #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L |
4284 | #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L |
4285 | //CP_HQD_EOP_WPTR_MEM |
4286 | #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 |
4287 | #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL |
4288 | //CP_HQD_AQL_CONTROL |
4289 | #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 |
4290 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf |
4291 | #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 |
4292 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f |
4293 | #define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL |
4294 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L |
4295 | #define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L |
4296 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L |
4297 | //CP_HQD_PQ_WPTR_LO |
4298 | #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 |
4299 | #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL |
4300 | //CP_HQD_PQ_WPTR_HI |
4301 | #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 |
4302 | #define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL |
4303 | |
4304 | |
4305 | |
4306 | |
4307 | // addressBlock: gc_didtdec |
4308 | //DIDT_IND_INDEX |
4309 | #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 |
4310 | #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL |
4311 | //DIDT_IND_DATA |
4312 | #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 |
4313 | #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL |
4314 | //DIDT_INDEX_AUTO_INCR_EN |
4315 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 |
4316 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L |
4317 | |
4318 | |
4319 | // addressBlock: gc_ea_gceadec |
4320 | //GCEA_DRAM_RD_CLI2GRP_MAP0 |
4321 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
4322 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
4323 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
4324 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
4325 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
4326 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
4327 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
4328 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
4329 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
4330 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
4331 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
4332 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
4333 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
4334 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
4335 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
4336 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
4337 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
4338 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
4339 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
4340 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
4341 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
4342 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
4343 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
4344 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
4345 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
4346 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
4347 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
4348 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
4349 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
4350 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
4351 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
4352 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
4353 | //GCEA_DRAM_RD_CLI2GRP_MAP1 |
4354 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
4355 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
4356 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
4357 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
4358 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
4359 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
4360 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
4361 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
4362 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
4363 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
4364 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
4365 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
4366 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
4367 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
4368 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
4369 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
4370 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
4371 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
4372 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
4373 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
4374 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
4375 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
4376 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
4377 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
4378 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
4379 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
4380 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
4381 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
4382 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
4383 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
4384 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
4385 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
4386 | //GCEA_DRAM_WR_CLI2GRP_MAP0 |
4387 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
4388 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
4389 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
4390 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
4391 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
4392 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
4393 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
4394 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
4395 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
4396 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
4397 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
4398 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
4399 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
4400 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
4401 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
4402 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
4403 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
4404 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
4405 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
4406 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
4407 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
4408 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
4409 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
4410 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
4411 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
4412 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
4413 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
4414 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
4415 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
4416 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
4417 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
4418 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
4419 | //GCEA_DRAM_WR_CLI2GRP_MAP1 |
4420 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
4421 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
4422 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
4423 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
4424 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
4425 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
4426 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
4427 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
4428 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
4429 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
4430 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
4431 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
4432 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
4433 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
4434 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
4435 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
4436 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
4437 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
4438 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
4439 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
4440 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
4441 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
4442 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
4443 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
4444 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
4445 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
4446 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
4447 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
4448 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
4449 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
4450 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
4451 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
4452 | //GCEA_DRAM_RD_GRP2VC_MAP |
4453 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
4454 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
4455 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
4456 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
4457 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
4458 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
4459 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
4460 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
4461 | //GCEA_DRAM_WR_GRP2VC_MAP |
4462 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
4463 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
4464 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
4465 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
4466 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
4467 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
4468 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
4469 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
4470 | //GCEA_DRAM_RD_LAZY |
4471 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
4472 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
4473 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
4474 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
4475 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
4476 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
4477 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
4478 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
4479 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
4480 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
4481 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
4482 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
4483 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
4484 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
4485 | //GCEA_DRAM_WR_LAZY |
4486 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
4487 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
4488 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
4489 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
4490 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
4491 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
4492 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
4493 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
4494 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
4495 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
4496 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
4497 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
4498 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
4499 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
4500 | //GCEA_DRAM_RD_CAM_CNTL |
4501 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
4502 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
4503 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
4504 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
4505 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
4506 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
4507 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
4508 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
4509 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
4510 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
4511 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
4512 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
4513 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
4514 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
4515 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
4516 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
4517 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
4518 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
4519 | //GCEA_DRAM_WR_CAM_CNTL |
4520 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
4521 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
4522 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
4523 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
4524 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
4525 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
4526 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
4527 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
4528 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
4529 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
4530 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
4531 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
4532 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
4533 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
4534 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
4535 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
4536 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
4537 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
4538 | //GCEA_DRAM_PAGE_BURST |
4539 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
4540 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
4541 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
4542 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
4543 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
4544 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
4545 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
4546 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
4547 | //GCEA_DRAM_RD_PRI_AGE |
4548 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
4549 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
4550 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
4551 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
4552 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
4553 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
4554 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
4555 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
4556 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
4557 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
4558 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
4559 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
4560 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
4561 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
4562 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
4563 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
4564 | //GCEA_DRAM_WR_PRI_AGE |
4565 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
4566 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
4567 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
4568 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
4569 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
4570 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
4571 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
4572 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
4573 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
4574 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
4575 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
4576 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
4577 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
4578 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
4579 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
4580 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
4581 | //GCEA_DRAM_RD_PRI_QUEUING |
4582 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
4583 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
4584 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
4585 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
4586 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
4587 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
4588 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
4589 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
4590 | //GCEA_DRAM_WR_PRI_QUEUING |
4591 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
4592 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
4593 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
4594 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
4595 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
4596 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
4597 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
4598 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
4599 | //GCEA_DRAM_RD_PRI_FIXED |
4600 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
4601 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
4602 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
4603 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
4604 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
4605 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
4606 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
4607 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
4608 | //GCEA_DRAM_WR_PRI_FIXED |
4609 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
4610 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
4611 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
4612 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
4613 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
4614 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
4615 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
4616 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
4617 | //GCEA_DRAM_RD_PRI_URGENCY |
4618 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
4619 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
4620 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
4621 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
4622 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
4623 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
4624 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
4625 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
4626 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
4627 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
4628 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
4629 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
4630 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
4631 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
4632 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
4633 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
4634 | //GCEA_DRAM_WR_PRI_URGENCY |
4635 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
4636 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
4637 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
4638 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
4639 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
4640 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
4641 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
4642 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
4643 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
4644 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
4645 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
4646 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
4647 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
4648 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
4649 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
4650 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
4651 | //GCEA_DRAM_RD_PRI_QUANT_PRI1 |
4652 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
4653 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
4654 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
4655 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
4656 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
4657 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4658 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4659 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
4660 | //GCEA_DRAM_RD_PRI_QUANT_PRI2 |
4661 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
4662 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
4663 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
4664 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
4665 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
4666 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4667 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4668 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
4669 | //GCEA_DRAM_RD_PRI_QUANT_PRI3 |
4670 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
4671 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
4672 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
4673 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
4674 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
4675 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4676 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4677 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
4678 | //GCEA_DRAM_WR_PRI_QUANT_PRI1 |
4679 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
4680 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
4681 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
4682 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
4683 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
4684 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4685 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4686 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
4687 | //GCEA_DRAM_WR_PRI_QUANT_PRI2 |
4688 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
4689 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
4690 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
4691 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
4692 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
4693 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4694 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4695 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
4696 | //GCEA_DRAM_WR_PRI_QUANT_PRI3 |
4697 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
4698 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
4699 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
4700 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
4701 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
4702 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
4703 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
4704 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
4705 | //GCEA_ADDRNORM_BASE_ADDR0 |
4706 | #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 |
4707 | #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4708 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 |
4709 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 |
4710 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4711 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 |
4712 | #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc |
4713 | #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L |
4714 | #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4715 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL |
4716 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L |
4717 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4718 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L |
4719 | #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L |
4720 | //GCEA_ADDRNORM_LIMIT_ADDR0 |
4721 | #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 |
4722 | #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc |
4723 | #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL |
4724 | #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L |
4725 | //GCEA_ADDRNORM_BASE_ADDR1 |
4726 | #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 |
4727 | #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4728 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 |
4729 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 |
4730 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4731 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 |
4732 | #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc |
4733 | #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L |
4734 | #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4735 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL |
4736 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L |
4737 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4738 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L |
4739 | #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L |
4740 | //GCEA_ADDRNORM_LIMIT_ADDR1 |
4741 | #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 |
4742 | #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc |
4743 | #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL |
4744 | #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L |
4745 | //GCEA_ADDRNORM_OFFSET_ADDR1 |
4746 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 |
4747 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc |
4748 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L |
4749 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L |
4750 | //GCEA_ADDRNORM_BASE_ADDR2 |
4751 | #define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 |
4752 | #define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4753 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 |
4754 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 |
4755 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4756 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 |
4757 | #define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc |
4758 | #define GCEA_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L |
4759 | #define GCEA_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4760 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL |
4761 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L |
4762 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4763 | #define GCEA_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L |
4764 | #define GCEA_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L |
4765 | //GCEA_ADDRNORM_LIMIT_ADDR2 |
4766 | #define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 |
4767 | #define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc |
4768 | #define GCEA_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL |
4769 | #define GCEA_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L |
4770 | //GCEA_ADDRNORM_BASE_ADDR3 |
4771 | #define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 |
4772 | #define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4773 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 |
4774 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 |
4775 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4776 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 |
4777 | #define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc |
4778 | #define GCEA_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L |
4779 | #define GCEA_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4780 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL |
4781 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L |
4782 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4783 | #define GCEA_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L |
4784 | #define GCEA_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L |
4785 | //GCEA_ADDRNORM_LIMIT_ADDR3 |
4786 | #define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 |
4787 | #define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc |
4788 | #define GCEA_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL |
4789 | #define GCEA_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L |
4790 | //GCEA_ADDRNORM_OFFSET_ADDR3 |
4791 | #define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 |
4792 | #define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc |
4793 | #define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L |
4794 | #define GCEA_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L |
4795 | //GCEA_ADDRNORM_MEGABASE_ADDR0 |
4796 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 |
4797 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4798 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 |
4799 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 |
4800 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4801 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 |
4802 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc |
4803 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L |
4804 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4805 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL |
4806 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L |
4807 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4808 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L |
4809 | #define GCEA_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L |
4810 | //GCEA_ADDRNORM_MEGALIMIT_ADDR0 |
4811 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 |
4812 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc |
4813 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL |
4814 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L |
4815 | //GCEA_ADDRNORM_MEGABASE_ADDR1 |
4816 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 |
4817 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
4818 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 |
4819 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 |
4820 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 |
4821 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 |
4822 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc |
4823 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L |
4824 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
4825 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL |
4826 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L |
4827 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L |
4828 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L |
4829 | #define GCEA_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L |
4830 | //GCEA_ADDRNORM_MEGALIMIT_ADDR1 |
4831 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 |
4832 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc |
4833 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL |
4834 | #define GCEA_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L |
4835 | //GCEA_ADDRNORMDRAM_HOLE_CNTL |
4836 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 |
4837 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 |
4838 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L |
4839 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L |
4840 | //GCEA_ADDRNORMGMI_HOLE_CNTL |
4841 | #define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 |
4842 | #define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 |
4843 | #define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L |
4844 | #define GCEA_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L |
4845 | //GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG |
4846 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 |
4847 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 |
4848 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL |
4849 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L |
4850 | //GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG |
4851 | #define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 |
4852 | #define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 |
4853 | #define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL |
4854 | #define GCEA_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L |
4855 | //GCEA_ADDRDEC_BANK_CFG |
4856 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 |
4857 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 |
4858 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc |
4859 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf |
4860 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 |
4861 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 |
4862 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL |
4863 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L |
4864 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L |
4865 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L |
4866 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L |
4867 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L |
4868 | //GCEA_ADDRDEC_MISC_CFG |
4869 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 |
4870 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 |
4871 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 |
4872 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 |
4873 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 |
4874 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc |
4875 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 |
4876 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 |
4877 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 |
4878 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a |
4879 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d |
4880 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L |
4881 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L |
4882 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L |
4883 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L |
4884 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L |
4885 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L |
4886 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L |
4887 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L |
4888 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L |
4889 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L |
4890 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L |
4891 | //GCEA_ADDRDECDRAM_HARVEST_ENABLE |
4892 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 |
4893 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 |
4894 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 |
4895 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 |
4896 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 |
4897 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 |
4898 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L |
4899 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L |
4900 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L |
4901 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L |
4902 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L |
4903 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L |
4904 | //GCEA_ADDRDECGMI_HARVEST_ENABLE |
4905 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 |
4906 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 |
4907 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 |
4908 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 |
4909 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 |
4910 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 |
4911 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L |
4912 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L |
4913 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L |
4914 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L |
4915 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L |
4916 | #define GCEA_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L |
4917 | //GCEA_ADDRDEC0_BASE_ADDR_CS0 |
4918 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 |
4919 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
4920 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L |
4921 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
4922 | //GCEA_ADDRDEC0_BASE_ADDR_CS1 |
4923 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 |
4924 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
4925 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L |
4926 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
4927 | //GCEA_ADDRDEC0_BASE_ADDR_CS2 |
4928 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 |
4929 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
4930 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L |
4931 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
4932 | //GCEA_ADDRDEC0_BASE_ADDR_CS3 |
4933 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 |
4934 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
4935 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L |
4936 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
4937 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS0 |
4938 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 |
4939 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
4940 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L |
4941 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
4942 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS1 |
4943 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 |
4944 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
4945 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L |
4946 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
4947 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS2 |
4948 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 |
4949 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
4950 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L |
4951 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
4952 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS3 |
4953 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 |
4954 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
4955 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L |
4956 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
4957 | //GCEA_ADDRDEC0_ADDR_MASK_CS01 |
4958 | #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
4959 | #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
4960 | //GCEA_ADDRDEC0_ADDR_MASK_CS23 |
4961 | #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
4962 | #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
4963 | //GCEA_ADDRDEC0_ADDR_MASK_SECCS01 |
4964 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
4965 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
4966 | //GCEA_ADDRDEC0_ADDR_MASK_SECCS23 |
4967 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
4968 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
4969 | //GCEA_ADDRDEC0_ADDR_CFG_CS01 |
4970 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 |
4971 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
4972 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
4973 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
4974 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
4975 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
4976 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f |
4977 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL |
4978 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
4979 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
4980 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
4981 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
4982 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
4983 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L |
4984 | //GCEA_ADDRDEC0_ADDR_CFG_CS23 |
4985 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 |
4986 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
4987 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
4988 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
4989 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
4990 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
4991 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f |
4992 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL |
4993 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
4994 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
4995 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
4996 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
4997 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
4998 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L |
4999 | //GCEA_ADDRDEC0_ADDR_SEL_CS01 |
5000 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
5001 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
5002 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
5003 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
5004 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
5005 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
5006 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
5007 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
5008 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
5009 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
5010 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
5011 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L |
5012 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
5013 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
5014 | //GCEA_ADDRDEC0_ADDR_SEL_CS23 |
5015 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
5016 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
5017 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
5018 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
5019 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
5020 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
5021 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
5022 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
5023 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
5024 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
5025 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
5026 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L |
5027 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
5028 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
5029 | //GCEA_ADDRDEC0_ADDR_SEL2_CS01 |
5030 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 |
5031 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc |
5032 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL |
5033 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L |
5034 | //GCEA_ADDRDEC0_ADDR_SEL2_CS23 |
5035 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 |
5036 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc |
5037 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL |
5038 | #define GCEA_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L |
5039 | //GCEA_ADDRDEC0_COL_SEL_LO_CS01 |
5040 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
5041 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
5042 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
5043 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
5044 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
5045 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
5046 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
5047 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
5048 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
5049 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
5050 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
5051 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
5052 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
5053 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
5054 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
5055 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
5056 | //GCEA_ADDRDEC0_COL_SEL_LO_CS23 |
5057 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
5058 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
5059 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
5060 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
5061 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
5062 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
5063 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
5064 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
5065 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
5066 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
5067 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
5068 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
5069 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
5070 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
5071 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
5072 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
5073 | //GCEA_ADDRDEC0_COL_SEL_HI_CS01 |
5074 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
5075 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
5076 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
5077 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
5078 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
5079 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
5080 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
5081 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
5082 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
5083 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
5084 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
5085 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
5086 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
5087 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
5088 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
5089 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
5090 | //GCEA_ADDRDEC0_COL_SEL_HI_CS23 |
5091 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
5092 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
5093 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
5094 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
5095 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
5096 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
5097 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
5098 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
5099 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
5100 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
5101 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
5102 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
5103 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
5104 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
5105 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
5106 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
5107 | //GCEA_ADDRDEC0_RM_SEL_CS01 |
5108 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 |
5109 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 |
5110 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 |
5111 | #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
5112 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5113 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5114 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL |
5115 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L |
5116 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L |
5117 | #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
5118 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5119 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5120 | //GCEA_ADDRDEC0_RM_SEL_CS23 |
5121 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 |
5122 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 |
5123 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 |
5124 | #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
5125 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5126 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5127 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL |
5128 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L |
5129 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L |
5130 | #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
5131 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5132 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5133 | //GCEA_ADDRDEC0_RM_SEL_SECCS01 |
5134 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
5135 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
5136 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
5137 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
5138 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5139 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5140 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
5141 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
5142 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
5143 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
5144 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5145 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5146 | //GCEA_ADDRDEC0_RM_SEL_SECCS23 |
5147 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
5148 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
5149 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
5150 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
5151 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5152 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5153 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
5154 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
5155 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
5156 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
5157 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5158 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5159 | //GCEA_ADDRDEC1_BASE_ADDR_CS0 |
5160 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 |
5161 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
5162 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L |
5163 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
5164 | //GCEA_ADDRDEC1_BASE_ADDR_CS1 |
5165 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 |
5166 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
5167 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L |
5168 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
5169 | //GCEA_ADDRDEC1_BASE_ADDR_CS2 |
5170 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 |
5171 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
5172 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L |
5173 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
5174 | //GCEA_ADDRDEC1_BASE_ADDR_CS3 |
5175 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 |
5176 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
5177 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L |
5178 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
5179 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS0 |
5180 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 |
5181 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
5182 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L |
5183 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
5184 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS1 |
5185 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 |
5186 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
5187 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L |
5188 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
5189 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS2 |
5190 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 |
5191 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
5192 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L |
5193 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
5194 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS3 |
5195 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 |
5196 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
5197 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L |
5198 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
5199 | //GCEA_ADDRDEC1_ADDR_MASK_CS01 |
5200 | #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
5201 | #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
5202 | //GCEA_ADDRDEC1_ADDR_MASK_CS23 |
5203 | #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
5204 | #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
5205 | //GCEA_ADDRDEC1_ADDR_MASK_SECCS01 |
5206 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
5207 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
5208 | //GCEA_ADDRDEC1_ADDR_MASK_SECCS23 |
5209 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
5210 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
5211 | //GCEA_ADDRDEC1_ADDR_CFG_CS01 |
5212 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 |
5213 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
5214 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
5215 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
5216 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
5217 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
5218 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f |
5219 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL |
5220 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
5221 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
5222 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
5223 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
5224 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
5225 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L |
5226 | //GCEA_ADDRDEC1_ADDR_CFG_CS23 |
5227 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 |
5228 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
5229 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
5230 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
5231 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
5232 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
5233 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f |
5234 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL |
5235 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
5236 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
5237 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
5238 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
5239 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
5240 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L |
5241 | //GCEA_ADDRDEC1_ADDR_SEL_CS01 |
5242 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
5243 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
5244 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
5245 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
5246 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
5247 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
5248 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
5249 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
5250 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
5251 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
5252 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
5253 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L |
5254 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
5255 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
5256 | //GCEA_ADDRDEC1_ADDR_SEL_CS23 |
5257 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
5258 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
5259 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
5260 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
5261 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
5262 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
5263 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
5264 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
5265 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
5266 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
5267 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
5268 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L |
5269 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
5270 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
5271 | //GCEA_ADDRDEC1_ADDR_SEL2_CS01 |
5272 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 |
5273 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc |
5274 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL |
5275 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L |
5276 | //GCEA_ADDRDEC1_ADDR_SEL2_CS23 |
5277 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 |
5278 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc |
5279 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL |
5280 | #define GCEA_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L |
5281 | //GCEA_ADDRDEC1_COL_SEL_LO_CS01 |
5282 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
5283 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
5284 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
5285 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
5286 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
5287 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
5288 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
5289 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
5290 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
5291 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
5292 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
5293 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
5294 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
5295 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
5296 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
5297 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
5298 | //GCEA_ADDRDEC1_COL_SEL_LO_CS23 |
5299 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
5300 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
5301 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
5302 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
5303 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
5304 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
5305 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
5306 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
5307 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
5308 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
5309 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
5310 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
5311 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
5312 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
5313 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
5314 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
5315 | //GCEA_ADDRDEC1_COL_SEL_HI_CS01 |
5316 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
5317 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
5318 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
5319 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
5320 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
5321 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
5322 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
5323 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
5324 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
5325 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
5326 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
5327 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
5328 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
5329 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
5330 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
5331 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
5332 | //GCEA_ADDRDEC1_COL_SEL_HI_CS23 |
5333 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
5334 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
5335 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
5336 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
5337 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
5338 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
5339 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
5340 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
5341 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
5342 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
5343 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
5344 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
5345 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
5346 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
5347 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
5348 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
5349 | //GCEA_ADDRDEC1_RM_SEL_CS01 |
5350 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 |
5351 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 |
5352 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 |
5353 | #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
5354 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5355 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5356 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL |
5357 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L |
5358 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L |
5359 | #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
5360 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5361 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5362 | //GCEA_ADDRDEC1_RM_SEL_CS23 |
5363 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 |
5364 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 |
5365 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 |
5366 | #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
5367 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5368 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5369 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL |
5370 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L |
5371 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L |
5372 | #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
5373 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5374 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5375 | //GCEA_ADDRDEC1_RM_SEL_SECCS01 |
5376 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
5377 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
5378 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
5379 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
5380 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5381 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5382 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
5383 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
5384 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
5385 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
5386 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5387 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5388 | //GCEA_ADDRDEC1_RM_SEL_SECCS23 |
5389 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
5390 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
5391 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
5392 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
5393 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5394 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5395 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
5396 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
5397 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
5398 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
5399 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5400 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5401 | //GCEA_ADDRDEC2_BASE_ADDR_CS0 |
5402 | #define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 |
5403 | #define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
5404 | #define GCEA_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L |
5405 | #define GCEA_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
5406 | //GCEA_ADDRDEC2_BASE_ADDR_CS1 |
5407 | #define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 |
5408 | #define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
5409 | #define GCEA_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L |
5410 | #define GCEA_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
5411 | //GCEA_ADDRDEC2_BASE_ADDR_CS2 |
5412 | #define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 |
5413 | #define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
5414 | #define GCEA_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L |
5415 | #define GCEA_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
5416 | //GCEA_ADDRDEC2_BASE_ADDR_CS3 |
5417 | #define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 |
5418 | #define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
5419 | #define GCEA_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L |
5420 | #define GCEA_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
5421 | //GCEA_ADDRDEC2_BASE_ADDR_SECCS0 |
5422 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 |
5423 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
5424 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L |
5425 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
5426 | //GCEA_ADDRDEC2_BASE_ADDR_SECCS1 |
5427 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 |
5428 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
5429 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L |
5430 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
5431 | //GCEA_ADDRDEC2_BASE_ADDR_SECCS2 |
5432 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 |
5433 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
5434 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L |
5435 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
5436 | //GCEA_ADDRDEC2_BASE_ADDR_SECCS3 |
5437 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 |
5438 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
5439 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L |
5440 | #define GCEA_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
5441 | //GCEA_ADDRDEC2_ADDR_MASK_CS01 |
5442 | #define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
5443 | #define GCEA_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
5444 | //GCEA_ADDRDEC2_ADDR_MASK_CS23 |
5445 | #define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
5446 | #define GCEA_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
5447 | //GCEA_ADDRDEC2_ADDR_MASK_SECCS01 |
5448 | #define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
5449 | #define GCEA_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
5450 | //GCEA_ADDRDEC2_ADDR_MASK_SECCS23 |
5451 | #define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
5452 | #define GCEA_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
5453 | //GCEA_ADDRDEC2_ADDR_CFG_CS01 |
5454 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 |
5455 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
5456 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
5457 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
5458 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
5459 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
5460 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f |
5461 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL |
5462 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
5463 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
5464 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
5465 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
5466 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
5467 | #define GCEA_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L |
5468 | //GCEA_ADDRDEC2_ADDR_CFG_CS23 |
5469 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 |
5470 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
5471 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
5472 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
5473 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
5474 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
5475 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f |
5476 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL |
5477 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
5478 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
5479 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
5480 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
5481 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
5482 | #define GCEA_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L |
5483 | //GCEA_ADDRDEC2_ADDR_SEL_CS01 |
5484 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
5485 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
5486 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
5487 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
5488 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
5489 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
5490 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
5491 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
5492 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
5493 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
5494 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
5495 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L |
5496 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
5497 | #define GCEA_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
5498 | //GCEA_ADDRDEC2_ADDR_SEL_CS23 |
5499 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
5500 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
5501 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
5502 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
5503 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
5504 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
5505 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
5506 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
5507 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
5508 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
5509 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
5510 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L |
5511 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
5512 | #define GCEA_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
5513 | //GCEA_ADDRDEC2_ADDR_SEL2_CS01 |
5514 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 |
5515 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc |
5516 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL |
5517 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L |
5518 | //GCEA_ADDRDEC2_ADDR_SEL2_CS23 |
5519 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 |
5520 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc |
5521 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL |
5522 | #define GCEA_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L |
5523 | //GCEA_ADDRDEC2_COL_SEL_LO_CS01 |
5524 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
5525 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
5526 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
5527 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
5528 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
5529 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
5530 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
5531 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
5532 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
5533 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
5534 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
5535 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
5536 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
5537 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
5538 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
5539 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
5540 | //GCEA_ADDRDEC2_COL_SEL_LO_CS23 |
5541 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
5542 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
5543 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
5544 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
5545 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
5546 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
5547 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
5548 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
5549 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
5550 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
5551 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
5552 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
5553 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
5554 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
5555 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
5556 | #define GCEA_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
5557 | //GCEA_ADDRDEC2_COL_SEL_HI_CS01 |
5558 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
5559 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
5560 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
5561 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
5562 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
5563 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
5564 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
5565 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
5566 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
5567 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
5568 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
5569 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
5570 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
5571 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
5572 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
5573 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
5574 | //GCEA_ADDRDEC2_COL_SEL_HI_CS23 |
5575 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
5576 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
5577 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
5578 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
5579 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
5580 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
5581 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
5582 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
5583 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
5584 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
5585 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
5586 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
5587 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
5588 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
5589 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
5590 | #define GCEA_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
5591 | //GCEA_ADDRDEC2_RM_SEL_CS01 |
5592 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 |
5593 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 |
5594 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 |
5595 | #define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
5596 | #define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5597 | #define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5598 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL |
5599 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L |
5600 | #define GCEA_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L |
5601 | #define GCEA_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
5602 | #define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5603 | #define GCEA_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5604 | //GCEA_ADDRDEC2_RM_SEL_CS23 |
5605 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 |
5606 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 |
5607 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 |
5608 | #define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
5609 | #define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5610 | #define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5611 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL |
5612 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L |
5613 | #define GCEA_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L |
5614 | #define GCEA_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
5615 | #define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5616 | #define GCEA_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5617 | //GCEA_ADDRDEC2_RM_SEL_SECCS01 |
5618 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
5619 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
5620 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
5621 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
5622 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5623 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5624 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
5625 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
5626 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
5627 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
5628 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5629 | #define GCEA_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5630 | //GCEA_ADDRDEC2_RM_SEL_SECCS23 |
5631 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
5632 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
5633 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
5634 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
5635 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
5636 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
5637 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
5638 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
5639 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
5640 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
5641 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
5642 | #define GCEA_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
5643 | //GCEA_ADDRNORMDRAM_GLOBAL_CNTL |
5644 | //GCEA_ADDRNORMGMI_GLOBAL_CNTL |
5645 | //GCEA_ADDRNORM_MEGACONTROL_ADDR0 |
5646 | #define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 |
5647 | #define GCEA_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL |
5648 | //GCEA_ADDRNORM_MEGACONTROL_ADDR1 |
5649 | #define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 |
5650 | #define GCEA_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL |
5651 | //GCEA_ADDRNORMDRAM_MASKING |
5652 | #define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 |
5653 | #define GCEA_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL |
5654 | //GCEA_ADDRNORMGMI_MASKING |
5655 | #define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 |
5656 | #define GCEA_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL |
5657 | //GCEA_IO_RD_CLI2GRP_MAP0 |
5658 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
5659 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
5660 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
5661 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
5662 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
5663 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
5664 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
5665 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
5666 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
5667 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
5668 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
5669 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
5670 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
5671 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
5672 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
5673 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
5674 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
5675 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
5676 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
5677 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
5678 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
5679 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
5680 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
5681 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
5682 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
5683 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
5684 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
5685 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
5686 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
5687 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
5688 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
5689 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
5690 | //GCEA_IO_RD_CLI2GRP_MAP1 |
5691 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
5692 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
5693 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
5694 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
5695 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
5696 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
5697 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
5698 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
5699 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
5700 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
5701 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
5702 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
5703 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
5704 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
5705 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
5706 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
5707 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
5708 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
5709 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
5710 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
5711 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
5712 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
5713 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
5714 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
5715 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
5716 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
5717 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
5718 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
5719 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
5720 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
5721 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
5722 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
5723 | //GCEA_IO_WR_CLI2GRP_MAP0 |
5724 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
5725 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
5726 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
5727 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
5728 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
5729 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
5730 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
5731 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
5732 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
5733 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
5734 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
5735 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
5736 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
5737 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
5738 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
5739 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
5740 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
5741 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
5742 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
5743 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
5744 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
5745 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
5746 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
5747 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
5748 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
5749 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
5750 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
5751 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
5752 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
5753 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
5754 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
5755 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
5756 | //GCEA_IO_WR_CLI2GRP_MAP1 |
5757 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
5758 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
5759 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
5760 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
5761 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
5762 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
5763 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
5764 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
5765 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
5766 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
5767 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
5768 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
5769 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
5770 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
5771 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
5772 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
5773 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
5774 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
5775 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
5776 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
5777 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
5778 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
5779 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
5780 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
5781 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
5782 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
5783 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
5784 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
5785 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
5786 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
5787 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
5788 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
5789 | //GCEA_IO_RD_COMBINE_FLUSH |
5790 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
5791 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
5792 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
5793 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
5794 | #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
5795 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
5796 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
5797 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
5798 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
5799 | #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
5800 | //GCEA_IO_WR_COMBINE_FLUSH |
5801 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
5802 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
5803 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
5804 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
5805 | #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
5806 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
5807 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
5808 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
5809 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
5810 | #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
5811 | //GCEA_IO_GROUP_BURST |
5812 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
5813 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
5814 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
5815 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
5816 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
5817 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
5818 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
5819 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
5820 | //GCEA_IO_RD_PRI_AGE |
5821 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
5822 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
5823 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
5824 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
5825 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
5826 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
5827 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
5828 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
5829 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
5830 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
5831 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
5832 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
5833 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
5834 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
5835 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
5836 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
5837 | //GCEA_IO_WR_PRI_AGE |
5838 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
5839 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
5840 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
5841 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
5842 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
5843 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
5844 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
5845 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
5846 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
5847 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
5848 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
5849 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
5850 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
5851 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
5852 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
5853 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
5854 | //GCEA_IO_RD_PRI_QUEUING |
5855 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
5856 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
5857 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
5858 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
5859 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
5860 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
5861 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
5862 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
5863 | //GCEA_IO_WR_PRI_QUEUING |
5864 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
5865 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
5866 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
5867 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
5868 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
5869 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
5870 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
5871 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
5872 | //GCEA_IO_RD_PRI_FIXED |
5873 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
5874 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
5875 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
5876 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
5877 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
5878 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
5879 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
5880 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
5881 | //GCEA_IO_WR_PRI_FIXED |
5882 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
5883 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
5884 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
5885 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
5886 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
5887 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
5888 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
5889 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
5890 | //GCEA_IO_RD_PRI_URGENCY |
5891 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
5892 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
5893 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
5894 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
5895 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
5896 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
5897 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
5898 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
5899 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
5900 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
5901 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
5902 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
5903 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
5904 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
5905 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
5906 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
5907 | //GCEA_IO_WR_PRI_URGENCY |
5908 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
5909 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
5910 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
5911 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
5912 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
5913 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
5914 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
5915 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
5916 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
5917 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
5918 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
5919 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
5920 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
5921 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
5922 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
5923 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
5924 | //GCEA_IO_RD_PRI_URGENCY_MASKING |
5925 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
5926 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
5927 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
5928 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
5929 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
5930 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
5931 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
5932 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
5933 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
5934 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
5935 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
5936 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
5937 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
5938 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
5939 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
5940 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
5941 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
5942 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
5943 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
5944 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
5945 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
5946 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
5947 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
5948 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
5949 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
5950 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
5951 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
5952 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
5953 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
5954 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
5955 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
5956 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
5957 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
5958 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
5959 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
5960 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
5961 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
5962 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
5963 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
5964 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
5965 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
5966 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
5967 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
5968 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
5969 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
5970 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
5971 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
5972 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
5973 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
5974 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
5975 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
5976 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
5977 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
5978 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
5979 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
5980 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
5981 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
5982 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
5983 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
5984 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
5985 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
5986 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
5987 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
5988 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
5989 | //GCEA_IO_WR_PRI_URGENCY_MASKING |
5990 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
5991 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
5992 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
5993 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
5994 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
5995 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
5996 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
5997 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
5998 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
5999 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
6000 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
6001 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
6002 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
6003 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
6004 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
6005 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
6006 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
6007 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
6008 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
6009 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
6010 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
6011 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
6012 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
6013 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
6014 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
6015 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
6016 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
6017 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
6018 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
6019 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
6020 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
6021 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
6022 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
6023 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
6024 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
6025 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
6026 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
6027 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
6028 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
6029 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
6030 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
6031 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
6032 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
6033 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
6034 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
6035 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
6036 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
6037 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
6038 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
6039 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
6040 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
6041 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
6042 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
6043 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
6044 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
6045 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
6046 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
6047 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
6048 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
6049 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
6050 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
6051 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
6052 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
6053 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
6054 | //GCEA_IO_RD_PRI_QUANT_PRI1 |
6055 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
6056 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
6057 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
6058 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
6059 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
6060 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6061 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6062 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
6063 | //GCEA_IO_RD_PRI_QUANT_PRI2 |
6064 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
6065 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
6066 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
6067 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
6068 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
6069 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6070 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6071 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
6072 | //GCEA_IO_RD_PRI_QUANT_PRI3 |
6073 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
6074 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
6075 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
6076 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
6077 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
6078 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6079 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6080 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
6081 | //GCEA_IO_WR_PRI_QUANT_PRI1 |
6082 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
6083 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
6084 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
6085 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
6086 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
6087 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6088 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6089 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
6090 | //GCEA_IO_WR_PRI_QUANT_PRI2 |
6091 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
6092 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
6093 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
6094 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
6095 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
6096 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6097 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6098 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
6099 | //GCEA_IO_WR_PRI_QUANT_PRI3 |
6100 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
6101 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
6102 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
6103 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
6104 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
6105 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
6106 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
6107 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
6108 | //GCEA_MISC |
6109 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
6110 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
6111 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
6112 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
6113 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
6114 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
6115 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
6116 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
6117 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
6118 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
6119 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
6120 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
6121 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
6122 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
6123 | #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
6124 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
6125 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
6126 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
6127 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
6128 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
6129 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
6130 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
6131 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
6132 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
6133 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
6134 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
6135 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
6136 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
6137 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
6138 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
6139 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
6140 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
6141 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
6142 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
6143 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
6144 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
6145 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
6146 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
6147 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
6148 | #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
6149 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
6150 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
6151 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
6152 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
6153 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
6154 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
6155 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
6156 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
6157 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
6158 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
6159 | //GCEA_LATENCY_SAMPLING |
6160 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
6161 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
6162 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
6163 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
6164 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
6165 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
6166 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
6167 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
6168 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
6169 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
6170 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
6171 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
6172 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
6173 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
6174 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
6175 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
6176 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
6177 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
6178 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
6179 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
6180 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
6181 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
6182 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
6183 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
6184 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
6185 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
6186 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
6187 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
6188 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
6189 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
6190 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
6191 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
6192 | //GCEA_PERFCOUNTER_LO |
6193 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
6194 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
6195 | //GCEA_PERFCOUNTER_HI |
6196 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
6197 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
6198 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
6199 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
6200 | //GCEA_PERFCOUNTER0_CFG |
6201 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
6202 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
6203 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
6204 | #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
6205 | #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
6206 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
6207 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6208 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
6209 | #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
6210 | #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
6211 | //GCEA_PERFCOUNTER1_CFG |
6212 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
6213 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
6214 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
6215 | #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
6216 | #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
6217 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
6218 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6219 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
6220 | #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
6221 | #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
6222 | |
6223 | |
6224 | // addressBlock: gc_ea_gceadec2 |
6225 | //GCEA_PERFCOUNTER_RSLT_CNTL |
6226 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
6227 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
6228 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
6229 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
6230 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
6231 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
6232 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
6233 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
6234 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
6235 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
6236 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
6237 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
6238 | //GCEA_EDC_CNT |
6239 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
6240 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
6241 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
6242 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
6243 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
6244 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa |
6245 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc |
6246 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe |
6247 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 |
6248 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 |
6249 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 |
6250 | #define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 |
6251 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 |
6252 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a |
6253 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c |
6254 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e |
6255 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
6256 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
6257 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
6258 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
6259 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
6260 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
6261 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L |
6262 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L |
6263 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L |
6264 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L |
6265 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L |
6266 | #define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L |
6267 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L |
6268 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L |
6269 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L |
6270 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L |
6271 | //GCEA_EDC_CNT2 |
6272 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
6273 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
6274 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
6275 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
6276 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
6277 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa |
6278 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc |
6279 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe |
6280 | #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 |
6281 | #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 |
6282 | #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 |
6283 | #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 |
6284 | #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 |
6285 | #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a |
6286 | #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c |
6287 | #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e |
6288 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
6289 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
6290 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
6291 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
6292 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
6293 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
6294 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L |
6295 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L |
6296 | #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L |
6297 | #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L |
6298 | #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L |
6299 | #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L |
6300 | #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L |
6301 | #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L |
6302 | #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L |
6303 | #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L |
6304 | //GCEA_DSM_CNTL |
6305 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
6306 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
6307 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
6308 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
6309 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
6310 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
6311 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
6312 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
6313 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
6314 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
6315 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
6316 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
6317 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
6318 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
6319 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
6320 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
6321 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
6322 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
6323 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
6324 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
6325 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
6326 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
6327 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
6328 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
6329 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
6330 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
6331 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
6332 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
6333 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
6334 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
6335 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
6336 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
6337 | //GCEA_DSM_CNTLA |
6338 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
6339 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
6340 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
6341 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
6342 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
6343 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
6344 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
6345 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
6346 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
6347 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
6348 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
6349 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
6350 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
6351 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
6352 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
6353 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
6354 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
6355 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
6356 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
6357 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
6358 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
6359 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
6360 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
6361 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
6362 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
6363 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
6364 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
6365 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
6366 | //GCEA_DSM_CNTLB |
6367 | //GCEA_DSM_CNTL2 |
6368 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
6369 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
6370 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
6371 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
6372 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
6373 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
6374 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
6375 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
6376 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
6377 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
6378 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
6379 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
6380 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
6381 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
6382 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
6383 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
6384 | #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
6385 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
6386 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
6387 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
6388 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
6389 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
6390 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
6391 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
6392 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
6393 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
6394 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
6395 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
6396 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
6397 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
6398 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
6399 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
6400 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
6401 | #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
6402 | //GCEA_DSM_CNTL2A |
6403 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
6404 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
6405 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
6406 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
6407 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
6408 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
6409 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
6410 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
6411 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
6412 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
6413 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
6414 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
6415 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
6416 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
6417 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
6418 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
6419 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
6420 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
6421 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
6422 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
6423 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
6424 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
6425 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
6426 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
6427 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
6428 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
6429 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
6430 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
6431 | //GCEA_DSM_CNTL2B |
6432 | //GCEA_TCC_XBR_CREDITS |
6433 | #define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 |
6434 | #define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 |
6435 | #define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 |
6436 | #define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe |
6437 | #define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 |
6438 | #define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 |
6439 | #define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 |
6440 | #define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e |
6441 | #define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL |
6442 | #define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L |
6443 | #define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L |
6444 | #define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L |
6445 | #define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L |
6446 | #define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L |
6447 | #define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L |
6448 | #define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L |
6449 | //GCEA_TCC_XBR_MAXBURST |
6450 | #define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 |
6451 | #define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 |
6452 | #define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 |
6453 | #define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc |
6454 | #define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL |
6455 | #define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L |
6456 | #define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L |
6457 | #define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L |
6458 | //GCEA_PROBE_CNTL |
6459 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 |
6460 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 |
6461 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL |
6462 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L |
6463 | //GCEA_PROBE_MAP |
6464 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 |
6465 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 |
6466 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 |
6467 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 |
6468 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 |
6469 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 |
6470 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 |
6471 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 |
6472 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 |
6473 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 |
6474 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa |
6475 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb |
6476 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc |
6477 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd |
6478 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe |
6479 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf |
6480 | #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 |
6481 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L |
6482 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L |
6483 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L |
6484 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L |
6485 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L |
6486 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L |
6487 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L |
6488 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L |
6489 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L |
6490 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L |
6491 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L |
6492 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L |
6493 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L |
6494 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L |
6495 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L |
6496 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L |
6497 | #define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L |
6498 | //GCEA_ERR_STATUS |
6499 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
6500 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
6501 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
6502 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
6503 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
6504 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
6505 | #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
6506 | #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
6507 | #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
6508 | #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
6509 | #define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
6510 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
6511 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
6512 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
6513 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
6514 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
6515 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
6516 | #define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
6517 | #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
6518 | #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
6519 | #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
6520 | #define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
6521 | //GCEA_MISC2 |
6522 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
6523 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
6524 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
6525 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
6526 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
6527 | #define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd |
6528 | #define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe |
6529 | #define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf |
6530 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
6531 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
6532 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
6533 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
6534 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
6535 | #define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L |
6536 | #define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L |
6537 | #define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L |
6538 | //GCEA_DRAM_BANK_ARB |
6539 | #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0 |
6540 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1 |
6541 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x9 |
6542 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xf |
6543 | #define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX__SHIFT 0x10 |
6544 | #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L |
6545 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000001FEL |
6546 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00007E00L |
6547 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00008000L |
6548 | #define GCEA_DRAM_BANK_ARB__DISABLE_STALLMODE_FIX_MASK 0x00010000L |
6549 | //GCEA_ADDRDEC_SELECT |
6550 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 |
6551 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 |
6552 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa |
6553 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf |
6554 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL |
6555 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L |
6556 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L |
6557 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L |
6558 | //GCEA_EDC_CNT3 |
6559 | #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 |
6560 | #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 |
6561 | #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 |
6562 | #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
6563 | #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 |
6564 | #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa |
6565 | #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0xc |
6566 | #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0xe |
6567 | #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x10 |
6568 | #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x12 |
6569 | #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x14 |
6570 | #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x16 |
6571 | #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x18 |
6572 | #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1a |
6573 | #define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT 0x1c |
6574 | #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0x1e |
6575 | #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L |
6576 | #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL |
6577 | #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L |
6578 | #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
6579 | #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L |
6580 | #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L |
6581 | #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00003000L |
6582 | #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x0000C000L |
6583 | #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00030000L |
6584 | #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x000C0000L |
6585 | #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x00300000L |
6586 | #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x00C00000L |
6587 | #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x03000000L |
6588 | #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0x0C000000L |
6589 | #define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK 0x30000000L |
6590 | #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0xC0000000L |
6591 | |
6592 | // addressBlock: gc_ea_pwrdec |
6593 | //GCEA_CGTT_CLK_CTRL |
6594 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
6595 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
6596 | #define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
6597 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
6598 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
6599 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
6600 | #define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
6601 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
6602 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
6603 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
6604 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
6605 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
6606 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
6607 | #define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
6608 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
6609 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
6610 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
6611 | #define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L |
6612 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
6613 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
6614 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
6615 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
6616 | |
6617 | |
6618 | // addressBlock: gc_gccacdec |
6619 | //GC_CAC_CTRL_1 |
6620 | #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 |
6621 | #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 |
6622 | #define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL |
6623 | #define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L |
6624 | //GC_CAC_CTRL_2 |
6625 | #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 |
6626 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 |
6627 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2 |
6628 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3 |
6629 | #define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L |
6630 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L |
6631 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L |
6632 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L |
6633 | //GC_CAC_INDEX_AUTO_INCR_EN |
6634 | #define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x0 |
6635 | #define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000001L |
6636 | //GC_CAC_AGGR_LOWER |
6637 | #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 |
6638 | #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL |
6639 | //GC_CAC_AGGR_UPPER |
6640 | #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 |
6641 | #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL |
6642 | //GC_EDC_PERF_COUNTER |
6643 | #define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 |
6644 | #define GC_EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL |
6645 | //PCC_PERF_COUNTER |
6646 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 |
6647 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
6648 | //GC_CAC_SOFT_CTRL |
6649 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 |
6650 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L |
6651 | //GC_DIDT_CTRL0 |
6652 | #define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
6653 | #define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
6654 | #define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 |
6655 | #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
6656 | #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 |
6657 | #define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
6658 | #define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
6659 | #define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L |
6660 | #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
6661 | #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L |
6662 | //GC_DIDT_CTRL1 |
6663 | #define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 |
6664 | #define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 |
6665 | #define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
6666 | #define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
6667 | //GC_DIDT_CTRL2 |
6668 | #define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
6669 | #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
6670 | #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
6671 | #define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
6672 | #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
6673 | #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
6674 | //GC_DIDT_WEIGHT |
6675 | #define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 |
6676 | #define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 |
6677 | #define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 |
6678 | #define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 |
6679 | #define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL |
6680 | #define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L |
6681 | #define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L |
6682 | #define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L |
6683 | //GC_THROTTLE_CTRL1 |
6684 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 |
6685 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 |
6686 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 |
6687 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa |
6688 | #define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN__SHIFT 0xd |
6689 | #define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE__SHIFT 0xe |
6690 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x11 |
6691 | #define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN__SHIFT 0x13 |
6692 | #define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN__SHIFT 0x14 |
6693 | #define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE__SHIFT 0x15 |
6694 | #define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL__SHIFT 0x16 |
6695 | #define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN__SHIFT 0x17 |
6696 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x18 |
6697 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L |
6698 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL |
6699 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L |
6700 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L |
6701 | #define GC_THROTTLE_CTRL1__PATTERN_EXTEND_EN_MASK 0x00002000L |
6702 | #define GC_THROTTLE_CTRL1__PATTERN_EXTEND_MODE_MASK 0x0001C000L |
6703 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x00060000L |
6704 | #define GC_THROTTLE_CTRL1__FP_PATTERN_CLAMP_EN_MASK 0x00080000L |
6705 | #define GC_THROTTLE_CTRL1__PWRBRK_STALL_EN_MASK 0x00100000L |
6706 | #define GC_THROTTLE_CTRL1__PWRBRK_OVERRIDE_MASK 0x00200000L |
6707 | #define GC_THROTTLE_CTRL1__PWRBRK_POLARITY_CNTL_MASK 0x00400000L |
6708 | #define GC_THROTTLE_CTRL1__PWRBRK_PERF_COUNTER_EN_MASK 0x00800000L |
6709 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x07000000L |
6710 | //GC_EDC_CTRL |
6711 | #define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 |
6712 | #define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
6713 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
6714 | #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
6715 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
6716 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 |
6717 | #define GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT 0xb |
6718 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xc |
6719 | #define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x10 |
6720 | #define GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0x14 |
6721 | #define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0x1e |
6722 | #define GC_EDC_CTRL__PCC_DITHER_MODE__SHIFT 0x1f |
6723 | #define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L |
6724 | #define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
6725 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
6726 | #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
6727 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
6728 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L |
6729 | #define GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000800L |
6730 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x0000F000L |
6731 | #define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x000F0000L |
6732 | #define GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK 0x3FF00000L |
6733 | #define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x40000000L |
6734 | #define GC_EDC_CTRL__PCC_DITHER_MODE_MASK 0x80000000L |
6735 | //GC_EDC_THRESHOLD |
6736 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
6737 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
6738 | //GC_EDC_STATUS |
6739 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 |
6740 | #define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX__SHIFT 0x3 |
6741 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L |
6742 | #define GC_EDC_STATUS__THROTTLE_PATTERN_INDEX_MASK 0x000001F8L |
6743 | //GC_EDC_OVERFLOW |
6744 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
6745 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
6746 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
6747 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
6748 | //GC_EDC_ROLLING_POWER_DELTA |
6749 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
6750 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
6751 | //GC_EDC_CTRL1 |
6752 | #define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL__SHIFT 0x0 |
6753 | #define GC_EDC_CTRL1__THROTTLE_SRC0_MASK__SHIFT 0x4 |
6754 | #define GC_EDC_CTRL1__THROTTLE_SRC1_MASK__SHIFT 0x5 |
6755 | #define GC_EDC_CTRL1__THROTTLE_SRC2_MASK__SHIFT 0x6 |
6756 | #define GC_EDC_CTRL1__THROTTLE_SRC3_MASK__SHIFT 0x7 |
6757 | #define GC_EDC_CTRL1__THROTTLE_SRC4_MASK__SHIFT 0x8 |
6758 | #define GC_EDC_CTRL1__THROTTLE_SRC5_MASK__SHIFT 0x9 |
6759 | #define GC_EDC_CTRL1__THROTTLE_SRC6_MASK__SHIFT 0xa |
6760 | #define GC_EDC_CTRL1__THROTTLE_SRC7_MASK__SHIFT 0xb |
6761 | #define GC_EDC_CTRL1__PSM_THROTTLE_SRC_SEL_MASK 0x0000000FL |
6762 | #define GC_EDC_CTRL1__THROTTLE_SRC0_MASK_MASK 0x00000010L |
6763 | #define GC_EDC_CTRL1__THROTTLE_SRC1_MASK_MASK 0x00000020L |
6764 | #define GC_EDC_CTRL1__THROTTLE_SRC2_MASK_MASK 0x00000040L |
6765 | #define GC_EDC_CTRL1__THROTTLE_SRC3_MASK_MASK 0x00000080L |
6766 | #define GC_EDC_CTRL1__THROTTLE_SRC4_MASK_MASK 0x00000100L |
6767 | #define GC_EDC_CTRL1__THROTTLE_SRC5_MASK_MASK 0x00000200L |
6768 | #define GC_EDC_CTRL1__THROTTLE_SRC6_MASK_MASK 0x00000400L |
6769 | #define GC_EDC_CTRL1__THROTTLE_SRC7_MASK_MASK 0x00000800L |
6770 | //GC_THROTTLE_CTRL2 |
6771 | #define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0x0 |
6772 | #define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0x1 |
6773 | #define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x5 |
6774 | #define GC_THROTTLE_CTRL2__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00000001L |
6775 | #define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0000001EL |
6776 | #define GC_THROTTLE_CTRL2__PWRBRK_PROGRAM_MAX_STEP_MASK 0x000003E0L |
6777 | //PWRBRK_PERF_COUNTER |
6778 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 |
6779 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL |
6780 | //GC_THROTTLE_CTRL |
6781 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 |
6782 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 |
6783 | #define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x2 |
6784 | #define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x3 |
6785 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x4 |
6786 | #define GC_THROTTLE_CTRL__NON_DITHER__SHIFT 0x5 |
6787 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x7 |
6788 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0x8 |
6789 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0x9 |
6790 | #define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa |
6791 | #define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT 0x14 |
6792 | #define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT 0x19 |
6793 | #define GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT 0x1e |
6794 | #define GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT 0x1f |
6795 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L |
6796 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L |
6797 | #define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000004L |
6798 | #define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000008L |
6799 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000010L |
6800 | #define GC_THROTTLE_CTRL__NON_DITHER_MASK 0x00000020L |
6801 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000080L |
6802 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000100L |
6803 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000200L |
6804 | #define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK 0x000FFC00L |
6805 | #define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK 0x01F00000L |
6806 | #define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK 0x3E000000L |
6807 | #define GC_THROTTLE_CTRL__INST_THROT_INCR_MASK 0x40000000L |
6808 | #define GC_THROTTLE_CTRL__INST_THROT_DECR_MASK 0x80000000L |
6809 | //GC_CAC_IND_INDEX |
6810 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 |
6811 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
6812 | //GC_CAC_IND_DATA |
6813 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 |
6814 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL |
6815 | //SE_CAC_IND_INDEX |
6816 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 |
6817 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
6818 | //SE_CAC_IND_DATA |
6819 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 |
6820 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL |
6821 | |
6822 | |
6823 | |
6824 | |
6825 | // addressBlock: gc_gdsdec |
6826 | //GDS_CONFIG |
6827 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 |
6828 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 |
6829 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 |
6830 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 |
6831 | #define GDS_CONFIG__SH4_GPR_PHASE_SEL__SHIFT 0x9 |
6832 | #define GDS_CONFIG__SH5_GPR_PHASE_SEL__SHIFT 0xb |
6833 | #define GDS_CONFIG__SH6_GPR_PHASE_SEL__SHIFT 0xd |
6834 | #define GDS_CONFIG__SH7_GPR_PHASE_SEL__SHIFT 0xf |
6835 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L |
6836 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L |
6837 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L |
6838 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L |
6839 | #define GDS_CONFIG__SH4_GPR_PHASE_SEL_MASK 0x00000600L |
6840 | #define GDS_CONFIG__SH5_GPR_PHASE_SEL_MASK 0x00001800L |
6841 | #define GDS_CONFIG__SH6_GPR_PHASE_SEL_MASK 0x00006000L |
6842 | #define GDS_CONFIG__SH7_GPR_PHASE_SEL_MASK 0x00018000L |
6843 | //GDS_CNTL_STATUS |
6844 | #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 |
6845 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 |
6846 | #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 |
6847 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 |
6848 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 |
6849 | #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 |
6850 | #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 |
6851 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 |
6852 | #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 |
6853 | #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 |
6854 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa |
6855 | #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb |
6856 | #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc |
6857 | #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd |
6858 | #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe |
6859 | #define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xf |
6860 | #define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0x10 |
6861 | #define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0x11 |
6862 | #define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x12 |
6863 | #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L |
6864 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L |
6865 | #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L |
6866 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L |
6867 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L |
6868 | #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L |
6869 | #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L |
6870 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L |
6871 | #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L |
6872 | #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L |
6873 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L |
6874 | #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L |
6875 | #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L |
6876 | #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L |
6877 | #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L |
6878 | #define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00008000L |
6879 | #define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00010000L |
6880 | #define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00020000L |
6881 | #define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00040000L |
6882 | //GDS_ENHANCE2 |
6883 | #define GDS_ENHANCE2__MISC__SHIFT 0x0 |
6884 | #define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE__SHIFT 0x10 |
6885 | #define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE__SHIFT 0x11 |
6886 | #define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE__SHIFT 0x12 |
6887 | #define GDS_ENHANCE2__UNUSED__SHIFT 0x13 |
6888 | #define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL |
6889 | #define GDS_ENHANCE2__GDS_TD_INTERFACES_FGCG_OVERRIDE_MASK 0x00010000L |
6890 | #define GDS_ENHANCE2__GDS_PHY_CMD_RAM_FGCG_OVERRIDE_MASK 0x00020000L |
6891 | #define GDS_ENHANCE2__GDS_FED_IN_PROPAGATE_MASK 0x00040000L |
6892 | #define GDS_ENHANCE2__UNUSED_MASK 0xFFF80000L |
6893 | //GDS_PROTECTION_FAULT |
6894 | #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
6895 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
6896 | #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 |
6897 | #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 |
6898 | #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 |
6899 | #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa |
6900 | #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc |
6901 | #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
6902 | #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
6903 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
6904 | #define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L |
6905 | #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L |
6906 | #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L |
6907 | #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L |
6908 | #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L |
6909 | #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
6910 | //GDS_VM_PROTECTION_FAULT |
6911 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
6912 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
6913 | #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 |
6914 | #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 |
6915 | #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 |
6916 | #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 |
6917 | #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 |
6918 | #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
6919 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
6920 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
6921 | #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L |
6922 | #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L |
6923 | #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L |
6924 | #define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L |
6925 | #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L |
6926 | #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
6927 | //GDS_EDC_CNT |
6928 | #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 |
6929 | #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 |
6930 | #define GDS_EDC_CNT__UNUSED__SHIFT 0x6 |
6931 | #define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L |
6932 | #define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L |
6933 | #define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L |
6934 | //GDS_EDC_GRBM_CNT |
6935 | #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 |
6936 | #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 |
6937 | #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 |
6938 | #define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L |
6939 | #define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL |
6940 | #define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L |
6941 | //GDS_EDC_OA_DED |
6942 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 |
6943 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 |
6944 | #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 |
6945 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 |
6946 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 |
6947 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 |
6948 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 |
6949 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 |
6950 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 |
6951 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 |
6952 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa |
6953 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb |
6954 | #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc |
6955 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L |
6956 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L |
6957 | #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L |
6958 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L |
6959 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L |
6960 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L |
6961 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L |
6962 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L |
6963 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L |
6964 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L |
6965 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L |
6966 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L |
6967 | #define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L |
6968 | //GDS_DSM_CNTL |
6969 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 |
6970 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 |
6971 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
6972 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 |
6973 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 |
6974 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
6975 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 |
6976 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 |
6977 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
6978 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 |
6979 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa |
6980 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
6981 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc |
6982 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd |
6983 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
6984 | #define GDS_DSM_CNTL__UNUSED__SHIFT 0xf |
6985 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L |
6986 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L |
6987 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
6988 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L |
6989 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L |
6990 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
6991 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L |
6992 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L |
6993 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
6994 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L |
6995 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L |
6996 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
6997 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L |
6998 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L |
6999 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
7000 | #define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L |
7001 | //GDS_EDC_OA_PHY_CNT |
7002 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 |
7003 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 |
7004 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 |
7005 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 |
7006 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8 |
7007 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa |
7008 | #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc |
7009 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L |
7010 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL |
7011 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L |
7012 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L |
7013 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L |
7014 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L |
7015 | #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L |
7016 | //GDS_EDC_OA_PIPE_CNT |
7017 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 |
7018 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 |
7019 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 |
7020 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 |
7021 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 |
7022 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa |
7023 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc |
7024 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe |
7025 | #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 |
7026 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L |
7027 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL |
7028 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L |
7029 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L |
7030 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L |
7031 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L |
7032 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L |
7033 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L |
7034 | #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L |
7035 | //GDS_DSM_CNTL2 |
7036 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
7037 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
7038 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 |
7039 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 |
7040 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
7041 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
7042 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
7043 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
7044 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
7045 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe |
7046 | #define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf |
7047 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a |
7048 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
7049 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
7050 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L |
7051 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L |
7052 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
7053 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
7054 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
7055 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
7056 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
7057 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
7058 | #define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L |
7059 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L |
7060 | //GDS_WD_GDS_CSB |
7061 | #define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 |
7062 | #define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd |
7063 | #define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL |
7064 | #define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L |
7065 | |
7066 | |
7067 | // addressBlock: gc_gdspdec |
7068 | //GDS_VMID0_BASE |
7069 | #define GDS_VMID0_BASE__BASE__SHIFT 0x0 |
7070 | #define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL |
7071 | //GDS_VMID0_SIZE |
7072 | #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 |
7073 | #define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL |
7074 | //GDS_VMID1_BASE |
7075 | #define GDS_VMID1_BASE__BASE__SHIFT 0x0 |
7076 | #define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL |
7077 | //GDS_VMID1_SIZE |
7078 | #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 |
7079 | #define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL |
7080 | //GDS_VMID2_BASE |
7081 | #define GDS_VMID2_BASE__BASE__SHIFT 0x0 |
7082 | #define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL |
7083 | //GDS_VMID2_SIZE |
7084 | #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 |
7085 | #define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL |
7086 | //GDS_VMID3_BASE |
7087 | #define GDS_VMID3_BASE__BASE__SHIFT 0x0 |
7088 | #define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL |
7089 | //GDS_VMID3_SIZE |
7090 | #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 |
7091 | #define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL |
7092 | //GDS_VMID4_BASE |
7093 | #define GDS_VMID4_BASE__BASE__SHIFT 0x0 |
7094 | #define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL |
7095 | //GDS_VMID4_SIZE |
7096 | #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 |
7097 | #define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL |
7098 | //GDS_VMID5_BASE |
7099 | #define GDS_VMID5_BASE__BASE__SHIFT 0x0 |
7100 | #define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL |
7101 | //GDS_VMID5_SIZE |
7102 | #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 |
7103 | #define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL |
7104 | //GDS_VMID6_BASE |
7105 | #define GDS_VMID6_BASE__BASE__SHIFT 0x0 |
7106 | #define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL |
7107 | //GDS_VMID6_SIZE |
7108 | #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 |
7109 | #define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL |
7110 | //GDS_VMID7_BASE |
7111 | #define GDS_VMID7_BASE__BASE__SHIFT 0x0 |
7112 | #define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL |
7113 | //GDS_VMID7_SIZE |
7114 | #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 |
7115 | #define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL |
7116 | //GDS_VMID8_BASE |
7117 | #define GDS_VMID8_BASE__BASE__SHIFT 0x0 |
7118 | #define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL |
7119 | //GDS_VMID8_SIZE |
7120 | #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 |
7121 | #define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL |
7122 | //GDS_VMID9_BASE |
7123 | #define GDS_VMID9_BASE__BASE__SHIFT 0x0 |
7124 | #define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL |
7125 | //GDS_VMID9_SIZE |
7126 | #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 |
7127 | #define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL |
7128 | //GDS_VMID10_BASE |
7129 | #define GDS_VMID10_BASE__BASE__SHIFT 0x0 |
7130 | #define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL |
7131 | //GDS_VMID10_SIZE |
7132 | #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 |
7133 | #define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL |
7134 | //GDS_VMID11_BASE |
7135 | #define GDS_VMID11_BASE__BASE__SHIFT 0x0 |
7136 | #define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL |
7137 | //GDS_VMID11_SIZE |
7138 | #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 |
7139 | #define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL |
7140 | //GDS_VMID12_BASE |
7141 | #define GDS_VMID12_BASE__BASE__SHIFT 0x0 |
7142 | #define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL |
7143 | //GDS_VMID12_SIZE |
7144 | #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 |
7145 | #define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL |
7146 | //GDS_VMID13_BASE |
7147 | #define GDS_VMID13_BASE__BASE__SHIFT 0x0 |
7148 | #define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL |
7149 | //GDS_VMID13_SIZE |
7150 | #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 |
7151 | #define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL |
7152 | //GDS_VMID14_BASE |
7153 | #define GDS_VMID14_BASE__BASE__SHIFT 0x0 |
7154 | #define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL |
7155 | //GDS_VMID14_SIZE |
7156 | #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 |
7157 | #define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL |
7158 | //GDS_VMID15_BASE |
7159 | #define GDS_VMID15_BASE__BASE__SHIFT 0x0 |
7160 | #define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL |
7161 | //GDS_VMID15_SIZE |
7162 | #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 |
7163 | #define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL |
7164 | //GDS_GWS_VMID0 |
7165 | #define GDS_GWS_VMID0__BASE__SHIFT 0x0 |
7166 | #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 |
7167 | #define GDS_GWS_VMID0__BASE_MASK 0x0000003FL |
7168 | #define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L |
7169 | //GDS_GWS_VMID1 |
7170 | #define GDS_GWS_VMID1__BASE__SHIFT 0x0 |
7171 | #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 |
7172 | #define GDS_GWS_VMID1__BASE_MASK 0x0000003FL |
7173 | #define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L |
7174 | //GDS_GWS_VMID2 |
7175 | #define GDS_GWS_VMID2__BASE__SHIFT 0x0 |
7176 | #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 |
7177 | #define GDS_GWS_VMID2__BASE_MASK 0x0000003FL |
7178 | #define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L |
7179 | //GDS_GWS_VMID3 |
7180 | #define GDS_GWS_VMID3__BASE__SHIFT 0x0 |
7181 | #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 |
7182 | #define GDS_GWS_VMID3__BASE_MASK 0x0000003FL |
7183 | #define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L |
7184 | //GDS_GWS_VMID4 |
7185 | #define GDS_GWS_VMID4__BASE__SHIFT 0x0 |
7186 | #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 |
7187 | #define GDS_GWS_VMID4__BASE_MASK 0x0000003FL |
7188 | #define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L |
7189 | //GDS_GWS_VMID5 |
7190 | #define GDS_GWS_VMID5__BASE__SHIFT 0x0 |
7191 | #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 |
7192 | #define GDS_GWS_VMID5__BASE_MASK 0x0000003FL |
7193 | #define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L |
7194 | //GDS_GWS_VMID6 |
7195 | #define GDS_GWS_VMID6__BASE__SHIFT 0x0 |
7196 | #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 |
7197 | #define GDS_GWS_VMID6__BASE_MASK 0x0000003FL |
7198 | #define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L |
7199 | //GDS_GWS_VMID7 |
7200 | #define GDS_GWS_VMID7__BASE__SHIFT 0x0 |
7201 | #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 |
7202 | #define GDS_GWS_VMID7__BASE_MASK 0x0000003FL |
7203 | #define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L |
7204 | //GDS_GWS_VMID8 |
7205 | #define GDS_GWS_VMID8__BASE__SHIFT 0x0 |
7206 | #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 |
7207 | #define GDS_GWS_VMID8__BASE_MASK 0x0000003FL |
7208 | #define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L |
7209 | //GDS_GWS_VMID9 |
7210 | #define GDS_GWS_VMID9__BASE__SHIFT 0x0 |
7211 | #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 |
7212 | #define GDS_GWS_VMID9__BASE_MASK 0x0000003FL |
7213 | #define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L |
7214 | //GDS_GWS_VMID10 |
7215 | #define GDS_GWS_VMID10__BASE__SHIFT 0x0 |
7216 | #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 |
7217 | #define GDS_GWS_VMID10__BASE_MASK 0x0000003FL |
7218 | #define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L |
7219 | //GDS_GWS_VMID11 |
7220 | #define GDS_GWS_VMID11__BASE__SHIFT 0x0 |
7221 | #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 |
7222 | #define GDS_GWS_VMID11__BASE_MASK 0x0000003FL |
7223 | #define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L |
7224 | //GDS_GWS_VMID12 |
7225 | #define GDS_GWS_VMID12__BASE__SHIFT 0x0 |
7226 | #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 |
7227 | #define GDS_GWS_VMID12__BASE_MASK 0x0000003FL |
7228 | #define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L |
7229 | //GDS_GWS_VMID13 |
7230 | #define GDS_GWS_VMID13__BASE__SHIFT 0x0 |
7231 | #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 |
7232 | #define GDS_GWS_VMID13__BASE_MASK 0x0000003FL |
7233 | #define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L |
7234 | //GDS_GWS_VMID14 |
7235 | #define GDS_GWS_VMID14__BASE__SHIFT 0x0 |
7236 | #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 |
7237 | #define GDS_GWS_VMID14__BASE_MASK 0x0000003FL |
7238 | #define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L |
7239 | //GDS_GWS_VMID15 |
7240 | #define GDS_GWS_VMID15__BASE__SHIFT 0x0 |
7241 | #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 |
7242 | #define GDS_GWS_VMID15__BASE_MASK 0x0000003FL |
7243 | #define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L |
7244 | //GDS_OA_VMID0 |
7245 | #define GDS_OA_VMID0__MASK__SHIFT 0x0 |
7246 | #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 |
7247 | #define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL |
7248 | #define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L |
7249 | //GDS_OA_VMID1 |
7250 | #define GDS_OA_VMID1__MASK__SHIFT 0x0 |
7251 | #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 |
7252 | #define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL |
7253 | #define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L |
7254 | //GDS_OA_VMID2 |
7255 | #define GDS_OA_VMID2__MASK__SHIFT 0x0 |
7256 | #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 |
7257 | #define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL |
7258 | #define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L |
7259 | //GDS_OA_VMID3 |
7260 | #define GDS_OA_VMID3__MASK__SHIFT 0x0 |
7261 | #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 |
7262 | #define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL |
7263 | #define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L |
7264 | //GDS_OA_VMID4 |
7265 | #define GDS_OA_VMID4__MASK__SHIFT 0x0 |
7266 | #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 |
7267 | #define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL |
7268 | #define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L |
7269 | //GDS_OA_VMID5 |
7270 | #define GDS_OA_VMID5__MASK__SHIFT 0x0 |
7271 | #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 |
7272 | #define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL |
7273 | #define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L |
7274 | //GDS_OA_VMID6 |
7275 | #define GDS_OA_VMID6__MASK__SHIFT 0x0 |
7276 | #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 |
7277 | #define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL |
7278 | #define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L |
7279 | //GDS_OA_VMID7 |
7280 | #define GDS_OA_VMID7__MASK__SHIFT 0x0 |
7281 | #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 |
7282 | #define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL |
7283 | #define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L |
7284 | //GDS_OA_VMID8 |
7285 | #define GDS_OA_VMID8__MASK__SHIFT 0x0 |
7286 | #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 |
7287 | #define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL |
7288 | #define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L |
7289 | //GDS_OA_VMID9 |
7290 | #define GDS_OA_VMID9__MASK__SHIFT 0x0 |
7291 | #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 |
7292 | #define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL |
7293 | #define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L |
7294 | //GDS_OA_VMID10 |
7295 | #define GDS_OA_VMID10__MASK__SHIFT 0x0 |
7296 | #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 |
7297 | #define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL |
7298 | #define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L |
7299 | //GDS_OA_VMID11 |
7300 | #define GDS_OA_VMID11__MASK__SHIFT 0x0 |
7301 | #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 |
7302 | #define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL |
7303 | #define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L |
7304 | //GDS_OA_VMID12 |
7305 | #define GDS_OA_VMID12__MASK__SHIFT 0x0 |
7306 | #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 |
7307 | #define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL |
7308 | #define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L |
7309 | //GDS_OA_VMID13 |
7310 | #define GDS_OA_VMID13__MASK__SHIFT 0x0 |
7311 | #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 |
7312 | #define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL |
7313 | #define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L |
7314 | //GDS_OA_VMID14 |
7315 | #define GDS_OA_VMID14__MASK__SHIFT 0x0 |
7316 | #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 |
7317 | #define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL |
7318 | #define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L |
7319 | //GDS_OA_VMID15 |
7320 | #define GDS_OA_VMID15__MASK__SHIFT 0x0 |
7321 | #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 |
7322 | #define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL |
7323 | #define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L |
7324 | //GDS_GWS_RESET0 |
7325 | #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 |
7326 | #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 |
7327 | #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 |
7328 | #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 |
7329 | #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 |
7330 | #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 |
7331 | #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 |
7332 | #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 |
7333 | #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 |
7334 | #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 |
7335 | #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa |
7336 | #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb |
7337 | #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc |
7338 | #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd |
7339 | #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe |
7340 | #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf |
7341 | #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 |
7342 | #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 |
7343 | #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 |
7344 | #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 |
7345 | #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 |
7346 | #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 |
7347 | #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 |
7348 | #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 |
7349 | #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 |
7350 | #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 |
7351 | #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a |
7352 | #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b |
7353 | #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c |
7354 | #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d |
7355 | #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e |
7356 | #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f |
7357 | #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L |
7358 | #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L |
7359 | #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L |
7360 | #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L |
7361 | #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L |
7362 | #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L |
7363 | #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L |
7364 | #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L |
7365 | #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L |
7366 | #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L |
7367 | #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L |
7368 | #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L |
7369 | #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L |
7370 | #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L |
7371 | #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L |
7372 | #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L |
7373 | #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L |
7374 | #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L |
7375 | #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L |
7376 | #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L |
7377 | #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L |
7378 | #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L |
7379 | #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L |
7380 | #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L |
7381 | #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L |
7382 | #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L |
7383 | #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L |
7384 | #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L |
7385 | #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L |
7386 | #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L |
7387 | #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L |
7388 | #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L |
7389 | //GDS_GWS_RESET1 |
7390 | #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 |
7391 | #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 |
7392 | #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 |
7393 | #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 |
7394 | #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 |
7395 | #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 |
7396 | #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 |
7397 | #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 |
7398 | #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 |
7399 | #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 |
7400 | #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa |
7401 | #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb |
7402 | #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc |
7403 | #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd |
7404 | #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe |
7405 | #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf |
7406 | #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 |
7407 | #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 |
7408 | #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 |
7409 | #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 |
7410 | #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 |
7411 | #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 |
7412 | #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 |
7413 | #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 |
7414 | #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 |
7415 | #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 |
7416 | #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a |
7417 | #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b |
7418 | #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c |
7419 | #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d |
7420 | #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e |
7421 | #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f |
7422 | #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L |
7423 | #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L |
7424 | #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L |
7425 | #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L |
7426 | #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L |
7427 | #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L |
7428 | #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L |
7429 | #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L |
7430 | #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L |
7431 | #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L |
7432 | #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L |
7433 | #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L |
7434 | #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L |
7435 | #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L |
7436 | #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L |
7437 | #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L |
7438 | #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L |
7439 | #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L |
7440 | #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L |
7441 | #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L |
7442 | #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L |
7443 | #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L |
7444 | #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L |
7445 | #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L |
7446 | #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L |
7447 | #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L |
7448 | #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L |
7449 | #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L |
7450 | #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L |
7451 | #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L |
7452 | #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L |
7453 | #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L |
7454 | //GDS_GWS_RESOURCE_RESET |
7455 | #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 |
7456 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 |
7457 | #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L |
7458 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L |
7459 | //GDS_COMPUTE_MAX_WAVE_ID |
7460 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7461 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7462 | //GDS_OA_RESET_MASK |
7463 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 |
7464 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 |
7465 | #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 |
7466 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 |
7467 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 |
7468 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 |
7469 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 |
7470 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 |
7471 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 |
7472 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 |
7473 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa |
7474 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb |
7475 | #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc |
7476 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L |
7477 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L |
7478 | #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L |
7479 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L |
7480 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L |
7481 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L |
7482 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L |
7483 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L |
7484 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L |
7485 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L |
7486 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L |
7487 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L |
7488 | #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L |
7489 | //GDS_OA_RESET |
7490 | #define GDS_OA_RESET__RESET__SHIFT 0x0 |
7491 | #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 |
7492 | #define GDS_OA_RESET__RESET_MASK 0x00000001L |
7493 | #define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L |
7494 | //GDS_ENHANCE |
7495 | #define GDS_ENHANCE__MISC__SHIFT 0x0 |
7496 | #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 |
7497 | #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 |
7498 | #define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 |
7499 | #define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 |
7500 | #define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 |
7501 | #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 |
7502 | #define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 |
7503 | #define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17 |
7504 | #define GDS_ENHANCE__UNUSED__SHIFT 0x18 |
7505 | #define GDS_ENHANCE__MISC_MASK 0x0000FFFFL |
7506 | #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L |
7507 | #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L |
7508 | #define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L |
7509 | #define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L |
7510 | #define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L |
7511 | #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L |
7512 | #define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L |
7513 | #define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L |
7514 | #define GDS_ENHANCE__UNUSED_MASK 0xFF000000L |
7515 | //GDS_OA_CGPG_RESTORE |
7516 | #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 |
7517 | #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 |
7518 | #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc |
7519 | #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 |
7520 | #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 |
7521 | #define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL |
7522 | #define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L |
7523 | #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L |
7524 | #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L |
7525 | #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L |
7526 | //GDS_CS_CTXSW_STATUS |
7527 | #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 |
7528 | #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 |
7529 | #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
7530 | #define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L |
7531 | #define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L |
7532 | #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
7533 | //GDS_CS_CTXSW_CNT0 |
7534 | #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7535 | #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 |
7536 | #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7537 | #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7538 | //GDS_CS_CTXSW_CNT1 |
7539 | #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7540 | #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 |
7541 | #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7542 | #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7543 | //GDS_CS_CTXSW_CNT2 |
7544 | #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7545 | #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 |
7546 | #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7547 | #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7548 | //GDS_CS_CTXSW_CNT3 |
7549 | #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7550 | #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 |
7551 | #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7552 | #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7553 | //GDS_GFX_CTXSW_STATUS |
7554 | #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 |
7555 | #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 |
7556 | #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
7557 | #define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L |
7558 | #define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L |
7559 | #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
7560 | //GDS_VS_CTXSW_CNT0 |
7561 | #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7562 | #define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 |
7563 | #define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7564 | #define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7565 | //GDS_VS_CTXSW_CNT1 |
7566 | #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7567 | #define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 |
7568 | #define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7569 | #define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7570 | //GDS_VS_CTXSW_CNT2 |
7571 | #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7572 | #define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 |
7573 | #define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7574 | #define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7575 | //GDS_VS_CTXSW_CNT3 |
7576 | #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7577 | #define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 |
7578 | #define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7579 | #define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7580 | //GDS_PS0_CTXSW_CNT0 |
7581 | #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7582 | #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 |
7583 | #define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7584 | #define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7585 | //GDS_PS0_CTXSW_CNT1 |
7586 | #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7587 | #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 |
7588 | #define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7589 | #define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7590 | //GDS_PS0_CTXSW_CNT2 |
7591 | #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7592 | #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 |
7593 | #define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7594 | #define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7595 | //GDS_PS0_CTXSW_CNT3 |
7596 | #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7597 | #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 |
7598 | #define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7599 | #define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7600 | //GDS_PS1_CTXSW_CNT0 |
7601 | #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7602 | #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 |
7603 | #define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7604 | #define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7605 | //GDS_PS1_CTXSW_CNT1 |
7606 | #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7607 | #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 |
7608 | #define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7609 | #define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7610 | //GDS_PS1_CTXSW_CNT2 |
7611 | #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7612 | #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 |
7613 | #define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7614 | #define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7615 | //GDS_PS1_CTXSW_CNT3 |
7616 | #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7617 | #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 |
7618 | #define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7619 | #define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7620 | //GDS_PS2_CTXSW_CNT0 |
7621 | #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7622 | #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 |
7623 | #define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7624 | #define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7625 | //GDS_PS2_CTXSW_CNT1 |
7626 | #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7627 | #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 |
7628 | #define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7629 | #define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7630 | //GDS_PS2_CTXSW_CNT2 |
7631 | #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7632 | #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 |
7633 | #define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7634 | #define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7635 | //GDS_PS2_CTXSW_CNT3 |
7636 | #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7637 | #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 |
7638 | #define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7639 | #define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7640 | //GDS_PS3_CTXSW_CNT0 |
7641 | #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7642 | #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 |
7643 | #define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7644 | #define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7645 | //GDS_PS3_CTXSW_CNT1 |
7646 | #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7647 | #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 |
7648 | #define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7649 | #define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7650 | //GDS_PS3_CTXSW_CNT2 |
7651 | #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7652 | #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 |
7653 | #define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7654 | #define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7655 | //GDS_PS3_CTXSW_CNT3 |
7656 | #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7657 | #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 |
7658 | #define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7659 | #define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7660 | //GDS_PS4_CTXSW_CNT0 |
7661 | #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7662 | #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 |
7663 | #define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7664 | #define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7665 | //GDS_PS4_CTXSW_CNT1 |
7666 | #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7667 | #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 |
7668 | #define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7669 | #define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7670 | //GDS_PS4_CTXSW_CNT2 |
7671 | #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7672 | #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 |
7673 | #define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7674 | #define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7675 | //GDS_PS4_CTXSW_CNT3 |
7676 | #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7677 | #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 |
7678 | #define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7679 | #define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7680 | //GDS_PS5_CTXSW_CNT0 |
7681 | #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7682 | #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 |
7683 | #define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7684 | #define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7685 | //GDS_PS5_CTXSW_CNT1 |
7686 | #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7687 | #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 |
7688 | #define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7689 | #define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7690 | //GDS_PS5_CTXSW_CNT2 |
7691 | #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7692 | #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 |
7693 | #define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7694 | #define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7695 | //GDS_PS5_CTXSW_CNT3 |
7696 | #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7697 | #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 |
7698 | #define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7699 | #define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7700 | //GDS_PS6_CTXSW_CNT0 |
7701 | #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7702 | #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 |
7703 | #define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7704 | #define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7705 | //GDS_PS6_CTXSW_CNT1 |
7706 | #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7707 | #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 |
7708 | #define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7709 | #define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7710 | //GDS_PS6_CTXSW_CNT2 |
7711 | #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7712 | #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 |
7713 | #define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7714 | #define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7715 | //GDS_PS6_CTXSW_CNT3 |
7716 | #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7717 | #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 |
7718 | #define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7719 | #define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7720 | //GDS_PS7_CTXSW_CNT0 |
7721 | #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7722 | #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 |
7723 | #define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7724 | #define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7725 | //GDS_PS7_CTXSW_CNT1 |
7726 | #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7727 | #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 |
7728 | #define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7729 | #define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7730 | //GDS_PS7_CTXSW_CNT2 |
7731 | #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7732 | #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 |
7733 | #define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7734 | #define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7735 | //GDS_PS7_CTXSW_CNT3 |
7736 | #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7737 | #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 |
7738 | #define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7739 | #define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7740 | //GDS_GS_CTXSW_CNT0 |
7741 | #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
7742 | #define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 |
7743 | #define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
7744 | #define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
7745 | //GDS_GS_CTXSW_CNT1 |
7746 | #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
7747 | #define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 |
7748 | #define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
7749 | #define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
7750 | //GDS_GS_CTXSW_CNT2 |
7751 | #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
7752 | #define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 |
7753 | #define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
7754 | #define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
7755 | //GDS_GS_CTXSW_CNT3 |
7756 | #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
7757 | #define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 |
7758 | #define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
7759 | #define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
7760 | |
7761 | |
7762 | // addressBlock: gc_gfxdec0 |
7763 | //DB_RENDER_CONTROL |
7764 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 |
7765 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 |
7766 | #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 |
7767 | #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 |
7768 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 |
7769 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 |
7770 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 |
7771 | #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 |
7772 | #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 |
7773 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc |
7774 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L |
7775 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L |
7776 | #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L |
7777 | #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L |
7778 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L |
7779 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L |
7780 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L |
7781 | #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L |
7782 | #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L |
7783 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L |
7784 | //DB_COUNT_CONTROL |
7785 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 |
7786 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 |
7787 | #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 |
7788 | #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 |
7789 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc |
7790 | #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 |
7791 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 |
7792 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 |
7793 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c |
7794 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L |
7795 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L |
7796 | #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L |
7797 | #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L |
7798 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L |
7799 | #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L |
7800 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L |
7801 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L |
7802 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L |
7803 | //DB_DEPTH_VIEW |
7804 | #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 |
7805 | #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd |
7806 | #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 |
7807 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 |
7808 | #define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a |
7809 | #define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL |
7810 | #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L |
7811 | #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L |
7812 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L |
7813 | #define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L |
7814 | //DB_RENDER_OVERRIDE |
7815 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 |
7816 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 |
7817 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 |
7818 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 |
7819 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 |
7820 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 |
7821 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 |
7822 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa |
7823 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb |
7824 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc |
7825 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd |
7826 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf |
7827 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 |
7828 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 |
7829 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 |
7830 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 |
7831 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 |
7832 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a |
7833 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b |
7834 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c |
7835 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d |
7836 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e |
7837 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f |
7838 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L |
7839 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL |
7840 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L |
7841 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L |
7842 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L |
7843 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L |
7844 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L |
7845 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L |
7846 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L |
7847 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L |
7848 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L |
7849 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L |
7850 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L |
7851 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L |
7852 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L |
7853 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L |
7854 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L |
7855 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L |
7856 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L |
7857 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L |
7858 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L |
7859 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L |
7860 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L |
7861 | //DB_RENDER_OVERRIDE2 |
7862 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 |
7863 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 |
7864 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 |
7865 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 |
7866 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 |
7867 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 |
7868 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 |
7869 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa |
7870 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb |
7871 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc |
7872 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf |
7873 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 |
7874 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 |
7875 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 |
7876 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 |
7877 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 |
7878 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L |
7879 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL |
7880 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L |
7881 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L |
7882 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L |
7883 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L |
7884 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L |
7885 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L |
7886 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L |
7887 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L |
7888 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L |
7889 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L |
7890 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L |
7891 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L |
7892 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L |
7893 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L |
7894 | //DB_HTILE_DATA_BASE |
7895 | #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 |
7896 | #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL |
7897 | //DB_HTILE_DATA_BASE_HI |
7898 | #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 |
7899 | #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL |
7900 | //DB_DEPTH_SIZE |
7901 | #define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 |
7902 | #define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 |
7903 | #define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL |
7904 | #define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L |
7905 | //DB_DEPTH_BOUNDS_MIN |
7906 | #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 |
7907 | #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL |
7908 | //DB_DEPTH_BOUNDS_MAX |
7909 | #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 |
7910 | #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL |
7911 | //DB_STENCIL_CLEAR |
7912 | #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 |
7913 | #define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL |
7914 | //DB_DEPTH_CLEAR |
7915 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 |
7916 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL |
7917 | //PA_SC_SCREEN_SCISSOR_TL |
7918 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 |
7919 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 |
7920 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL |
7921 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L |
7922 | //PA_SC_SCREEN_SCISSOR_BR |
7923 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 |
7924 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 |
7925 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL |
7926 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L |
7927 | //DB_Z_INFO |
7928 | #define DB_Z_INFO__FORMAT__SHIFT 0x0 |
7929 | #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 |
7930 | #define DB_Z_INFO__SW_MODE__SHIFT 0x4 |
7931 | #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
7932 | #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd |
7933 | #define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf |
7934 | #define DB_Z_INFO__MAXMIP__SHIFT 0x10 |
7935 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 |
7936 | #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
7937 | #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c |
7938 | #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d |
7939 | #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e |
7940 | #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f |
7941 | #define DB_Z_INFO__FORMAT_MASK 0x00000003L |
7942 | #define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL |
7943 | #define DB_Z_INFO__SW_MODE_MASK 0x000001F0L |
7944 | #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
7945 | #define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L |
7946 | #define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L |
7947 | #define DB_Z_INFO__MAXMIP_MASK 0x000F0000L |
7948 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L |
7949 | #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
7950 | #define DB_Z_INFO__READ_SIZE_MASK 0x10000000L |
7951 | #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L |
7952 | #define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L |
7953 | #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L |
7954 | //DB_STENCIL_INFO |
7955 | #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 |
7956 | #define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 |
7957 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
7958 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd |
7959 | #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf |
7960 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
7961 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d |
7962 | #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e |
7963 | #define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L |
7964 | #define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L |
7965 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
7966 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L |
7967 | #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L |
7968 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
7969 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L |
7970 | #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L |
7971 | //DB_Z_READ_BASE |
7972 | #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 |
7973 | #define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
7974 | //DB_Z_READ_BASE_HI |
7975 | #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
7976 | #define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
7977 | //DB_STENCIL_READ_BASE |
7978 | #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 |
7979 | #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
7980 | //DB_STENCIL_READ_BASE_HI |
7981 | #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
7982 | #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
7983 | //DB_Z_WRITE_BASE |
7984 | #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 |
7985 | #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
7986 | //DB_Z_WRITE_BASE_HI |
7987 | #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
7988 | #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
7989 | //DB_STENCIL_WRITE_BASE |
7990 | #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 |
7991 | #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
7992 | //DB_STENCIL_WRITE_BASE_HI |
7993 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
7994 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
7995 | //DB_DFSM_CONTROL |
7996 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 |
7997 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 |
7998 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 |
7999 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L |
8000 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L |
8001 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L |
8002 | //DB_Z_INFO2 |
8003 | #define DB_Z_INFO2__EPITCH__SHIFT 0x0 |
8004 | #define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL |
8005 | //DB_STENCIL_INFO2 |
8006 | #define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 |
8007 | #define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL |
8008 | //COHER_DEST_BASE_HI_0 |
8009 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 |
8010 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL |
8011 | //COHER_DEST_BASE_HI_1 |
8012 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 |
8013 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL |
8014 | //COHER_DEST_BASE_HI_2 |
8015 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 |
8016 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL |
8017 | //COHER_DEST_BASE_HI_3 |
8018 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 |
8019 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL |
8020 | //COHER_DEST_BASE_2 |
8021 | #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 |
8022 | #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL |
8023 | //COHER_DEST_BASE_3 |
8024 | #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 |
8025 | #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL |
8026 | //PA_SC_WINDOW_OFFSET |
8027 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 |
8028 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 |
8029 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL |
8030 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L |
8031 | //PA_SC_WINDOW_SCISSOR_TL |
8032 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 |
8033 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 |
8034 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8035 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
8036 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
8037 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8038 | //PA_SC_WINDOW_SCISSOR_BR |
8039 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 |
8040 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 |
8041 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
8042 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
8043 | //PA_SC_CLIPRECT_RULE |
8044 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 |
8045 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL |
8046 | //PA_SC_CLIPRECT_0_TL |
8047 | #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 |
8048 | #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 |
8049 | #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL |
8050 | #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L |
8051 | //PA_SC_CLIPRECT_0_BR |
8052 | #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 |
8053 | #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 |
8054 | #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL |
8055 | #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L |
8056 | //PA_SC_CLIPRECT_1_TL |
8057 | #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 |
8058 | #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 |
8059 | #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL |
8060 | #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L |
8061 | //PA_SC_CLIPRECT_1_BR |
8062 | #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 |
8063 | #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 |
8064 | #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL |
8065 | #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L |
8066 | //PA_SC_CLIPRECT_2_TL |
8067 | #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 |
8068 | #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 |
8069 | #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL |
8070 | #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L |
8071 | //PA_SC_CLIPRECT_2_BR |
8072 | #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 |
8073 | #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 |
8074 | #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL |
8075 | #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L |
8076 | //PA_SC_CLIPRECT_3_TL |
8077 | #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 |
8078 | #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 |
8079 | #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL |
8080 | #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L |
8081 | //PA_SC_CLIPRECT_3_BR |
8082 | #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 |
8083 | #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 |
8084 | #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL |
8085 | #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L |
8086 | //PA_SC_EDGERULE |
8087 | #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 |
8088 | #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 |
8089 | #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 |
8090 | #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc |
8091 | #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 |
8092 | #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 |
8093 | #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c |
8094 | #define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL |
8095 | #define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L |
8096 | #define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L |
8097 | #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L |
8098 | #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L |
8099 | #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L |
8100 | #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L |
8101 | //PA_SU_HARDWARE_SCREEN_OFFSET |
8102 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 |
8103 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 |
8104 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL |
8105 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L |
8106 | //CB_TARGET_MASK |
8107 | #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 |
8108 | #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 |
8109 | #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 |
8110 | #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc |
8111 | #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 |
8112 | #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 |
8113 | #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 |
8114 | #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c |
8115 | #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL |
8116 | #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L |
8117 | #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L |
8118 | #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L |
8119 | #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L |
8120 | #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L |
8121 | #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L |
8122 | #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L |
8123 | //CB_SHADER_MASK |
8124 | #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 |
8125 | #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 |
8126 | #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 |
8127 | #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc |
8128 | #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 |
8129 | #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 |
8130 | #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 |
8131 | #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c |
8132 | #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL |
8133 | #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L |
8134 | #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L |
8135 | #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L |
8136 | #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L |
8137 | #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L |
8138 | #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L |
8139 | #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L |
8140 | //PA_SC_GENERIC_SCISSOR_TL |
8141 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 |
8142 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 |
8143 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8144 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
8145 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
8146 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8147 | //PA_SC_GENERIC_SCISSOR_BR |
8148 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 |
8149 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 |
8150 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
8151 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
8152 | //COHER_DEST_BASE_0 |
8153 | #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 |
8154 | #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL |
8155 | //COHER_DEST_BASE_1 |
8156 | #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 |
8157 | #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL |
8158 | //PA_SC_VPORT_SCISSOR_0_TL |
8159 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 |
8160 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 |
8161 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8162 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL |
8163 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L |
8164 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8165 | //PA_SC_VPORT_SCISSOR_0_BR |
8166 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 |
8167 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 |
8168 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL |
8169 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L |
8170 | //PA_SC_VPORT_SCISSOR_1_TL |
8171 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 |
8172 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 |
8173 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8174 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL |
8175 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L |
8176 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8177 | //PA_SC_VPORT_SCISSOR_1_BR |
8178 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 |
8179 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 |
8180 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL |
8181 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L |
8182 | //PA_SC_VPORT_SCISSOR_2_TL |
8183 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 |
8184 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 |
8185 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8186 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL |
8187 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L |
8188 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8189 | //PA_SC_VPORT_SCISSOR_2_BR |
8190 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 |
8191 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 |
8192 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL |
8193 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L |
8194 | //PA_SC_VPORT_SCISSOR_3_TL |
8195 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 |
8196 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 |
8197 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8198 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL |
8199 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L |
8200 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8201 | //PA_SC_VPORT_SCISSOR_3_BR |
8202 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 |
8203 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 |
8204 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL |
8205 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L |
8206 | //PA_SC_VPORT_SCISSOR_4_TL |
8207 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 |
8208 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 |
8209 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8210 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL |
8211 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L |
8212 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8213 | //PA_SC_VPORT_SCISSOR_4_BR |
8214 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 |
8215 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 |
8216 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL |
8217 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L |
8218 | //PA_SC_VPORT_SCISSOR_5_TL |
8219 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 |
8220 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 |
8221 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8222 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL |
8223 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L |
8224 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8225 | //PA_SC_VPORT_SCISSOR_5_BR |
8226 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 |
8227 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 |
8228 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL |
8229 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L |
8230 | //PA_SC_VPORT_SCISSOR_6_TL |
8231 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 |
8232 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 |
8233 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8234 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL |
8235 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L |
8236 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8237 | //PA_SC_VPORT_SCISSOR_6_BR |
8238 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 |
8239 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 |
8240 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL |
8241 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L |
8242 | //PA_SC_VPORT_SCISSOR_7_TL |
8243 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 |
8244 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 |
8245 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8246 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL |
8247 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L |
8248 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8249 | //PA_SC_VPORT_SCISSOR_7_BR |
8250 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 |
8251 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 |
8252 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL |
8253 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L |
8254 | //PA_SC_VPORT_SCISSOR_8_TL |
8255 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 |
8256 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 |
8257 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8258 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL |
8259 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L |
8260 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8261 | //PA_SC_VPORT_SCISSOR_8_BR |
8262 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 |
8263 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 |
8264 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL |
8265 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L |
8266 | //PA_SC_VPORT_SCISSOR_9_TL |
8267 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 |
8268 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 |
8269 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8270 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL |
8271 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L |
8272 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8273 | //PA_SC_VPORT_SCISSOR_9_BR |
8274 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 |
8275 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 |
8276 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL |
8277 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L |
8278 | //PA_SC_VPORT_SCISSOR_10_TL |
8279 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 |
8280 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 |
8281 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8282 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL |
8283 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L |
8284 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8285 | //PA_SC_VPORT_SCISSOR_10_BR |
8286 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 |
8287 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 |
8288 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL |
8289 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L |
8290 | //PA_SC_VPORT_SCISSOR_11_TL |
8291 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 |
8292 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 |
8293 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8294 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL |
8295 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L |
8296 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8297 | //PA_SC_VPORT_SCISSOR_11_BR |
8298 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 |
8299 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 |
8300 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL |
8301 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L |
8302 | //PA_SC_VPORT_SCISSOR_12_TL |
8303 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 |
8304 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 |
8305 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8306 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL |
8307 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L |
8308 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8309 | //PA_SC_VPORT_SCISSOR_12_BR |
8310 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 |
8311 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 |
8312 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL |
8313 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L |
8314 | //PA_SC_VPORT_SCISSOR_13_TL |
8315 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 |
8316 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 |
8317 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8318 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL |
8319 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L |
8320 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8321 | //PA_SC_VPORT_SCISSOR_13_BR |
8322 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 |
8323 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 |
8324 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL |
8325 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L |
8326 | //PA_SC_VPORT_SCISSOR_14_TL |
8327 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 |
8328 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 |
8329 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8330 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL |
8331 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L |
8332 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8333 | //PA_SC_VPORT_SCISSOR_14_BR |
8334 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 |
8335 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 |
8336 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL |
8337 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L |
8338 | //PA_SC_VPORT_SCISSOR_15_TL |
8339 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 |
8340 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 |
8341 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
8342 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL |
8343 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L |
8344 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
8345 | //PA_SC_VPORT_SCISSOR_15_BR |
8346 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 |
8347 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 |
8348 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL |
8349 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L |
8350 | //PA_SC_VPORT_ZMIN_0 |
8351 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 |
8352 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8353 | //PA_SC_VPORT_ZMAX_0 |
8354 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 |
8355 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8356 | //PA_SC_VPORT_ZMIN_1 |
8357 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 |
8358 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8359 | //PA_SC_VPORT_ZMAX_1 |
8360 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 |
8361 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8362 | //PA_SC_VPORT_ZMIN_2 |
8363 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 |
8364 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8365 | //PA_SC_VPORT_ZMAX_2 |
8366 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 |
8367 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8368 | //PA_SC_VPORT_ZMIN_3 |
8369 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 |
8370 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8371 | //PA_SC_VPORT_ZMAX_3 |
8372 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 |
8373 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8374 | //PA_SC_VPORT_ZMIN_4 |
8375 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 |
8376 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8377 | //PA_SC_VPORT_ZMAX_4 |
8378 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 |
8379 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8380 | //PA_SC_VPORT_ZMIN_5 |
8381 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 |
8382 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8383 | //PA_SC_VPORT_ZMAX_5 |
8384 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 |
8385 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8386 | //PA_SC_VPORT_ZMIN_6 |
8387 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 |
8388 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8389 | //PA_SC_VPORT_ZMAX_6 |
8390 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 |
8391 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8392 | //PA_SC_VPORT_ZMIN_7 |
8393 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 |
8394 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8395 | //PA_SC_VPORT_ZMAX_7 |
8396 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 |
8397 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8398 | //PA_SC_VPORT_ZMIN_8 |
8399 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 |
8400 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8401 | //PA_SC_VPORT_ZMAX_8 |
8402 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 |
8403 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8404 | //PA_SC_VPORT_ZMIN_9 |
8405 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 |
8406 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8407 | //PA_SC_VPORT_ZMAX_9 |
8408 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 |
8409 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8410 | //PA_SC_VPORT_ZMIN_10 |
8411 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 |
8412 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8413 | //PA_SC_VPORT_ZMAX_10 |
8414 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 |
8415 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8416 | //PA_SC_VPORT_ZMIN_11 |
8417 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 |
8418 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8419 | //PA_SC_VPORT_ZMAX_11 |
8420 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 |
8421 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8422 | //PA_SC_VPORT_ZMIN_12 |
8423 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 |
8424 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8425 | //PA_SC_VPORT_ZMAX_12 |
8426 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 |
8427 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8428 | //PA_SC_VPORT_ZMIN_13 |
8429 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 |
8430 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8431 | //PA_SC_VPORT_ZMAX_13 |
8432 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 |
8433 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8434 | //PA_SC_VPORT_ZMIN_14 |
8435 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 |
8436 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8437 | //PA_SC_VPORT_ZMAX_14 |
8438 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 |
8439 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8440 | //PA_SC_VPORT_ZMIN_15 |
8441 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 |
8442 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL |
8443 | //PA_SC_VPORT_ZMAX_15 |
8444 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 |
8445 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL |
8446 | //PA_SC_RASTER_CONFIG |
8447 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 |
8448 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 |
8449 | #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 |
8450 | #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 |
8451 | #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 |
8452 | #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 |
8453 | #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa |
8454 | #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc |
8455 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe |
8456 | #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 |
8457 | #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 |
8458 | #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 |
8459 | #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 |
8460 | #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a |
8461 | #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d |
8462 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L |
8463 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL |
8464 | #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L |
8465 | #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L |
8466 | #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L |
8467 | #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L |
8468 | #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L |
8469 | #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L |
8470 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L |
8471 | #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L |
8472 | #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L |
8473 | #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L |
8474 | #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L |
8475 | #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L |
8476 | #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L |
8477 | //PA_SC_RASTER_CONFIG_1 |
8478 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 |
8479 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 |
8480 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 |
8481 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L |
8482 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL |
8483 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L |
8484 | //PA_SC_SCREEN_EXTENT_CONTROL |
8485 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 |
8486 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 |
8487 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L |
8488 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL |
8489 | //PA_SC_TILE_STEERING_OVERRIDE |
8490 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 |
8491 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 |
8492 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 |
8493 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L |
8494 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L |
8495 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L |
8496 | //CP_PERFMON_CNTX_CNTL |
8497 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f |
8498 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L |
8499 | //CP_PIPEID |
8500 | #define CP_PIPEID__PIPE_ID__SHIFT 0x0 |
8501 | #define CP_PIPEID__PIPE_ID_MASK 0x00000003L |
8502 | //CP_RINGID |
8503 | #define CP_RINGID__RINGID__SHIFT 0x0 |
8504 | #define CP_RINGID__RINGID_MASK 0x00000003L |
8505 | //CP_VMID |
8506 | #define CP_VMID__VMID__SHIFT 0x0 |
8507 | #define CP_VMID__VMID_MASK 0x0000000FL |
8508 | //PA_SC_RIGHT_VERT_GRID |
8509 | #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 |
8510 | #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 |
8511 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 |
8512 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 |
8513 | #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL |
8514 | #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L |
8515 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L |
8516 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L |
8517 | //PA_SC_LEFT_VERT_GRID |
8518 | #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 |
8519 | #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 |
8520 | #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 |
8521 | #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 |
8522 | #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL |
8523 | #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L |
8524 | #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L |
8525 | #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L |
8526 | //PA_SC_HORIZ_GRID |
8527 | #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 |
8528 | #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 |
8529 | #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 |
8530 | #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 |
8531 | #define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL |
8532 | #define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L |
8533 | #define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L |
8534 | #define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L |
8535 | //VGT_MULTI_PRIM_IB_RESET_INDX |
8536 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 |
8537 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL |
8538 | //CB_BLEND_RED |
8539 | #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 |
8540 | #define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL |
8541 | //CB_BLEND_GREEN |
8542 | #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 |
8543 | #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL |
8544 | //CB_BLEND_BLUE |
8545 | #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 |
8546 | #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL |
8547 | //CB_BLEND_ALPHA |
8548 | #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 |
8549 | #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL |
8550 | //CB_DCC_CONTROL |
8551 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
8552 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 |
8553 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 |
8554 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 |
8555 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 |
8556 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa |
8557 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc |
8558 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd |
8559 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe |
8560 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
8561 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L |
8562 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL |
8563 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L |
8564 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L |
8565 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L |
8566 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L |
8567 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L |
8568 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L |
8569 | //DB_STENCIL_CONTROL |
8570 | #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 |
8571 | #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 |
8572 | #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 |
8573 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc |
8574 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 |
8575 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 |
8576 | #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL |
8577 | #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L |
8578 | #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L |
8579 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L |
8580 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L |
8581 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L |
8582 | //DB_STENCILREFMASK |
8583 | #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 |
8584 | #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 |
8585 | #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 |
8586 | #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 |
8587 | #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL |
8588 | #define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L |
8589 | #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L |
8590 | #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L |
8591 | //DB_STENCILREFMASK_BF |
8592 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 |
8593 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 |
8594 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 |
8595 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 |
8596 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL |
8597 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L |
8598 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L |
8599 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L |
8600 | //PA_CL_VPORT_XSCALE |
8601 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 |
8602 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8603 | //PA_CL_VPORT_XOFFSET |
8604 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 |
8605 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8606 | //PA_CL_VPORT_YSCALE |
8607 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 |
8608 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8609 | //PA_CL_VPORT_YOFFSET |
8610 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 |
8611 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8612 | //PA_CL_VPORT_ZSCALE |
8613 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 |
8614 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8615 | //PA_CL_VPORT_ZOFFSET |
8616 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 |
8617 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8618 | //PA_CL_VPORT_XSCALE_1 |
8619 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 |
8620 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8621 | //PA_CL_VPORT_XOFFSET_1 |
8622 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 |
8623 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8624 | //PA_CL_VPORT_YSCALE_1 |
8625 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 |
8626 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8627 | //PA_CL_VPORT_YOFFSET_1 |
8628 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 |
8629 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8630 | //PA_CL_VPORT_ZSCALE_1 |
8631 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 |
8632 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8633 | //PA_CL_VPORT_ZOFFSET_1 |
8634 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 |
8635 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8636 | //PA_CL_VPORT_XSCALE_2 |
8637 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 |
8638 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8639 | //PA_CL_VPORT_XOFFSET_2 |
8640 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 |
8641 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8642 | //PA_CL_VPORT_YSCALE_2 |
8643 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 |
8644 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8645 | //PA_CL_VPORT_YOFFSET_2 |
8646 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 |
8647 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8648 | //PA_CL_VPORT_ZSCALE_2 |
8649 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 |
8650 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8651 | //PA_CL_VPORT_ZOFFSET_2 |
8652 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 |
8653 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8654 | //PA_CL_VPORT_XSCALE_3 |
8655 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 |
8656 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8657 | //PA_CL_VPORT_XOFFSET_3 |
8658 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 |
8659 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8660 | //PA_CL_VPORT_YSCALE_3 |
8661 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 |
8662 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8663 | //PA_CL_VPORT_YOFFSET_3 |
8664 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 |
8665 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8666 | //PA_CL_VPORT_ZSCALE_3 |
8667 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 |
8668 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8669 | //PA_CL_VPORT_ZOFFSET_3 |
8670 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 |
8671 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8672 | //PA_CL_VPORT_XSCALE_4 |
8673 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 |
8674 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8675 | //PA_CL_VPORT_XOFFSET_4 |
8676 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 |
8677 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8678 | //PA_CL_VPORT_YSCALE_4 |
8679 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 |
8680 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8681 | //PA_CL_VPORT_YOFFSET_4 |
8682 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 |
8683 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8684 | //PA_CL_VPORT_ZSCALE_4 |
8685 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 |
8686 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8687 | //PA_CL_VPORT_ZOFFSET_4 |
8688 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 |
8689 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8690 | //PA_CL_VPORT_XSCALE_5 |
8691 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 |
8692 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8693 | //PA_CL_VPORT_XOFFSET_5 |
8694 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 |
8695 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8696 | //PA_CL_VPORT_YSCALE_5 |
8697 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 |
8698 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8699 | //PA_CL_VPORT_YOFFSET_5 |
8700 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 |
8701 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8702 | //PA_CL_VPORT_ZSCALE_5 |
8703 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 |
8704 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8705 | //PA_CL_VPORT_ZOFFSET_5 |
8706 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 |
8707 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8708 | //PA_CL_VPORT_XSCALE_6 |
8709 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 |
8710 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8711 | //PA_CL_VPORT_XOFFSET_6 |
8712 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 |
8713 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8714 | //PA_CL_VPORT_YSCALE_6 |
8715 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 |
8716 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8717 | //PA_CL_VPORT_YOFFSET_6 |
8718 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 |
8719 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8720 | //PA_CL_VPORT_ZSCALE_6 |
8721 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 |
8722 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8723 | //PA_CL_VPORT_ZOFFSET_6 |
8724 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 |
8725 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8726 | //PA_CL_VPORT_XSCALE_7 |
8727 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 |
8728 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8729 | //PA_CL_VPORT_XOFFSET_7 |
8730 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 |
8731 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8732 | //PA_CL_VPORT_YSCALE_7 |
8733 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 |
8734 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8735 | //PA_CL_VPORT_YOFFSET_7 |
8736 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 |
8737 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8738 | //PA_CL_VPORT_ZSCALE_7 |
8739 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 |
8740 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8741 | //PA_CL_VPORT_ZOFFSET_7 |
8742 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 |
8743 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8744 | //PA_CL_VPORT_XSCALE_8 |
8745 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 |
8746 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8747 | //PA_CL_VPORT_XOFFSET_8 |
8748 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 |
8749 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8750 | //PA_CL_VPORT_YSCALE_8 |
8751 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 |
8752 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8753 | //PA_CL_VPORT_YOFFSET_8 |
8754 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 |
8755 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8756 | //PA_CL_VPORT_ZSCALE_8 |
8757 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 |
8758 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8759 | //PA_CL_VPORT_ZOFFSET_8 |
8760 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 |
8761 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8762 | //PA_CL_VPORT_XSCALE_9 |
8763 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 |
8764 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8765 | //PA_CL_VPORT_XOFFSET_9 |
8766 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 |
8767 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8768 | //PA_CL_VPORT_YSCALE_9 |
8769 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 |
8770 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8771 | //PA_CL_VPORT_YOFFSET_9 |
8772 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 |
8773 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8774 | //PA_CL_VPORT_ZSCALE_9 |
8775 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 |
8776 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8777 | //PA_CL_VPORT_ZOFFSET_9 |
8778 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 |
8779 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8780 | //PA_CL_VPORT_XSCALE_10 |
8781 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 |
8782 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8783 | //PA_CL_VPORT_XOFFSET_10 |
8784 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 |
8785 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8786 | //PA_CL_VPORT_YSCALE_10 |
8787 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 |
8788 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8789 | //PA_CL_VPORT_YOFFSET_10 |
8790 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 |
8791 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8792 | //PA_CL_VPORT_ZSCALE_10 |
8793 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 |
8794 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8795 | //PA_CL_VPORT_ZOFFSET_10 |
8796 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 |
8797 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8798 | //PA_CL_VPORT_XSCALE_11 |
8799 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 |
8800 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8801 | //PA_CL_VPORT_XOFFSET_11 |
8802 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 |
8803 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8804 | //PA_CL_VPORT_YSCALE_11 |
8805 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 |
8806 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8807 | //PA_CL_VPORT_YOFFSET_11 |
8808 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 |
8809 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8810 | //PA_CL_VPORT_ZSCALE_11 |
8811 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 |
8812 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8813 | //PA_CL_VPORT_ZOFFSET_11 |
8814 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 |
8815 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8816 | //PA_CL_VPORT_XSCALE_12 |
8817 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 |
8818 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8819 | //PA_CL_VPORT_XOFFSET_12 |
8820 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 |
8821 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8822 | //PA_CL_VPORT_YSCALE_12 |
8823 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 |
8824 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8825 | //PA_CL_VPORT_YOFFSET_12 |
8826 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 |
8827 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8828 | //PA_CL_VPORT_ZSCALE_12 |
8829 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 |
8830 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8831 | //PA_CL_VPORT_ZOFFSET_12 |
8832 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 |
8833 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8834 | //PA_CL_VPORT_XSCALE_13 |
8835 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 |
8836 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8837 | //PA_CL_VPORT_XOFFSET_13 |
8838 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 |
8839 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8840 | //PA_CL_VPORT_YSCALE_13 |
8841 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 |
8842 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8843 | //PA_CL_VPORT_YOFFSET_13 |
8844 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 |
8845 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8846 | //PA_CL_VPORT_ZSCALE_13 |
8847 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 |
8848 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8849 | //PA_CL_VPORT_ZOFFSET_13 |
8850 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 |
8851 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8852 | //PA_CL_VPORT_XSCALE_14 |
8853 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 |
8854 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8855 | //PA_CL_VPORT_XOFFSET_14 |
8856 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 |
8857 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8858 | //PA_CL_VPORT_YSCALE_14 |
8859 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 |
8860 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8861 | //PA_CL_VPORT_YOFFSET_14 |
8862 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 |
8863 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8864 | //PA_CL_VPORT_ZSCALE_14 |
8865 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 |
8866 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8867 | //PA_CL_VPORT_ZOFFSET_14 |
8868 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 |
8869 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8870 | //PA_CL_VPORT_XSCALE_15 |
8871 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 |
8872 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL |
8873 | //PA_CL_VPORT_XOFFSET_15 |
8874 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 |
8875 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
8876 | //PA_CL_VPORT_YSCALE_15 |
8877 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 |
8878 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL |
8879 | //PA_CL_VPORT_YOFFSET_15 |
8880 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 |
8881 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
8882 | //PA_CL_VPORT_ZSCALE_15 |
8883 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 |
8884 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
8885 | //PA_CL_VPORT_ZOFFSET_15 |
8886 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 |
8887 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
8888 | //PA_CL_UCP_0_X |
8889 | #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 |
8890 | #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8891 | //PA_CL_UCP_0_Y |
8892 | #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 |
8893 | #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8894 | //PA_CL_UCP_0_Z |
8895 | #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 |
8896 | #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8897 | //PA_CL_UCP_0_W |
8898 | #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 |
8899 | #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8900 | //PA_CL_UCP_1_X |
8901 | #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 |
8902 | #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8903 | //PA_CL_UCP_1_Y |
8904 | #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 |
8905 | #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8906 | //PA_CL_UCP_1_Z |
8907 | #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 |
8908 | #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8909 | //PA_CL_UCP_1_W |
8910 | #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 |
8911 | #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8912 | //PA_CL_UCP_2_X |
8913 | #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 |
8914 | #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8915 | //PA_CL_UCP_2_Y |
8916 | #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 |
8917 | #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8918 | //PA_CL_UCP_2_Z |
8919 | #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 |
8920 | #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8921 | //PA_CL_UCP_2_W |
8922 | #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 |
8923 | #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8924 | //PA_CL_UCP_3_X |
8925 | #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 |
8926 | #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8927 | //PA_CL_UCP_3_Y |
8928 | #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 |
8929 | #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8930 | //PA_CL_UCP_3_Z |
8931 | #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 |
8932 | #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8933 | //PA_CL_UCP_3_W |
8934 | #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 |
8935 | #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8936 | //PA_CL_UCP_4_X |
8937 | #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 |
8938 | #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8939 | //PA_CL_UCP_4_Y |
8940 | #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 |
8941 | #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8942 | //PA_CL_UCP_4_Z |
8943 | #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 |
8944 | #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8945 | //PA_CL_UCP_4_W |
8946 | #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 |
8947 | #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8948 | //PA_CL_UCP_5_X |
8949 | #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 |
8950 | #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
8951 | //PA_CL_UCP_5_Y |
8952 | #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 |
8953 | #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
8954 | //PA_CL_UCP_5_Z |
8955 | #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 |
8956 | #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8957 | //PA_CL_UCP_5_W |
8958 | #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 |
8959 | #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
8960 | //PA_CL_PROG_NEAR_CLIP_Z |
8961 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 |
8962 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
8963 | //SPI_PS_INPUT_CNTL_0 |
8964 | #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 |
8965 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 |
8966 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa |
8967 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd |
8968 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 |
8969 | #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 |
8970 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 |
8971 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 |
8972 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
8973 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
8974 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 |
8975 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 |
8976 | #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL |
8977 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L |
8978 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L |
8979 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L |
8980 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L |
8981 | #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L |
8982 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L |
8983 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L |
8984 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
8985 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
8986 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L |
8987 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L |
8988 | //SPI_PS_INPUT_CNTL_1 |
8989 | #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 |
8990 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 |
8991 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa |
8992 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd |
8993 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 |
8994 | #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 |
8995 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 |
8996 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 |
8997 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
8998 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
8999 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 |
9000 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 |
9001 | #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL |
9002 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L |
9003 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L |
9004 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L |
9005 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L |
9006 | #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L |
9007 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L |
9008 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9009 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9010 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9011 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L |
9012 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L |
9013 | //SPI_PS_INPUT_CNTL_2 |
9014 | #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 |
9015 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 |
9016 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa |
9017 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd |
9018 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 |
9019 | #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 |
9020 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 |
9021 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9022 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9023 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9024 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 |
9025 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 |
9026 | #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL |
9027 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L |
9028 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L |
9029 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L |
9030 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L |
9031 | #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L |
9032 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L |
9033 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9034 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9035 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9036 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L |
9037 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L |
9038 | //SPI_PS_INPUT_CNTL_3 |
9039 | #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 |
9040 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 |
9041 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa |
9042 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd |
9043 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 |
9044 | #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 |
9045 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 |
9046 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9047 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9048 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9049 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 |
9050 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 |
9051 | #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL |
9052 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L |
9053 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L |
9054 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L |
9055 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L |
9056 | #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L |
9057 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L |
9058 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9059 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9060 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9061 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L |
9062 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L |
9063 | //SPI_PS_INPUT_CNTL_4 |
9064 | #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 |
9065 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 |
9066 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa |
9067 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd |
9068 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 |
9069 | #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 |
9070 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 |
9071 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9072 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9073 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9074 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 |
9075 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 |
9076 | #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL |
9077 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L |
9078 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L |
9079 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L |
9080 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L |
9081 | #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L |
9082 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L |
9083 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9084 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9085 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9086 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L |
9087 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L |
9088 | //SPI_PS_INPUT_CNTL_5 |
9089 | #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 |
9090 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 |
9091 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa |
9092 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd |
9093 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 |
9094 | #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 |
9095 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 |
9096 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9097 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9098 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9099 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 |
9100 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 |
9101 | #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL |
9102 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L |
9103 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L |
9104 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L |
9105 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L |
9106 | #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L |
9107 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L |
9108 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9109 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9110 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9111 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L |
9112 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L |
9113 | //SPI_PS_INPUT_CNTL_6 |
9114 | #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 |
9115 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 |
9116 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa |
9117 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd |
9118 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 |
9119 | #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 |
9120 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 |
9121 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9122 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9123 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9124 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 |
9125 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 |
9126 | #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL |
9127 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L |
9128 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L |
9129 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L |
9130 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L |
9131 | #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L |
9132 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L |
9133 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9134 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9135 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9136 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L |
9137 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L |
9138 | //SPI_PS_INPUT_CNTL_7 |
9139 | #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 |
9140 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 |
9141 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa |
9142 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd |
9143 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 |
9144 | #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 |
9145 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 |
9146 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9147 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9148 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9149 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 |
9150 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 |
9151 | #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL |
9152 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L |
9153 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L |
9154 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L |
9155 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L |
9156 | #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L |
9157 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L |
9158 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9159 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9160 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9161 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L |
9162 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L |
9163 | //SPI_PS_INPUT_CNTL_8 |
9164 | #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 |
9165 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 |
9166 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa |
9167 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd |
9168 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 |
9169 | #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 |
9170 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 |
9171 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9172 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9173 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9174 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 |
9175 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 |
9176 | #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL |
9177 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L |
9178 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L |
9179 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L |
9180 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L |
9181 | #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L |
9182 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L |
9183 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9184 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9185 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9186 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L |
9187 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L |
9188 | //SPI_PS_INPUT_CNTL_9 |
9189 | #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 |
9190 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 |
9191 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa |
9192 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd |
9193 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 |
9194 | #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 |
9195 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 |
9196 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9197 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9198 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9199 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 |
9200 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 |
9201 | #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL |
9202 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L |
9203 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L |
9204 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L |
9205 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L |
9206 | #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L |
9207 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L |
9208 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9209 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9210 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9211 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L |
9212 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L |
9213 | //SPI_PS_INPUT_CNTL_10 |
9214 | #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 |
9215 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 |
9216 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa |
9217 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd |
9218 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 |
9219 | #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 |
9220 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 |
9221 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9222 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9223 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9224 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 |
9225 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 |
9226 | #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL |
9227 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L |
9228 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L |
9229 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L |
9230 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L |
9231 | #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L |
9232 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L |
9233 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9234 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9235 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9236 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L |
9237 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L |
9238 | //SPI_PS_INPUT_CNTL_11 |
9239 | #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 |
9240 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 |
9241 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa |
9242 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd |
9243 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 |
9244 | #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 |
9245 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 |
9246 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9247 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9248 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9249 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 |
9250 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 |
9251 | #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL |
9252 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L |
9253 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L |
9254 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L |
9255 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L |
9256 | #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L |
9257 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L |
9258 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9259 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9260 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9261 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L |
9262 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L |
9263 | //SPI_PS_INPUT_CNTL_12 |
9264 | #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 |
9265 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 |
9266 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa |
9267 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd |
9268 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 |
9269 | #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 |
9270 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 |
9271 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9272 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9273 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9274 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 |
9275 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 |
9276 | #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL |
9277 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L |
9278 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L |
9279 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L |
9280 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L |
9281 | #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L |
9282 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L |
9283 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9284 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9285 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9286 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L |
9287 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L |
9288 | //SPI_PS_INPUT_CNTL_13 |
9289 | #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 |
9290 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 |
9291 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa |
9292 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd |
9293 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 |
9294 | #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 |
9295 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 |
9296 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9297 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9298 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9299 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 |
9300 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 |
9301 | #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL |
9302 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L |
9303 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L |
9304 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L |
9305 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L |
9306 | #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L |
9307 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L |
9308 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9309 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9310 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9311 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L |
9312 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L |
9313 | //SPI_PS_INPUT_CNTL_14 |
9314 | #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 |
9315 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 |
9316 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa |
9317 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd |
9318 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 |
9319 | #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 |
9320 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 |
9321 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9322 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9323 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9324 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 |
9325 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 |
9326 | #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL |
9327 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L |
9328 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L |
9329 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L |
9330 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L |
9331 | #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L |
9332 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L |
9333 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9334 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9335 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9336 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L |
9337 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L |
9338 | //SPI_PS_INPUT_CNTL_15 |
9339 | #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 |
9340 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 |
9341 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa |
9342 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd |
9343 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 |
9344 | #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 |
9345 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 |
9346 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9347 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9348 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9349 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 |
9350 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 |
9351 | #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL |
9352 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L |
9353 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L |
9354 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L |
9355 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L |
9356 | #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L |
9357 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L |
9358 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9359 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9360 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9361 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L |
9362 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L |
9363 | //SPI_PS_INPUT_CNTL_16 |
9364 | #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 |
9365 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 |
9366 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa |
9367 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd |
9368 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 |
9369 | #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 |
9370 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 |
9371 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9372 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9373 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9374 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 |
9375 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 |
9376 | #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL |
9377 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L |
9378 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L |
9379 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L |
9380 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L |
9381 | #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L |
9382 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L |
9383 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9384 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9385 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9386 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L |
9387 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L |
9388 | //SPI_PS_INPUT_CNTL_17 |
9389 | #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 |
9390 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 |
9391 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa |
9392 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd |
9393 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 |
9394 | #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 |
9395 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 |
9396 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9397 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9398 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9399 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 |
9400 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 |
9401 | #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL |
9402 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L |
9403 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L |
9404 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L |
9405 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L |
9406 | #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L |
9407 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L |
9408 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9409 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9410 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9411 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L |
9412 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L |
9413 | //SPI_PS_INPUT_CNTL_18 |
9414 | #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 |
9415 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 |
9416 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa |
9417 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd |
9418 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 |
9419 | #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 |
9420 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 |
9421 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9422 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9423 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9424 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 |
9425 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 |
9426 | #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL |
9427 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L |
9428 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L |
9429 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L |
9430 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L |
9431 | #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L |
9432 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L |
9433 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9434 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9435 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9436 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L |
9437 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L |
9438 | //SPI_PS_INPUT_CNTL_19 |
9439 | #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 |
9440 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 |
9441 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa |
9442 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd |
9443 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 |
9444 | #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 |
9445 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 |
9446 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9447 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9448 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
9449 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 |
9450 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 |
9451 | #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL |
9452 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L |
9453 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L |
9454 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L |
9455 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L |
9456 | #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L |
9457 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L |
9458 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9459 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9460 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
9461 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L |
9462 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L |
9463 | //SPI_PS_INPUT_CNTL_20 |
9464 | #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 |
9465 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 |
9466 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa |
9467 | #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 |
9468 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 |
9469 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9470 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9471 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 |
9472 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 |
9473 | #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL |
9474 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L |
9475 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L |
9476 | #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L |
9477 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L |
9478 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9479 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9480 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L |
9481 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L |
9482 | //SPI_PS_INPUT_CNTL_21 |
9483 | #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 |
9484 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 |
9485 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa |
9486 | #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 |
9487 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 |
9488 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9489 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9490 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 |
9491 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 |
9492 | #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL |
9493 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L |
9494 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L |
9495 | #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L |
9496 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L |
9497 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9498 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9499 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L |
9500 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L |
9501 | //SPI_PS_INPUT_CNTL_22 |
9502 | #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 |
9503 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 |
9504 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa |
9505 | #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 |
9506 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 |
9507 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9508 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9509 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 |
9510 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 |
9511 | #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL |
9512 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L |
9513 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L |
9514 | #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L |
9515 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L |
9516 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9517 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9518 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L |
9519 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L |
9520 | //SPI_PS_INPUT_CNTL_23 |
9521 | #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 |
9522 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 |
9523 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa |
9524 | #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 |
9525 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 |
9526 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9527 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9528 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 |
9529 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 |
9530 | #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL |
9531 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L |
9532 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L |
9533 | #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L |
9534 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L |
9535 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9536 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9537 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L |
9538 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L |
9539 | //SPI_PS_INPUT_CNTL_24 |
9540 | #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 |
9541 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 |
9542 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa |
9543 | #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 |
9544 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 |
9545 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9546 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9547 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 |
9548 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 |
9549 | #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL |
9550 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L |
9551 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L |
9552 | #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L |
9553 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L |
9554 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9555 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9556 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L |
9557 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L |
9558 | //SPI_PS_INPUT_CNTL_25 |
9559 | #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 |
9560 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 |
9561 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa |
9562 | #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 |
9563 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 |
9564 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9565 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9566 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 |
9567 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 |
9568 | #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL |
9569 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L |
9570 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L |
9571 | #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L |
9572 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L |
9573 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9574 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9575 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L |
9576 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L |
9577 | //SPI_PS_INPUT_CNTL_26 |
9578 | #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 |
9579 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 |
9580 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa |
9581 | #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 |
9582 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 |
9583 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9584 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9585 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 |
9586 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 |
9587 | #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL |
9588 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L |
9589 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L |
9590 | #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L |
9591 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L |
9592 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9593 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9594 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L |
9595 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L |
9596 | //SPI_PS_INPUT_CNTL_27 |
9597 | #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 |
9598 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 |
9599 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa |
9600 | #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 |
9601 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 |
9602 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9603 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9604 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 |
9605 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 |
9606 | #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL |
9607 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L |
9608 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L |
9609 | #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L |
9610 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L |
9611 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9612 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9613 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L |
9614 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L |
9615 | //SPI_PS_INPUT_CNTL_28 |
9616 | #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 |
9617 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 |
9618 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa |
9619 | #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 |
9620 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 |
9621 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9622 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9623 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 |
9624 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 |
9625 | #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL |
9626 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L |
9627 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L |
9628 | #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L |
9629 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L |
9630 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9631 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9632 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L |
9633 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L |
9634 | //SPI_PS_INPUT_CNTL_29 |
9635 | #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 |
9636 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 |
9637 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa |
9638 | #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 |
9639 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 |
9640 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9641 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9642 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 |
9643 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 |
9644 | #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL |
9645 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L |
9646 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L |
9647 | #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L |
9648 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L |
9649 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9650 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9651 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L |
9652 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L |
9653 | //SPI_PS_INPUT_CNTL_30 |
9654 | #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 |
9655 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 |
9656 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa |
9657 | #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 |
9658 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 |
9659 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9660 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9661 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 |
9662 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 |
9663 | #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL |
9664 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L |
9665 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L |
9666 | #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L |
9667 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L |
9668 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9669 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9670 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L |
9671 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L |
9672 | //SPI_PS_INPUT_CNTL_31 |
9673 | #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 |
9674 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 |
9675 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa |
9676 | #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 |
9677 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 |
9678 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 |
9679 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
9680 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 |
9681 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 |
9682 | #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL |
9683 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L |
9684 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L |
9685 | #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L |
9686 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L |
9687 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L |
9688 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
9689 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L |
9690 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L |
9691 | //SPI_VS_OUT_CONFIG |
9692 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 |
9693 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 |
9694 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL |
9695 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L |
9696 | //SPI_PS_INPUT_ENA |
9697 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 |
9698 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 |
9699 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 |
9700 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
9701 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
9702 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 |
9703 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 |
9704 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
9705 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 |
9706 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 |
9707 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa |
9708 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb |
9709 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc |
9710 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd |
9711 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
9712 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf |
9713 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L |
9714 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L |
9715 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L |
9716 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
9717 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
9718 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L |
9719 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L |
9720 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
9721 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L |
9722 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L |
9723 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L |
9724 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L |
9725 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L |
9726 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L |
9727 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
9728 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L |
9729 | //SPI_PS_INPUT_ADDR |
9730 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 |
9731 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 |
9732 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 |
9733 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
9734 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
9735 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 |
9736 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 |
9737 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
9738 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 |
9739 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 |
9740 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa |
9741 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb |
9742 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc |
9743 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd |
9744 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
9745 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf |
9746 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L |
9747 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L |
9748 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L |
9749 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
9750 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
9751 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L |
9752 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L |
9753 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
9754 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L |
9755 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L |
9756 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L |
9757 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L |
9758 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L |
9759 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L |
9760 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
9761 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L |
9762 | //SPI_INTERP_CONTROL_0 |
9763 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 |
9764 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 |
9765 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 |
9766 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 |
9767 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 |
9768 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb |
9769 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe |
9770 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L |
9771 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L |
9772 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL |
9773 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L |
9774 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L |
9775 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L |
9776 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L |
9777 | //SPI_PS_IN_CONTROL |
9778 | #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 |
9779 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 |
9780 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 |
9781 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe |
9782 | #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL |
9783 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L |
9784 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L |
9785 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L |
9786 | //SPI_BARYC_CNTL |
9787 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 |
9788 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 |
9789 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 |
9790 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc |
9791 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 |
9792 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 |
9793 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 |
9794 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L |
9795 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L |
9796 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L |
9797 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L |
9798 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L |
9799 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L |
9800 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L |
9801 | //SPI_TMPRING_SIZE |
9802 | #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 |
9803 | #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
9804 | #define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
9805 | #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
9806 | //SPI_SHADER_POS_FORMAT |
9807 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 |
9808 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 |
9809 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 |
9810 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc |
9811 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL |
9812 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L |
9813 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L |
9814 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L |
9815 | //SPI_SHADER_Z_FORMAT |
9816 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 |
9817 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL |
9818 | //SPI_SHADER_COL_FORMAT |
9819 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 |
9820 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 |
9821 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 |
9822 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc |
9823 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 |
9824 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 |
9825 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 |
9826 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c |
9827 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL |
9828 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L |
9829 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L |
9830 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L |
9831 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L |
9832 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L |
9833 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L |
9834 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L |
9835 | //SX_PS_DOWNCONVERT |
9836 | #define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 |
9837 | #define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 |
9838 | #define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 |
9839 | #define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc |
9840 | #define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 |
9841 | #define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 |
9842 | #define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 |
9843 | #define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c |
9844 | #define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL |
9845 | #define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L |
9846 | #define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L |
9847 | #define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L |
9848 | #define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L |
9849 | #define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L |
9850 | #define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L |
9851 | #define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L |
9852 | //SX_BLEND_OPT_EPSILON |
9853 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 |
9854 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 |
9855 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 |
9856 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc |
9857 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 |
9858 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 |
9859 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 |
9860 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c |
9861 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL |
9862 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L |
9863 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L |
9864 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L |
9865 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L |
9866 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L |
9867 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L |
9868 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L |
9869 | //SX_BLEND_OPT_CONTROL |
9870 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 |
9871 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 |
9872 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 |
9873 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 |
9874 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 |
9875 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 |
9876 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc |
9877 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd |
9878 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 |
9879 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 |
9880 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 |
9881 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 |
9882 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 |
9883 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 |
9884 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c |
9885 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d |
9886 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f |
9887 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L |
9888 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L |
9889 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L |
9890 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L |
9891 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L |
9892 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L |
9893 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L |
9894 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L |
9895 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L |
9896 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L |
9897 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L |
9898 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L |
9899 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L |
9900 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L |
9901 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L |
9902 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L |
9903 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L |
9904 | //SX_MRT0_BLEND_OPT |
9905 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9906 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9907 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9908 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9909 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9910 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9911 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9912 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9913 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9914 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9915 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9916 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9917 | //SX_MRT1_BLEND_OPT |
9918 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9919 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9920 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9921 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9922 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9923 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9924 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9925 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9926 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9927 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9928 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9929 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9930 | //SX_MRT2_BLEND_OPT |
9931 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9932 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9933 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9934 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9935 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9936 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9937 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9938 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9939 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9940 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9941 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9942 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9943 | //SX_MRT3_BLEND_OPT |
9944 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9945 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9946 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9947 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9948 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9949 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9950 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9951 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9952 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9953 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9954 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9955 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9956 | //SX_MRT4_BLEND_OPT |
9957 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9958 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9959 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9960 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9961 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9962 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9963 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9964 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9965 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9966 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9967 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9968 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9969 | //SX_MRT5_BLEND_OPT |
9970 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9971 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9972 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9973 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9974 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9975 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9976 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9977 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9978 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9979 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9980 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9981 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9982 | //SX_MRT6_BLEND_OPT |
9983 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9984 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9985 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9986 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
9987 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
9988 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
9989 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
9990 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
9991 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
9992 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
9993 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
9994 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
9995 | //SX_MRT7_BLEND_OPT |
9996 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
9997 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
9998 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
9999 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
10000 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
10001 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
10002 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
10003 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
10004 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
10005 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
10006 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
10007 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
10008 | //CB_BLEND0_CONTROL |
10009 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10010 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10011 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10012 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10013 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10014 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10015 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10016 | #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e |
10017 | #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10018 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10019 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10020 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10021 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10022 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10023 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10024 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10025 | #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L |
10026 | #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10027 | //CB_BLEND1_CONTROL |
10028 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10029 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10030 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10031 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10032 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10033 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10034 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10035 | #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e |
10036 | #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10037 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10038 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10039 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10040 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10041 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10042 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10043 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10044 | #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L |
10045 | #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10046 | //CB_BLEND2_CONTROL |
10047 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10048 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10049 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10050 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10051 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10052 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10053 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10054 | #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e |
10055 | #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10056 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10057 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10058 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10059 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10060 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10061 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10062 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10063 | #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L |
10064 | #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10065 | //CB_BLEND3_CONTROL |
10066 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10067 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10068 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10069 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10070 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10071 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10072 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10073 | #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e |
10074 | #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10075 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10076 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10077 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10078 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10079 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10080 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10081 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10082 | #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L |
10083 | #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10084 | //CB_BLEND4_CONTROL |
10085 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10086 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10087 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10088 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10089 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10090 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10091 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10092 | #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e |
10093 | #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10094 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10095 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10096 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10097 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10098 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10099 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10100 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10101 | #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L |
10102 | #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10103 | //CB_BLEND5_CONTROL |
10104 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10105 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10106 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10107 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10108 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10109 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10110 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10111 | #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e |
10112 | #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10113 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10114 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10115 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10116 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10117 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10118 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10119 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10120 | #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L |
10121 | #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10122 | //CB_BLEND6_CONTROL |
10123 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10124 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10125 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10126 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10127 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10128 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10129 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10130 | #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e |
10131 | #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10132 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10133 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10134 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10135 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10136 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10137 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10138 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10139 | #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L |
10140 | #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10141 | //CB_BLEND7_CONTROL |
10142 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
10143 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
10144 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
10145 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
10146 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
10147 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
10148 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
10149 | #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e |
10150 | #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
10151 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
10152 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
10153 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
10154 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
10155 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
10156 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
10157 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
10158 | #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L |
10159 | #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
10160 | //CB_MRT0_EPITCH |
10161 | #define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 |
10162 | #define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL |
10163 | //CB_MRT1_EPITCH |
10164 | #define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 |
10165 | #define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL |
10166 | //CB_MRT2_EPITCH |
10167 | #define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 |
10168 | #define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL |
10169 | //CB_MRT3_EPITCH |
10170 | #define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 |
10171 | #define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL |
10172 | //CB_MRT4_EPITCH |
10173 | #define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 |
10174 | #define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL |
10175 | //CB_MRT5_EPITCH |
10176 | #define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 |
10177 | #define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL |
10178 | //CB_MRT6_EPITCH |
10179 | #define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 |
10180 | #define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL |
10181 | //CB_MRT7_EPITCH |
10182 | #define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 |
10183 | #define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL |
10184 | //CS_COPY_STATE |
10185 | #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
10186 | #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
10187 | //GFX_COPY_STATE |
10188 | #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
10189 | #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
10190 | //PA_CL_POINT_X_RAD |
10191 | #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 |
10192 | #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
10193 | //PA_CL_POINT_Y_RAD |
10194 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 |
10195 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
10196 | //PA_CL_POINT_SIZE |
10197 | #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 |
10198 | #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL |
10199 | //PA_CL_POINT_CULL_RAD |
10200 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 |
10201 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
10202 | //VGT_DMA_BASE_HI |
10203 | #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 |
10204 | #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL |
10205 | //VGT_DMA_BASE |
10206 | #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 |
10207 | #define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL |
10208 | //VGT_DRAW_INITIATOR |
10209 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 |
10210 | #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 |
10211 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 |
10212 | #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 |
10213 | #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 |
10214 | #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 |
10215 | #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 |
10216 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d |
10217 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L |
10218 | #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL |
10219 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L |
10220 | #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L |
10221 | #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L |
10222 | #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L |
10223 | #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L |
10224 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L |
10225 | //VGT_IMMED_DATA |
10226 | #define VGT_IMMED_DATA__DATA__SHIFT 0x0 |
10227 | #define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL |
10228 | //VGT_EVENT_ADDRESS_REG |
10229 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 |
10230 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL |
10231 | //DB_DEPTH_CONTROL |
10232 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 |
10233 | #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 |
10234 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 |
10235 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 |
10236 | #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 |
10237 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 |
10238 | #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 |
10239 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 |
10240 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e |
10241 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f |
10242 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L |
10243 | #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L |
10244 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L |
10245 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L |
10246 | #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L |
10247 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L |
10248 | #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L |
10249 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L |
10250 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L |
10251 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L |
10252 | //DB_EQAA |
10253 | #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 |
10254 | #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 |
10255 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 |
10256 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc |
10257 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 |
10258 | #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 |
10259 | #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 |
10260 | #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 |
10261 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 |
10262 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 |
10263 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 |
10264 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b |
10265 | #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L |
10266 | #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L |
10267 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L |
10268 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L |
10269 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L |
10270 | #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L |
10271 | #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L |
10272 | #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L |
10273 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L |
10274 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L |
10275 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L |
10276 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L |
10277 | //CB_COLOR_CONTROL |
10278 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 |
10279 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 |
10280 | #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 |
10281 | #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 |
10282 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L |
10283 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L |
10284 | #define CB_COLOR_CONTROL__MODE_MASK 0x00000070L |
10285 | #define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L |
10286 | //DB_SHADER_CONTROL |
10287 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 |
10288 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 |
10289 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 |
10290 | #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 |
10291 | #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 |
10292 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 |
10293 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 |
10294 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 |
10295 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa |
10296 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb |
10297 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc |
10298 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd |
10299 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf |
10300 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 |
10301 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 |
10302 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 |
10303 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L |
10304 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L |
10305 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L |
10306 | #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L |
10307 | #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L |
10308 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L |
10309 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L |
10310 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L |
10311 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L |
10312 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L |
10313 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L |
10314 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L |
10315 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L |
10316 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L |
10317 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L |
10318 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L |
10319 | //PA_CL_CLIP_CNTL |
10320 | #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 |
10321 | #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 |
10322 | #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 |
10323 | #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 |
10324 | #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 |
10325 | #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 |
10326 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd |
10327 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe |
10328 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 |
10329 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 |
10330 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 |
10331 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 |
10332 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 |
10333 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 |
10334 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 |
10335 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 |
10336 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 |
10337 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a |
10338 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b |
10339 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c |
10340 | #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L |
10341 | #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L |
10342 | #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L |
10343 | #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L |
10344 | #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L |
10345 | #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L |
10346 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L |
10347 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L |
10348 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L |
10349 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L |
10350 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L |
10351 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L |
10352 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L |
10353 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L |
10354 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L |
10355 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L |
10356 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L |
10357 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L |
10358 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L |
10359 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L |
10360 | //PA_SU_SC_MODE_CNTL |
10361 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 |
10362 | #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 |
10363 | #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 |
10364 | #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 |
10365 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 |
10366 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 |
10367 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb |
10368 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc |
10369 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd |
10370 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 |
10371 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 |
10372 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 |
10373 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 |
10374 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 |
10375 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 |
10376 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L |
10377 | #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L |
10378 | #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L |
10379 | #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L |
10380 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L |
10381 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L |
10382 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L |
10383 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L |
10384 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L |
10385 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L |
10386 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L |
10387 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L |
10388 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L |
10389 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L |
10390 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L |
10391 | //PA_CL_VTE_CNTL |
10392 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 |
10393 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 |
10394 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 |
10395 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 |
10396 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 |
10397 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 |
10398 | #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 |
10399 | #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 |
10400 | #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa |
10401 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb |
10402 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L |
10403 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L |
10404 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L |
10405 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L |
10406 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L |
10407 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L |
10408 | #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L |
10409 | #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L |
10410 | #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L |
10411 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L |
10412 | //PA_CL_VS_OUT_CNTL |
10413 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 |
10414 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 |
10415 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 |
10416 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 |
10417 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 |
10418 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 |
10419 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 |
10420 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 |
10421 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 |
10422 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 |
10423 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa |
10424 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb |
10425 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc |
10426 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd |
10427 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe |
10428 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf |
10429 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 |
10430 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 |
10431 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 |
10432 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 |
10433 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 |
10434 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 |
10435 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 |
10436 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 |
10437 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 |
10438 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 |
10439 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a |
10440 | #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b |
10441 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L |
10442 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L |
10443 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L |
10444 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L |
10445 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L |
10446 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L |
10447 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L |
10448 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L |
10449 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L |
10450 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L |
10451 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L |
10452 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L |
10453 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L |
10454 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L |
10455 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L |
10456 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L |
10457 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L |
10458 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L |
10459 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L |
10460 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L |
10461 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L |
10462 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L |
10463 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L |
10464 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L |
10465 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L |
10466 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L |
10467 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L |
10468 | #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L |
10469 | //PA_CL_NANINF_CNTL |
10470 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 |
10471 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 |
10472 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 |
10473 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 |
10474 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 |
10475 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 |
10476 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 |
10477 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 |
10478 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 |
10479 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 |
10480 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa |
10481 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb |
10482 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc |
10483 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd |
10484 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe |
10485 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 |
10486 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L |
10487 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L |
10488 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L |
10489 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L |
10490 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L |
10491 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L |
10492 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L |
10493 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L |
10494 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L |
10495 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L |
10496 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L |
10497 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L |
10498 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L |
10499 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L |
10500 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L |
10501 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L |
10502 | //PA_SU_LINE_STIPPLE_CNTL |
10503 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 |
10504 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 |
10505 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 |
10506 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 |
10507 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L |
10508 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L |
10509 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L |
10510 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L |
10511 | //PA_SU_LINE_STIPPLE_SCALE |
10512 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 |
10513 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL |
10514 | //PA_SU_PRIM_FILTER_CNTL |
10515 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 |
10516 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 |
10517 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 |
10518 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 |
10519 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 |
10520 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 |
10521 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 |
10522 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 |
10523 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 |
10524 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e |
10525 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f |
10526 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L |
10527 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L |
10528 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L |
10529 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L |
10530 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L |
10531 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L |
10532 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L |
10533 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L |
10534 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L |
10535 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L |
10536 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L |
10537 | //PA_SU_SMALL_PRIM_FILTER_CNTL |
10538 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 |
10539 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 |
10540 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 |
10541 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 |
10542 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 |
10543 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L |
10544 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L |
10545 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L |
10546 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L |
10547 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L |
10548 | //PA_CL_OBJPRIM_ID_CNTL |
10549 | #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 |
10550 | #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 |
10551 | #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 |
10552 | #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L |
10553 | #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L |
10554 | #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L |
10555 | //PA_CL_NGG_CNTL |
10556 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 |
10557 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 |
10558 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L |
10559 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L |
10560 | //PA_SU_OVER_RASTERIZATION_CNTL |
10561 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 |
10562 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 |
10563 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 |
10564 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 |
10565 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 |
10566 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L |
10567 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L |
10568 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L |
10569 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L |
10570 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L |
10571 | //PA_STEREO_CNTL |
10572 | #define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0 |
10573 | #define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 |
10574 | #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 |
10575 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 |
10576 | #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa |
10577 | #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd |
10578 | #define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L |
10579 | #define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL |
10580 | #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L |
10581 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L |
10582 | #define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L |
10583 | #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L |
10584 | //PA_SU_POINT_SIZE |
10585 | #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 |
10586 | #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 |
10587 | #define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL |
10588 | #define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L |
10589 | //PA_SU_POINT_MINMAX |
10590 | #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 |
10591 | #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 |
10592 | #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL |
10593 | #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L |
10594 | //PA_SU_LINE_CNTL |
10595 | #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 |
10596 | #define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL |
10597 | //PA_SC_LINE_STIPPLE |
10598 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 |
10599 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 |
10600 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c |
10601 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d |
10602 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL |
10603 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L |
10604 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L |
10605 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L |
10606 | //VGT_OUTPUT_PATH_CNTL |
10607 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 |
10608 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L |
10609 | //VGT_HOS_CNTL |
10610 | #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 |
10611 | #define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L |
10612 | //VGT_HOS_MAX_TESS_LEVEL |
10613 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 |
10614 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL |
10615 | //VGT_HOS_MIN_TESS_LEVEL |
10616 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 |
10617 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL |
10618 | //VGT_HOS_REUSE_DEPTH |
10619 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 |
10620 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL |
10621 | //VGT_GROUP_PRIM_TYPE |
10622 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 |
10623 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe |
10624 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf |
10625 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 |
10626 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL |
10627 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L |
10628 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L |
10629 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L |
10630 | //VGT_GROUP_FIRST_DECR |
10631 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 |
10632 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL |
10633 | //VGT_GROUP_DECR |
10634 | #define VGT_GROUP_DECR__DECR__SHIFT 0x0 |
10635 | #define VGT_GROUP_DECR__DECR_MASK 0x0000000FL |
10636 | //VGT_GROUP_VECT_0_CNTL |
10637 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 |
10638 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 |
10639 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 |
10640 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 |
10641 | #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 |
10642 | #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 |
10643 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L |
10644 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L |
10645 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L |
10646 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L |
10647 | #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L |
10648 | #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L |
10649 | //VGT_GROUP_VECT_1_CNTL |
10650 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 |
10651 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 |
10652 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 |
10653 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 |
10654 | #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 |
10655 | #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 |
10656 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L |
10657 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L |
10658 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L |
10659 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L |
10660 | #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L |
10661 | #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L |
10662 | //VGT_GROUP_VECT_0_FMT_CNTL |
10663 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 |
10664 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
10665 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 |
10666 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
10667 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 |
10668 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
10669 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 |
10670 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
10671 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL |
10672 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
10673 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
10674 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
10675 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
10676 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
10677 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L |
10678 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
10679 | //VGT_GROUP_VECT_1_FMT_CNTL |
10680 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 |
10681 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
10682 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 |
10683 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
10684 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 |
10685 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
10686 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 |
10687 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
10688 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL |
10689 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
10690 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
10691 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
10692 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
10693 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
10694 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L |
10695 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
10696 | //VGT_GS_MODE |
10697 | #define VGT_GS_MODE__MODE__SHIFT 0x0 |
10698 | #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 |
10699 | #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 |
10700 | #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 |
10701 | #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb |
10702 | #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc |
10703 | #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd |
10704 | #define VGT_GS_MODE__RESERVED_3__SHIFT 0xe |
10705 | #define VGT_GS_MODE__RESERVED_4__SHIFT 0xf |
10706 | #define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 |
10707 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 |
10708 | #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 |
10709 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 |
10710 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 |
10711 | #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 |
10712 | #define VGT_GS_MODE__MODE_MASK 0x00000007L |
10713 | #define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L |
10714 | #define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L |
10715 | #define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L |
10716 | #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L |
10717 | #define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L |
10718 | #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L |
10719 | #define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L |
10720 | #define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L |
10721 | #define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L |
10722 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L |
10723 | #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L |
10724 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L |
10725 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L |
10726 | #define VGT_GS_MODE__ONCHIP_MASK 0x00600000L |
10727 | //VGT_GS_ONCHIP_CNTL |
10728 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 |
10729 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb |
10730 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 |
10731 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL |
10732 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L |
10733 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L |
10734 | //PA_SC_MODE_CNTL_0 |
10735 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 |
10736 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 |
10737 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 |
10738 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 |
10739 | #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 |
10740 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 |
10741 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 |
10742 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L |
10743 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L |
10744 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L |
10745 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L |
10746 | #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L |
10747 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L |
10748 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L |
10749 | //PA_SC_MODE_CNTL_1 |
10750 | #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 |
10751 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 |
10752 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 |
10753 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 |
10754 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 |
10755 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 |
10756 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 |
10757 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 |
10758 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa |
10759 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb |
10760 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc |
10761 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd |
10762 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe |
10763 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf |
10764 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 |
10765 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 |
10766 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 |
10767 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 |
10768 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 |
10769 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 |
10770 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 |
10771 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a |
10772 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b |
10773 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c |
10774 | #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L |
10775 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L |
10776 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L |
10777 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L |
10778 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L |
10779 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L |
10780 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L |
10781 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L |
10782 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L |
10783 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L |
10784 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L |
10785 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L |
10786 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L |
10787 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L |
10788 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L |
10789 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L |
10790 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L |
10791 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L |
10792 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L |
10793 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L |
10794 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L |
10795 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L |
10796 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L |
10797 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L |
10798 | //VGT_ENHANCE |
10799 | #define VGT_ENHANCE__MISC__SHIFT 0x0 |
10800 | #define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL |
10801 | //VGT_GS_PER_ES |
10802 | #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 |
10803 | #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL |
10804 | //VGT_ES_PER_GS |
10805 | #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 |
10806 | #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL |
10807 | //VGT_GS_PER_VS |
10808 | #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 |
10809 | #define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL |
10810 | //VGT_GSVS_RING_OFFSET_1 |
10811 | #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 |
10812 | #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL |
10813 | //VGT_GSVS_RING_OFFSET_2 |
10814 | #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 |
10815 | #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL |
10816 | //VGT_GSVS_RING_OFFSET_3 |
10817 | #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 |
10818 | #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL |
10819 | //VGT_GS_OUT_PRIM_TYPE |
10820 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 |
10821 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 |
10822 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 |
10823 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 |
10824 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f |
10825 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL |
10826 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L |
10827 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L |
10828 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L |
10829 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L |
10830 | //IA_ENHANCE |
10831 | #define IA_ENHANCE__MISC__SHIFT 0x0 |
10832 | #define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL |
10833 | //VGT_DMA_SIZE |
10834 | #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 |
10835 | #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL |
10836 | //VGT_DMA_MAX_SIZE |
10837 | #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 |
10838 | #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL |
10839 | //VGT_DMA_INDEX_TYPE |
10840 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
10841 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 |
10842 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 |
10843 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 |
10844 | #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 |
10845 | #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 |
10846 | #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa |
10847 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
10848 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL |
10849 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L |
10850 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L |
10851 | #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L |
10852 | #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L |
10853 | #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L |
10854 | //WD_ENHANCE |
10855 | #define WD_ENHANCE__MISC__SHIFT 0x0 |
10856 | #define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL |
10857 | //VGT_PRIMITIVEID_EN |
10858 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 |
10859 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 |
10860 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 |
10861 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L |
10862 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L |
10863 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L |
10864 | //VGT_DMA_NUM_INSTANCES |
10865 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
10866 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
10867 | //VGT_PRIMITIVEID_RESET |
10868 | #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 |
10869 | #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL |
10870 | //VGT_EVENT_INITIATOR |
10871 | #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
10872 | #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
10873 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
10874 | #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
10875 | #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
10876 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
10877 | //VGT_GS_MAX_PRIMS_PER_SUBGROUP |
10878 | #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 |
10879 | #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL |
10880 | //VGT_DRAW_PAYLOAD_CNTL |
10881 | #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 |
10882 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 |
10883 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 |
10884 | #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 |
10885 | #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L |
10886 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L |
10887 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L |
10888 | #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L |
10889 | //VGT_INSTANCE_STEP_RATE_0 |
10890 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 |
10891 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL |
10892 | //VGT_INSTANCE_STEP_RATE_1 |
10893 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 |
10894 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL |
10895 | //IA_MULTI_VGT_PARAM_BC |
10896 | //VGT_ESGS_RING_ITEMSIZE |
10897 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
10898 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
10899 | //VGT_GSVS_RING_ITEMSIZE |
10900 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
10901 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
10902 | //VGT_REUSE_OFF |
10903 | #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 |
10904 | #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L |
10905 | //VGT_VTX_CNT_EN |
10906 | #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 |
10907 | #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L |
10908 | //DB_HTILE_SURFACE |
10909 | #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 |
10910 | #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 |
10911 | #define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 |
10912 | #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 |
10913 | #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa |
10914 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 |
10915 | #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 |
10916 | #define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 |
10917 | #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L |
10918 | #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L |
10919 | #define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L |
10920 | #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L |
10921 | #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L |
10922 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L |
10923 | #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L |
10924 | #define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L |
10925 | //DB_SRESULTS_COMPARE_STATE0 |
10926 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 |
10927 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 |
10928 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc |
10929 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 |
10930 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L |
10931 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L |
10932 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L |
10933 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L |
10934 | //DB_SRESULTS_COMPARE_STATE1 |
10935 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 |
10936 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 |
10937 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc |
10938 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 |
10939 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L |
10940 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L |
10941 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L |
10942 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L |
10943 | //DB_PRELOAD_CONTROL |
10944 | #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 |
10945 | #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 |
10946 | #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 |
10947 | #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 |
10948 | #define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL |
10949 | #define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L |
10950 | #define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L |
10951 | #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L |
10952 | //VGT_STRMOUT_BUFFER_SIZE_0 |
10953 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 |
10954 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
10955 | //VGT_STRMOUT_VTX_STRIDE_0 |
10956 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 |
10957 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL |
10958 | //VGT_STRMOUT_BUFFER_OFFSET_0 |
10959 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 |
10960 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL |
10961 | //VGT_STRMOUT_BUFFER_SIZE_1 |
10962 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 |
10963 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
10964 | //VGT_STRMOUT_VTX_STRIDE_1 |
10965 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 |
10966 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL |
10967 | //VGT_STRMOUT_BUFFER_OFFSET_1 |
10968 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 |
10969 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL |
10970 | //VGT_STRMOUT_BUFFER_SIZE_2 |
10971 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 |
10972 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
10973 | //VGT_STRMOUT_VTX_STRIDE_2 |
10974 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 |
10975 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL |
10976 | //VGT_STRMOUT_BUFFER_OFFSET_2 |
10977 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 |
10978 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL |
10979 | //VGT_STRMOUT_BUFFER_SIZE_3 |
10980 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 |
10981 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
10982 | //VGT_STRMOUT_VTX_STRIDE_3 |
10983 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 |
10984 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL |
10985 | //VGT_STRMOUT_BUFFER_OFFSET_3 |
10986 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 |
10987 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL |
10988 | //VGT_STRMOUT_DRAW_OPAQUE_OFFSET |
10989 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 |
10990 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
10991 | //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE |
10992 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 |
10993 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL |
10994 | //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE |
10995 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 |
10996 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL |
10997 | //VGT_GS_MAX_VERT_OUT |
10998 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 |
10999 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL |
11000 | //VGT_TESS_DISTRIBUTION |
11001 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 |
11002 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 |
11003 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 |
11004 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 |
11005 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d |
11006 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL |
11007 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L |
11008 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L |
11009 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L |
11010 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L |
11011 | //VGT_SHADER_STAGES_EN |
11012 | #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 |
11013 | #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 |
11014 | #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 |
11015 | #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 |
11016 | #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 |
11017 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 |
11018 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa |
11019 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb |
11020 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc |
11021 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd |
11022 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe |
11023 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf |
11024 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 |
11025 | #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L |
11026 | #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L |
11027 | #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L |
11028 | #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L |
11029 | #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L |
11030 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L |
11031 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L |
11032 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L |
11033 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L |
11034 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L |
11035 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L |
11036 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L |
11037 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L |
11038 | //VGT_LS_HS_CONFIG |
11039 | #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 |
11040 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
11041 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe |
11042 | #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL |
11043 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
11044 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L |
11045 | //VGT_GS_VERT_ITEMSIZE |
11046 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
11047 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
11048 | //VGT_GS_VERT_ITEMSIZE_1 |
11049 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 |
11050 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL |
11051 | //VGT_GS_VERT_ITEMSIZE_2 |
11052 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 |
11053 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL |
11054 | //VGT_GS_VERT_ITEMSIZE_3 |
11055 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 |
11056 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL |
11057 | //VGT_TF_PARAM |
11058 | #define VGT_TF_PARAM__TYPE__SHIFT 0x0 |
11059 | #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 |
11060 | #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 |
11061 | #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 |
11062 | #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe |
11063 | #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf |
11064 | #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 |
11065 | #define VGT_TF_PARAM__TYPE_MASK 0x00000003L |
11066 | #define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL |
11067 | #define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L |
11068 | #define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L |
11069 | #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L |
11070 | #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L |
11071 | #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L |
11072 | //DB_ALPHA_TO_MASK |
11073 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 |
11074 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 |
11075 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa |
11076 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc |
11077 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe |
11078 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 |
11079 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L |
11080 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L |
11081 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L |
11082 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L |
11083 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L |
11084 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L |
11085 | //VGT_DISPATCH_DRAW_INDEX |
11086 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 |
11087 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL |
11088 | //PA_SU_POLY_OFFSET_DB_FMT_CNTL |
11089 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 |
11090 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 |
11091 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL |
11092 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L |
11093 | //PA_SU_POLY_OFFSET_CLAMP |
11094 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 |
11095 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL |
11096 | //PA_SU_POLY_OFFSET_FRONT_SCALE |
11097 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 |
11098 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL |
11099 | //PA_SU_POLY_OFFSET_FRONT_OFFSET |
11100 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 |
11101 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
11102 | //PA_SU_POLY_OFFSET_BACK_SCALE |
11103 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 |
11104 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL |
11105 | //PA_SU_POLY_OFFSET_BACK_OFFSET |
11106 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 |
11107 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
11108 | //VGT_GS_INSTANCE_CNT |
11109 | #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 |
11110 | #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 |
11111 | #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L |
11112 | #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL |
11113 | //VGT_STRMOUT_CONFIG |
11114 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 |
11115 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 |
11116 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 |
11117 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 |
11118 | #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 |
11119 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 |
11120 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 |
11121 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f |
11122 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L |
11123 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L |
11124 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L |
11125 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L |
11126 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L |
11127 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L |
11128 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L |
11129 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L |
11130 | //VGT_STRMOUT_BUFFER_CONFIG |
11131 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 |
11132 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 |
11133 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 |
11134 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc |
11135 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL |
11136 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L |
11137 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L |
11138 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L |
11139 | //VGT_DMA_EVENT_INITIATOR |
11140 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
11141 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
11142 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
11143 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
11144 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
11145 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
11146 | //PA_SC_CENTROID_PRIORITY_0 |
11147 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 |
11148 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 |
11149 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 |
11150 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc |
11151 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 |
11152 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 |
11153 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 |
11154 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c |
11155 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL |
11156 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L |
11157 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L |
11158 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L |
11159 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L |
11160 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L |
11161 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L |
11162 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L |
11163 | //PA_SC_CENTROID_PRIORITY_1 |
11164 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 |
11165 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 |
11166 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 |
11167 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc |
11168 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 |
11169 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 |
11170 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 |
11171 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c |
11172 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL |
11173 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L |
11174 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L |
11175 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L |
11176 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L |
11177 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L |
11178 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L |
11179 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L |
11180 | //PA_SC_LINE_CNTL |
11181 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 |
11182 | #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa |
11183 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb |
11184 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc |
11185 | #define 0xd |
11186 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L |
11187 | #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L |
11188 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L |
11189 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L |
11190 | #define 0x00002000L |
11191 | //PA_SC_AA_CONFIG |
11192 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 |
11193 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 |
11194 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd |
11195 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 |
11196 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 |
11197 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a |
11198 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L |
11199 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L |
11200 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L |
11201 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L |
11202 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L |
11203 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L |
11204 | //PA_SU_VTX_CNTL |
11205 | #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 |
11206 | #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 |
11207 | #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 |
11208 | #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L |
11209 | #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L |
11210 | #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L |
11211 | //PA_CL_GB_VERT_CLIP_ADJ |
11212 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
11213 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
11214 | //PA_CL_GB_VERT_DISC_ADJ |
11215 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
11216 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
11217 | //PA_CL_GB_HORZ_CLIP_ADJ |
11218 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
11219 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
11220 | //PA_CL_GB_HORZ_DISC_ADJ |
11221 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
11222 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
11223 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 |
11224 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 |
11225 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 |
11226 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 |
11227 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc |
11228 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 |
11229 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 |
11230 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 |
11231 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c |
11232 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL |
11233 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L |
11234 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L |
11235 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L |
11236 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L |
11237 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L |
11238 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L |
11239 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L |
11240 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 |
11241 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 |
11242 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 |
11243 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 |
11244 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc |
11245 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 |
11246 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 |
11247 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 |
11248 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c |
11249 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL |
11250 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L |
11251 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L |
11252 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L |
11253 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L |
11254 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L |
11255 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L |
11256 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L |
11257 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 |
11258 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 |
11259 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 |
11260 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 |
11261 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc |
11262 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 |
11263 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 |
11264 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 |
11265 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c |
11266 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL |
11267 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L |
11268 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L |
11269 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L |
11270 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L |
11271 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L |
11272 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L |
11273 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L |
11274 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 |
11275 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 |
11276 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 |
11277 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 |
11278 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc |
11279 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 |
11280 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 |
11281 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 |
11282 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c |
11283 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL |
11284 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L |
11285 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L |
11286 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L |
11287 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L |
11288 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L |
11289 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L |
11290 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L |
11291 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 |
11292 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 |
11293 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 |
11294 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 |
11295 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc |
11296 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 |
11297 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 |
11298 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 |
11299 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c |
11300 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL |
11301 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L |
11302 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L |
11303 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L |
11304 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L |
11305 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L |
11306 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L |
11307 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L |
11308 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 |
11309 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 |
11310 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 |
11311 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 |
11312 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc |
11313 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 |
11314 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 |
11315 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 |
11316 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c |
11317 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL |
11318 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L |
11319 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L |
11320 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L |
11321 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L |
11322 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L |
11323 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L |
11324 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L |
11325 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 |
11326 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 |
11327 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 |
11328 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 |
11329 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc |
11330 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 |
11331 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 |
11332 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 |
11333 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c |
11334 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL |
11335 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L |
11336 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L |
11337 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L |
11338 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L |
11339 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L |
11340 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L |
11341 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L |
11342 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 |
11343 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 |
11344 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 |
11345 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 |
11346 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc |
11347 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 |
11348 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 |
11349 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 |
11350 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c |
11351 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL |
11352 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L |
11353 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L |
11354 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L |
11355 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L |
11356 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L |
11357 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L |
11358 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L |
11359 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 |
11360 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 |
11361 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 |
11362 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 |
11363 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc |
11364 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 |
11365 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 |
11366 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 |
11367 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c |
11368 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL |
11369 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L |
11370 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L |
11371 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L |
11372 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L |
11373 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L |
11374 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L |
11375 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L |
11376 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 |
11377 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 |
11378 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 |
11379 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 |
11380 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc |
11381 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 |
11382 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 |
11383 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 |
11384 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c |
11385 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL |
11386 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L |
11387 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L |
11388 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L |
11389 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L |
11390 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L |
11391 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L |
11392 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L |
11393 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 |
11394 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 |
11395 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 |
11396 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 |
11397 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc |
11398 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 |
11399 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 |
11400 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 |
11401 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c |
11402 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL |
11403 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L |
11404 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L |
11405 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L |
11406 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L |
11407 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L |
11408 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L |
11409 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L |
11410 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 |
11411 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 |
11412 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 |
11413 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 |
11414 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc |
11415 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 |
11416 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 |
11417 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 |
11418 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c |
11419 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL |
11420 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L |
11421 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L |
11422 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L |
11423 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L |
11424 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L |
11425 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L |
11426 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L |
11427 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 |
11428 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 |
11429 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 |
11430 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 |
11431 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc |
11432 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 |
11433 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 |
11434 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 |
11435 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c |
11436 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL |
11437 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L |
11438 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L |
11439 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L |
11440 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L |
11441 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L |
11442 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L |
11443 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L |
11444 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 |
11445 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 |
11446 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 |
11447 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 |
11448 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc |
11449 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 |
11450 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 |
11451 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 |
11452 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c |
11453 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL |
11454 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L |
11455 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L |
11456 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L |
11457 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L |
11458 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L |
11459 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L |
11460 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L |
11461 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 |
11462 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 |
11463 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 |
11464 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 |
11465 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc |
11466 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 |
11467 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 |
11468 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 |
11469 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c |
11470 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL |
11471 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L |
11472 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L |
11473 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L |
11474 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L |
11475 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L |
11476 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L |
11477 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L |
11478 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 |
11479 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 |
11480 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 |
11481 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 |
11482 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc |
11483 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 |
11484 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 |
11485 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 |
11486 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c |
11487 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL |
11488 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L |
11489 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L |
11490 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L |
11491 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L |
11492 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L |
11493 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L |
11494 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L |
11495 | //PA_SC_AA_MASK_X0Y0_X1Y0 |
11496 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 |
11497 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 |
11498 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL |
11499 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L |
11500 | //PA_SC_AA_MASK_X0Y1_X1Y1 |
11501 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 |
11502 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 |
11503 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL |
11504 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L |
11505 | //PA_SC_SHADER_CONTROL |
11506 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 |
11507 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 |
11508 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 |
11509 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L |
11510 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L |
11511 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L |
11512 | //PA_SC_BINNER_CNTL_0 |
11513 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 |
11514 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 |
11515 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 |
11516 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 |
11517 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 |
11518 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
11519 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
11520 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 |
11521 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 |
11522 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b |
11523 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c |
11524 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L |
11525 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L |
11526 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L |
11527 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L |
11528 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L |
11529 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
11530 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
11531 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L |
11532 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L |
11533 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L |
11534 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L |
11535 | //PA_SC_BINNER_CNTL_1 |
11536 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 |
11537 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 |
11538 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL |
11539 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L |
11540 | //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL |
11541 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 |
11542 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 |
11543 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 |
11544 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 |
11545 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa |
11546 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb |
11547 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc |
11548 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd |
11549 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe |
11550 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf |
11551 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 |
11552 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 |
11553 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 |
11554 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 |
11555 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 |
11556 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 |
11557 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 |
11558 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 |
11559 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L |
11560 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL |
11561 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L |
11562 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L |
11563 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L |
11564 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L |
11565 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L |
11566 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L |
11567 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L |
11568 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L |
11569 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L |
11570 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L |
11571 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L |
11572 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L |
11573 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L |
11574 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L |
11575 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L |
11576 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L |
11577 | //PA_SC_NGG_MODE_CNTL |
11578 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
11579 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
11580 | //VGT_VERTEX_REUSE_BLOCK_CNTL |
11581 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 |
11582 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL |
11583 | //VGT_OUT_DEALLOC_CNTL |
11584 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 |
11585 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL |
11586 | //CB_COLOR0_BASE |
11587 | #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 |
11588 | #define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11589 | //CB_COLOR0_BASE_EXT |
11590 | #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 |
11591 | #define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11592 | //CB_COLOR0_ATTRIB2 |
11593 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
11594 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
11595 | #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c |
11596 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
11597 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
11598 | #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
11599 | //CB_COLOR0_VIEW |
11600 | #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 |
11601 | #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd |
11602 | #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 |
11603 | #define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL |
11604 | #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L |
11605 | #define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L |
11606 | //CB_COLOR0_INFO |
11607 | #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 |
11608 | #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 |
11609 | #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 |
11610 | #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb |
11611 | #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd |
11612 | #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe |
11613 | #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf |
11614 | #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 |
11615 | #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
11616 | #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 |
11617 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
11618 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
11619 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
11620 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
11621 | #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c |
11622 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
11623 | #define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L |
11624 | #define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL |
11625 | #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L |
11626 | #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L |
11627 | #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L |
11628 | #define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L |
11629 | #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L |
11630 | #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L |
11631 | #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
11632 | #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L |
11633 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
11634 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
11635 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
11636 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
11637 | #define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L |
11638 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
11639 | //CB_COLOR0_ATTRIB |
11640 | #define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
11641 | #define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb |
11642 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
11643 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
11644 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
11645 | #define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
11646 | #define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
11647 | #define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
11648 | #define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
11649 | #define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
11650 | #define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
11651 | #define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L |
11652 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
11653 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
11654 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
11655 | #define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
11656 | #define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
11657 | #define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
11658 | #define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
11659 | #define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
11660 | //CB_COLOR0_DCC_CONTROL |
11661 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
11662 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
11663 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
11664 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
11665 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
11666 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
11667 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
11668 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
11669 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
11670 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
11671 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
11672 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
11673 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
11674 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
11675 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
11676 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
11677 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
11678 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
11679 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
11680 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
11681 | //CB_COLOR0_CMASK |
11682 | #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 |
11683 | #define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
11684 | //CB_COLOR0_CMASK_BASE_EXT |
11685 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11686 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11687 | //CB_COLOR0_FMASK |
11688 | #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 |
11689 | #define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
11690 | //CB_COLOR0_FMASK_BASE_EXT |
11691 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11692 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11693 | //CB_COLOR0_CLEAR_WORD0 |
11694 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
11695 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
11696 | //CB_COLOR0_CLEAR_WORD1 |
11697 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
11698 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
11699 | //CB_COLOR0_DCC_BASE |
11700 | #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 |
11701 | #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11702 | //CB_COLOR0_DCC_BASE_EXT |
11703 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
11704 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11705 | //CB_COLOR1_BASE |
11706 | #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 |
11707 | #define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11708 | //CB_COLOR1_BASE_EXT |
11709 | #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 |
11710 | #define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11711 | //CB_COLOR1_ATTRIB2 |
11712 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
11713 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
11714 | #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c |
11715 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
11716 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
11717 | #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
11718 | //CB_COLOR1_VIEW |
11719 | #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 |
11720 | #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd |
11721 | #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 |
11722 | #define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL |
11723 | #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L |
11724 | #define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L |
11725 | //CB_COLOR1_INFO |
11726 | #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 |
11727 | #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 |
11728 | #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 |
11729 | #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb |
11730 | #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd |
11731 | #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe |
11732 | #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf |
11733 | #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 |
11734 | #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
11735 | #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 |
11736 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
11737 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
11738 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
11739 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
11740 | #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c |
11741 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
11742 | #define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L |
11743 | #define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL |
11744 | #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L |
11745 | #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L |
11746 | #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L |
11747 | #define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L |
11748 | #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L |
11749 | #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L |
11750 | #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
11751 | #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L |
11752 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
11753 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
11754 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
11755 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
11756 | #define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L |
11757 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
11758 | //CB_COLOR1_ATTRIB |
11759 | #define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
11760 | #define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb |
11761 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
11762 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
11763 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
11764 | #define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
11765 | #define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
11766 | #define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
11767 | #define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
11768 | #define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
11769 | #define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
11770 | #define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L |
11771 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
11772 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
11773 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
11774 | #define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
11775 | #define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
11776 | #define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
11777 | #define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
11778 | #define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
11779 | //CB_COLOR1_DCC_CONTROL |
11780 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
11781 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
11782 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
11783 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
11784 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
11785 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
11786 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
11787 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
11788 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
11789 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
11790 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
11791 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
11792 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
11793 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
11794 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
11795 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
11796 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
11797 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
11798 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
11799 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
11800 | //CB_COLOR1_CMASK |
11801 | #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 |
11802 | #define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
11803 | //CB_COLOR1_CMASK_BASE_EXT |
11804 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11805 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11806 | //CB_COLOR1_FMASK |
11807 | #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 |
11808 | #define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
11809 | //CB_COLOR1_FMASK_BASE_EXT |
11810 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11811 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11812 | //CB_COLOR1_CLEAR_WORD0 |
11813 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
11814 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
11815 | //CB_COLOR1_CLEAR_WORD1 |
11816 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
11817 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
11818 | //CB_COLOR1_DCC_BASE |
11819 | #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 |
11820 | #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11821 | //CB_COLOR1_DCC_BASE_EXT |
11822 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
11823 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11824 | //CB_COLOR2_BASE |
11825 | #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 |
11826 | #define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11827 | //CB_COLOR2_BASE_EXT |
11828 | #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 |
11829 | #define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11830 | //CB_COLOR2_ATTRIB2 |
11831 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
11832 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
11833 | #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c |
11834 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
11835 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
11836 | #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
11837 | //CB_COLOR2_VIEW |
11838 | #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 |
11839 | #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd |
11840 | #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 |
11841 | #define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL |
11842 | #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L |
11843 | #define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L |
11844 | //CB_COLOR2_INFO |
11845 | #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 |
11846 | #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 |
11847 | #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 |
11848 | #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb |
11849 | #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd |
11850 | #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe |
11851 | #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf |
11852 | #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 |
11853 | #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
11854 | #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 |
11855 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
11856 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
11857 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
11858 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
11859 | #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c |
11860 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
11861 | #define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L |
11862 | #define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL |
11863 | #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L |
11864 | #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L |
11865 | #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L |
11866 | #define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L |
11867 | #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L |
11868 | #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L |
11869 | #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
11870 | #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L |
11871 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
11872 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
11873 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
11874 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
11875 | #define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L |
11876 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
11877 | //CB_COLOR2_ATTRIB |
11878 | #define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
11879 | #define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb |
11880 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
11881 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
11882 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
11883 | #define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
11884 | #define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
11885 | #define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
11886 | #define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
11887 | #define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
11888 | #define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
11889 | #define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L |
11890 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
11891 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
11892 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
11893 | #define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
11894 | #define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
11895 | #define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
11896 | #define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
11897 | #define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
11898 | //CB_COLOR2_DCC_CONTROL |
11899 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
11900 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
11901 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
11902 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
11903 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
11904 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
11905 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
11906 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
11907 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
11908 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
11909 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
11910 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
11911 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
11912 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
11913 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
11914 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
11915 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
11916 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
11917 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
11918 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
11919 | //CB_COLOR2_CMASK |
11920 | #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 |
11921 | #define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
11922 | //CB_COLOR2_CMASK_BASE_EXT |
11923 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11924 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11925 | //CB_COLOR2_FMASK |
11926 | #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 |
11927 | #define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
11928 | //CB_COLOR2_FMASK_BASE_EXT |
11929 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
11930 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11931 | //CB_COLOR2_CLEAR_WORD0 |
11932 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
11933 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
11934 | //CB_COLOR2_CLEAR_WORD1 |
11935 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
11936 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
11937 | //CB_COLOR2_DCC_BASE |
11938 | #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 |
11939 | #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11940 | //CB_COLOR2_DCC_BASE_EXT |
11941 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
11942 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11943 | //CB_COLOR3_BASE |
11944 | #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 |
11945 | #define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL |
11946 | //CB_COLOR3_BASE_EXT |
11947 | #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 |
11948 | #define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL |
11949 | //CB_COLOR3_ATTRIB2 |
11950 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
11951 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
11952 | #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c |
11953 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
11954 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
11955 | #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
11956 | //CB_COLOR3_VIEW |
11957 | #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 |
11958 | #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd |
11959 | #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 |
11960 | #define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL |
11961 | #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L |
11962 | #define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L |
11963 | //CB_COLOR3_INFO |
11964 | #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 |
11965 | #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 |
11966 | #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 |
11967 | #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb |
11968 | #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd |
11969 | #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe |
11970 | #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf |
11971 | #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 |
11972 | #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
11973 | #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 |
11974 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
11975 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
11976 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
11977 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
11978 | #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c |
11979 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
11980 | #define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L |
11981 | #define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL |
11982 | #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L |
11983 | #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L |
11984 | #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L |
11985 | #define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L |
11986 | #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L |
11987 | #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L |
11988 | #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
11989 | #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L |
11990 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
11991 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
11992 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
11993 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
11994 | #define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L |
11995 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
11996 | //CB_COLOR3_ATTRIB |
11997 | #define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
11998 | #define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb |
11999 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
12000 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
12001 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
12002 | #define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
12003 | #define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
12004 | #define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
12005 | #define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
12006 | #define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
12007 | #define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
12008 | #define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L |
12009 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
12010 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
12011 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
12012 | #define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
12013 | #define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
12014 | #define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
12015 | #define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
12016 | #define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
12017 | //CB_COLOR3_DCC_CONTROL |
12018 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
12019 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
12020 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
12021 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
12022 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
12023 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
12024 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
12025 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
12026 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
12027 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
12028 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
12029 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
12030 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
12031 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
12032 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
12033 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
12034 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
12035 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
12036 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
12037 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
12038 | //CB_COLOR3_CMASK |
12039 | #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 |
12040 | #define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
12041 | //CB_COLOR3_CMASK_BASE_EXT |
12042 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12043 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12044 | //CB_COLOR3_FMASK |
12045 | #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 |
12046 | #define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
12047 | //CB_COLOR3_FMASK_BASE_EXT |
12048 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12049 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12050 | //CB_COLOR3_CLEAR_WORD0 |
12051 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
12052 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
12053 | //CB_COLOR3_CLEAR_WORD1 |
12054 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
12055 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
12056 | //CB_COLOR3_DCC_BASE |
12057 | #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 |
12058 | #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12059 | //CB_COLOR3_DCC_BASE_EXT |
12060 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
12061 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12062 | //CB_COLOR4_BASE |
12063 | #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 |
12064 | #define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12065 | //CB_COLOR4_BASE_EXT |
12066 | #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 |
12067 | #define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12068 | //CB_COLOR4_ATTRIB2 |
12069 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
12070 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
12071 | #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c |
12072 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
12073 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
12074 | #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
12075 | //CB_COLOR4_VIEW |
12076 | #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 |
12077 | #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd |
12078 | #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 |
12079 | #define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL |
12080 | #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L |
12081 | #define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L |
12082 | //CB_COLOR4_INFO |
12083 | #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 |
12084 | #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 |
12085 | #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 |
12086 | #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb |
12087 | #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd |
12088 | #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe |
12089 | #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf |
12090 | #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 |
12091 | #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
12092 | #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 |
12093 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
12094 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
12095 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
12096 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
12097 | #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c |
12098 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
12099 | #define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L |
12100 | #define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL |
12101 | #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L |
12102 | #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L |
12103 | #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L |
12104 | #define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L |
12105 | #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L |
12106 | #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L |
12107 | #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
12108 | #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L |
12109 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
12110 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
12111 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
12112 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
12113 | #define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L |
12114 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
12115 | //CB_COLOR4_ATTRIB |
12116 | #define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
12117 | #define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb |
12118 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
12119 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
12120 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
12121 | #define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
12122 | #define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
12123 | #define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
12124 | #define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
12125 | #define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
12126 | #define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
12127 | #define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L |
12128 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
12129 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
12130 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
12131 | #define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
12132 | #define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
12133 | #define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
12134 | #define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
12135 | #define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
12136 | //CB_COLOR4_DCC_CONTROL |
12137 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
12138 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
12139 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
12140 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
12141 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
12142 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
12143 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
12144 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
12145 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
12146 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
12147 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
12148 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
12149 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
12150 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
12151 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
12152 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
12153 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
12154 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
12155 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
12156 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
12157 | //CB_COLOR4_CMASK |
12158 | #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 |
12159 | #define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
12160 | //CB_COLOR4_CMASK_BASE_EXT |
12161 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12162 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12163 | //CB_COLOR4_FMASK |
12164 | #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 |
12165 | #define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
12166 | //CB_COLOR4_FMASK_BASE_EXT |
12167 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12168 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12169 | //CB_COLOR4_CLEAR_WORD0 |
12170 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
12171 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
12172 | //CB_COLOR4_CLEAR_WORD1 |
12173 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
12174 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
12175 | //CB_COLOR4_DCC_BASE |
12176 | #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 |
12177 | #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12178 | //CB_COLOR4_DCC_BASE_EXT |
12179 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
12180 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12181 | //CB_COLOR5_BASE |
12182 | #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 |
12183 | #define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12184 | //CB_COLOR5_BASE_EXT |
12185 | #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 |
12186 | #define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12187 | //CB_COLOR5_ATTRIB2 |
12188 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
12189 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
12190 | #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c |
12191 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
12192 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
12193 | #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
12194 | //CB_COLOR5_VIEW |
12195 | #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 |
12196 | #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd |
12197 | #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 |
12198 | #define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL |
12199 | #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L |
12200 | #define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L |
12201 | //CB_COLOR5_INFO |
12202 | #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 |
12203 | #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 |
12204 | #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 |
12205 | #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb |
12206 | #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd |
12207 | #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe |
12208 | #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf |
12209 | #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 |
12210 | #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
12211 | #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 |
12212 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
12213 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
12214 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
12215 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
12216 | #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c |
12217 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
12218 | #define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L |
12219 | #define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL |
12220 | #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L |
12221 | #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L |
12222 | #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L |
12223 | #define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L |
12224 | #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L |
12225 | #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L |
12226 | #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
12227 | #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L |
12228 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
12229 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
12230 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
12231 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
12232 | #define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L |
12233 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
12234 | //CB_COLOR5_ATTRIB |
12235 | #define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
12236 | #define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb |
12237 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
12238 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
12239 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
12240 | #define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
12241 | #define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
12242 | #define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
12243 | #define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
12244 | #define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
12245 | #define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
12246 | #define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L |
12247 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
12248 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
12249 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
12250 | #define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
12251 | #define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
12252 | #define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
12253 | #define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
12254 | #define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
12255 | //CB_COLOR5_DCC_CONTROL |
12256 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
12257 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
12258 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
12259 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
12260 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
12261 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
12262 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
12263 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
12264 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
12265 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
12266 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
12267 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
12268 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
12269 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
12270 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
12271 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
12272 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
12273 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
12274 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
12275 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
12276 | //CB_COLOR5_CMASK |
12277 | #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 |
12278 | #define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
12279 | //CB_COLOR5_CMASK_BASE_EXT |
12280 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12281 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12282 | //CB_COLOR5_FMASK |
12283 | #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 |
12284 | #define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
12285 | //CB_COLOR5_FMASK_BASE_EXT |
12286 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12287 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12288 | //CB_COLOR5_CLEAR_WORD0 |
12289 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
12290 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
12291 | //CB_COLOR5_CLEAR_WORD1 |
12292 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
12293 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
12294 | //CB_COLOR5_DCC_BASE |
12295 | #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 |
12296 | #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12297 | //CB_COLOR5_DCC_BASE_EXT |
12298 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
12299 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12300 | //CB_COLOR6_BASE |
12301 | #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 |
12302 | #define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12303 | //CB_COLOR6_BASE_EXT |
12304 | #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 |
12305 | #define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12306 | //CB_COLOR6_ATTRIB2 |
12307 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
12308 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
12309 | #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c |
12310 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
12311 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
12312 | #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
12313 | //CB_COLOR6_VIEW |
12314 | #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 |
12315 | #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd |
12316 | #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 |
12317 | #define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL |
12318 | #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L |
12319 | #define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L |
12320 | //CB_COLOR6_INFO |
12321 | #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 |
12322 | #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 |
12323 | #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 |
12324 | #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb |
12325 | #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd |
12326 | #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe |
12327 | #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf |
12328 | #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 |
12329 | #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
12330 | #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 |
12331 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
12332 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
12333 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
12334 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
12335 | #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c |
12336 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
12337 | #define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L |
12338 | #define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL |
12339 | #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L |
12340 | #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L |
12341 | #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L |
12342 | #define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L |
12343 | #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L |
12344 | #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L |
12345 | #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
12346 | #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L |
12347 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
12348 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
12349 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
12350 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
12351 | #define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L |
12352 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
12353 | //CB_COLOR6_ATTRIB |
12354 | #define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
12355 | #define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb |
12356 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
12357 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
12358 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
12359 | #define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
12360 | #define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
12361 | #define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
12362 | #define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
12363 | #define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
12364 | #define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
12365 | #define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L |
12366 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
12367 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
12368 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
12369 | #define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
12370 | #define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
12371 | #define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
12372 | #define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
12373 | #define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
12374 | //CB_COLOR6_DCC_CONTROL |
12375 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
12376 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
12377 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
12378 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
12379 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
12380 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
12381 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
12382 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
12383 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
12384 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
12385 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
12386 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
12387 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
12388 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
12389 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
12390 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
12391 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
12392 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
12393 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
12394 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
12395 | //CB_COLOR6_CMASK |
12396 | #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 |
12397 | #define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
12398 | //CB_COLOR6_CMASK_BASE_EXT |
12399 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12400 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12401 | //CB_COLOR6_FMASK |
12402 | #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 |
12403 | #define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
12404 | //CB_COLOR6_FMASK_BASE_EXT |
12405 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12406 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12407 | //CB_COLOR6_CLEAR_WORD0 |
12408 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
12409 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
12410 | //CB_COLOR6_CLEAR_WORD1 |
12411 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
12412 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
12413 | //CB_COLOR6_DCC_BASE |
12414 | #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 |
12415 | #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12416 | //CB_COLOR6_DCC_BASE_EXT |
12417 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
12418 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12419 | //CB_COLOR7_BASE |
12420 | #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 |
12421 | #define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12422 | //CB_COLOR7_BASE_EXT |
12423 | #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 |
12424 | #define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12425 | //CB_COLOR7_ATTRIB2 |
12426 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
12427 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
12428 | #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c |
12429 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
12430 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
12431 | #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
12432 | //CB_COLOR7_VIEW |
12433 | #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 |
12434 | #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd |
12435 | #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 |
12436 | #define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL |
12437 | #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L |
12438 | #define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L |
12439 | //CB_COLOR7_INFO |
12440 | #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 |
12441 | #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 |
12442 | #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 |
12443 | #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb |
12444 | #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd |
12445 | #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe |
12446 | #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf |
12447 | #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 |
12448 | #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
12449 | #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 |
12450 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
12451 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
12452 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
12453 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
12454 | #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c |
12455 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
12456 | #define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L |
12457 | #define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL |
12458 | #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L |
12459 | #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L |
12460 | #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L |
12461 | #define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L |
12462 | #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L |
12463 | #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L |
12464 | #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
12465 | #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L |
12466 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
12467 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
12468 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
12469 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
12470 | #define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L |
12471 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
12472 | //CB_COLOR7_ATTRIB |
12473 | #define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 |
12474 | #define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb |
12475 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
12476 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
12477 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
12478 | #define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 |
12479 | #define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 |
12480 | #define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c |
12481 | #define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e |
12482 | #define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f |
12483 | #define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL |
12484 | #define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L |
12485 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
12486 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
12487 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
12488 | #define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L |
12489 | #define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L |
12490 | #define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L |
12491 | #define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L |
12492 | #define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L |
12493 | //CB_COLOR7_DCC_CONTROL |
12494 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
12495 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
12496 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
12497 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
12498 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
12499 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
12500 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
12501 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
12502 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
12503 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
12504 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
12505 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
12506 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
12507 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
12508 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
12509 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
12510 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
12511 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
12512 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
12513 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
12514 | //CB_COLOR7_CMASK |
12515 | #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 |
12516 | #define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
12517 | //CB_COLOR7_CMASK_BASE_EXT |
12518 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12519 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12520 | //CB_COLOR7_FMASK |
12521 | #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 |
12522 | #define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
12523 | //CB_COLOR7_FMASK_BASE_EXT |
12524 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
12525 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12526 | //CB_COLOR7_CLEAR_WORD0 |
12527 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
12528 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
12529 | //CB_COLOR7_CLEAR_WORD1 |
12530 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
12531 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
12532 | //CB_COLOR7_DCC_BASE |
12533 | #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 |
12534 | #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
12535 | //CB_COLOR7_DCC_BASE_EXT |
12536 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
12537 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
12538 | |
12539 | |
12540 | // addressBlock: gc_gfxudec |
12541 | //CP_EOP_DONE_ADDR_LO |
12542 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
12543 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
12544 | //CP_EOP_DONE_ADDR_HI |
12545 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
12546 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
12547 | //CP_EOP_DONE_DATA_LO |
12548 | #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 |
12549 | #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
12550 | //CP_EOP_DONE_DATA_HI |
12551 | #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 |
12552 | #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
12553 | //CP_EOP_LAST_FENCE_LO |
12554 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 |
12555 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL |
12556 | //CP_EOP_LAST_FENCE_HI |
12557 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 |
12558 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL |
12559 | //CP_STREAM_OUT_ADDR_LO |
12560 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 |
12561 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL |
12562 | //CP_STREAM_OUT_ADDR_HI |
12563 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 |
12564 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL |
12565 | //CP_NUM_PRIM_WRITTEN_COUNT0_LO |
12566 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 |
12567 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL |
12568 | //CP_NUM_PRIM_WRITTEN_COUNT0_HI |
12569 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 |
12570 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL |
12571 | //CP_NUM_PRIM_NEEDED_COUNT0_LO |
12572 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 |
12573 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL |
12574 | //CP_NUM_PRIM_NEEDED_COUNT0_HI |
12575 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 |
12576 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL |
12577 | //CP_NUM_PRIM_WRITTEN_COUNT1_LO |
12578 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 |
12579 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL |
12580 | //CP_NUM_PRIM_WRITTEN_COUNT1_HI |
12581 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 |
12582 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL |
12583 | //CP_NUM_PRIM_NEEDED_COUNT1_LO |
12584 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 |
12585 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL |
12586 | //CP_NUM_PRIM_NEEDED_COUNT1_HI |
12587 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 |
12588 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL |
12589 | //CP_NUM_PRIM_WRITTEN_COUNT2_LO |
12590 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 |
12591 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL |
12592 | //CP_NUM_PRIM_WRITTEN_COUNT2_HI |
12593 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 |
12594 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL |
12595 | //CP_NUM_PRIM_NEEDED_COUNT2_LO |
12596 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 |
12597 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL |
12598 | //CP_NUM_PRIM_NEEDED_COUNT2_HI |
12599 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 |
12600 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL |
12601 | //CP_NUM_PRIM_WRITTEN_COUNT3_LO |
12602 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 |
12603 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL |
12604 | //CP_NUM_PRIM_WRITTEN_COUNT3_HI |
12605 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 |
12606 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL |
12607 | //CP_NUM_PRIM_NEEDED_COUNT3_LO |
12608 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 |
12609 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL |
12610 | //CP_NUM_PRIM_NEEDED_COUNT3_HI |
12611 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 |
12612 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL |
12613 | //CP_PIPE_STATS_ADDR_LO |
12614 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 |
12615 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL |
12616 | //CP_PIPE_STATS_ADDR_HI |
12617 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 |
12618 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL |
12619 | //CP_VGT_IAVERT_COUNT_LO |
12620 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 |
12621 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL |
12622 | //CP_VGT_IAVERT_COUNT_HI |
12623 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 |
12624 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL |
12625 | //CP_VGT_IAPRIM_COUNT_LO |
12626 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 |
12627 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
12628 | //CP_VGT_IAPRIM_COUNT_HI |
12629 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 |
12630 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
12631 | //CP_VGT_GSPRIM_COUNT_LO |
12632 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 |
12633 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
12634 | //CP_VGT_GSPRIM_COUNT_HI |
12635 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 |
12636 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
12637 | //CP_VGT_VSINVOC_COUNT_LO |
12638 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 |
12639 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12640 | //CP_VGT_VSINVOC_COUNT_HI |
12641 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 |
12642 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12643 | //CP_VGT_GSINVOC_COUNT_LO |
12644 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 |
12645 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12646 | //CP_VGT_GSINVOC_COUNT_HI |
12647 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 |
12648 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12649 | //CP_VGT_HSINVOC_COUNT_LO |
12650 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 |
12651 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12652 | //CP_VGT_HSINVOC_COUNT_HI |
12653 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 |
12654 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12655 | //CP_VGT_DSINVOC_COUNT_LO |
12656 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 |
12657 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12658 | //CP_VGT_DSINVOC_COUNT_HI |
12659 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 |
12660 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12661 | //CP_PA_CINVOC_COUNT_LO |
12662 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 |
12663 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12664 | //CP_PA_CINVOC_COUNT_HI |
12665 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 |
12666 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12667 | //CP_PA_CPRIM_COUNT_LO |
12668 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 |
12669 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
12670 | //CP_PA_CPRIM_COUNT_HI |
12671 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 |
12672 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
12673 | //CP_SC_PSINVOC_COUNT0_LO |
12674 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 |
12675 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL |
12676 | //CP_SC_PSINVOC_COUNT0_HI |
12677 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 |
12678 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL |
12679 | //CP_SC_PSINVOC_COUNT1_LO |
12680 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 |
12681 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL |
12682 | //CP_SC_PSINVOC_COUNT1_HI |
12683 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 |
12684 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL |
12685 | //CP_VGT_CSINVOC_COUNT_LO |
12686 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 |
12687 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
12688 | //CP_VGT_CSINVOC_COUNT_HI |
12689 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 |
12690 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
12691 | //CP_PIPE_STATS_CONTROL |
12692 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 |
12693 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L |
12694 | //CP_STREAM_OUT_CONTROL |
12695 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 |
12696 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L |
12697 | //CP_STRMOUT_CNTL |
12698 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 |
12699 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L |
12700 | //SCRATCH_REG0 |
12701 | #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
12702 | #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
12703 | //SCRATCH_REG1 |
12704 | #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
12705 | #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
12706 | //SCRATCH_REG2 |
12707 | #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
12708 | #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
12709 | //SCRATCH_REG3 |
12710 | #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
12711 | #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
12712 | //SCRATCH_REG4 |
12713 | #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
12714 | #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
12715 | //SCRATCH_REG5 |
12716 | #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
12717 | #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
12718 | //SCRATCH_REG6 |
12719 | #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
12720 | #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
12721 | //SCRATCH_REG7 |
12722 | #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
12723 | #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
12724 | //CP_APPEND_DATA_HI |
12725 | #define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 |
12726 | #define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL |
12727 | //CP_APPEND_LAST_CS_FENCE_HI |
12728 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
12729 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
12730 | //CP_APPEND_LAST_PS_FENCE_HI |
12731 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
12732 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
12733 | //SCRATCH_UMSK |
12734 | #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 |
12735 | #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 |
12736 | #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL |
12737 | #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L |
12738 | //SCRATCH_ADDR |
12739 | #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 |
12740 | #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL |
12741 | //CP_PFP_ATOMIC_PREOP_LO |
12742 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
12743 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
12744 | //CP_PFP_ATOMIC_PREOP_HI |
12745 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
12746 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
12747 | //CP_PFP_GDS_ATOMIC0_PREOP_LO |
12748 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
12749 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
12750 | //CP_PFP_GDS_ATOMIC0_PREOP_HI |
12751 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
12752 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
12753 | //CP_PFP_GDS_ATOMIC1_PREOP_LO |
12754 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
12755 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
12756 | //CP_PFP_GDS_ATOMIC1_PREOP_HI |
12757 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
12758 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
12759 | //CP_APPEND_ADDR_LO |
12760 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 |
12761 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL |
12762 | //CP_APPEND_ADDR_HI |
12763 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 |
12764 | #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 |
12765 | #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 |
12766 | #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d |
12767 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL |
12768 | #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L |
12769 | #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L |
12770 | #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L |
12771 | //CP_APPEND_DATA_LO |
12772 | #define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 |
12773 | #define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL |
12774 | //CP_APPEND_LAST_CS_FENCE_LO |
12775 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
12776 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
12777 | //CP_APPEND_LAST_PS_FENCE_LO |
12778 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
12779 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
12780 | //CP_ATOMIC_PREOP_LO |
12781 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
12782 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
12783 | //CP_ME_ATOMIC_PREOP_LO |
12784 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
12785 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
12786 | //CP_ATOMIC_PREOP_HI |
12787 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
12788 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
12789 | //CP_ME_ATOMIC_PREOP_HI |
12790 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
12791 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
12792 | //CP_GDS_ATOMIC0_PREOP_LO |
12793 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
12794 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
12795 | //CP_ME_GDS_ATOMIC0_PREOP_LO |
12796 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
12797 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
12798 | //CP_GDS_ATOMIC0_PREOP_HI |
12799 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
12800 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
12801 | //CP_ME_GDS_ATOMIC0_PREOP_HI |
12802 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
12803 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
12804 | //CP_GDS_ATOMIC1_PREOP_LO |
12805 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
12806 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
12807 | //CP_ME_GDS_ATOMIC1_PREOP_LO |
12808 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
12809 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
12810 | //CP_GDS_ATOMIC1_PREOP_HI |
12811 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
12812 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
12813 | //CP_ME_GDS_ATOMIC1_PREOP_HI |
12814 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
12815 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
12816 | //CP_ME_MC_WADDR_LO |
12817 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 |
12818 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL |
12819 | //CP_ME_MC_WADDR_HI |
12820 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 |
12821 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 |
12822 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL |
12823 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L |
12824 | //CP_ME_MC_WDATA_LO |
12825 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 |
12826 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL |
12827 | //CP_ME_MC_WDATA_HI |
12828 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 |
12829 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL |
12830 | //CP_ME_MC_RADDR_LO |
12831 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 |
12832 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL |
12833 | //CP_ME_MC_RADDR_HI |
12834 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 |
12835 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 |
12836 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL |
12837 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L |
12838 | //CP_SEM_WAIT_TIMER |
12839 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 |
12840 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL |
12841 | //CP_SIG_SEM_ADDR_LO |
12842 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 |
12843 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
12844 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L |
12845 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
12846 | //CP_SIG_SEM_ADDR_HI |
12847 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
12848 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
12849 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
12850 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
12851 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
12852 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
12853 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
12854 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
12855 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
12856 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
12857 | //CP_WAIT_REG_MEM_TIMEOUT |
12858 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 |
12859 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL |
12860 | //CP_WAIT_SEM_ADDR_LO |
12861 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 |
12862 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
12863 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L |
12864 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
12865 | //CP_WAIT_SEM_ADDR_HI |
12866 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
12867 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
12868 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
12869 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
12870 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
12871 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
12872 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
12873 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
12874 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
12875 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
12876 | //CP_DMA_PFP_CONTROL |
12877 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
12878 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
12879 | #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 |
12880 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
12881 | #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d |
12882 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
12883 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L |
12884 | #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L |
12885 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L |
12886 | #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L |
12887 | //CP_DMA_ME_CONTROL |
12888 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
12889 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
12890 | #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 |
12891 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
12892 | #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d |
12893 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
12894 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L |
12895 | #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L |
12896 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L |
12897 | #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L |
12898 | //CP_COHER_BASE_HI |
12899 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
12900 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
12901 | //CP_COHER_START_DELAY |
12902 | #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 |
12903 | #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL |
12904 | //CP_COHER_CNTL |
12905 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 |
12906 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 |
12907 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 |
12908 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf |
12909 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 |
12910 | #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 |
12911 | #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 |
12912 | #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 |
12913 | #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a |
12914 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b |
12915 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c |
12916 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d |
12917 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e |
12918 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L |
12919 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L |
12920 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L |
12921 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L |
12922 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L |
12923 | #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L |
12924 | #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L |
12925 | #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L |
12926 | #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L |
12927 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L |
12928 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L |
12929 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L |
12930 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L |
12931 | //CP_COHER_SIZE |
12932 | #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
12933 | #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
12934 | //CP_COHER_BASE |
12935 | #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
12936 | #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
12937 | //CP_COHER_STATUS |
12938 | #define CP_COHER_STATUS__MEID__SHIFT 0x18 |
12939 | #define CP_COHER_STATUS__STATUS__SHIFT 0x1f |
12940 | #define CP_COHER_STATUS__MEID_MASK 0x03000000L |
12941 | #define CP_COHER_STATUS__STATUS_MASK 0x80000000L |
12942 | //CP_DMA_ME_SRC_ADDR |
12943 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
12944 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
12945 | //CP_DMA_ME_SRC_ADDR_HI |
12946 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
12947 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
12948 | //CP_DMA_ME_DST_ADDR |
12949 | #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 |
12950 | #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
12951 | //CP_DMA_ME_DST_ADDR_HI |
12952 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
12953 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
12954 | //CP_DMA_ME_COMMAND |
12955 | #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 |
12956 | #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a |
12957 | #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b |
12958 | #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c |
12959 | #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d |
12960 | #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e |
12961 | #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f |
12962 | #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
12963 | #define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L |
12964 | #define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L |
12965 | #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L |
12966 | #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L |
12967 | #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L |
12968 | #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L |
12969 | //CP_DMA_PFP_SRC_ADDR |
12970 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
12971 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
12972 | //CP_DMA_PFP_SRC_ADDR_HI |
12973 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
12974 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
12975 | //CP_DMA_PFP_DST_ADDR |
12976 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 |
12977 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
12978 | //CP_DMA_PFP_DST_ADDR_HI |
12979 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
12980 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
12981 | //CP_DMA_PFP_COMMAND |
12982 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 |
12983 | #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a |
12984 | #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b |
12985 | #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c |
12986 | #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d |
12987 | #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e |
12988 | #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f |
12989 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
12990 | #define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L |
12991 | #define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L |
12992 | #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L |
12993 | #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L |
12994 | #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L |
12995 | #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L |
12996 | //CP_DMA_CNTL |
12997 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 |
12998 | #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 |
12999 | #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 |
13000 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c |
13001 | #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d |
13002 | #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e |
13003 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L |
13004 | #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L |
13005 | #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L |
13006 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L |
13007 | #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L |
13008 | #define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L |
13009 | //CP_DMA_READ_TAGS |
13010 | #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 |
13011 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c |
13012 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL |
13013 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L |
13014 | //CP_COHER_SIZE_HI |
13015 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
13016 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
13017 | //CP_PFP_IB_CONTROL |
13018 | #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 |
13019 | #define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL |
13020 | //CP_PFP_LOAD_CONTROL |
13021 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 |
13022 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 |
13023 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 |
13024 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 |
13025 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L |
13026 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L |
13027 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L |
13028 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L |
13029 | //CP_SCRATCH_INDEX |
13030 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
13031 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL |
13032 | //CP_SCRATCH_DATA |
13033 | #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
13034 | #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
13035 | //CP_RB_OFFSET |
13036 | #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 |
13037 | #define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
13038 | //CP_IB2_OFFSET |
13039 | #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
13040 | #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
13041 | //CP_IB2_PREAMBLE_BEGIN |
13042 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 |
13043 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
13044 | //CP_IB2_PREAMBLE_END |
13045 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 |
13046 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL |
13047 | //CP_CE_IB1_OFFSET |
13048 | #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 |
13049 | #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL |
13050 | //CP_CE_IB2_OFFSET |
13051 | #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
13052 | #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
13053 | //CP_CE_COUNTER |
13054 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 |
13055 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
13056 | //CP_CE_RB_OFFSET |
13057 | #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 |
13058 | #define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
13059 | //CP_CE_INIT_CMD_BUFSZ |
13060 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 |
13061 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL |
13062 | //CP_CE_IB1_CMD_BUFSZ |
13063 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 |
13064 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL |
13065 | //CP_CE_IB2_CMD_BUFSZ |
13066 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
13067 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
13068 | //CP_IB2_CMD_BUFSZ |
13069 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
13070 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
13071 | //CP_ST_CMD_BUFSZ |
13072 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 |
13073 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL |
13074 | //CP_CE_INIT_BASE_LO |
13075 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 |
13076 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L |
13077 | //CP_CE_INIT_BASE_HI |
13078 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 |
13079 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL |
13080 | //CP_CE_INIT_BUFSZ |
13081 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 |
13082 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL |
13083 | //CP_CE_IB1_BASE_LO |
13084 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
13085 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
13086 | //CP_CE_IB1_BASE_HI |
13087 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
13088 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
13089 | //CP_CE_IB1_BUFSZ |
13090 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
13091 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
13092 | //CP_CE_IB2_BASE_LO |
13093 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
13094 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
13095 | //CP_CE_IB2_BASE_HI |
13096 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
13097 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
13098 | //CP_CE_IB2_BUFSZ |
13099 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
13100 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
13101 | //CP_IB2_BASE_LO |
13102 | #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
13103 | #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
13104 | //CP_IB2_BASE_HI |
13105 | #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
13106 | #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
13107 | //CP_IB2_BUFSZ |
13108 | #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
13109 | #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
13110 | //CP_ST_BASE_LO |
13111 | #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 |
13112 | #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL |
13113 | //CP_ST_BASE_HI |
13114 | #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 |
13115 | #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL |
13116 | //CP_ST_BUFSZ |
13117 | #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 |
13118 | #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL |
13119 | //CP_EOP_DONE_EVENT_CNTL |
13120 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 |
13121 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc |
13122 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 |
13123 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c |
13124 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL |
13125 | #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L |
13126 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L |
13127 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L |
13128 | //CP_EOP_DONE_DATA_CNTL |
13129 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 |
13130 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 |
13131 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d |
13132 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L |
13133 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L |
13134 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L |
13135 | //CP_EOP_DONE_CNTX_ID |
13136 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 |
13137 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
13138 | //CP_PFP_COMPLETION_STATUS |
13139 | #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
13140 | #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
13141 | //CP_CE_COMPLETION_STATUS |
13142 | #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
13143 | #define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
13144 | //CP_PRED_NOT_VISIBLE |
13145 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 |
13146 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L |
13147 | //CP_PFP_METADATA_BASE_ADDR |
13148 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
13149 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13150 | //CP_PFP_METADATA_BASE_ADDR_HI |
13151 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13152 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13153 | //CP_CE_METADATA_BASE_ADDR |
13154 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
13155 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13156 | //CP_CE_METADATA_BASE_ADDR_HI |
13157 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13158 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13159 | //CP_DRAW_INDX_INDR_ADDR |
13160 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
13161 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13162 | //CP_DRAW_INDX_INDR_ADDR_HI |
13163 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13164 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13165 | //CP_DISPATCH_INDR_ADDR |
13166 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
13167 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13168 | //CP_DISPATCH_INDR_ADDR_HI |
13169 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13170 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13171 | //CP_INDEX_BASE_ADDR |
13172 | #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
13173 | #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13174 | //CP_INDEX_BASE_ADDR_HI |
13175 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13176 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13177 | //CP_INDEX_TYPE |
13178 | #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
13179 | #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
13180 | //CP_GDS_BKUP_ADDR |
13181 | #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 |
13182 | #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
13183 | //CP_GDS_BKUP_ADDR_HI |
13184 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 |
13185 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
13186 | //CP_SAMPLE_STATUS |
13187 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 |
13188 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 |
13189 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 |
13190 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 |
13191 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 |
13192 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 |
13193 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 |
13194 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 |
13195 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L |
13196 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L |
13197 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L |
13198 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L |
13199 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L |
13200 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L |
13201 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L |
13202 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L |
13203 | //CP_ME_COHER_CNTL |
13204 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 |
13205 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 |
13206 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 |
13207 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 |
13208 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 |
13209 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 |
13210 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa |
13211 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb |
13212 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc |
13213 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd |
13214 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe |
13215 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 |
13216 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 |
13217 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L |
13218 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L |
13219 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L |
13220 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L |
13221 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L |
13222 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L |
13223 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L |
13224 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L |
13225 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L |
13226 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L |
13227 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L |
13228 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L |
13229 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L |
13230 | //CP_ME_COHER_SIZE |
13231 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
13232 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
13233 | //CP_ME_COHER_SIZE_HI |
13234 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
13235 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
13236 | //CP_ME_COHER_BASE |
13237 | #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
13238 | #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
13239 | //CP_ME_COHER_BASE_HI |
13240 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
13241 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
13242 | //CP_ME_COHER_STATUS |
13243 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 |
13244 | #define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f |
13245 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL |
13246 | #define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L |
13247 | //RLC_GPM_PERF_COUNT_0 |
13248 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 |
13249 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 |
13250 | #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 |
13251 | #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc |
13252 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 |
13253 | #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 |
13254 | #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 |
13255 | #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 |
13256 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL |
13257 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L |
13258 | #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L |
13259 | #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L |
13260 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L |
13261 | #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L |
13262 | #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L |
13263 | #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L |
13264 | //RLC_GPM_PERF_COUNT_1 |
13265 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 |
13266 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 |
13267 | #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 |
13268 | #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc |
13269 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 |
13270 | #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 |
13271 | #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 |
13272 | #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 |
13273 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL |
13274 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L |
13275 | #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L |
13276 | #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L |
13277 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L |
13278 | #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L |
13279 | #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L |
13280 | #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L |
13281 | //GRBM_GFX_INDEX |
13282 | #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 |
13283 | #define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 |
13284 | #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 |
13285 | #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d |
13286 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
13287 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f |
13288 | #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL |
13289 | #define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L |
13290 | #define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L |
13291 | #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L |
13292 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
13293 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L |
13294 | //VGT_GSVS_RING_SIZE |
13295 | #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
13296 | #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL |
13297 | //VGT_PRIMITIVE_TYPE |
13298 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
13299 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
13300 | //VGT_INDEX_TYPE |
13301 | #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
13302 | #define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 |
13303 | #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
13304 | #define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L |
13305 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_0 |
13306 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 |
13307 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
13308 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_1 |
13309 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 |
13310 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
13311 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_2 |
13312 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 |
13313 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
13314 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_3 |
13315 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 |
13316 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
13317 | //VGT_MAX_VTX_INDX |
13318 | #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
13319 | #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
13320 | //VGT_MIN_VTX_INDX |
13321 | #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
13322 | #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
13323 | //VGT_INDX_OFFSET |
13324 | #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
13325 | #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
13326 | //VGT_MULTI_PRIM_IB_RESET_EN |
13327 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
13328 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
13329 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
13330 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
13331 | //VGT_NUM_INDICES |
13332 | #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 |
13333 | #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL |
13334 | //VGT_NUM_INSTANCES |
13335 | #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
13336 | #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
13337 | //VGT_TF_RING_SIZE |
13338 | #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 |
13339 | #define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL |
13340 | //VGT_HS_OFFCHIP_PARAM |
13341 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 |
13342 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 |
13343 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL |
13344 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L |
13345 | //VGT_TF_MEMORY_BASE |
13346 | #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 |
13347 | #define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL |
13348 | //VGT_TF_MEMORY_BASE_HI |
13349 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 |
13350 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL |
13351 | //WD_POS_BUF_BASE |
13352 | #define WD_POS_BUF_BASE__BASE__SHIFT 0x0 |
13353 | #define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
13354 | //WD_POS_BUF_BASE_HI |
13355 | #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
13356 | #define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
13357 | //WD_CNTL_SB_BUF_BASE |
13358 | #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 |
13359 | #define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
13360 | //WD_CNTL_SB_BUF_BASE_HI |
13361 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
13362 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
13363 | //WD_INDEX_BUF_BASE |
13364 | #define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 |
13365 | #define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
13366 | //WD_INDEX_BUF_BASE_HI |
13367 | #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
13368 | #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
13369 | //IA_MULTI_VGT_PARAM |
13370 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 |
13371 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 |
13372 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 |
13373 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 |
13374 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 |
13375 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 |
13376 | #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 |
13377 | #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 |
13378 | #define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 |
13379 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
13380 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L |
13381 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L |
13382 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L |
13383 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L |
13384 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L |
13385 | #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L |
13386 | #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L |
13387 | #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L |
13388 | //VGT_INSTANCE_BASE_ID |
13389 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 |
13390 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL |
13391 | //PA_SU_LINE_STIPPLE_VALUE |
13392 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 |
13393 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL |
13394 | //PA_SC_LINE_STIPPLE_STATE |
13395 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 |
13396 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 |
13397 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL |
13398 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L |
13399 | //PA_SC_SCREEN_EXTENT_MIN_0 |
13400 | #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 |
13401 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 |
13402 | #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL |
13403 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L |
13404 | //PA_SC_SCREEN_EXTENT_MAX_0 |
13405 | #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 |
13406 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 |
13407 | #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL |
13408 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L |
13409 | //PA_SC_SCREEN_EXTENT_MIN_1 |
13410 | #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 |
13411 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 |
13412 | #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL |
13413 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L |
13414 | //PA_SC_SCREEN_EXTENT_MAX_1 |
13415 | #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 |
13416 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 |
13417 | #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL |
13418 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L |
13419 | //PA_SC_P3D_TRAP_SCREEN_HV_EN |
13420 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
13421 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
13422 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
13423 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
13424 | //PA_SC_P3D_TRAP_SCREEN_H |
13425 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
13426 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
13427 | //PA_SC_P3D_TRAP_SCREEN_V |
13428 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
13429 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
13430 | //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE |
13431 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
13432 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
13433 | //PA_SC_P3D_TRAP_SCREEN_COUNT |
13434 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
13435 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
13436 | //PA_SC_HP3D_TRAP_SCREEN_HV_EN |
13437 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
13438 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
13439 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
13440 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
13441 | //PA_SC_HP3D_TRAP_SCREEN_H |
13442 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
13443 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
13444 | //PA_SC_HP3D_TRAP_SCREEN_V |
13445 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
13446 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
13447 | //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE |
13448 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
13449 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
13450 | //PA_SC_HP3D_TRAP_SCREEN_COUNT |
13451 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
13452 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
13453 | //PA_SC_TRAP_SCREEN_HV_EN |
13454 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
13455 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
13456 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
13457 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
13458 | //PA_SC_TRAP_SCREEN_H |
13459 | #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
13460 | #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
13461 | //PA_SC_TRAP_SCREEN_V |
13462 | #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
13463 | #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
13464 | //PA_SC_TRAP_SCREEN_OCCURRENCE |
13465 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
13466 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
13467 | //PA_SC_TRAP_SCREEN_COUNT |
13468 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
13469 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
13470 | //PA_STATE_STEREO_X |
13471 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 |
13472 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL |
13473 | //SQ_THREAD_TRACE_BASE |
13474 | #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 |
13475 | #define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL |
13476 | //SQ_THREAD_TRACE_SIZE |
13477 | #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 |
13478 | #define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL |
13479 | //SQ_THREAD_TRACE_MASK |
13480 | #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 |
13481 | #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 |
13482 | #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 |
13483 | #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 |
13484 | #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc |
13485 | #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe |
13486 | #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf |
13487 | #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL |
13488 | #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L |
13489 | #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L |
13490 | #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L |
13491 | #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L |
13492 | #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L |
13493 | #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L |
13494 | //SQ_THREAD_TRACE_TOKEN_MASK |
13495 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 |
13496 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 |
13497 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 |
13498 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL |
13499 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L |
13500 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L |
13501 | //SQ_THREAD_TRACE_PERF_MASK |
13502 | #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 |
13503 | #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 |
13504 | #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL |
13505 | #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L |
13506 | //SQ_THREAD_TRACE_CTRL |
13507 | #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f |
13508 | #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L |
13509 | //SQ_THREAD_TRACE_MODE |
13510 | #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 |
13511 | #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 |
13512 | #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 |
13513 | #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 |
13514 | #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc |
13515 | #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf |
13516 | #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 |
13517 | #define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 |
13518 | #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 |
13519 | #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 |
13520 | #define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a |
13521 | #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b |
13522 | #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d |
13523 | #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e |
13524 | #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f |
13525 | #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L |
13526 | #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L |
13527 | #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L |
13528 | #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L |
13529 | #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L |
13530 | #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L |
13531 | #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L |
13532 | #define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L |
13533 | #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L |
13534 | #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L |
13535 | #define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L |
13536 | #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L |
13537 | #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L |
13538 | #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L |
13539 | #define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L |
13540 | //SQ_THREAD_TRACE_BASE2 |
13541 | #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 |
13542 | #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL |
13543 | //SQ_THREAD_TRACE_TOKEN_MASK2 |
13544 | #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 |
13545 | #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL |
13546 | //SQ_THREAD_TRACE_WPTR |
13547 | #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 |
13548 | #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e |
13549 | #define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL |
13550 | #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L |
13551 | //SQ_THREAD_TRACE_STATUS |
13552 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 |
13553 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 |
13554 | #define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c |
13555 | #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d |
13556 | #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e |
13557 | #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f |
13558 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL |
13559 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L |
13560 | #define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L |
13561 | #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L |
13562 | #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L |
13563 | #define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L |
13564 | //SQ_THREAD_TRACE_HIWATER |
13565 | #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 |
13566 | #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L |
13567 | //SQ_THREAD_TRACE_CNTR |
13568 | #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 |
13569 | #define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL |
13570 | //SQ_THREAD_TRACE_USERDATA_0 |
13571 | #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 |
13572 | #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL |
13573 | //SQ_THREAD_TRACE_USERDATA_1 |
13574 | #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 |
13575 | #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL |
13576 | //SQ_THREAD_TRACE_USERDATA_2 |
13577 | #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 |
13578 | #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL |
13579 | //SQ_THREAD_TRACE_USERDATA_3 |
13580 | #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 |
13581 | #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL |
13582 | //SQC_CACHES |
13583 | #define SQC_CACHES__TARGET_INST__SHIFT 0x0 |
13584 | #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 |
13585 | #define SQC_CACHES__INVALIDATE__SHIFT 0x2 |
13586 | #define SQC_CACHES__WRITEBACK__SHIFT 0x3 |
13587 | #define SQC_CACHES__VOL__SHIFT 0x4 |
13588 | #define SQC_CACHES__COMPLETE__SHIFT 0x10 |
13589 | #define SQC_CACHES__TARGET_INST_MASK 0x00000001L |
13590 | #define SQC_CACHES__TARGET_DATA_MASK 0x00000002L |
13591 | #define SQC_CACHES__INVALIDATE_MASK 0x00000004L |
13592 | #define SQC_CACHES__WRITEBACK_MASK 0x00000008L |
13593 | #define SQC_CACHES__VOL_MASK 0x00000010L |
13594 | #define SQC_CACHES__COMPLETE_MASK 0x00010000L |
13595 | //SQC_WRITEBACK |
13596 | #define SQC_WRITEBACK__DWB__SHIFT 0x0 |
13597 | #define SQC_WRITEBACK__DIRTY__SHIFT 0x1 |
13598 | #define SQC_WRITEBACK__DWB_MASK 0x00000001L |
13599 | #define SQC_WRITEBACK__DIRTY_MASK 0x00000002L |
13600 | //DB_OCCLUSION_COUNT0_LOW |
13601 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 |
13602 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
13603 | //DB_OCCLUSION_COUNT0_HI |
13604 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 |
13605 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL |
13606 | //DB_OCCLUSION_COUNT1_LOW |
13607 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 |
13608 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
13609 | //DB_OCCLUSION_COUNT1_HI |
13610 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 |
13611 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL |
13612 | //DB_OCCLUSION_COUNT2_LOW |
13613 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 |
13614 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
13615 | //DB_OCCLUSION_COUNT2_HI |
13616 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 |
13617 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL |
13618 | //DB_OCCLUSION_COUNT3_LOW |
13619 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 |
13620 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
13621 | //DB_OCCLUSION_COUNT3_HI |
13622 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 |
13623 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL |
13624 | //DB_ZPASS_COUNT_LOW |
13625 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 |
13626 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
13627 | //DB_ZPASS_COUNT_HI |
13628 | #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 |
13629 | #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL |
13630 | //GDS_RD_ADDR |
13631 | #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 |
13632 | #define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL |
13633 | //GDS_RD_DATA |
13634 | #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 |
13635 | #define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL |
13636 | //GDS_RD_BURST_ADDR |
13637 | #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 |
13638 | #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL |
13639 | //GDS_RD_BURST_COUNT |
13640 | #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 |
13641 | #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL |
13642 | //GDS_RD_BURST_DATA |
13643 | #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 |
13644 | #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL |
13645 | //GDS_WR_ADDR |
13646 | #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 |
13647 | #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
13648 | //GDS_WR_DATA |
13649 | #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 |
13650 | #define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
13651 | //GDS_WR_BURST_ADDR |
13652 | #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 |
13653 | #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
13654 | //GDS_WR_BURST_DATA |
13655 | #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 |
13656 | #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
13657 | //GDS_WRITE_COMPLETE |
13658 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 |
13659 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL |
13660 | //GDS_ATOM_CNTL |
13661 | #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 |
13662 | #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 |
13663 | #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 |
13664 | #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa |
13665 | #define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL |
13666 | #define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L |
13667 | #define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L |
13668 | #define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L |
13669 | //GDS_ATOM_COMPLETE |
13670 | #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 |
13671 | #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 |
13672 | #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L |
13673 | #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL |
13674 | //GDS_ATOM_BASE |
13675 | #define GDS_ATOM_BASE__BASE__SHIFT 0x0 |
13676 | #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 |
13677 | #define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL |
13678 | #define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L |
13679 | //GDS_ATOM_SIZE |
13680 | #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 |
13681 | #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 |
13682 | #define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL |
13683 | #define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L |
13684 | //GDS_ATOM_OFFSET0 |
13685 | #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 |
13686 | #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 |
13687 | #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL |
13688 | #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L |
13689 | //GDS_ATOM_OFFSET1 |
13690 | #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 |
13691 | #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 |
13692 | #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL |
13693 | #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L |
13694 | //GDS_ATOM_DST |
13695 | #define GDS_ATOM_DST__DST__SHIFT 0x0 |
13696 | #define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL |
13697 | //GDS_ATOM_OP |
13698 | #define GDS_ATOM_OP__OP__SHIFT 0x0 |
13699 | #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 |
13700 | #define GDS_ATOM_OP__OP_MASK 0x000000FFL |
13701 | #define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L |
13702 | //GDS_ATOM_SRC0 |
13703 | #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 |
13704 | #define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL |
13705 | //GDS_ATOM_SRC0_U |
13706 | #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 |
13707 | #define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL |
13708 | //GDS_ATOM_SRC1 |
13709 | #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 |
13710 | #define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL |
13711 | //GDS_ATOM_SRC1_U |
13712 | #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 |
13713 | #define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL |
13714 | //GDS_ATOM_READ0 |
13715 | #define GDS_ATOM_READ0__DATA__SHIFT 0x0 |
13716 | #define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL |
13717 | //GDS_ATOM_READ0_U |
13718 | #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 |
13719 | #define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL |
13720 | //GDS_ATOM_READ1 |
13721 | #define GDS_ATOM_READ1__DATA__SHIFT 0x0 |
13722 | #define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL |
13723 | //GDS_ATOM_READ1_U |
13724 | #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 |
13725 | #define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL |
13726 | //GDS_GWS_RESOURCE_CNTL |
13727 | #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 |
13728 | #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 |
13729 | #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL |
13730 | #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L |
13731 | //GDS_GWS_RESOURCE |
13732 | #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 |
13733 | #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 |
13734 | #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xe |
13735 | #define GDS_GWS_RESOURCE__DED__SHIFT 0xf |
13736 | #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0x10 |
13737 | #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x11 |
13738 | #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d |
13739 | #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e |
13740 | #define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f |
13741 | #define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L |
13742 | #define GDS_GWS_RESOURCE__COUNTER_MASK 0x00003FFEL |
13743 | #define GDS_GWS_RESOURCE__TYPE_MASK 0x00004000L |
13744 | #define GDS_GWS_RESOURCE__DED_MASK 0x00008000L |
13745 | #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00010000L |
13746 | #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFE0000L |
13747 | #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L |
13748 | #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L |
13749 | #define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L |
13750 | //GDS_GWS_RESOURCE_CNT |
13751 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 |
13752 | #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 |
13753 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL |
13754 | #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L |
13755 | //GDS_OA_CNTL |
13756 | #define GDS_OA_CNTL__INDEX__SHIFT 0x0 |
13757 | #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 |
13758 | #define GDS_OA_CNTL__INDEX_MASK 0x0000000FL |
13759 | #define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L |
13760 | //GDS_OA_COUNTER |
13761 | #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 |
13762 | #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL |
13763 | //GDS_OA_ADDRESS |
13764 | #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 |
13765 | #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 |
13766 | #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 |
13767 | #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 |
13768 | #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e |
13769 | #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f |
13770 | #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL |
13771 | #define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L |
13772 | #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L |
13773 | #define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L |
13774 | #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L |
13775 | #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L |
13776 | //GDS_OA_INCDEC |
13777 | #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 |
13778 | #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f |
13779 | #define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL |
13780 | #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L |
13781 | //GDS_OA_RING_SIZE |
13782 | #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 |
13783 | #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL |
13784 | //SPI_CONFIG_CNTL |
13785 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 |
13786 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 |
13787 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 |
13788 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 |
13789 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a |
13790 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b |
13791 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c |
13792 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d |
13793 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e |
13794 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL |
13795 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L |
13796 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L |
13797 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L |
13798 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L |
13799 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L |
13800 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L |
13801 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L |
13802 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L |
13803 | //SPI_CONFIG_CNTL_1 |
13804 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 |
13805 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 |
13806 | #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 |
13807 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 |
13808 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 |
13809 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 |
13810 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 |
13811 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa |
13812 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe |
13813 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf |
13814 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 |
13815 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL |
13816 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L |
13817 | #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L |
13818 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L |
13819 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L |
13820 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L |
13821 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L |
13822 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L |
13823 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L |
13824 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L |
13825 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L |
13826 | //SPI_CONFIG_CNTL_2 |
13827 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 |
13828 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 |
13829 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL |
13830 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L |
13831 | //SPI_WAVE_LIMIT_CNTL |
13832 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 |
13833 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 |
13834 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 |
13835 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 |
13836 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L |
13837 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL |
13838 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L |
13839 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L |
13840 | |
13841 | |
13842 | // addressBlock: gc_grbmdec |
13843 | //GRBM_CNTL |
13844 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 |
13845 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f |
13846 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL |
13847 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L |
13848 | //GRBM_SKEW_CNTL |
13849 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 |
13850 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 |
13851 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL |
13852 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L |
13853 | //GRBM_STATUS2 |
13854 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 |
13855 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 |
13856 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 |
13857 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 |
13858 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 |
13859 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 |
13860 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 |
13861 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa |
13862 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb |
13863 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc |
13864 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd |
13865 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe |
13866 | #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf |
13867 | #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 |
13868 | #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 |
13869 | #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 |
13870 | #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 |
13871 | #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 |
13872 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 |
13873 | #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 |
13874 | #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a |
13875 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c |
13876 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d |
13877 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e |
13878 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL |
13879 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L |
13880 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L |
13881 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L |
13882 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L |
13883 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L |
13884 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L |
13885 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L |
13886 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L |
13887 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L |
13888 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L |
13889 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L |
13890 | #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L |
13891 | #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L |
13892 | #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L |
13893 | #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L |
13894 | #define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L |
13895 | #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L |
13896 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L |
13897 | #define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L |
13898 | #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L |
13899 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L |
13900 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L |
13901 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L |
13902 | //GRBM_PWR_CNTL |
13903 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 |
13904 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 |
13905 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 |
13906 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 |
13907 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe |
13908 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf |
13909 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L |
13910 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL |
13911 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L |
13912 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L |
13913 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L |
13914 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L |
13915 | //GRBM_STATUS |
13916 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 |
13917 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 |
13918 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 |
13919 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 |
13920 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc |
13921 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd |
13922 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe |
13923 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf |
13924 | #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 |
13925 | #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 |
13926 | #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 |
13927 | #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 |
13928 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 |
13929 | #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 |
13930 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 |
13931 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 |
13932 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 |
13933 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 |
13934 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a |
13935 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c |
13936 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d |
13937 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e |
13938 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f |
13939 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL |
13940 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L |
13941 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L |
13942 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L |
13943 | #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L |
13944 | #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L |
13945 | #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L |
13946 | #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L |
13947 | #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L |
13948 | #define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L |
13949 | #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L |
13950 | #define GRBM_STATUS__IA_BUSY_MASK 0x00080000L |
13951 | #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L |
13952 | #define GRBM_STATUS__WD_BUSY_MASK 0x00200000L |
13953 | #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L |
13954 | #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L |
13955 | #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L |
13956 | #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L |
13957 | #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L |
13958 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L |
13959 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L |
13960 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L |
13961 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
13962 | //GRBM_STATUS_SE0 |
13963 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 |
13964 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 |
13965 | #define GRBM_STATUS_SE0__TA_BUSY_SE4__SHIFT 0x3 |
13966 | #define GRBM_STATUS_SE0__SX_BUSY_SE4__SHIFT 0x4 |
13967 | #define GRBM_STATUS_SE0__SPI_BUSY_SE4__SHIFT 0x5 |
13968 | #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 |
13969 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 |
13970 | #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 |
13971 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 |
13972 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 |
13973 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a |
13974 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b |
13975 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d |
13976 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e |
13977 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f |
13978 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L |
13979 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L |
13980 | #define GRBM_STATUS_SE0__TA_BUSY_SE4_MASK 0x00000008L |
13981 | #define GRBM_STATUS_SE0__SX_BUSY_SE4_MASK 0x00000010L |
13982 | #define GRBM_STATUS_SE0__SPI_BUSY_SE4_MASK 0x00000020L |
13983 | #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L |
13984 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L |
13985 | #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L |
13986 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L |
13987 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L |
13988 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L |
13989 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L |
13990 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L |
13991 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L |
13992 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L |
13993 | //GRBM_STATUS_SE1 |
13994 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 |
13995 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 |
13996 | #define GRBM_STATUS_SE1__TA_BUSY_SE5__SHIFT 0x3 |
13997 | #define GRBM_STATUS_SE1__SX_BUSY_SE5__SHIFT 0x4 |
13998 | #define GRBM_STATUS_SE1__SPI_BUSY_SE5__SHIFT 0x5 |
13999 | #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 |
14000 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 |
14001 | #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 |
14002 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 |
14003 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 |
14004 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a |
14005 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b |
14006 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d |
14007 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e |
14008 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f |
14009 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L |
14010 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L |
14011 | #define GRBM_STATUS_SE1__TA_BUSY_SE5_MASK 0x00000008L |
14012 | #define GRBM_STATUS_SE1__SX_BUSY_SE5_MASK 0x00000010L |
14013 | #define GRBM_STATUS_SE1__SPI_BUSY_SE5_MASK 0x00000020L |
14014 | #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L |
14015 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L |
14016 | #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L |
14017 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L |
14018 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L |
14019 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L |
14020 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L |
14021 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L |
14022 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L |
14023 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L |
14024 | //GRBM_SOFT_RESET |
14025 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 |
14026 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 |
14027 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 |
14028 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 |
14029 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 |
14030 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 |
14031 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 |
14032 | #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 |
14033 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L |
14034 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L |
14035 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L |
14036 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L |
14037 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L |
14038 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L |
14039 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L |
14040 | #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L |
14041 | //GRBM_GFX_CLKEN_CNTL |
14042 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 |
14043 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 |
14044 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL |
14045 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L |
14046 | //GRBM_WAIT_IDLE_CLOCKS |
14047 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 |
14048 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL |
14049 | //GRBM_STATUS_SE2 |
14050 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 |
14051 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 |
14052 | #define GRBM_STATUS_SE2__TA_BUSY_SE6__SHIFT 0x3 |
14053 | #define GRBM_STATUS_SE2__SX_BUSY_SE6__SHIFT 0x4 |
14054 | #define GRBM_STATUS_SE2__SPI_BUSY_SE6__SHIFT 0x5 |
14055 | #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 |
14056 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 |
14057 | #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 |
14058 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 |
14059 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 |
14060 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a |
14061 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b |
14062 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d |
14063 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e |
14064 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f |
14065 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L |
14066 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L |
14067 | #define GRBM_STATUS_SE2__TA_BUSY_SE6_MASK 0x00000008L |
14068 | #define GRBM_STATUS_SE2__SX_BUSY_SE6_MASK 0x00000010L |
14069 | #define GRBM_STATUS_SE2__SPI_BUSY_SE6_MASK 0x00000020L |
14070 | #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L |
14071 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L |
14072 | #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L |
14073 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L |
14074 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L |
14075 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L |
14076 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L |
14077 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L |
14078 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L |
14079 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L |
14080 | //GRBM_STATUS_SE3 |
14081 | #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 |
14082 | #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 |
14083 | #define GRBM_STATUS_SE3__TA_BUSY_SE7__SHIFT 0x3 |
14084 | #define GRBM_STATUS_SE3__SX_BUSY_SE7__SHIFT 0x4 |
14085 | #define GRBM_STATUS_SE3__SPI_BUSY_SE7__SHIFT 0x5 |
14086 | #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 |
14087 | #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 |
14088 | #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 |
14089 | #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 |
14090 | #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 |
14091 | #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a |
14092 | #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b |
14093 | #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d |
14094 | #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e |
14095 | #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f |
14096 | #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L |
14097 | #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L |
14098 | #define GRBM_STATUS_SE3__TA_BUSY_SE7_MASK 0x00000008L |
14099 | #define GRBM_STATUS_SE3__SX_BUSY_SE7_MASK 0x00000010L |
14100 | #define GRBM_STATUS_SE3__SPI_BUSY_SE7_MASK 0x00000020L |
14101 | #define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L |
14102 | #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L |
14103 | #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L |
14104 | #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L |
14105 | #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L |
14106 | #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L |
14107 | #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L |
14108 | #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L |
14109 | #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L |
14110 | #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L |
14111 | //GRBM_READ_ERROR |
14112 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 |
14113 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 |
14114 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 |
14115 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f |
14116 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL |
14117 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L |
14118 | #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L |
14119 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
14120 | //GRBM_READ_ERROR2 |
14121 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 |
14122 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 |
14123 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 |
14124 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 |
14125 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 |
14126 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 |
14127 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 |
14128 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 |
14129 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 |
14130 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a |
14131 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b |
14132 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c |
14133 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d |
14134 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e |
14135 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f |
14136 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L |
14137 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L |
14138 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L |
14139 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L |
14140 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L |
14141 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L |
14142 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L |
14143 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L |
14144 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L |
14145 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L |
14146 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L |
14147 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L |
14148 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L |
14149 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L |
14150 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L |
14151 | //GRBM_INT_CNTL |
14152 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 |
14153 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 |
14154 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L |
14155 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L |
14156 | //GRBM_TRAP_OP |
14157 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 |
14158 | #define GRBM_TRAP_OP__RW_MASK 0x00000001L |
14159 | //GRBM_TRAP_ADDR |
14160 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 |
14161 | #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL |
14162 | //GRBM_TRAP_ADDR_MSK |
14163 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 |
14164 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL |
14165 | //GRBM_TRAP_WD |
14166 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 |
14167 | #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL |
14168 | //GRBM_TRAP_WD_MSK |
14169 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 |
14170 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL |
14171 | //GRBM_WRITE_ERROR |
14172 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 |
14173 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 |
14174 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 |
14175 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc |
14176 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd |
14177 | #define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 |
14178 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 |
14179 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 |
14180 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f |
14181 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L |
14182 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL |
14183 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L |
14184 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L |
14185 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L |
14186 | #define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L |
14187 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L |
14188 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L |
14189 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L |
14190 | //GRBM_CHIP_REVISION |
14191 | #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 |
14192 | #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL |
14193 | //GRBM_GFX_CNTL |
14194 | #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 |
14195 | #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 |
14196 | #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 |
14197 | #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 |
14198 | #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L |
14199 | #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL |
14200 | #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L |
14201 | #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L |
14202 | //GRBM_IH_CREDIT |
14203 | #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
14204 | #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 |
14205 | #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
14206 | #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L |
14207 | //GRBM_PWR_CNTL2 |
14208 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 |
14209 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 |
14210 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L |
14211 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L |
14212 | //GRBM_UTCL2_INVAL_RANGE_START |
14213 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 |
14214 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL |
14215 | //GRBM_UTCL2_INVAL_RANGE_END |
14216 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 |
14217 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL |
14218 | //GRBM_CHICKEN_BITS |
14219 | #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 |
14220 | #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L |
14221 | //GRBM_FENCE_RANGE0 |
14222 | #define GRBM_FENCE_RANGE0__START__SHIFT 0x0 |
14223 | #define GRBM_FENCE_RANGE0__END__SHIFT 0x10 |
14224 | #define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL |
14225 | #define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L |
14226 | //GRBM_FENCE_RANGE1 |
14227 | #define GRBM_FENCE_RANGE1__START__SHIFT 0x0 |
14228 | #define GRBM_FENCE_RANGE1__END__SHIFT 0x10 |
14229 | #define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL |
14230 | #define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L |
14231 | //GRBM_NOWHERE |
14232 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 |
14233 | #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL |
14234 | //GRBM_SCRATCH_REG0 |
14235 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
14236 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
14237 | //GRBM_SCRATCH_REG1 |
14238 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
14239 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
14240 | //GRBM_SCRATCH_REG2 |
14241 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
14242 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
14243 | //GRBM_SCRATCH_REG3 |
14244 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
14245 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
14246 | //GRBM_SCRATCH_REG4 |
14247 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
14248 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
14249 | //GRBM_SCRATCH_REG5 |
14250 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
14251 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
14252 | //GRBM_SCRATCH_REG6 |
14253 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
14254 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
14255 | //GRBM_SCRATCH_REG7 |
14256 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
14257 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
14258 | //VIOLATION_DATA_ASYNC_VF_PROG |
14259 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 |
14260 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 |
14261 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f |
14262 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL |
14263 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L |
14264 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L |
14265 | |
14266 | |
14267 | // addressBlock: gc_hypdec |
14268 | //CP_HYP_PFP_UCODE_ADDR |
14269 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14270 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
14271 | //CP_PFP_UCODE_ADDR |
14272 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14273 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
14274 | //CP_HYP_PFP_UCODE_DATA |
14275 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14276 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14277 | //CP_PFP_UCODE_DATA |
14278 | #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14279 | #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14280 | //CP_HYP_ME_UCODE_ADDR |
14281 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14282 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL |
14283 | //CP_ME_RAM_RADDR |
14284 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 |
14285 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL |
14286 | //CP_ME_RAM_WADDR |
14287 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 |
14288 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL |
14289 | //CP_HYP_ME_UCODE_DATA |
14290 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14291 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14292 | //CP_ME_RAM_DATA |
14293 | #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 |
14294 | #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL |
14295 | //CP_CE_UCODE_ADDR |
14296 | #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14297 | #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
14298 | //CP_HYP_CE_UCODE_ADDR |
14299 | #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14300 | #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
14301 | //CP_CE_UCODE_DATA |
14302 | #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14303 | #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14304 | //CP_HYP_CE_UCODE_DATA |
14305 | #define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14306 | #define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14307 | //CP_HYP_MEC1_UCODE_ADDR |
14308 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14309 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL |
14310 | //CP_MEC_ME1_UCODE_ADDR |
14311 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14312 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL |
14313 | //CP_HYP_MEC1_UCODE_DATA |
14314 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14315 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14316 | //CP_MEC_ME1_UCODE_DATA |
14317 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14318 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14319 | //CP_HYP_MEC2_UCODE_ADDR |
14320 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14321 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL |
14322 | //CP_MEC_ME2_UCODE_ADDR |
14323 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14324 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL |
14325 | //CP_HYP_MEC2_UCODE_DATA |
14326 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14327 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14328 | //CP_MEC_ME2_UCODE_DATA |
14329 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14330 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14331 | //RLC_GPM_UCODE_ADDR |
14332 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14333 | #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe |
14334 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
14335 | #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L |
14336 | //RLC_GPM_UCODE_DATA |
14337 | #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14338 | #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14339 | //GRBM_GFX_INDEX_SR_SELECT |
14340 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 |
14341 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f |
14342 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L |
14343 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L |
14344 | //GRBM_GFX_INDEX_SR_DATA |
14345 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 |
14346 | #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 |
14347 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 |
14348 | #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d |
14349 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
14350 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f |
14351 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL |
14352 | #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L |
14353 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L |
14354 | #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L |
14355 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
14356 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L |
14357 | //GRBM_GFX_CNTL_SR_SELECT |
14358 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 |
14359 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f |
14360 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L |
14361 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L |
14362 | //GRBM_GFX_CNTL_SR_DATA |
14363 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 |
14364 | #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 |
14365 | #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 |
14366 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 |
14367 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L |
14368 | #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL |
14369 | #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L |
14370 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L |
14371 | //GRBM_CAM_INDEX |
14372 | #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
14373 | #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L |
14374 | //GRBM_HYP_CAM_INDEX |
14375 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
14376 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L |
14377 | //GRBM_CAM_DATA |
14378 | #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
14379 | #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
14380 | #define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
14381 | #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
14382 | //GRBM_HYP_CAM_DATA |
14383 | #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
14384 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
14385 | #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
14386 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
14387 | //RLC_GPU_IOV_VF_ENABLE |
14388 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
14389 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 |
14390 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 |
14391 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
14392 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL |
14393 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L |
14394 | //RLC_GPU_IOV_CFG_REG6 |
14395 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 |
14396 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 |
14397 | #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 |
14398 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa |
14399 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL |
14400 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L |
14401 | #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L |
14402 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L |
14403 | //RLC_GPU_IOV_CFG_REG8 |
14404 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 |
14405 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14406 | //RLC_RLCV_TIMER_INT_0 |
14407 | #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 |
14408 | #define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
14409 | //RLC_RLCV_TIMER_CTRL |
14410 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
14411 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
14412 | #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2 |
14413 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
14414 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
14415 | #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL |
14416 | //RLC_RLCV_TIMER_STAT |
14417 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
14418 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
14419 | #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 |
14420 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
14421 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
14422 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
14423 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
14424 | #define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL |
14425 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
14426 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
14427 | //RLC_GPU_IOV_VF_DOORBELL_STATUS |
14428 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 |
14429 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 |
14430 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f |
14431 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL |
14432 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L |
14433 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L |
14434 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET |
14435 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 |
14436 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 |
14437 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f |
14438 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL |
14439 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L |
14440 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L |
14441 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR |
14442 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 |
14443 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 |
14444 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f |
14445 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL |
14446 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L |
14447 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L |
14448 | //RLC_GPU_IOV_VF_MASK |
14449 | #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 |
14450 | #define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 |
14451 | #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL |
14452 | #define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L |
14453 | //RLC_HYP_SEMAPHORE_0 |
14454 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
14455 | #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
14456 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
14457 | #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
14458 | //RLC_HYP_SEMAPHORE_1 |
14459 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
14460 | #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
14461 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
14462 | #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
14463 | //RLC_CLK_CNTL |
14464 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 |
14465 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 |
14466 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 |
14467 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 |
14468 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 |
14469 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7 |
14470 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 |
14471 | #define RLC_CLK_CNTL__RLC_EDC_OVERRIDE__SHIFT 0x9 |
14472 | #define RLC_CLK_CNTL__RESERVED_11_10__SHIFT 0xa |
14473 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc |
14474 | #define RLC_CLK_CNTL__RESERVED_1__SHIFT 0xe |
14475 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 |
14476 | #define RLC_CLK_CNTL__RESERVED__SHIFT 0x13 |
14477 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L |
14478 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL |
14479 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L |
14480 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L |
14481 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L |
14482 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L |
14483 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L |
14484 | #define RLC_CLK_CNTL__RLC_EDC_OVERRIDE_MASK 0x00000200L |
14485 | #define RLC_CLK_CNTL__RESERVED_11_10_MASK 0x00000C00L |
14486 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L |
14487 | #define RLC_CLK_CNTL__RESERVED_1_MASK 0x0003C000L |
14488 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L |
14489 | #define RLC_CLK_CNTL__RESERVED_MASK 0xFFF80000L |
14490 | //RLC_GPU_IOV_SCH_BLOCK |
14491 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 |
14492 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 |
14493 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 |
14494 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 |
14495 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL |
14496 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L |
14497 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L |
14498 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L |
14499 | //RLC_GPU_IOV_CFG_REG1 |
14500 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 |
14501 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 |
14502 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
14503 | #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 |
14504 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 |
14505 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 |
14506 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 |
14507 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL |
14508 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L |
14509 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
14510 | #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L |
14511 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L |
14512 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L |
14513 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L |
14514 | //RLC_GPU_IOV_CFG_REG2 |
14515 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 |
14516 | #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 |
14517 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL |
14518 | #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L |
14519 | //RLC_GPU_IOV_VM_BUSY_STATUS |
14520 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14521 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14522 | //RLC_GPU_IOV_SCH_0 |
14523 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 |
14524 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL |
14525 | //RLC_GPU_IOV_ACTIVE_FCN_ID |
14526 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
14527 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 |
14528 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
14529 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL |
14530 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L |
14531 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
14532 | //RLC_GPU_IOV_SCH_3 |
14533 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 |
14534 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL |
14535 | //RLC_GPU_IOV_SCH_1 |
14536 | #define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 |
14537 | #define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL |
14538 | //RLC_GPU_IOV_SCH_2 |
14539 | #define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 |
14540 | #define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL |
14541 | //RLC_GPU_IOV_INT_STAT |
14542 | #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 |
14543 | #define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
14544 | //RLC_RLCV_TIMER_INT_1 |
14545 | #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 |
14546 | #define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
14547 | //RLC_GPU_IOV_UCODE_ADDR |
14548 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
14549 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc |
14550 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
14551 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
14552 | //RLC_GPU_IOV_UCODE_DATA |
14553 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
14554 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
14555 | //RLC_GPU_IOV_SCRATCH_ADDR |
14556 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
14557 | #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 |
14558 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL |
14559 | #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L |
14560 | //RLC_GPU_IOV_SCRATCH_DATA |
14561 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 |
14562 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
14563 | //RLC_GPU_IOV_F32_CNTL |
14564 | #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 |
14565 | #define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 |
14566 | #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L |
14567 | #define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL |
14568 | //RLC_GPU_IOV_F32_RESET |
14569 | #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 |
14570 | #define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 |
14571 | #define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L |
14572 | #define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL |
14573 | //RLC_GPU_IOV_SDMA0_STATUS |
14574 | #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 |
14575 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 |
14576 | #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 |
14577 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 |
14578 | #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc |
14579 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd |
14580 | #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L |
14581 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL |
14582 | #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L |
14583 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L |
14584 | #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L |
14585 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L |
14586 | //RLC_GPU_IOV_SDMA1_STATUS |
14587 | #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 |
14588 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 |
14589 | #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 |
14590 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 |
14591 | #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc |
14592 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd |
14593 | #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L |
14594 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL |
14595 | #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L |
14596 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L |
14597 | #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L |
14598 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L |
14599 | //RLC_GPU_IOV_VIRT_RESET_REQ |
14600 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 |
14601 | #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 |
14602 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f |
14603 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL |
14604 | #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L |
14605 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L |
14606 | //RLC_GPU_IOV_RLC_RESPONSE |
14607 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 |
14608 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
14609 | //RLC_GPU_IOV_INT_DISABLE |
14610 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 |
14611 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL |
14612 | //RLC_GPU_IOV_INT_FORCE |
14613 | #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 |
14614 | #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL |
14615 | //RLC_GPU_IOV_SDMA0_BUSY_STATUS |
14616 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14617 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14618 | //RLC_GPU_IOV_SDMA1_BUSY_STATUS |
14619 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14620 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14621 | //RLC_HYP_SEMAPHORE_2 |
14622 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
14623 | #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
14624 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
14625 | #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
14626 | //RLC_HYP_SEMAPHORE_3 |
14627 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
14628 | #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
14629 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
14630 | #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
14631 | //RLC_GPU_IOV_SDMA2_STATUS |
14632 | #define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED__SHIFT 0x0 |
14633 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED__SHIFT 0x1 |
14634 | #define RLC_GPU_IOV_SDMA2_STATUS__SAVED__SHIFT 0x8 |
14635 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1__SHIFT 0x9 |
14636 | #define RLC_GPU_IOV_SDMA2_STATUS__RESTORED__SHIFT 0xc |
14637 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2__SHIFT 0xd |
14638 | #define RLC_GPU_IOV_SDMA2_STATUS__PREEMPTED_MASK 0x00000001L |
14639 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED_MASK 0x000000FEL |
14640 | #define RLC_GPU_IOV_SDMA2_STATUS__SAVED_MASK 0x00000100L |
14641 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED1_MASK 0x00000E00L |
14642 | #define RLC_GPU_IOV_SDMA2_STATUS__RESTORED_MASK 0x00001000L |
14643 | #define RLC_GPU_IOV_SDMA2_STATUS__RESERVED2_MASK 0xFFFFE000L |
14644 | //RLC_GPU_IOV_SDMA3_STATUS |
14645 | #define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED__SHIFT 0x0 |
14646 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED__SHIFT 0x1 |
14647 | #define RLC_GPU_IOV_SDMA3_STATUS__SAVED__SHIFT 0x8 |
14648 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1__SHIFT 0x9 |
14649 | #define RLC_GPU_IOV_SDMA3_STATUS__RESTORED__SHIFT 0xc |
14650 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2__SHIFT 0xd |
14651 | #define RLC_GPU_IOV_SDMA3_STATUS__PREEMPTED_MASK 0x00000001L |
14652 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED_MASK 0x000000FEL |
14653 | #define RLC_GPU_IOV_SDMA3_STATUS__SAVED_MASK 0x00000100L |
14654 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED1_MASK 0x00000E00L |
14655 | #define RLC_GPU_IOV_SDMA3_STATUS__RESTORED_MASK 0x00001000L |
14656 | #define RLC_GPU_IOV_SDMA3_STATUS__RESERVED2_MASK 0xFFFFE000L |
14657 | //RLC_GPU_IOV_SDMA4_STATUS |
14658 | #define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED__SHIFT 0x0 |
14659 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED__SHIFT 0x1 |
14660 | #define RLC_GPU_IOV_SDMA4_STATUS__SAVED__SHIFT 0x8 |
14661 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1__SHIFT 0x9 |
14662 | #define RLC_GPU_IOV_SDMA4_STATUS__RESTORED__SHIFT 0xc |
14663 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2__SHIFT 0xd |
14664 | #define RLC_GPU_IOV_SDMA4_STATUS__PREEMPTED_MASK 0x00000001L |
14665 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED_MASK 0x000000FEL |
14666 | #define RLC_GPU_IOV_SDMA4_STATUS__SAVED_MASK 0x00000100L |
14667 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED1_MASK 0x00000E00L |
14668 | #define RLC_GPU_IOV_SDMA4_STATUS__RESTORED_MASK 0x00001000L |
14669 | #define RLC_GPU_IOV_SDMA4_STATUS__RESERVED2_MASK 0xFFFFE000L |
14670 | //RLC_GPU_IOV_SDMA5_STATUS |
14671 | #define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED__SHIFT 0x0 |
14672 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED__SHIFT 0x1 |
14673 | #define RLC_GPU_IOV_SDMA5_STATUS__SAVED__SHIFT 0x8 |
14674 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1__SHIFT 0x9 |
14675 | #define RLC_GPU_IOV_SDMA5_STATUS__RESTORED__SHIFT 0xc |
14676 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2__SHIFT 0xd |
14677 | #define RLC_GPU_IOV_SDMA5_STATUS__PREEMPTED_MASK 0x00000001L |
14678 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED_MASK 0x000000FEL |
14679 | #define RLC_GPU_IOV_SDMA5_STATUS__SAVED_MASK 0x00000100L |
14680 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED1_MASK 0x00000E00L |
14681 | #define RLC_GPU_IOV_SDMA5_STATUS__RESTORED_MASK 0x00001000L |
14682 | #define RLC_GPU_IOV_SDMA5_STATUS__RESERVED2_MASK 0xFFFFE000L |
14683 | //RLC_GPU_IOV_SDMA6_STATUS |
14684 | #define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED__SHIFT 0x0 |
14685 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED__SHIFT 0x1 |
14686 | #define RLC_GPU_IOV_SDMA6_STATUS__SAVED__SHIFT 0x8 |
14687 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1__SHIFT 0x9 |
14688 | #define RLC_GPU_IOV_SDMA6_STATUS__RESTORED__SHIFT 0xc |
14689 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2__SHIFT 0xd |
14690 | #define RLC_GPU_IOV_SDMA6_STATUS__PREEMPTED_MASK 0x00000001L |
14691 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED_MASK 0x000000FEL |
14692 | #define RLC_GPU_IOV_SDMA6_STATUS__SAVED_MASK 0x00000100L |
14693 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED1_MASK 0x00000E00L |
14694 | #define RLC_GPU_IOV_SDMA6_STATUS__RESTORED_MASK 0x00001000L |
14695 | #define RLC_GPU_IOV_SDMA6_STATUS__RESERVED2_MASK 0xFFFFE000L |
14696 | //RLC_GPU_IOV_SDMA7_STATUS |
14697 | #define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED__SHIFT 0x0 |
14698 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED__SHIFT 0x1 |
14699 | #define RLC_GPU_IOV_SDMA7_STATUS__SAVED__SHIFT 0x8 |
14700 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1__SHIFT 0x9 |
14701 | #define RLC_GPU_IOV_SDMA7_STATUS__RESTORED__SHIFT 0xc |
14702 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2__SHIFT 0xd |
14703 | #define RLC_GPU_IOV_SDMA7_STATUS__PREEMPTED_MASK 0x00000001L |
14704 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED_MASK 0x000000FEL |
14705 | #define RLC_GPU_IOV_SDMA7_STATUS__SAVED_MASK 0x00000100L |
14706 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED1_MASK 0x00000E00L |
14707 | #define RLC_GPU_IOV_SDMA7_STATUS__RESTORED_MASK 0x00001000L |
14708 | #define RLC_GPU_IOV_SDMA7_STATUS__RESERVED2_MASK 0xFFFFE000L |
14709 | //RLC_GPU_IOV_SDMA2_BUSY_STATUS |
14710 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14711 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14712 | //RLC_GPU_IOV_SDMA3_BUSY_STATUS |
14713 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14714 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14715 | //RLC_GPU_IOV_SDMA4_BUSY_STATUS |
14716 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14717 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14718 | //RLC_GPU_IOV_SDMA5_BUSY_STATUS |
14719 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14720 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14721 | //RLC_GPU_IOV_SDMA6_BUSY_STATUS |
14722 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14723 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14724 | //RLC_GPU_IOV_SDMA7_BUSY_STATUS |
14725 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
14726 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
14727 | |
14728 | |
14729 | // addressBlock: gc_padec |
14730 | //VGT_VTX_VECT_EJECT_REG |
14731 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 |
14732 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL |
14733 | //VGT_DMA_DATA_FIFO_DEPTH |
14734 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 |
14735 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 |
14736 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL |
14737 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L |
14738 | //VGT_DMA_REQ_FIFO_DEPTH |
14739 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 |
14740 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL |
14741 | //VGT_DRAW_INIT_FIFO_DEPTH |
14742 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 |
14743 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL |
14744 | //VGT_LAST_COPY_STATE |
14745 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
14746 | #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 |
14747 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
14748 | #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L |
14749 | //VGT_CACHE_INVALIDATION |
14750 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 |
14751 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 |
14752 | #define 0x5 |
14753 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 |
14754 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 |
14755 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb |
14756 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc |
14757 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd |
14758 | #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 |
14759 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 |
14760 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 |
14761 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 |
14762 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c |
14763 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d |
14764 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L |
14765 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L |
14766 | #define 0x00000020L |
14767 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L |
14768 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L |
14769 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L |
14770 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L |
14771 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L |
14772 | #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L |
14773 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L |
14774 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L |
14775 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L |
14776 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L |
14777 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L |
14778 | //VGT_STRMOUT_DELAY |
14779 | #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 |
14780 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 |
14781 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb |
14782 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe |
14783 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 |
14784 | #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL |
14785 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L |
14786 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L |
14787 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L |
14788 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L |
14789 | //VGT_FIFO_DEPTHS |
14790 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 |
14791 | #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 |
14792 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 |
14793 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 |
14794 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL |
14795 | #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L |
14796 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L |
14797 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L |
14798 | //VGT_GS_VERTEX_REUSE |
14799 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 |
14800 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL |
14801 | //VGT_MC_LAT_CNTL |
14802 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 |
14803 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL |
14804 | //IA_CNTL_STATUS |
14805 | #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 |
14806 | #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 |
14807 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 |
14808 | #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 |
14809 | #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 |
14810 | #define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L |
14811 | #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L |
14812 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L |
14813 | #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L |
14814 | #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L |
14815 | //VGT_CNTL_STATUS |
14816 | #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 |
14817 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 |
14818 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 |
14819 | #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 |
14820 | #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 |
14821 | #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 |
14822 | #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 |
14823 | #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 |
14824 | #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 |
14825 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 |
14826 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa |
14827 | #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L |
14828 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L |
14829 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L |
14830 | #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L |
14831 | #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L |
14832 | #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L |
14833 | #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L |
14834 | #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L |
14835 | #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L |
14836 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L |
14837 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L |
14838 | //WD_CNTL_STATUS |
14839 | #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 |
14840 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 |
14841 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 |
14842 | #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 |
14843 | #define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L |
14844 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L |
14845 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L |
14846 | #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L |
14847 | //CC_GC_PRIM_CONFIG |
14848 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
14849 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
14850 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
14851 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
14852 | //GC_USER_PRIM_CONFIG |
14853 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
14854 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
14855 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
14856 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
14857 | //WD_QOS |
14858 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 |
14859 | #define WD_QOS__DRAW_STALL_MASK 0x00000001L |
14860 | //WD_UTCL1_CNTL |
14861 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
14862 | #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
14863 | #define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
14864 | #define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
14865 | #define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
14866 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
14867 | #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
14868 | #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
14869 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
14870 | #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
14871 | #define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
14872 | #define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
14873 | #define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
14874 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
14875 | #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
14876 | #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
14877 | //WD_UTCL1_STATUS |
14878 | #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
14879 | #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
14880 | #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
14881 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
14882 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
14883 | #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
14884 | #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
14885 | #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
14886 | #define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
14887 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
14888 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
14889 | #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
14890 | //IA_UTCL1_CNTL |
14891 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
14892 | #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
14893 | #define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
14894 | #define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
14895 | #define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
14896 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
14897 | #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
14898 | #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
14899 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
14900 | #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
14901 | #define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
14902 | #define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
14903 | #define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
14904 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
14905 | #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
14906 | #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
14907 | //IA_UTCL1_STATUS |
14908 | #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
14909 | #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
14910 | #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
14911 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
14912 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
14913 | #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
14914 | #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
14915 | #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
14916 | #define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
14917 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
14918 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
14919 | #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
14920 | //VGT_SYS_CONFIG |
14921 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 |
14922 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 |
14923 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 |
14924 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L |
14925 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL |
14926 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L |
14927 | //VGT_VS_MAX_WAVE_ID |
14928 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
14929 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
14930 | //VGT_GS_MAX_WAVE_ID |
14931 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
14932 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
14933 | //GFX_PIPE_CONTROL |
14934 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 |
14935 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd |
14936 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 |
14937 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL |
14938 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L |
14939 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L |
14940 | //CC_GC_SHADER_ARRAY_CONFIG |
14941 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 |
14942 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L |
14943 | //GC_USER_SHADER_ARRAY_CONFIG |
14944 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 |
14945 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L |
14946 | //VGT_DMA_PRIMITIVE_TYPE |
14947 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
14948 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
14949 | //VGT_DMA_CONTROL |
14950 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 |
14951 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 |
14952 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 |
14953 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 |
14954 | #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 |
14955 | #define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 |
14956 | #define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 |
14957 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
14958 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L |
14959 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L |
14960 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L |
14961 | #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L |
14962 | #define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L |
14963 | #define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L |
14964 | //VGT_DMA_LS_HS_CONFIG |
14965 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
14966 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
14967 | //WD_BUF_RESOURCE_1 |
14968 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 |
14969 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 |
14970 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL |
14971 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L |
14972 | //WD_BUF_RESOURCE_2 |
14973 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 |
14974 | #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf |
14975 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 |
14976 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL |
14977 | #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L |
14978 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L |
14979 | //PA_CL_CNTL_STATUS |
14980 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 |
14981 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 |
14982 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 |
14983 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L |
14984 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L |
14985 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L |
14986 | //PA_CL_ENHANCE |
14987 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 |
14988 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 |
14989 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 |
14990 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 |
14991 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 |
14992 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 |
14993 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 |
14994 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 |
14995 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb |
14996 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc |
14997 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe |
14998 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 |
14999 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 |
15000 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 |
15001 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 |
15002 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 |
15003 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c |
15004 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d |
15005 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e |
15006 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f |
15007 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L |
15008 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L |
15009 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L |
15010 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L |
15011 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L |
15012 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L |
15013 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L |
15014 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L |
15015 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L |
15016 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L |
15017 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L |
15018 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L |
15019 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L |
15020 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L |
15021 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L |
15022 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L |
15023 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L |
15024 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L |
15025 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L |
15026 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L |
15027 | //PA_SU_CNTL_STATUS |
15028 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f |
15029 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L |
15030 | //PA_SC_FIFO_DEPTH_CNTL |
15031 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 |
15032 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL |
15033 | //PA_SC_P3D_TRAP_SCREEN_HV_LOCK |
15034 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
15035 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
15036 | //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK |
15037 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
15038 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
15039 | //PA_SC_TRAP_SCREEN_HV_LOCK |
15040 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
15041 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
15042 | //PA_SC_FORCE_EOV_MAX_CNTS |
15043 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 |
15044 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 |
15045 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL |
15046 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L |
15047 | //PA_SC_BINNER_EVENT_CNTL_0 |
15048 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 |
15049 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 |
15050 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 |
15051 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 |
15052 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 |
15053 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa |
15054 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc |
15055 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe |
15056 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 |
15057 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 |
15058 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 |
15059 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 |
15060 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 |
15061 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a |
15062 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c |
15063 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e |
15064 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L |
15065 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL |
15066 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L |
15067 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L |
15068 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L |
15069 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L |
15070 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L |
15071 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L |
15072 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L |
15073 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L |
15074 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L |
15075 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L |
15076 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L |
15077 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L |
15078 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L |
15079 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L |
15080 | //PA_SC_BINNER_EVENT_CNTL_1 |
15081 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 |
15082 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 |
15083 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 |
15084 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 |
15085 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 |
15086 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa |
15087 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc |
15088 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe |
15089 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 |
15090 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 |
15091 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 |
15092 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 |
15093 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 |
15094 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a |
15095 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c |
15096 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e |
15097 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L |
15098 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL |
15099 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L |
15100 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L |
15101 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L |
15102 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L |
15103 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L |
15104 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L |
15105 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L |
15106 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L |
15107 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L |
15108 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L |
15109 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L |
15110 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L |
15111 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L |
15112 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L |
15113 | //PA_SC_BINNER_EVENT_CNTL_2 |
15114 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 |
15115 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 |
15116 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 |
15117 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 |
15118 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 |
15119 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa |
15120 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc |
15121 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe |
15122 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 |
15123 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 |
15124 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 |
15125 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 |
15126 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 |
15127 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a |
15128 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c |
15129 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e |
15130 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L |
15131 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL |
15132 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L |
15133 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L |
15134 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L |
15135 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L |
15136 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L |
15137 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L |
15138 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L |
15139 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L |
15140 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L |
15141 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L |
15142 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L |
15143 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L |
15144 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L |
15145 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L |
15146 | //PA_SC_BINNER_EVENT_CNTL_3 |
15147 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 |
15148 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 |
15149 | #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 |
15150 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 |
15151 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 |
15152 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa |
15153 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc |
15154 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe |
15155 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 |
15156 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 |
15157 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 |
15158 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 |
15159 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 |
15160 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a |
15161 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c |
15162 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e |
15163 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L |
15164 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL |
15165 | #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L |
15166 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L |
15167 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L |
15168 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L |
15169 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L |
15170 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L |
15171 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L |
15172 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L |
15173 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L |
15174 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L |
15175 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L |
15176 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L |
15177 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L |
15178 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L |
15179 | //PA_SC_BINNER_TIMEOUT_COUNTER |
15180 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 |
15181 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL |
15182 | //PA_SC_BINNER_PERF_CNTL_0 |
15183 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 |
15184 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa |
15185 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 |
15186 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 |
15187 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL |
15188 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L |
15189 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L |
15190 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L |
15191 | //PA_SC_BINNER_PERF_CNTL_1 |
15192 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 |
15193 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 |
15194 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa |
15195 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL |
15196 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L |
15197 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L |
15198 | //PA_SC_BINNER_PERF_CNTL_2 |
15199 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 |
15200 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb |
15201 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL |
15202 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L |
15203 | //PA_SC_BINNER_PERF_CNTL_3 |
15204 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 |
15205 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL |
15206 | //PA_SC_ENHANCE_2 |
15207 | #define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0 |
15208 | #define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1 |
15209 | #define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2 |
15210 | #define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3 |
15211 | #define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4 |
15212 | #define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5 |
15213 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6 |
15214 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7 |
15215 | #define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8 |
15216 | #define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L |
15217 | #define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L |
15218 | #define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L |
15219 | #define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L |
15220 | #define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L |
15221 | #define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L |
15222 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L |
15223 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L |
15224 | #define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L |
15225 | //PA_SC_FIFO_SIZE |
15226 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 |
15227 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 |
15228 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf |
15229 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 |
15230 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL |
15231 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L |
15232 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L |
15233 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L |
15234 | //PA_SC_IF_FIFO_SIZE |
15235 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 |
15236 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 |
15237 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc |
15238 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 |
15239 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL |
15240 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L |
15241 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L |
15242 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L |
15243 | //PA_SC_PKR_WAVE_TABLE_CNTL |
15244 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 |
15245 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL |
15246 | //PA_UTCL1_CNTL1 |
15247 | #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
15248 | #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 |
15249 | #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
15250 | #define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
15251 | #define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
15252 | #define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
15253 | #define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 |
15254 | #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
15255 | #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
15256 | #define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
15257 | #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
15258 | #define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
15259 | #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 |
15260 | #define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
15261 | #define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
15262 | #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
15263 | #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
15264 | #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
15265 | #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L |
15266 | #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
15267 | #define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
15268 | #define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
15269 | #define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
15270 | #define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L |
15271 | #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
15272 | #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
15273 | #define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
15274 | #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
15275 | #define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
15276 | #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L |
15277 | #define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
15278 | #define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
15279 | #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
15280 | #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
15281 | //PA_UTCL1_CNTL2 |
15282 | #define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 |
15283 | #define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 |
15284 | #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
15285 | #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
15286 | #define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb |
15287 | #define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
15288 | #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd |
15289 | #define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
15290 | #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
15291 | #define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 |
15292 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
15293 | #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
15294 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
15295 | #define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
15296 | #define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 |
15297 | #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
15298 | #define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b |
15299 | #define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL |
15300 | #define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L |
15301 | #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
15302 | #define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
15303 | #define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L |
15304 | #define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
15305 | #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L |
15306 | #define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
15307 | #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
15308 | #define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L |
15309 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
15310 | #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
15311 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
15312 | #define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
15313 | #define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L |
15314 | #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
15315 | #define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L |
15316 | //PA_SIDEBAND_REQUEST_DELAYS |
15317 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 |
15318 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 |
15319 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL |
15320 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L |
15321 | //PA_SC_ENHANCE |
15322 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 |
15323 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 |
15324 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 |
15325 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 |
15326 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 |
15327 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 |
15328 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 |
15329 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 |
15330 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 |
15331 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 |
15332 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa |
15333 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb |
15334 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc |
15335 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd |
15336 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe |
15337 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf |
15338 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 |
15339 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 |
15340 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 |
15341 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 |
15342 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 |
15343 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 |
15344 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 |
15345 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 |
15346 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
15347 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 |
15348 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a |
15349 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b |
15350 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c |
15351 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d |
15352 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L |
15353 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L |
15354 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L |
15355 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L |
15356 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L |
15357 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L |
15358 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L |
15359 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L |
15360 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L |
15361 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L |
15362 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L |
15363 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L |
15364 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L |
15365 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L |
15366 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L |
15367 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L |
15368 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L |
15369 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L |
15370 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L |
15371 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L |
15372 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L |
15373 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L |
15374 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L |
15375 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L |
15376 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
15377 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L |
15378 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L |
15379 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L |
15380 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L |
15381 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L |
15382 | //PA_SC_ENHANCE_1 |
15383 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 |
15384 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 |
15385 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 |
15386 | #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 |
15387 | #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 |
15388 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 |
15389 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 |
15390 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 |
15391 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 |
15392 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa |
15393 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb |
15394 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd |
15395 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe |
15396 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf |
15397 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 |
15398 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 |
15399 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 |
15400 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 |
15401 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 |
15402 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 |
15403 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 |
15404 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 |
15405 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
15406 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 |
15407 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a |
15408 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b |
15409 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c |
15410 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d |
15411 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e |
15412 | #define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f |
15413 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L |
15414 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L |
15415 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L |
15416 | #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L |
15417 | #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L |
15418 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L |
15419 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L |
15420 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L |
15421 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L |
15422 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L |
15423 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L |
15424 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L |
15425 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L |
15426 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L |
15427 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L |
15428 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L |
15429 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L |
15430 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L |
15431 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L |
15432 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L |
15433 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L |
15434 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L |
15435 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
15436 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L |
15437 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L |
15438 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L |
15439 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L |
15440 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L |
15441 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L |
15442 | #define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L |
15443 | //PA_SC_DSM_CNTL |
15444 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 |
15445 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 |
15446 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L |
15447 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L |
15448 | //PA_SC_TILE_STEERING_CREST_OVERRIDE |
15449 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 |
15450 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 |
15451 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 |
15452 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L |
15453 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L |
15454 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L |
15455 | |
15456 | |
15457 | // addressBlock: gc_perfddec |
15458 | //CPG_PERFCOUNTER1_LO |
15459 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15460 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15461 | //CPG_PERFCOUNTER1_HI |
15462 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15463 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15464 | //CPG_PERFCOUNTER0_LO |
15465 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15466 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15467 | //CPG_PERFCOUNTER0_HI |
15468 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15469 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15470 | //CPC_PERFCOUNTER1_LO |
15471 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15472 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15473 | //CPC_PERFCOUNTER1_HI |
15474 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15475 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15476 | //CPC_PERFCOUNTER0_LO |
15477 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15478 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15479 | //CPC_PERFCOUNTER0_HI |
15480 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15481 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15482 | //CPF_PERFCOUNTER1_LO |
15483 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15484 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15485 | //CPF_PERFCOUNTER1_HI |
15486 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15487 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15488 | //CPF_PERFCOUNTER0_LO |
15489 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15490 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15491 | //CPF_PERFCOUNTER0_HI |
15492 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15493 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15494 | //CPF_LATENCY_STATS_DATA |
15495 | #define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
15496 | #define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
15497 | //CPG_LATENCY_STATS_DATA |
15498 | #define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
15499 | #define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
15500 | //CPC_LATENCY_STATS_DATA |
15501 | #define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
15502 | #define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
15503 | //GRBM_PERFCOUNTER0_LO |
15504 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15505 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15506 | //GRBM_PERFCOUNTER0_HI |
15507 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15508 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15509 | //GRBM_PERFCOUNTER1_LO |
15510 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15511 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15512 | //GRBM_PERFCOUNTER1_HI |
15513 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15514 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15515 | //GRBM_SE0_PERFCOUNTER_LO |
15516 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15517 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15518 | //GRBM_SE0_PERFCOUNTER_HI |
15519 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15520 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15521 | //GRBM_SE1_PERFCOUNTER_LO |
15522 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15523 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15524 | //GRBM_SE1_PERFCOUNTER_HI |
15525 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15526 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15527 | //GRBM_SE2_PERFCOUNTER_LO |
15528 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15529 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15530 | //GRBM_SE2_PERFCOUNTER_HI |
15531 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15532 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15533 | //GRBM_SE3_PERFCOUNTER_LO |
15534 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15535 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15536 | //GRBM_SE3_PERFCOUNTER_HI |
15537 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15538 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15539 | //WD_PERFCOUNTER0_LO |
15540 | #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15541 | #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15542 | //WD_PERFCOUNTER0_HI |
15543 | #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15544 | #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15545 | //WD_PERFCOUNTER1_LO |
15546 | #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15547 | #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15548 | //WD_PERFCOUNTER1_HI |
15549 | #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15550 | #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15551 | //WD_PERFCOUNTER2_LO |
15552 | #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15553 | #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15554 | //WD_PERFCOUNTER2_HI |
15555 | #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15556 | #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15557 | //WD_PERFCOUNTER3_LO |
15558 | #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15559 | #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15560 | //WD_PERFCOUNTER3_HI |
15561 | #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15562 | #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15563 | //IA_PERFCOUNTER0_LO |
15564 | #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15565 | #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15566 | //IA_PERFCOUNTER0_HI |
15567 | #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15568 | #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15569 | //IA_PERFCOUNTER1_LO |
15570 | #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15571 | #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15572 | //IA_PERFCOUNTER1_HI |
15573 | #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15574 | #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15575 | //IA_PERFCOUNTER2_LO |
15576 | #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15577 | #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15578 | //IA_PERFCOUNTER2_HI |
15579 | #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15580 | #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15581 | //IA_PERFCOUNTER3_LO |
15582 | #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15583 | #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15584 | //IA_PERFCOUNTER3_HI |
15585 | #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15586 | #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15587 | //VGT_PERFCOUNTER0_LO |
15588 | #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15589 | #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15590 | //VGT_PERFCOUNTER0_HI |
15591 | #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15592 | #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15593 | //VGT_PERFCOUNTER1_LO |
15594 | #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15595 | #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15596 | //VGT_PERFCOUNTER1_HI |
15597 | #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15598 | #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15599 | //VGT_PERFCOUNTER2_LO |
15600 | #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15601 | #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15602 | //VGT_PERFCOUNTER2_HI |
15603 | #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15604 | #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15605 | //VGT_PERFCOUNTER3_LO |
15606 | #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15607 | #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15608 | //VGT_PERFCOUNTER3_HI |
15609 | #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15610 | #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15611 | //PA_SU_PERFCOUNTER0_LO |
15612 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15613 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15614 | //PA_SU_PERFCOUNTER0_HI |
15615 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15616 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
15617 | //PA_SU_PERFCOUNTER1_LO |
15618 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15619 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15620 | //PA_SU_PERFCOUNTER1_HI |
15621 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15622 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
15623 | //PA_SU_PERFCOUNTER2_LO |
15624 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15625 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15626 | //PA_SU_PERFCOUNTER2_HI |
15627 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15628 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
15629 | //PA_SU_PERFCOUNTER3_LO |
15630 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15631 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15632 | //PA_SU_PERFCOUNTER3_HI |
15633 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15634 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
15635 | //PA_SC_PERFCOUNTER0_LO |
15636 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15637 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15638 | //PA_SC_PERFCOUNTER0_HI |
15639 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15640 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15641 | //PA_SC_PERFCOUNTER1_LO |
15642 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15643 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15644 | //PA_SC_PERFCOUNTER1_HI |
15645 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15646 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15647 | //PA_SC_PERFCOUNTER2_LO |
15648 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15649 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15650 | //PA_SC_PERFCOUNTER2_HI |
15651 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15652 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15653 | //PA_SC_PERFCOUNTER3_LO |
15654 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15655 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15656 | //PA_SC_PERFCOUNTER3_HI |
15657 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15658 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15659 | //PA_SC_PERFCOUNTER4_LO |
15660 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15661 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15662 | //PA_SC_PERFCOUNTER4_HI |
15663 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15664 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15665 | //PA_SC_PERFCOUNTER5_LO |
15666 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15667 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15668 | //PA_SC_PERFCOUNTER5_HI |
15669 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15670 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15671 | //PA_SC_PERFCOUNTER6_LO |
15672 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15673 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15674 | //PA_SC_PERFCOUNTER6_HI |
15675 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15676 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15677 | //PA_SC_PERFCOUNTER7_LO |
15678 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15679 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15680 | //PA_SC_PERFCOUNTER7_HI |
15681 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15682 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15683 | //SPI_PERFCOUNTER0_HI |
15684 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15685 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15686 | //SPI_PERFCOUNTER0_LO |
15687 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15688 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15689 | //SPI_PERFCOUNTER1_HI |
15690 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15691 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15692 | //SPI_PERFCOUNTER1_LO |
15693 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15694 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15695 | //SPI_PERFCOUNTER2_HI |
15696 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15697 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15698 | //SPI_PERFCOUNTER2_LO |
15699 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15700 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15701 | //SPI_PERFCOUNTER3_HI |
15702 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15703 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15704 | //SPI_PERFCOUNTER3_LO |
15705 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15706 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15707 | //SPI_PERFCOUNTER4_HI |
15708 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15709 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15710 | //SPI_PERFCOUNTER4_LO |
15711 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15712 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15713 | //SPI_PERFCOUNTER5_HI |
15714 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15715 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15716 | //SPI_PERFCOUNTER5_LO |
15717 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15718 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15719 | //SQ_PERFCOUNTER0_LO |
15720 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15721 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15722 | //SQ_PERFCOUNTER0_HI |
15723 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15724 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15725 | //SQ_PERFCOUNTER1_LO |
15726 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15727 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15728 | //SQ_PERFCOUNTER1_HI |
15729 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15730 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15731 | //SQ_PERFCOUNTER2_LO |
15732 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15733 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15734 | //SQ_PERFCOUNTER2_HI |
15735 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15736 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15737 | //SQ_PERFCOUNTER3_LO |
15738 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15739 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15740 | //SQ_PERFCOUNTER3_HI |
15741 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15742 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15743 | //SQ_PERFCOUNTER4_LO |
15744 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15745 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15746 | //SQ_PERFCOUNTER4_HI |
15747 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15748 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15749 | //SQ_PERFCOUNTER5_LO |
15750 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15751 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15752 | //SQ_PERFCOUNTER5_HI |
15753 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15754 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15755 | //SQ_PERFCOUNTER6_LO |
15756 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15757 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15758 | //SQ_PERFCOUNTER6_HI |
15759 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15760 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15761 | //SQ_PERFCOUNTER7_LO |
15762 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15763 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15764 | //SQ_PERFCOUNTER7_HI |
15765 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15766 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15767 | //SQ_PERFCOUNTER8_LO |
15768 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15769 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15770 | //SQ_PERFCOUNTER8_HI |
15771 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15772 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15773 | //SQ_PERFCOUNTER9_LO |
15774 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15775 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15776 | //SQ_PERFCOUNTER9_HI |
15777 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15778 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15779 | //SQ_PERFCOUNTER10_LO |
15780 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15781 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15782 | //SQ_PERFCOUNTER10_HI |
15783 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15784 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15785 | //SQ_PERFCOUNTER11_LO |
15786 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15787 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15788 | //SQ_PERFCOUNTER11_HI |
15789 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15790 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15791 | //SQ_PERFCOUNTER12_LO |
15792 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15793 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15794 | //SQ_PERFCOUNTER12_HI |
15795 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15796 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15797 | //SQ_PERFCOUNTER13_LO |
15798 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15799 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15800 | //SQ_PERFCOUNTER13_HI |
15801 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15802 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15803 | //SQ_PERFCOUNTER14_LO |
15804 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15805 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15806 | //SQ_PERFCOUNTER14_HI |
15807 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15808 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15809 | //SQ_PERFCOUNTER15_LO |
15810 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15811 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15812 | //SQ_PERFCOUNTER15_HI |
15813 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15814 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15815 | //SX_PERFCOUNTER0_LO |
15816 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15817 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15818 | //SX_PERFCOUNTER0_HI |
15819 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15820 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15821 | //SX_PERFCOUNTER1_LO |
15822 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15823 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15824 | //SX_PERFCOUNTER1_HI |
15825 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15826 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15827 | //SX_PERFCOUNTER2_LO |
15828 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15829 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15830 | //SX_PERFCOUNTER2_HI |
15831 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15832 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15833 | //SX_PERFCOUNTER3_LO |
15834 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15835 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15836 | //SX_PERFCOUNTER3_HI |
15837 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15838 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15839 | //GDS_PERFCOUNTER0_LO |
15840 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15841 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15842 | //GDS_PERFCOUNTER0_HI |
15843 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15844 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15845 | //GDS_PERFCOUNTER1_LO |
15846 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15847 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15848 | //GDS_PERFCOUNTER1_HI |
15849 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15850 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15851 | //GDS_PERFCOUNTER2_LO |
15852 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15853 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15854 | //GDS_PERFCOUNTER2_HI |
15855 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15856 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15857 | //GDS_PERFCOUNTER3_LO |
15858 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15859 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15860 | //GDS_PERFCOUNTER3_HI |
15861 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15862 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15863 | //TA_PERFCOUNTER0_LO |
15864 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15865 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15866 | //TA_PERFCOUNTER0_HI |
15867 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15868 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15869 | //TA_PERFCOUNTER1_LO |
15870 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15871 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15872 | //TA_PERFCOUNTER1_HI |
15873 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15874 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15875 | //TD_PERFCOUNTER0_LO |
15876 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15877 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15878 | //TD_PERFCOUNTER0_HI |
15879 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15880 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15881 | //TD_PERFCOUNTER1_LO |
15882 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15883 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15884 | //TD_PERFCOUNTER1_HI |
15885 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15886 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15887 | //TCP_PERFCOUNTER0_LO |
15888 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15889 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15890 | //TCP_PERFCOUNTER0_HI |
15891 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15892 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15893 | //TCP_PERFCOUNTER1_LO |
15894 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15895 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15896 | //TCP_PERFCOUNTER1_HI |
15897 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15898 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15899 | //TCP_PERFCOUNTER2_LO |
15900 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15901 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15902 | //TCP_PERFCOUNTER2_HI |
15903 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15904 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15905 | //TCP_PERFCOUNTER3_LO |
15906 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15907 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15908 | //TCP_PERFCOUNTER3_HI |
15909 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15910 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15911 | //TCC_PERFCOUNTER0_LO |
15912 | #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15913 | #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15914 | //TCC_PERFCOUNTER0_HI |
15915 | #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15916 | #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15917 | //TCC_PERFCOUNTER1_LO |
15918 | #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15919 | #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15920 | //TCC_PERFCOUNTER1_HI |
15921 | #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15922 | #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15923 | //TCC_PERFCOUNTER2_LO |
15924 | #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15925 | #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15926 | //TCC_PERFCOUNTER2_HI |
15927 | #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15928 | #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15929 | //TCC_PERFCOUNTER3_LO |
15930 | #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15931 | #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15932 | //TCC_PERFCOUNTER3_HI |
15933 | #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15934 | #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15935 | //TCA_PERFCOUNTER0_LO |
15936 | #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15937 | #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15938 | //TCA_PERFCOUNTER0_HI |
15939 | #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15940 | #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15941 | //TCA_PERFCOUNTER1_LO |
15942 | #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15943 | #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15944 | //TCA_PERFCOUNTER1_HI |
15945 | #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15946 | #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15947 | //TCA_PERFCOUNTER2_LO |
15948 | #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15949 | #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15950 | //TCA_PERFCOUNTER2_HI |
15951 | #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15952 | #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15953 | //TCA_PERFCOUNTER3_LO |
15954 | #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15955 | #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15956 | //TCA_PERFCOUNTER3_HI |
15957 | #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15958 | #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15959 | //CB_PERFCOUNTER0_LO |
15960 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15961 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15962 | //CB_PERFCOUNTER0_HI |
15963 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15964 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15965 | //CB_PERFCOUNTER1_LO |
15966 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15967 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15968 | //CB_PERFCOUNTER1_HI |
15969 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15970 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15971 | //CB_PERFCOUNTER2_LO |
15972 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15973 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15974 | //CB_PERFCOUNTER2_HI |
15975 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15976 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15977 | //CB_PERFCOUNTER3_LO |
15978 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15979 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15980 | //CB_PERFCOUNTER3_HI |
15981 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15982 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15983 | //DB_PERFCOUNTER0_LO |
15984 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15985 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15986 | //DB_PERFCOUNTER0_HI |
15987 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15988 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15989 | //DB_PERFCOUNTER1_LO |
15990 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15991 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15992 | //DB_PERFCOUNTER1_HI |
15993 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15994 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15995 | //DB_PERFCOUNTER2_LO |
15996 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15997 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15998 | //DB_PERFCOUNTER2_HI |
15999 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16000 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16001 | //DB_PERFCOUNTER3_LO |
16002 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16003 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16004 | //DB_PERFCOUNTER3_HI |
16005 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16006 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16007 | //RLC_PERFCOUNTER0_LO |
16008 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16009 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16010 | //RLC_PERFCOUNTER0_HI |
16011 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16012 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16013 | //RLC_PERFCOUNTER1_LO |
16014 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16015 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16016 | //RLC_PERFCOUNTER1_HI |
16017 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16018 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16019 | //RMI_PERFCOUNTER0_LO |
16020 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16021 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16022 | //RMI_PERFCOUNTER0_HI |
16023 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16024 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16025 | //RMI_PERFCOUNTER1_LO |
16026 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16027 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16028 | //RMI_PERFCOUNTER1_HI |
16029 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16030 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16031 | //RMI_PERFCOUNTER2_LO |
16032 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16033 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16034 | //RMI_PERFCOUNTER2_HI |
16035 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16036 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16037 | //RMI_PERFCOUNTER3_LO |
16038 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
16039 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
16040 | //RMI_PERFCOUNTER3_HI |
16041 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
16042 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
16043 | |
16044 | |
16045 | // addressBlock: gc_perfsdec |
16046 | //CPG_PERFCOUNTER1_SELECT |
16047 | #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 |
16048 | #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa |
16049 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
16050 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
16051 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
16052 | #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16053 | #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16054 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
16055 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16056 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16057 | //CPG_PERFCOUNTER0_SELECT1 |
16058 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 |
16059 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa |
16060 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
16061 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
16062 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL |
16063 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L |
16064 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
16065 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
16066 | //CPG_PERFCOUNTER0_SELECT |
16067 | #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 |
16068 | #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa |
16069 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
16070 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
16071 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
16072 | #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16073 | #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16074 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
16075 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16076 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16077 | //CPC_PERFCOUNTER1_SELECT |
16078 | #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 |
16079 | #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa |
16080 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
16081 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
16082 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
16083 | #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16084 | #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16085 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
16086 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16087 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16088 | //CPC_PERFCOUNTER0_SELECT1 |
16089 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 |
16090 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa |
16091 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
16092 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
16093 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL |
16094 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L |
16095 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
16096 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
16097 | //CPF_PERFCOUNTER1_SELECT |
16098 | #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 |
16099 | #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa |
16100 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
16101 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
16102 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
16103 | #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16104 | #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16105 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
16106 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16107 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16108 | //CPF_PERFCOUNTER0_SELECT1 |
16109 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 |
16110 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa |
16111 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
16112 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
16113 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL |
16114 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L |
16115 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
16116 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
16117 | //CPF_PERFCOUNTER0_SELECT |
16118 | #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 |
16119 | #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa |
16120 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
16121 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
16122 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
16123 | #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16124 | #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16125 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
16126 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16127 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16128 | //CP_PERFMON_CNTL |
16129 | #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
16130 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 |
16131 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 |
16132 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
16133 | #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL |
16134 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L |
16135 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L |
16136 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
16137 | //CPC_PERFCOUNTER0_SELECT |
16138 | #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 |
16139 | #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa |
16140 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
16141 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
16142 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
16143 | #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL |
16144 | #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L |
16145 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
16146 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
16147 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
16148 | //CPF_TC_PERF_COUNTER_WINDOW_SELECT |
16149 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
16150 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
16151 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
16152 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L |
16153 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
16154 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
16155 | //CPG_TC_PERF_COUNTER_WINDOW_SELECT |
16156 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
16157 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
16158 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
16159 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL |
16160 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
16161 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
16162 | //CPF_LATENCY_STATS_SELECT |
16163 | #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
16164 | #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
16165 | #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
16166 | #define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
16167 | #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
16168 | #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
16169 | //CPG_LATENCY_STATS_SELECT |
16170 | #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
16171 | #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
16172 | #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
16173 | #define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL |
16174 | #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
16175 | #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
16176 | //CPC_LATENCY_STATS_SELECT |
16177 | #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
16178 | #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
16179 | #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
16180 | #define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L |
16181 | #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
16182 | #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
16183 | //CP_DRAW_OBJECT |
16184 | #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 |
16185 | #define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL |
16186 | //CP_DRAW_OBJECT_COUNTER |
16187 | #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 |
16188 | #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL |
16189 | //CP_DRAW_WINDOW_MASK_HI |
16190 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 |
16191 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL |
16192 | //CP_DRAW_WINDOW_HI |
16193 | #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 |
16194 | #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL |
16195 | //CP_DRAW_WINDOW_LO |
16196 | #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 |
16197 | #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 |
16198 | #define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL |
16199 | #define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L |
16200 | //CP_DRAW_WINDOW_CNTL |
16201 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 |
16202 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 |
16203 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 |
16204 | #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 |
16205 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L |
16206 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L |
16207 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L |
16208 | #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L |
16209 | //GRBM_PERFCOUNTER0_SELECT |
16210 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16211 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16212 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16213 | #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16214 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16215 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
16216 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16217 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16218 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16219 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16220 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16221 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16222 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16223 | #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
16224 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
16225 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
16226 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
16227 | #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
16228 | #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
16229 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
16230 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
16231 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
16232 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL |
16233 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16234 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16235 | #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16236 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16237 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
16238 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16239 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16240 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16241 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16242 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16243 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16244 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16245 | #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
16246 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
16247 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
16248 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
16249 | #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
16250 | #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
16251 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
16252 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
16253 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
16254 | //GRBM_PERFCOUNTER1_SELECT |
16255 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16256 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16257 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16258 | #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16259 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16260 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
16261 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16262 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16263 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16264 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16265 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16266 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16267 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16268 | #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
16269 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
16270 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
16271 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
16272 | #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
16273 | #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
16274 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
16275 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
16276 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
16277 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL |
16278 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16279 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16280 | #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16281 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16282 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
16283 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16284 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16285 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16286 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16287 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16288 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16289 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16290 | #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
16291 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
16292 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
16293 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
16294 | #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
16295 | #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
16296 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
16297 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
16298 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
16299 | //GRBM_SE0_PERFCOUNTER_SELECT |
16300 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
16301 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16302 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16303 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16304 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16305 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
16306 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16307 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16308 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16309 | #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16310 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16311 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16312 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16313 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x17 |
16314 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x18 |
16315 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4__SHIFT 0x19 |
16316 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
16317 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16318 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16319 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16320 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16321 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
16322 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16323 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16324 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16325 | #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16326 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16327 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16328 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16329 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE4_MASK 0x00800000L |
16330 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE4_MASK 0x01000000L |
16331 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE4_MASK 0x02000000L |
16332 | //GRBM_SE1_PERFCOUNTER_SELECT |
16333 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
16334 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16335 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16336 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16337 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16338 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
16339 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16340 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16341 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16342 | #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16343 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16344 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16345 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16346 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x17 |
16347 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x18 |
16348 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5__SHIFT 0x19 |
16349 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
16350 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16351 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16352 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16353 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16354 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
16355 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16356 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16357 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16358 | #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16359 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16360 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16361 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16362 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE5_MASK 0x00800000L |
16363 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE5_MASK 0x01000000L |
16364 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE5_MASK 0x02000000L |
16365 | //GRBM_SE2_PERFCOUNTER_SELECT |
16366 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
16367 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16368 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16369 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16370 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16371 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
16372 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16373 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16374 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16375 | #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16376 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16377 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16378 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16379 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x17 |
16380 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x18 |
16381 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6__SHIFT 0x19 |
16382 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
16383 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16384 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16385 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16386 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16387 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
16388 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16389 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16390 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16391 | #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16392 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16393 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16394 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16395 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE6_MASK 0x00800000L |
16396 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE6_MASK 0x01000000L |
16397 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE6_MASK 0x02000000L |
16398 | //GRBM_SE3_PERFCOUNTER_SELECT |
16399 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
16400 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
16401 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
16402 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
16403 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
16404 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
16405 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
16406 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
16407 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
16408 | #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
16409 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
16410 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
16411 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
16412 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x17 |
16413 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x18 |
16414 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7__SHIFT 0x19 |
16415 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
16416 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
16417 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
16418 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
16419 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
16420 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
16421 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
16422 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
16423 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
16424 | #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
16425 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
16426 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
16427 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
16428 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_SE7_MASK 0x00800000L |
16429 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_SE7_MASK 0x01000000L |
16430 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_SE7_MASK 0x02000000L |
16431 | //WD_PERFCOUNTER0_SELECT |
16432 | #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16433 | #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16434 | #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL |
16435 | #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16436 | //WD_PERFCOUNTER1_SELECT |
16437 | #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16438 | #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16439 | #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
16440 | #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16441 | //WD_PERFCOUNTER2_SELECT |
16442 | #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16443 | #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16444 | #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL |
16445 | #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16446 | //WD_PERFCOUNTER3_SELECT |
16447 | #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16448 | #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16449 | #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL |
16450 | #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16451 | //IA_PERFCOUNTER0_SELECT |
16452 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16453 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16454 | #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16455 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16456 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16457 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16458 | #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16459 | #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16460 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16461 | #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16462 | //IA_PERFCOUNTER1_SELECT |
16463 | #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16464 | #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16465 | #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
16466 | #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16467 | //IA_PERFCOUNTER2_SELECT |
16468 | #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16469 | #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16470 | #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL |
16471 | #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16472 | //IA_PERFCOUNTER3_SELECT |
16473 | #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16474 | #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16475 | #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL |
16476 | #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16477 | //IA_PERFCOUNTER0_SELECT1 |
16478 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
16479 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
16480 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
16481 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
16482 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16483 | #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16484 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16485 | #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16486 | //VGT_PERFCOUNTER0_SELECT |
16487 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16488 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16489 | #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16490 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16491 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16492 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16493 | #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16494 | #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16495 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16496 | #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16497 | //VGT_PERFCOUNTER1_SELECT |
16498 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16499 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
16500 | #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
16501 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
16502 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16503 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
16504 | #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16505 | #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
16506 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
16507 | #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16508 | //VGT_PERFCOUNTER2_SELECT |
16509 | #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16510 | #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16511 | #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL |
16512 | #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16513 | //VGT_PERFCOUNTER3_SELECT |
16514 | #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16515 | #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16516 | #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL |
16517 | #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16518 | //VGT_PERFCOUNTER0_SELECT1 |
16519 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
16520 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
16521 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
16522 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
16523 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16524 | #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16525 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16526 | #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16527 | //VGT_PERFCOUNTER1_SELECT1 |
16528 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
16529 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
16530 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
16531 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
16532 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16533 | #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16534 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16535 | #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16536 | //VGT_PERFCOUNTER_SEID_MASK |
16537 | #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 |
16538 | #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL |
16539 | //PA_SU_PERFCOUNTER0_SELECT |
16540 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16541 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16542 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16543 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16544 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16545 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16546 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16547 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16548 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16549 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16550 | //PA_SU_PERFCOUNTER0_SELECT1 |
16551 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
16552 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
16553 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
16554 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
16555 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16556 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16557 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16558 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16559 | //PA_SU_PERFCOUNTER1_SELECT |
16560 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16561 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
16562 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
16563 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
16564 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16565 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
16566 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16567 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
16568 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
16569 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16570 | //PA_SU_PERFCOUNTER1_SELECT1 |
16571 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
16572 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
16573 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
16574 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
16575 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16576 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16577 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16578 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16579 | //PA_SU_PERFCOUNTER2_SELECT |
16580 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16581 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
16582 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16583 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
16584 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
16585 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16586 | //PA_SU_PERFCOUNTER3_SELECT |
16587 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16588 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
16589 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16590 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
16591 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
16592 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16593 | //PA_SC_PERFCOUNTER0_SELECT |
16594 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16595 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16596 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16597 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16598 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16599 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16600 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16601 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16602 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16603 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16604 | //PA_SC_PERFCOUNTER0_SELECT1 |
16605 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
16606 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
16607 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
16608 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
16609 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16610 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16611 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16612 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16613 | //PA_SC_PERFCOUNTER1_SELECT |
16614 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16615 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
16616 | //PA_SC_PERFCOUNTER2_SELECT |
16617 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16618 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
16619 | //PA_SC_PERFCOUNTER3_SELECT |
16620 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16621 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
16622 | //PA_SC_PERFCOUNTER4_SELECT |
16623 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
16624 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
16625 | //PA_SC_PERFCOUNTER5_SELECT |
16626 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
16627 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
16628 | //PA_SC_PERFCOUNTER6_SELECT |
16629 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
16630 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
16631 | //PA_SC_PERFCOUNTER7_SELECT |
16632 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
16633 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
16634 | //SPI_PERFCOUNTER0_SELECT |
16635 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16636 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16637 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16638 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16639 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16640 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16641 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16642 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16643 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16644 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16645 | //SPI_PERFCOUNTER1_SELECT |
16646 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16647 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
16648 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
16649 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
16650 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16651 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
16652 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16653 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
16654 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
16655 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16656 | //SPI_PERFCOUNTER2_SELECT |
16657 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16658 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
16659 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
16660 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
16661 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16662 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
16663 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16664 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
16665 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
16666 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16667 | //SPI_PERFCOUNTER3_SELECT |
16668 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16669 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
16670 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
16671 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
16672 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16673 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
16674 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16675 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
16676 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
16677 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16678 | //SPI_PERFCOUNTER0_SELECT1 |
16679 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
16680 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
16681 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
16682 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
16683 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16684 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16685 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16686 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16687 | //SPI_PERFCOUNTER1_SELECT1 |
16688 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
16689 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
16690 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
16691 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
16692 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16693 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16694 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16695 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16696 | //SPI_PERFCOUNTER2_SELECT1 |
16697 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
16698 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
16699 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
16700 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
16701 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16702 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16703 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16704 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16705 | //SPI_PERFCOUNTER3_SELECT1 |
16706 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
16707 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
16708 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
16709 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
16710 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
16711 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
16712 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
16713 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
16714 | //SPI_PERFCOUNTER4_SELECT |
16715 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
16716 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL |
16717 | //SPI_PERFCOUNTER5_SELECT |
16718 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
16719 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL |
16720 | //SPI_PERFCOUNTER_BINS |
16721 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 |
16722 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 |
16723 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 |
16724 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc |
16725 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 |
16726 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 |
16727 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 |
16728 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c |
16729 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL |
16730 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L |
16731 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L |
16732 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L |
16733 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L |
16734 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L |
16735 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L |
16736 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L |
16737 | //SQ_PERFCOUNTER0_SELECT |
16738 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16739 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16740 | #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16741 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
16742 | #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 |
16743 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16744 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
16745 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16746 | #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16747 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
16748 | #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L |
16749 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16750 | //SQ_PERFCOUNTER1_SELECT |
16751 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16752 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16753 | #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16754 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
16755 | #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 |
16756 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16757 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
16758 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16759 | #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16760 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
16761 | #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L |
16762 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16763 | //SQ_PERFCOUNTER2_SELECT |
16764 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16765 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16766 | #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16767 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 |
16768 | #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 |
16769 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
16770 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
16771 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16772 | #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16773 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L |
16774 | #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L |
16775 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
16776 | //SQ_PERFCOUNTER3_SELECT |
16777 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
16778 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16779 | #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16780 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 |
16781 | #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 |
16782 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
16783 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
16784 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16785 | #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16786 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L |
16787 | #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L |
16788 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
16789 | //SQ_PERFCOUNTER4_SELECT |
16790 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
16791 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16792 | #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16793 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 |
16794 | #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 |
16795 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
16796 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL |
16797 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16798 | #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16799 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L |
16800 | #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L |
16801 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
16802 | //SQ_PERFCOUNTER5_SELECT |
16803 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
16804 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16805 | #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16806 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 |
16807 | #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 |
16808 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
16809 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL |
16810 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16811 | #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16812 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L |
16813 | #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L |
16814 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
16815 | //SQ_PERFCOUNTER6_SELECT |
16816 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
16817 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16818 | #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16819 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 |
16820 | #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 |
16821 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
16822 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL |
16823 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16824 | #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16825 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L |
16826 | #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L |
16827 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
16828 | //SQ_PERFCOUNTER7_SELECT |
16829 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
16830 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16831 | #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16832 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 |
16833 | #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 |
16834 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
16835 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL |
16836 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16837 | #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16838 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L |
16839 | #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L |
16840 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
16841 | //SQ_PERFCOUNTER8_SELECT |
16842 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 |
16843 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16844 | #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16845 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 |
16846 | #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 |
16847 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c |
16848 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL |
16849 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16850 | #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16851 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L |
16852 | #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L |
16853 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L |
16854 | //SQ_PERFCOUNTER9_SELECT |
16855 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 |
16856 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16857 | #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16858 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 |
16859 | #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 |
16860 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c |
16861 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL |
16862 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16863 | #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16864 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L |
16865 | #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L |
16866 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L |
16867 | //SQ_PERFCOUNTER10_SELECT |
16868 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 |
16869 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16870 | #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16871 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 |
16872 | #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 |
16873 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c |
16874 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL |
16875 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16876 | #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16877 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L |
16878 | #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L |
16879 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L |
16880 | //SQ_PERFCOUNTER11_SELECT |
16881 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 |
16882 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16883 | #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16884 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 |
16885 | #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 |
16886 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c |
16887 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL |
16888 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16889 | #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16890 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L |
16891 | #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L |
16892 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L |
16893 | //SQ_PERFCOUNTER12_SELECT |
16894 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 |
16895 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16896 | #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16897 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 |
16898 | #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 |
16899 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c |
16900 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL |
16901 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16902 | #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16903 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L |
16904 | #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L |
16905 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L |
16906 | //SQ_PERFCOUNTER13_SELECT |
16907 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 |
16908 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16909 | #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16910 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 |
16911 | #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 |
16912 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c |
16913 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL |
16914 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16915 | #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16916 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L |
16917 | #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L |
16918 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L |
16919 | //SQ_PERFCOUNTER14_SELECT |
16920 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 |
16921 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16922 | #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16923 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 |
16924 | #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 |
16925 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c |
16926 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL |
16927 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16928 | #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16929 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L |
16930 | #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L |
16931 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L |
16932 | //SQ_PERFCOUNTER15_SELECT |
16933 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 |
16934 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc |
16935 | #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 |
16936 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 |
16937 | #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 |
16938 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c |
16939 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL |
16940 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
16941 | #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L |
16942 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L |
16943 | #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L |
16944 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L |
16945 | //SQ_PERFCOUNTER_CTRL |
16946 | #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 |
16947 | #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 |
16948 | #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 |
16949 | #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 |
16950 | #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 |
16951 | #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 |
16952 | #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 |
16953 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 |
16954 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd |
16955 | #define SQ_PERFCOUNTER_CTRL__VMID_MASK__SHIFT 0x10 |
16956 | #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L |
16957 | #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L |
16958 | #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L |
16959 | #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L |
16960 | #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L |
16961 | #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L |
16962 | #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L |
16963 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L |
16964 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L |
16965 | #define SQ_PERFCOUNTER_CTRL__VMID_MASK_MASK 0xFFFF0000L |
16966 | //SQ_PERFCOUNTER_MASK |
16967 | #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 |
16968 | #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 |
16969 | #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL |
16970 | #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L |
16971 | //SQ_PERFCOUNTER_CTRL2 |
16972 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 |
16973 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L |
16974 | //SX_PERFCOUNTER0_SELECT |
16975 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
16976 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
16977 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
16978 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
16979 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
16980 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
16981 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16982 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
16983 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
16984 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
16985 | //SX_PERFCOUNTER1_SELECT |
16986 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
16987 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
16988 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
16989 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
16990 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
16991 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
16992 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
16993 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
16994 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
16995 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
16996 | //SX_PERFCOUNTER2_SELECT |
16997 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
16998 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
16999 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17000 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17001 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17002 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17003 | //SX_PERFCOUNTER3_SELECT |
17004 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17005 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17006 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17007 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17008 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17009 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17010 | //SX_PERFCOUNTER0_SELECT1 |
17011 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17012 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17013 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17014 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17015 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17016 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17017 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17018 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17019 | //SX_PERFCOUNTER1_SELECT1 |
17020 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
17021 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
17022 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
17023 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
17024 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17025 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17026 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17027 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17028 | //GDS_PERFCOUNTER0_SELECT |
17029 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17030 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17031 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17032 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17033 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17034 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
17035 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17036 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17037 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17038 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17039 | //GDS_PERFCOUNTER1_SELECT |
17040 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17041 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
17042 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17043 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
17044 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17045 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
17046 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17047 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17048 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
17049 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17050 | //GDS_PERFCOUNTER2_SELECT |
17051 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17052 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
17053 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17054 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
17055 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17056 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17057 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17058 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17059 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
17060 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17061 | //GDS_PERFCOUNTER3_SELECT |
17062 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17063 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
17064 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17065 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
17066 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17067 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17068 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17069 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17070 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
17071 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17072 | //GDS_PERFCOUNTER0_SELECT1 |
17073 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17074 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17075 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17076 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17077 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17078 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17079 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17080 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17081 | //TA_PERFCOUNTER0_SELECT |
17082 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17083 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17084 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17085 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17086 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17087 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL |
17088 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L |
17089 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17090 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17091 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17092 | //TA_PERFCOUNTER0_SELECT1 |
17093 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17094 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17095 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17096 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17097 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL |
17098 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L |
17099 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17100 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17101 | //TA_PERFCOUNTER1_SELECT |
17102 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17103 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17104 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17105 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
17106 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17107 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17108 | //TD_PERFCOUNTER0_SELECT |
17109 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17110 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17111 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17112 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17113 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17114 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL |
17115 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L |
17116 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17117 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17118 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17119 | //TD_PERFCOUNTER0_SELECT1 |
17120 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17121 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17122 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17123 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17124 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL |
17125 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L |
17126 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17127 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17128 | //TD_PERFCOUNTER1_SELECT |
17129 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17130 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17131 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17132 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
17133 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17134 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17135 | //TCP_PERFCOUNTER0_SELECT |
17136 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17137 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17138 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17139 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17140 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17141 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
17142 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17143 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17144 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17145 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17146 | //TCP_PERFCOUNTER0_SELECT1 |
17147 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17148 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17149 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17150 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17151 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17152 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17153 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17154 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17155 | //TCP_PERFCOUNTER1_SELECT |
17156 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17157 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
17158 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17159 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
17160 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17161 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
17162 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17163 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17164 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
17165 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17166 | //TCP_PERFCOUNTER1_SELECT1 |
17167 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
17168 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
17169 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
17170 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
17171 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17172 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17173 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17174 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17175 | //TCP_PERFCOUNTER2_SELECT |
17176 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17177 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17178 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17179 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17180 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17181 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17182 | //TCP_PERFCOUNTER3_SELECT |
17183 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17184 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17185 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17186 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17187 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17188 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17189 | //TCC_PERFCOUNTER0_SELECT |
17190 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17191 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17192 | #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17193 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17194 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17195 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
17196 | #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17197 | #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17198 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17199 | #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17200 | //TCC_PERFCOUNTER0_SELECT1 |
17201 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17202 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17203 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
17204 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
17205 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17206 | #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17207 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
17208 | #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
17209 | //TCC_PERFCOUNTER1_SELECT |
17210 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17211 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
17212 | #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17213 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
17214 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17215 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
17216 | #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17217 | #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17218 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
17219 | #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17220 | //TCC_PERFCOUNTER1_SELECT1 |
17221 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
17222 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
17223 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
17224 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
17225 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17226 | #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17227 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
17228 | #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
17229 | //TCC_PERFCOUNTER2_SELECT |
17230 | #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17231 | #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17232 | #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17233 | #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17234 | #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17235 | #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17236 | //TCC_PERFCOUNTER3_SELECT |
17237 | #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17238 | #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17239 | #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17240 | #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17241 | #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17242 | #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17243 | //TCA_PERFCOUNTER0_SELECT |
17244 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17245 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17246 | #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17247 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17248 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17249 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
17250 | #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17251 | #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17252 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17253 | #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17254 | //TCA_PERFCOUNTER0_SELECT1 |
17255 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17256 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17257 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
17258 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
17259 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17260 | #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17261 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
17262 | #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
17263 | //TCA_PERFCOUNTER1_SELECT |
17264 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17265 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
17266 | #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17267 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
17268 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17269 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
17270 | #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17271 | #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17272 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
17273 | #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17274 | //TCA_PERFCOUNTER1_SELECT1 |
17275 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
17276 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
17277 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
17278 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
17279 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17280 | #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17281 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
17282 | #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
17283 | //TCA_PERFCOUNTER2_SELECT |
17284 | #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17285 | #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17286 | #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17287 | #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17288 | #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17289 | #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17290 | //TCA_PERFCOUNTER3_SELECT |
17291 | #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17292 | #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17293 | #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17294 | #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17295 | #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17296 | #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17297 | //CB_PERFCOUNTER_FILTER |
17298 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 |
17299 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 |
17300 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 |
17301 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 |
17302 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa |
17303 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb |
17304 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc |
17305 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd |
17306 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 |
17307 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 |
17308 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 |
17309 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 |
17310 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L |
17311 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL |
17312 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L |
17313 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L |
17314 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L |
17315 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L |
17316 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L |
17317 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L |
17318 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L |
17319 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L |
17320 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L |
17321 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L |
17322 | //CB_PERFCOUNTER0_SELECT |
17323 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17324 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17325 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17326 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17327 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17328 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
17329 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
17330 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17331 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17332 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17333 | //CB_PERFCOUNTER0_SELECT1 |
17334 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17335 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17336 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17337 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17338 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
17339 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
17340 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17341 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17342 | //CB_PERFCOUNTER1_SELECT |
17343 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17344 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17345 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
17346 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17347 | //CB_PERFCOUNTER2_SELECT |
17348 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17349 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17350 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
17351 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17352 | //CB_PERFCOUNTER3_SELECT |
17353 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17354 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17355 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
17356 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17357 | //DB_PERFCOUNTER0_SELECT |
17358 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17359 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17360 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17361 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17362 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17363 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
17364 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17365 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17366 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17367 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17368 | //DB_PERFCOUNTER0_SELECT1 |
17369 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17370 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17371 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17372 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17373 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17374 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17375 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17376 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17377 | //DB_PERFCOUNTER1_SELECT |
17378 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17379 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
17380 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
17381 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
17382 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17383 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
17384 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17385 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
17386 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
17387 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17388 | //DB_PERFCOUNTER1_SELECT1 |
17389 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
17390 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
17391 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
17392 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
17393 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
17394 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
17395 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17396 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17397 | //DB_PERFCOUNTER2_SELECT |
17398 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17399 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
17400 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17401 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
17402 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17403 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
17404 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17405 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17406 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
17407 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17408 | //DB_PERFCOUNTER3_SELECT |
17409 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17410 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
17411 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
17412 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
17413 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17414 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
17415 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
17416 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
17417 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
17418 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17419 | //RLC_SPM_PERFMON_CNTL |
17420 | #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 |
17421 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc |
17422 | #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe |
17423 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 |
17424 | #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL |
17425 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L |
17426 | #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L |
17427 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
17428 | //RLC_SPM_PERFMON_RING_BASE_LO |
17429 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 |
17430 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL |
17431 | //RLC_SPM_PERFMON_RING_BASE_HI |
17432 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 |
17433 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 |
17434 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL |
17435 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L |
17436 | //RLC_SPM_PERFMON_RING_SIZE |
17437 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 |
17438 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL |
17439 | //RLC_SPM_PERFMON_SEGMENT_SIZE |
17440 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
17441 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 |
17442 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb |
17443 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 |
17444 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 |
17445 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a |
17446 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f |
17447 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
17448 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L |
17449 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L |
17450 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L |
17451 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L |
17452 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L |
17453 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L |
17454 | //RLC_SPM_SE_MUXSEL_ADDR |
17455 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
17456 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL |
17457 | //RLC_SPM_SE_MUXSEL_DATA |
17458 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
17459 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
17460 | //RLC_SPM_CPG_PERFMON_SAMPLE_DELAY |
17461 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17462 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17463 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17464 | #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17465 | //RLC_SPM_CPC_PERFMON_SAMPLE_DELAY |
17466 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17467 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17468 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17469 | #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17470 | //RLC_SPM_CPF_PERFMON_SAMPLE_DELAY |
17471 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17472 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17473 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17474 | #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17475 | //RLC_SPM_CB_PERFMON_SAMPLE_DELAY |
17476 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17477 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17478 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17479 | #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17480 | //RLC_SPM_DB_PERFMON_SAMPLE_DELAY |
17481 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17482 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17483 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17484 | #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17485 | //RLC_SPM_PA_PERFMON_SAMPLE_DELAY |
17486 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17487 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17488 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17489 | #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17490 | //RLC_SPM_GDS_PERFMON_SAMPLE_DELAY |
17491 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17492 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17493 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17494 | #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17495 | //RLC_SPM_IA_PERFMON_SAMPLE_DELAY |
17496 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17497 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17498 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17499 | #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17500 | //RLC_SPM_SC_PERFMON_SAMPLE_DELAY |
17501 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17502 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17503 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17504 | #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17505 | //RLC_SPM_TCC_PERFMON_SAMPLE_DELAY |
17506 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17507 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17508 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17509 | #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17510 | //RLC_SPM_TCA_PERFMON_SAMPLE_DELAY |
17511 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17512 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17513 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17514 | #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17515 | //RLC_SPM_TCP_PERFMON_SAMPLE_DELAY |
17516 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17517 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17518 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17519 | #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17520 | //RLC_SPM_TA_PERFMON_SAMPLE_DELAY |
17521 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17522 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17523 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17524 | #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17525 | //RLC_SPM_TD_PERFMON_SAMPLE_DELAY |
17526 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17527 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17528 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17529 | #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17530 | //RLC_SPM_VGT_PERFMON_SAMPLE_DELAY |
17531 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17532 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17533 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17534 | #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17535 | //RLC_SPM_SPI_PERFMON_SAMPLE_DELAY |
17536 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17537 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17538 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17539 | #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17540 | //RLC_SPM_SQG_PERFMON_SAMPLE_DELAY |
17541 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17542 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17543 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17544 | #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17545 | //RLC_SPM_SX_PERFMON_SAMPLE_DELAY |
17546 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17547 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17548 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17549 | #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17550 | //RLC_SPM_GLOBAL_MUXSEL_ADDR |
17551 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
17552 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL |
17553 | //RLC_SPM_GLOBAL_MUXSEL_DATA |
17554 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
17555 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
17556 | //RLC_SPM_RING_RDPTR |
17557 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 |
17558 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL |
17559 | //RLC_SPM_SEGMENT_THRESHOLD |
17560 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 |
17561 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL |
17562 | //RLC_SPM_RMI_PERFMON_SAMPLE_DELAY |
17563 | #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 |
17564 | #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 |
17565 | #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL |
17566 | #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L |
17567 | //RLC_SPM_PERFMON_SAMPLE_DELAY_MAX |
17568 | #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0 |
17569 | #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8 |
17570 | #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL |
17571 | #define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L |
17572 | //RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 |
17573 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1__SHIFT 0x0 |
17574 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1__SHIFT 0x7 |
17575 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE__SHIFT 0xc |
17576 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE__SHIFT 0x11 |
17577 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE__SHIFT 0x16 |
17578 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE__SHIFT 0x1b |
17579 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__PERFMON_SEGMENT_SIZE_CORE1_MASK 0x0000007FL |
17580 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__RESERVED1_MASK 0x00000F80L |
17581 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE4_NUM_LINE_MASK 0x0001F000L |
17582 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE5_NUM_LINE_MASK 0x003E0000L |
17583 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE6_NUM_LINE_MASK 0x07C00000L |
17584 | #define RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__SE7_NUM_LINE_MASK 0xF8000000L |
17585 | //RLC_PERFMON_CLK_CNTL_UCODE |
17586 | #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 |
17587 | #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L |
17588 | //RLC_PERFMON_CLK_CNTL |
17589 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 |
17590 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L |
17591 | //RLC_PERFMON_CNTL |
17592 | #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
17593 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
17594 | #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L |
17595 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
17596 | //RLC_PERFCOUNTER0_SELECT |
17597 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
17598 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL |
17599 | //RLC_PERFCOUNTER1_SELECT |
17600 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
17601 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL |
17602 | //RLC_GPU_IOV_PERF_CNT_CNTL |
17603 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 |
17604 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 |
17605 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 |
17606 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 |
17607 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L |
17608 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L |
17609 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L |
17610 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L |
17611 | //RLC_GPU_IOV_PERF_CNT_WR_ADDR |
17612 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 |
17613 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 |
17614 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 |
17615 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL |
17616 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L |
17617 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L |
17618 | //RLC_GPU_IOV_PERF_CNT_WR_DATA |
17619 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 |
17620 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL |
17621 | //RLC_GPU_IOV_PERF_CNT_RD_ADDR |
17622 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 |
17623 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 |
17624 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 |
17625 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL |
17626 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L |
17627 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L |
17628 | //RLC_GPU_IOV_PERF_CNT_RD_DATA |
17629 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 |
17630 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL |
17631 | //RMI_PERFCOUNTER0_SELECT |
17632 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
17633 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
17634 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
17635 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
17636 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
17637 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
17638 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
17639 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
17640 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
17641 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
17642 | //RMI_PERFCOUNTER0_SELECT1 |
17643 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
17644 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
17645 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
17646 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
17647 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
17648 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
17649 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17650 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17651 | //RMI_PERFCOUNTER1_SELECT |
17652 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
17653 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
17654 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
17655 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
17656 | //RMI_PERFCOUNTER2_SELECT |
17657 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
17658 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
17659 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
17660 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
17661 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
17662 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
17663 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L |
17664 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
17665 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
17666 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
17667 | //RMI_PERFCOUNTER2_SELECT1 |
17668 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
17669 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
17670 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
17671 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
17672 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL |
17673 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
17674 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
17675 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
17676 | //RMI_PERFCOUNTER3_SELECT |
17677 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
17678 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
17679 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
17680 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
17681 | //RMI_PERF_COUNTER_CNTL |
17682 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 |
17683 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 |
17684 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 |
17685 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 |
17686 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 |
17687 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa |
17688 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe |
17689 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 |
17690 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 |
17691 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a |
17692 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L |
17693 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL |
17694 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L |
17695 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L |
17696 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L |
17697 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L |
17698 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L |
17699 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L |
17700 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L |
17701 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L |
17702 | |
17703 | |
17704 | // addressBlock: gc_pwrdec |
17705 | //CGTS_SM_CTRL_REG |
17706 | #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 |
17707 | #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 |
17708 | #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc |
17709 | #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 |
17710 | #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 |
17711 | #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 |
17712 | #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 |
17713 | #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 |
17714 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 |
17715 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 |
17716 | #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL |
17717 | #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L |
17718 | #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L |
17719 | #define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L |
17720 | #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L |
17721 | #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L |
17722 | #define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L |
17723 | #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L |
17724 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L |
17725 | #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L |
17726 | //CGTS_RD_CTRL_REG |
17727 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 |
17728 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 |
17729 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL |
17730 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L |
17731 | //CGTS_RD_REG |
17732 | #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 |
17733 | #define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL |
17734 | //CGTS_TCC_DISABLE |
17735 | #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
17736 | #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
17737 | //CGTS_USER_TCC_DISABLE |
17738 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
17739 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
17740 | //CGTS_TCC_DISABLE2 |
17741 | #define CGTS_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10 |
17742 | #define CGTS_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L |
17743 | //CGTS_USER_TCC_DISABLE2 |
17744 | #define CGTS_USER_TCC_DISABLE2__TCC_DISABLE__SHIFT 0x10 |
17745 | #define CGTS_USER_TCC_DISABLE2__TCC_DISABLE_MASK 0xFFFF0000L |
17746 | //CGTS_CU0_SP0_CTRL_REG |
17747 | #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 |
17748 | #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
17749 | #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
17750 | #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
17751 | #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17752 | #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 |
17753 | #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
17754 | #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
17755 | #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
17756 | #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17757 | #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
17758 | #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
17759 | #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
17760 | #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
17761 | #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17762 | #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
17763 | #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
17764 | #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
17765 | #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
17766 | #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17767 | //CGTS_CU0_LDS_SQ_CTRL_REG |
17768 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
17769 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
17770 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
17771 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
17772 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17773 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
17774 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
17775 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
17776 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
17777 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17778 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
17779 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
17780 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
17781 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
17782 | #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17783 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
17784 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
17785 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
17786 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
17787 | #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17788 | //CGTS_CU0_TA_SQC_CTRL_REG |
17789 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
17790 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
17791 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
17792 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
17793 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17794 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
17795 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
17796 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
17797 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
17798 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17799 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
17800 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
17801 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
17802 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
17803 | #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17804 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
17805 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
17806 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
17807 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
17808 | #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17809 | //CGTS_CU0_SP1_CTRL_REG |
17810 | #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 |
17811 | #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
17812 | #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
17813 | #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
17814 | #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17815 | #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 |
17816 | #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
17817 | #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
17818 | #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
17819 | #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17820 | #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
17821 | #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
17822 | #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
17823 | #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
17824 | #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17825 | #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
17826 | #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
17827 | #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
17828 | #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
17829 | #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17830 | //CGTS_CU1_SP0_CTRL_REG |
17831 | #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 |
17832 | #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
17833 | #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
17834 | #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
17835 | #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17836 | #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 |
17837 | #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
17838 | #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
17839 | #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
17840 | #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17841 | #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
17842 | #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
17843 | #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
17844 | #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
17845 | #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17846 | #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
17847 | #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
17848 | #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
17849 | #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
17850 | #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17851 | //CGTS_CU1_LDS_SQ_CTRL_REG |
17852 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
17853 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
17854 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
17855 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
17856 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17857 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
17858 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
17859 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
17860 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
17861 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17862 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
17863 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
17864 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
17865 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
17866 | #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17867 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
17868 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
17869 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
17870 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
17871 | #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17872 | //CGTS_CU1_TA_SQC_CTRL_REG |
17873 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
17874 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
17875 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
17876 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
17877 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17878 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
17879 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
17880 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
17881 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
17882 | #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17883 | //CGTS_CU1_SP1_CTRL_REG |
17884 | #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 |
17885 | #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
17886 | #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
17887 | #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
17888 | #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17889 | #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 |
17890 | #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
17891 | #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
17892 | #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
17893 | #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17894 | #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
17895 | #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
17896 | #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
17897 | #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
17898 | #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17899 | #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
17900 | #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
17901 | #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
17902 | #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
17903 | #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17904 | //CGTS_CU2_SP0_CTRL_REG |
17905 | #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 |
17906 | #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
17907 | #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
17908 | #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
17909 | #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17910 | #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 |
17911 | #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
17912 | #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
17913 | #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
17914 | #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17915 | #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
17916 | #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
17917 | #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
17918 | #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
17919 | #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17920 | #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
17921 | #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
17922 | #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
17923 | #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
17924 | #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17925 | //CGTS_CU2_LDS_SQ_CTRL_REG |
17926 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
17927 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
17928 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
17929 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
17930 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17931 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
17932 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
17933 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
17934 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
17935 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17936 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
17937 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
17938 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
17939 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
17940 | #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17941 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
17942 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
17943 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
17944 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
17945 | #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17946 | //CGTS_CU2_TA_SQC_CTRL_REG |
17947 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
17948 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
17949 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
17950 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
17951 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17952 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
17953 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
17954 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
17955 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
17956 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17957 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
17958 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
17959 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
17960 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
17961 | #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17962 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
17963 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
17964 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
17965 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
17966 | #define CGTS_CU2_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17967 | //CGTS_CU2_SP1_CTRL_REG |
17968 | #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 |
17969 | #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
17970 | #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
17971 | #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
17972 | #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17973 | #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 |
17974 | #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
17975 | #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
17976 | #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
17977 | #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17978 | #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
17979 | #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
17980 | #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
17981 | #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
17982 | #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
17983 | #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
17984 | #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
17985 | #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
17986 | #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
17987 | #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
17988 | //CGTS_CU3_SP0_CTRL_REG |
17989 | #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 |
17990 | #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
17991 | #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
17992 | #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
17993 | #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
17994 | #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 |
17995 | #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
17996 | #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
17997 | #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
17998 | #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
17999 | #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18000 | #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18001 | #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18002 | #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18003 | #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18004 | #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18005 | #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18006 | #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18007 | #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18008 | #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18009 | //CGTS_CU3_LDS_SQ_CTRL_REG |
18010 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18011 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18012 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18013 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18014 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18015 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18016 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18017 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18018 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18019 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18020 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18021 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18022 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18023 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18024 | #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18025 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18026 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18027 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18028 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18029 | #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18030 | //CGTS_CU3_TA_SQC_CTRL_REG |
18031 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18032 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18033 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18034 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18035 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18036 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18037 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18038 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18039 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18040 | #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18041 | //CGTS_CU3_SP1_CTRL_REG |
18042 | #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18043 | #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18044 | #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18045 | #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18046 | #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18047 | #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18048 | #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18049 | #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18050 | #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18051 | #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18052 | #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18053 | #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18054 | #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18055 | #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18056 | #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18057 | #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18058 | #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18059 | #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18060 | #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18061 | #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18062 | //CGTS_CU4_SP0_CTRL_REG |
18063 | #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18064 | #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18065 | #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18066 | #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18067 | #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18068 | #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18069 | #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18070 | #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18071 | #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18072 | #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18073 | #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18074 | #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18075 | #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18076 | #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18077 | #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18078 | #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18079 | #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18080 | #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18081 | #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18082 | #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18083 | //CGTS_CU4_LDS_SQ_CTRL_REG |
18084 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18085 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18086 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18087 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18088 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18089 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18090 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18091 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18092 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18093 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18094 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18095 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18096 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18097 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18098 | #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18099 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18100 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18101 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18102 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18103 | #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18104 | //CGTS_CU4_TA_SQC_CTRL_REG |
18105 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18106 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18107 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18108 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18109 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18110 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18111 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18112 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18113 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18114 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18115 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18116 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18117 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18118 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18119 | #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18120 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18121 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18122 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18123 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18124 | #define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18125 | //CGTS_CU4_SP1_CTRL_REG |
18126 | #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18127 | #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18128 | #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18129 | #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18130 | #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18131 | #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18132 | #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18133 | #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18134 | #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18135 | #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18136 | #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18137 | #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18138 | #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18139 | #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18140 | #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18141 | #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18142 | #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18143 | #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18144 | #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18145 | #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18146 | //CGTS_CU5_SP0_CTRL_REG |
18147 | #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18148 | #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18149 | #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18150 | #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18151 | #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18152 | #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18153 | #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18154 | #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18155 | #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18156 | #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18157 | #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18158 | #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18159 | #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18160 | #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18161 | #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18162 | #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18163 | #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18164 | #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18165 | #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18166 | #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18167 | //CGTS_CU5_LDS_SQ_CTRL_REG |
18168 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18169 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18170 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18171 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18172 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18173 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18174 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18175 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18176 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18177 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18178 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18179 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18180 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18181 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18182 | #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18183 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18184 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18185 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18186 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18187 | #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18188 | //CGTS_CU5_TA_SQC_CTRL_REG |
18189 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18190 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18191 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18192 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18193 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18194 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18195 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18196 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18197 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18198 | #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18199 | //CGTS_CU5_SP1_CTRL_REG |
18200 | #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18201 | #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18202 | #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18203 | #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18204 | #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18205 | #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18206 | #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18207 | #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18208 | #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18209 | #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18210 | #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18211 | #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18212 | #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18213 | #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18214 | #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18215 | #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18216 | #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18217 | #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18218 | #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18219 | #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18220 | //CGTS_CU6_SP0_CTRL_REG |
18221 | #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18222 | #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18223 | #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18224 | #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18225 | #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18226 | #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18227 | #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18228 | #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18229 | #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18230 | #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18231 | #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18232 | #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18233 | #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18234 | #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18235 | #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18236 | #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18237 | #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18238 | #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18239 | #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18240 | #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18241 | //CGTS_CU6_LDS_SQ_CTRL_REG |
18242 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18243 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18244 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18245 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18246 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18247 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18248 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18249 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18250 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18251 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18252 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18253 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18254 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18255 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18256 | #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18257 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18258 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18259 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18260 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18261 | #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18262 | //CGTS_CU6_TA_SQC_CTRL_REG |
18263 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18264 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18265 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18266 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18267 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18268 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18269 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18270 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18271 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18272 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18273 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18274 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18275 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18276 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18277 | #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18278 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18279 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18280 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18281 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18282 | #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18283 | //CGTS_CU6_SP1_CTRL_REG |
18284 | #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18285 | #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18286 | #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18287 | #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18288 | #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18289 | #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18290 | #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18291 | #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18292 | #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18293 | #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18294 | #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18295 | #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18296 | #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18297 | #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18298 | #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18299 | #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18300 | #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18301 | #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18302 | #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18303 | #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18304 | //CGTS_CU7_SP0_CTRL_REG |
18305 | #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18306 | #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18307 | #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18308 | #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18309 | #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18310 | #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18311 | #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18312 | #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18313 | #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18314 | #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18315 | #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18316 | #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18317 | #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18318 | #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18319 | #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18320 | #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18321 | #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18322 | #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18323 | #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18324 | #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18325 | //CGTS_CU7_LDS_SQ_CTRL_REG |
18326 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18327 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18328 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18329 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18330 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18331 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18332 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18333 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18334 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18335 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18336 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18337 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18338 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18339 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18340 | #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18341 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18342 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18343 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18344 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18345 | #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18346 | //CGTS_CU7_TA_SQC_CTRL_REG |
18347 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18348 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18349 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18350 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18351 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18352 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18353 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18354 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18355 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18356 | #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18357 | //CGTS_CU7_SP1_CTRL_REG |
18358 | #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18359 | #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18360 | #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18361 | #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18362 | #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18363 | #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18364 | #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18365 | #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18366 | #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18367 | #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18368 | #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18369 | #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18370 | #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18371 | #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18372 | #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18373 | #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18374 | #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18375 | #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18376 | #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18377 | #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18378 | //CGTS_CU8_SP0_CTRL_REG |
18379 | #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18380 | #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18381 | #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18382 | #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18383 | #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18384 | #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18385 | #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18386 | #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18387 | #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18388 | #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18389 | #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18390 | #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18391 | #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18392 | #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18393 | #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18394 | #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18395 | #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18396 | #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18397 | #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18398 | #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18399 | //CGTS_CU8_LDS_SQ_CTRL_REG |
18400 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18401 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18402 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18403 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18404 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18405 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18406 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18407 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18408 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18409 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18410 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18411 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18412 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18413 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18414 | #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18415 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18416 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18417 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18418 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18419 | #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18420 | //CGTS_CU8_TA_SQC_CTRL_REG |
18421 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18422 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18423 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18424 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18425 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18426 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18427 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18428 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18429 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18430 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18431 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18432 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18433 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18434 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18435 | #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18436 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18437 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18438 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18439 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18440 | #define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18441 | //CGTS_CU8_SP1_CTRL_REG |
18442 | #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18443 | #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18444 | #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18445 | #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18446 | #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18447 | #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18448 | #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18449 | #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18450 | #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18451 | #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18452 | #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18453 | #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18454 | #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18455 | #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18456 | #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18457 | #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18458 | #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18459 | #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18460 | #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18461 | #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18462 | //CGTS_CU9_SP0_CTRL_REG |
18463 | #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18464 | #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18465 | #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18466 | #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18467 | #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18468 | #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18469 | #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18470 | #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18471 | #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18472 | #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18473 | #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18474 | #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18475 | #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18476 | #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18477 | #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18478 | #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18479 | #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18480 | #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18481 | #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18482 | #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18483 | //CGTS_CU9_LDS_SQ_CTRL_REG |
18484 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18485 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18486 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18487 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18488 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18489 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18490 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18491 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18492 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18493 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18494 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18495 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18496 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18497 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18498 | #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18499 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18500 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18501 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18502 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18503 | #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18504 | //CGTS_CU9_TA_SQC_CTRL_REG |
18505 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18506 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18507 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18508 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18509 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18510 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18511 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18512 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18513 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18514 | #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18515 | //CGTS_CU9_SP1_CTRL_REG |
18516 | #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18517 | #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18518 | #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18519 | #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18520 | #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18521 | #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18522 | #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18523 | #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18524 | #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18525 | #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18526 | #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18527 | #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18528 | #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18529 | #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18530 | #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18531 | #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18532 | #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18533 | #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18534 | #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18535 | #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18536 | //CGTS_CU10_SP0_CTRL_REG |
18537 | #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18538 | #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18539 | #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18540 | #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18541 | #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18542 | #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18543 | #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18544 | #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18545 | #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18546 | #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18547 | #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18548 | #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18549 | #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18550 | #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18551 | #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18552 | #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18553 | #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18554 | #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18555 | #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18556 | #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18557 | //CGTS_CU10_LDS_SQ_CTRL_REG |
18558 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18559 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18560 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18561 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18562 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18563 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18564 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18565 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18566 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18567 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18568 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18569 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18570 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18571 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18572 | #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18573 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18574 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18575 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18576 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18577 | #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18578 | //CGTS_CU10_TA_SQC_CTRL_REG |
18579 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18580 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18581 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18582 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18583 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18584 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18585 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18586 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18587 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18588 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18589 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18590 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18591 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18592 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18593 | #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18594 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18595 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18596 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18597 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18598 | #define CGTS_CU10_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18599 | //CGTS_CU10_SP1_CTRL_REG |
18600 | #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18601 | #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18602 | #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18603 | #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18604 | #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18605 | #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18606 | #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18607 | #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18608 | #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18609 | #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18610 | #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18611 | #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18612 | #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18613 | #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18614 | #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18615 | #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18616 | #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18617 | #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18618 | #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18619 | #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18620 | //CGTS_CU11_SP0_CTRL_REG |
18621 | #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18622 | #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18623 | #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18624 | #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18625 | #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18626 | #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18627 | #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18628 | #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18629 | #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18630 | #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18631 | #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18632 | #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18633 | #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18634 | #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18635 | #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18636 | #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18637 | #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18638 | #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18639 | #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18640 | #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18641 | //CGTS_CU11_LDS_SQ_CTRL_REG |
18642 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18643 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18644 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18645 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18646 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18647 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18648 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18649 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18650 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18651 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18652 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18653 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18654 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18655 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18656 | #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18657 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18658 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18659 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18660 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18661 | #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18662 | //CGTS_CU11_TA_SQC_CTRL_REG |
18663 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18664 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18665 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18666 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18667 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18668 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18669 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18670 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18671 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18672 | #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18673 | //CGTS_CU11_SP1_CTRL_REG |
18674 | #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18675 | #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18676 | #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18677 | #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18678 | #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18679 | #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18680 | #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18681 | #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18682 | #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18683 | #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18684 | #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18685 | #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18686 | #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18687 | #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18688 | #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18689 | #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18690 | #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18691 | #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18692 | #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18693 | #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18694 | //CGTS_CU12_SP0_CTRL_REG |
18695 | #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18696 | #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18697 | #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18698 | #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18699 | #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18700 | #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18701 | #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18702 | #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18703 | #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18704 | #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18705 | #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18706 | #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18707 | #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18708 | #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18709 | #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18710 | #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18711 | #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18712 | #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18713 | #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18714 | #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18715 | //CGTS_CU12_LDS_SQ_CTRL_REG |
18716 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18717 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18718 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18719 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18720 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18721 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18722 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18723 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18724 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18725 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18726 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18727 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18728 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18729 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18730 | #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18731 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18732 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18733 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18734 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18735 | #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18736 | //CGTS_CU12_TA_SQC_CTRL_REG |
18737 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18738 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18739 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18740 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18741 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18742 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18743 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18744 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18745 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18746 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18747 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18748 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18749 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18750 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18751 | #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18752 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18753 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18754 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18755 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18756 | #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18757 | //CGTS_CU12_SP1_CTRL_REG |
18758 | #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18759 | #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18760 | #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18761 | #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18762 | #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18763 | #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18764 | #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18765 | #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18766 | #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18767 | #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18768 | #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18769 | #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18770 | #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18771 | #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18772 | #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18773 | #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18774 | #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18775 | #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18776 | #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18777 | #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18778 | //CGTS_CU13_SP0_CTRL_REG |
18779 | #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18780 | #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18781 | #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18782 | #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18783 | #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18784 | #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18785 | #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18786 | #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18787 | #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18788 | #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18789 | #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18790 | #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18791 | #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18792 | #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18793 | #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18794 | #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18795 | #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18796 | #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18797 | #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18798 | #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18799 | //CGTS_CU13_LDS_SQ_CTRL_REG |
18800 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18801 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18802 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18803 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18804 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18805 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18806 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18807 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18808 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18809 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18810 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18811 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18812 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18813 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18814 | #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18815 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18816 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18817 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18818 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18819 | #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18820 | //CGTS_CU13_TA_SQC_CTRL_REG |
18821 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18822 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18823 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18824 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18825 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18826 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18827 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18828 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18829 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18830 | #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18831 | //CGTS_CU13_SP1_CTRL_REG |
18832 | #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18833 | #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18834 | #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18835 | #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18836 | #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18837 | #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18838 | #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18839 | #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18840 | #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18841 | #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18842 | #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18843 | #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18844 | #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18845 | #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18846 | #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18847 | #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18848 | #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18849 | #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18850 | #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18851 | #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18852 | //CGTS_CU14_SP0_CTRL_REG |
18853 | #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18854 | #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18855 | #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18856 | #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18857 | #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18858 | #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18859 | #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18860 | #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18861 | #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18862 | #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18863 | #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18864 | #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18865 | #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18866 | #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18867 | #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18868 | #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18869 | #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18870 | #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18871 | #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18872 | #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18873 | //CGTS_CU14_LDS_SQ_CTRL_REG |
18874 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18875 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18876 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18877 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18878 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18879 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18880 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18881 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18882 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18883 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18884 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18885 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18886 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18887 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18888 | #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18889 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18890 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18891 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18892 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18893 | #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18894 | //CGTS_CU14_TA_SQC_CTRL_REG |
18895 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18896 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18897 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18898 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18899 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18900 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 |
18901 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 |
18902 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 |
18903 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a |
18904 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18905 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18906 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18907 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18908 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18909 | #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18910 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L |
18911 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L |
18912 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L |
18913 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L |
18914 | #define CGTS_CU14_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18915 | //CGTS_CU14_SP1_CTRL_REG |
18916 | #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18917 | #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18918 | #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18919 | #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18920 | #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18921 | #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18922 | #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18923 | #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18924 | #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18925 | #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18926 | #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
18927 | #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
18928 | #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
18929 | #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
18930 | #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18931 | #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
18932 | #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
18933 | #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
18934 | #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
18935 | #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18936 | //CGTS_CU15_SP0_CTRL_REG |
18937 | #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 |
18938 | #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 |
18939 | #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 |
18940 | #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa |
18941 | #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18942 | #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 |
18943 | #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 |
18944 | #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 |
18945 | #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a |
18946 | #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18947 | #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL |
18948 | #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L |
18949 | #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L |
18950 | #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L |
18951 | #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18952 | #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L |
18953 | #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L |
18954 | #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L |
18955 | #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L |
18956 | #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18957 | //CGTS_CU15_LDS_SQ_CTRL_REG |
18958 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 |
18959 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 |
18960 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 |
18961 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa |
18962 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18963 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 |
18964 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 |
18965 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 |
18966 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a |
18967 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
18968 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL |
18969 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L |
18970 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L |
18971 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L |
18972 | #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18973 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L |
18974 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L |
18975 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L |
18976 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L |
18977 | #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
18978 | //CGTS_CU15_TA_SQC_CTRL_REG |
18979 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 |
18980 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 |
18981 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 |
18982 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa |
18983 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18984 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL |
18985 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L |
18986 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L |
18987 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L |
18988 | #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
18989 | //CGTS_CU15_SP1_CTRL_REG |
18990 | #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 |
18991 | #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 |
18992 | #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 |
18993 | #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa |
18994 | #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb |
18995 | #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 |
18996 | #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 |
18997 | #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 |
18998 | #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a |
18999 | #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b |
19000 | #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL |
19001 | #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L |
19002 | #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L |
19003 | #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L |
19004 | #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19005 | #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L |
19006 | #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L |
19007 | #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L |
19008 | #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L |
19009 | #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L |
19010 | //CGTS_CU0_TCPI_CTRL_REG |
19011 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19012 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19013 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19014 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19015 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19016 | #define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19017 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19018 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19019 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19020 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19021 | #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19022 | #define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19023 | //CGTS_CU1_TCPI_CTRL_REG |
19024 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19025 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19026 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19027 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19028 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19029 | #define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19030 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19031 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19032 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19033 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19034 | #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19035 | #define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19036 | //CGTS_CU2_TCPI_CTRL_REG |
19037 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19038 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19039 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19040 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19041 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19042 | #define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19043 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19044 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19045 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19046 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19047 | #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19048 | #define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19049 | //CGTS_CU3_TCPI_CTRL_REG |
19050 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19051 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19052 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19053 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19054 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19055 | #define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19056 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19057 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19058 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19059 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19060 | #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19061 | #define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19062 | //CGTS_CU4_TCPI_CTRL_REG |
19063 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19064 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19065 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19066 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19067 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19068 | #define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19069 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19070 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19071 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19072 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19073 | #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19074 | #define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19075 | //CGTS_CU5_TCPI_CTRL_REG |
19076 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19077 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19078 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19079 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19080 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19081 | #define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19082 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19083 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19084 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19085 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19086 | #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19087 | #define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19088 | //CGTS_CU6_TCPI_CTRL_REG |
19089 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19090 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19091 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19092 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19093 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19094 | #define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19095 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19096 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19097 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19098 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19099 | #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19100 | #define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19101 | //CGTS_CU7_TCPI_CTRL_REG |
19102 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19103 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19104 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19105 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19106 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19107 | #define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19108 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19109 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19110 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19111 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19112 | #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19113 | #define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19114 | //CGTS_CU8_TCPI_CTRL_REG |
19115 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19116 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19117 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19118 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19119 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19120 | #define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19121 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19122 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19123 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19124 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19125 | #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19126 | #define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19127 | //CGTS_CU9_TCPI_CTRL_REG |
19128 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19129 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19130 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19131 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19132 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19133 | #define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19134 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19135 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19136 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19137 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19138 | #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19139 | #define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19140 | //CGTS_CU10_TCPI_CTRL_REG |
19141 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19142 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19143 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19144 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19145 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19146 | #define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19147 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19148 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19149 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19150 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19151 | #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19152 | #define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19153 | //CGTS_CU11_TCPI_CTRL_REG |
19154 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19155 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19156 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19157 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19158 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19159 | #define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19160 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19161 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19162 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19163 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19164 | #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19165 | #define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19166 | //CGTS_CU12_TCPI_CTRL_REG |
19167 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19168 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19169 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19170 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19171 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19172 | #define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19173 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19174 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19175 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19176 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19177 | #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19178 | #define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19179 | //CGTS_CU13_TCPI_CTRL_REG |
19180 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19181 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19182 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19183 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19184 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19185 | #define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19186 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19187 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19188 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19189 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19190 | #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19191 | #define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19192 | //CGTS_CU14_TCPI_CTRL_REG |
19193 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19194 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19195 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19196 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19197 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19198 | #define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19199 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19200 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19201 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19202 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19203 | #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19204 | #define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19205 | //CGTS_CU15_TCPI_CTRL_REG |
19206 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 |
19207 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 |
19208 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 |
19209 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa |
19210 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb |
19211 | #define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc |
19212 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL |
19213 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L |
19214 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L |
19215 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L |
19216 | #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L |
19217 | #define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L |
19218 | //CGTT_SPI_PS_CLK_CTRL |
19219 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19220 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19221 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
19222 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
19223 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
19224 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
19225 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
19226 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
19227 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
19228 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
19229 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
19230 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
19231 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
19232 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
19233 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
19234 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
19235 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19236 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19237 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19238 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
19239 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
19240 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
19241 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
19242 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
19243 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
19244 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
19245 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
19246 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
19247 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
19248 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
19249 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
19250 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
19251 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
19252 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19253 | //CGTT_SPIS_CLK_CTRL |
19254 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19255 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19256 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
19257 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
19258 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
19259 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
19260 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
19261 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
19262 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
19263 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
19264 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
19265 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
19266 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
19267 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
19268 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
19269 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
19270 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19271 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19272 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19273 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
19274 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
19275 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
19276 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
19277 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
19278 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
19279 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
19280 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
19281 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
19282 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
19283 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
19284 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
19285 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
19286 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
19287 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19288 | //CGTT_SPI_CLK_CTRL |
19289 | #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19290 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19291 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
19292 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
19293 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
19294 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
19295 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
19296 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
19297 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19298 | #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19299 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19300 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
19301 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
19302 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
19303 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
19304 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
19305 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
19306 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19307 | //CGTT_PC_CLK_CTRL |
19308 | #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19309 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19310 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 |
19311 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 |
19312 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 |
19313 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 |
19314 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a |
19315 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
19316 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
19317 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
19318 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
19319 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19320 | #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19321 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19322 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L |
19323 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L |
19324 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L |
19325 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L |
19326 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L |
19327 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
19328 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
19329 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
19330 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
19331 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19332 | //CGTT_BCI_CLK_CTRL |
19333 | #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19334 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19335 | #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc |
19336 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19337 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19338 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19339 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19340 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19341 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19342 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19343 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19344 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 |
19345 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 |
19346 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a |
19347 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
19348 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
19349 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
19350 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
19351 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19352 | #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19353 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19354 | #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L |
19355 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19356 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19357 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19358 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19359 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19360 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19361 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19362 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19363 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L |
19364 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L |
19365 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L |
19366 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
19367 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
19368 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
19369 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
19370 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19371 | //CGTT_PA_CLK_CTRL |
19372 | #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19373 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19374 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19375 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19376 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19377 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19378 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19379 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19380 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19381 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19382 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19383 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19384 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19385 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19386 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d |
19387 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e |
19388 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f |
19389 | #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19390 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19391 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19392 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19393 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19394 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19395 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19396 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19397 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19398 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19399 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19400 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19401 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19402 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19403 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L |
19404 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L |
19405 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L |
19406 | //CGTT_SC_CLK_CTRL0 |
19407 | #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
19408 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
19409 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 |
19410 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
19411 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
19412 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
19413 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
19414 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
19415 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
19416 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 |
19417 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 |
19418 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 |
19419 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a |
19420 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b |
19421 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c |
19422 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d |
19423 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e |
19424 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
19425 | #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
19426 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
19427 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L |
19428 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
19429 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
19430 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
19431 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
19432 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
19433 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
19434 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L |
19435 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L |
19436 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L |
19437 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L |
19438 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L |
19439 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L |
19440 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L |
19441 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L |
19442 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
19443 | //CGTT_SC_CLK_CTRL1 |
19444 | #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
19445 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
19446 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 |
19447 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 |
19448 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 |
19449 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 |
19450 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 |
19451 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 |
19452 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 |
19453 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a |
19454 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b |
19455 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c |
19456 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d |
19457 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e |
19458 | #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
19459 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
19460 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L |
19461 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L |
19462 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L |
19463 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L |
19464 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L |
19465 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L |
19466 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L |
19467 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L |
19468 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L |
19469 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L |
19470 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L |
19471 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L |
19472 | //CGTT_SC_CLK_CTRL2 |
19473 | #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
19474 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
19475 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b |
19476 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c |
19477 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d |
19478 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e |
19479 | #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
19480 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
19481 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L |
19482 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L |
19483 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L |
19484 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L |
19485 | //CGTT_SQG_CLK_CTRL |
19486 | #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19487 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19488 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19489 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19490 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19491 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19492 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19493 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19494 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19495 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19496 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c |
19497 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d |
19498 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
19499 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
19500 | #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19501 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19502 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19503 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19504 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19505 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19506 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19507 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19508 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19509 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19510 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L |
19511 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L |
19512 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
19513 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
19514 | //SQ_ALU_CLK_CTRL |
19515 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 |
19516 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 |
19517 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL |
19518 | #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L |
19519 | //SQ_TEX_CLK_CTRL |
19520 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 |
19521 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 |
19522 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL |
19523 | #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L |
19524 | //SQ_LDS_CLK_CTRL |
19525 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 |
19526 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 |
19527 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL |
19528 | #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L |
19529 | //SQ_POWER_THROTTLE |
19530 | #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 |
19531 | #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 |
19532 | #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e |
19533 | #define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL |
19534 | #define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L |
19535 | #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L |
19536 | //SQ_POWER_THROTTLE2 |
19537 | #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 |
19538 | #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
19539 | #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
19540 | #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f |
19541 | #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL |
19542 | #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
19543 | #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
19544 | #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L |
19545 | //CGTT_SX_CLK_CTRL0 |
19546 | #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
19547 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
19548 | #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc |
19549 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19550 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19551 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19552 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19553 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19554 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19555 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19556 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19557 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 |
19558 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
19559 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
19560 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
19561 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
19562 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
19563 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e |
19564 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f |
19565 | #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
19566 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
19567 | #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L |
19568 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19569 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19570 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19571 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19572 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19573 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19574 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19575 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19576 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L |
19577 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
19578 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
19579 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
19580 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
19581 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
19582 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L |
19583 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L |
19584 | //CGTT_SX_CLK_CTRL1 |
19585 | #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
19586 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
19587 | #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc |
19588 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19589 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19590 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19591 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19592 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19593 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19594 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19595 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19596 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
19597 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
19598 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
19599 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
19600 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
19601 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
19602 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f |
19603 | #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
19604 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
19605 | #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L |
19606 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19607 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19608 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19609 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19610 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19611 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19612 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19613 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19614 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
19615 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
19616 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
19617 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
19618 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
19619 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
19620 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L |
19621 | //CGTT_SX_CLK_CTRL2 |
19622 | #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
19623 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
19624 | #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd |
19625 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19626 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19627 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19628 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19629 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19630 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19631 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19632 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19633 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
19634 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
19635 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
19636 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
19637 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
19638 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
19639 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f |
19640 | #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
19641 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
19642 | #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L |
19643 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19644 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19645 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19646 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19647 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19648 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19649 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19650 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19651 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
19652 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
19653 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
19654 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
19655 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
19656 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
19657 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L |
19658 | //CGTT_SX_CLK_CTRL3 |
19659 | #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
19660 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
19661 | #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd |
19662 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19663 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19664 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19665 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19666 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19667 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19668 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19669 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19670 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
19671 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
19672 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
19673 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
19674 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
19675 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
19676 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f |
19677 | #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
19678 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
19679 | #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L |
19680 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19681 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19682 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19683 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19684 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19685 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19686 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19687 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19688 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
19689 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
19690 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
19691 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
19692 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
19693 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
19694 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L |
19695 | //CGTT_SX_CLK_CTRL4 |
19696 | #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 |
19697 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 |
19698 | #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc |
19699 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19700 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19701 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19702 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19703 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19704 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19705 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19706 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19707 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 |
19708 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a |
19709 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b |
19710 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c |
19711 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d |
19712 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e |
19713 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f |
19714 | #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL |
19715 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L |
19716 | #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L |
19717 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19718 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19719 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19720 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19721 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19722 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19723 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19724 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19725 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L |
19726 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L |
19727 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L |
19728 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L |
19729 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L |
19730 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L |
19731 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L |
19732 | //TD_CGTT_CTRL |
19733 | #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
19734 | #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19735 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19736 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19737 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19738 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19739 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19740 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19741 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19742 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19743 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19744 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19745 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19746 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19747 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19748 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19749 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19750 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19751 | #define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
19752 | #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19753 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19754 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19755 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19756 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19757 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19758 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19759 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19760 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19761 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19762 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19763 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19764 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19765 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19766 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19767 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19768 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19769 | //TA_CGTT_CTRL |
19770 | #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
19771 | #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19772 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19773 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19774 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19775 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19776 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19777 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19778 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19779 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19780 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19781 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19782 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19783 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19784 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19785 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19786 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19787 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19788 | #define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
19789 | #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19790 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19791 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19792 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19793 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19794 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19795 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19796 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19797 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19798 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19799 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19800 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19801 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19802 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19803 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19804 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19805 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19806 | //CGTT_TCI_CLK_CTRL |
19807 | #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19808 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19809 | #define CGTT_TCI_CLK_CTRL__SPARE__SHIFT 0xc |
19810 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19811 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19812 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19813 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19814 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19815 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19816 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19817 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19818 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19819 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19820 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19821 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19822 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19823 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19824 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19825 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19826 | #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19827 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19828 | #define CGTT_TCI_CLK_CTRL__SPARE_MASK 0x0000F000L |
19829 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19830 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19831 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19832 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19833 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19834 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19835 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19836 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19837 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19838 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19839 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19840 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19841 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19842 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19843 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19844 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19845 | //CGTT_GDS_CLK_CTRL |
19846 | #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19847 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19848 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19849 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19850 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19851 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19852 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19853 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19854 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19855 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19856 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19857 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19858 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19859 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19860 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19861 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19862 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19863 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19864 | #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19865 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19866 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19867 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19868 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19869 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19870 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19871 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19872 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19873 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19874 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19875 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19876 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19877 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19878 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19879 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19880 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19881 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19882 | //CGTT_TCP_TCR_CLK_CTRL |
19883 | #define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19884 | #define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19885 | #define CGTT_TCP_TCR_CLK_CTRL__SPARE__SHIFT 0xc |
19886 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19887 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19888 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19889 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19890 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19891 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19892 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19893 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19894 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19895 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19896 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19897 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19898 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19899 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19900 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19901 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19902 | #define CGTT_TCP_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19903 | #define CGTT_TCP_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19904 | #define CGTT_TCP_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L |
19905 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19906 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19907 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19908 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19909 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19910 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19911 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19912 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19913 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19914 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19915 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19916 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19917 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19918 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19919 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19920 | #define CGTT_TCP_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19921 | //CGTT_TCI_TCR_CLK_CTRL |
19922 | #define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
19923 | #define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19924 | #define CGTT_TCI_TCR_CLK_CTRL__SPARE__SHIFT 0xc |
19925 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19926 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19927 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19928 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19929 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19930 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19931 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19932 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19933 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
19934 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
19935 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19936 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19937 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19938 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19939 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19940 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
19941 | #define CGTT_TCI_TCR_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
19942 | #define CGTT_TCI_TCR_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19943 | #define CGTT_TCI_TCR_CLK_CTRL__SPARE_MASK 0x0000F000L |
19944 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19945 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19946 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19947 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
19948 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
19949 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
19950 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
19951 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
19952 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
19953 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
19954 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19955 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19956 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19957 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19958 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19959 | #define CGTT_TCI_TCR_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
19960 | //TCX_CGTT_SCLK_CTRL |
19961 | #define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
19962 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
19963 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
19964 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
19965 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
19966 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
19967 | #define TCX_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
19968 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
19969 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
19970 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
19971 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
19972 | #define TCX_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
19973 | //DB_CGTT_CLK_CTRL_0 |
19974 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 |
19975 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 |
19976 | #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc |
19977 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
19978 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
19979 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
19980 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
19981 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
19982 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
19983 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
19984 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
19985 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 |
19986 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 |
19987 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a |
19988 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b |
19989 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c |
19990 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d |
19991 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e |
19992 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f |
19993 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL |
19994 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L |
19995 | #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L |
19996 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
19997 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
19998 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
19999 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20000 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20001 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20002 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20003 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20004 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L |
20005 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L |
20006 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L |
20007 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L |
20008 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L |
20009 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L |
20010 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L |
20011 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L |
20012 | //CB_CGTT_SCLK_CTRL |
20013 | #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
20014 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20015 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20016 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20017 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20018 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20019 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20020 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20021 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20022 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20023 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
20024 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
20025 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
20026 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
20027 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
20028 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
20029 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
20030 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
20031 | #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20032 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20033 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20034 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20035 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20036 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20037 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20038 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20039 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20040 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20041 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
20042 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
20043 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
20044 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
20045 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
20046 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
20047 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
20048 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
20049 | //TCC_CGTT_SCLK_CTRL |
20050 | #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20051 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
20052 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
20053 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
20054 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
20055 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
20056 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
20057 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
20058 | #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20059 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
20060 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
20061 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
20062 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
20063 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
20064 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
20065 | #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
20066 | //TCC_CGTT_SCLK_CTRL2 |
20067 | #define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
20068 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
20069 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
20070 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
20071 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
20072 | #define TCC_CGTT_SCLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
20073 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
20074 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
20075 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
20076 | #define TCC_CGTT_SCLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
20077 | //TCC_CGTT_SCLK_CTRL3 |
20078 | #define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
20079 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18__SHIFT 0xc |
20080 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17__SHIFT 0xd |
20081 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16__SHIFT 0xe |
20082 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15__SHIFT 0xf |
20083 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14__SHIFT 0x10 |
20084 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13__SHIFT 0x11 |
20085 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12__SHIFT 0x12 |
20086 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11__SHIFT 0x13 |
20087 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10__SHIFT 0x14 |
20088 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9__SHIFT 0x15 |
20089 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8__SHIFT 0x17 |
20090 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 |
20091 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
20092 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
20093 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
20094 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
20095 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
20096 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
20097 | #define TCC_CGTT_SCLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
20098 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE18_MASK 0x00001000L |
20099 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE17_MASK 0x00002000L |
20100 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE16_MASK 0x00004000L |
20101 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE15_MASK 0x00008000L |
20102 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE14_MASK 0x00010000L |
20103 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE13_MASK 0x00020000L |
20104 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE12_MASK 0x00040000L |
20105 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE11_MASK 0x00080000L |
20106 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE10_MASK 0x00100000L |
20107 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE9_MASK 0x00200000L |
20108 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE8_MASK 0x00800000L |
20109 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L |
20110 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
20111 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
20112 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
20113 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
20114 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
20115 | #define TCC_CGTT_SCLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
20116 | //TCA_CGTT_SCLK_CTRL |
20117 | #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20118 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
20119 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
20120 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
20121 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
20122 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
20123 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
20124 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
20125 | #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20126 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
20127 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
20128 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
20129 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
20130 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
20131 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
20132 | #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
20133 | //CGTT_CP_CLK_CTRL |
20134 | #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20135 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20136 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
20137 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20138 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20139 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20140 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20141 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20142 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20143 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20144 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20145 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
20146 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20147 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20148 | #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20149 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20150 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
20151 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20152 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20153 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20154 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20155 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20156 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20157 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20158 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20159 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
20160 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20161 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20162 | //CGTT_CPF_CLK_CTRL |
20163 | #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20164 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20165 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
20166 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20167 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20168 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20169 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20170 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20171 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20172 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20173 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20174 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
20175 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20176 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20177 | #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20178 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20179 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
20180 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20181 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20182 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20183 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20184 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20185 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20186 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20187 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20188 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
20189 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20190 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20191 | //CGTT_CPC_CLK_CTRL |
20192 | #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20193 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20194 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
20195 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20196 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20197 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20198 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20199 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20200 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20201 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20202 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20203 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
20204 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20205 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20206 | #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20207 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20208 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
20209 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20210 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20211 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20212 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20213 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20214 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20215 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20216 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20217 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
20218 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20219 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20220 | //CGTT_RLC_CLK_CTRL |
20221 | #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20222 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20223 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20224 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20225 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20226 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20227 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20228 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20229 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20230 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20231 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20232 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20233 | #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20234 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20235 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20236 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20237 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20238 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20239 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20240 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20241 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20242 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20243 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20244 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20245 | //RLC_GFX_RM_CNTL |
20246 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 |
20247 | #define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 |
20248 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L |
20249 | #define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL |
20250 | //RMI_CGTT_SCLK_CTRL |
20251 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
20252 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20253 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20254 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20255 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20256 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20257 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20258 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20259 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20260 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20261 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
20262 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
20263 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
20264 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
20265 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
20266 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
20267 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
20268 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20269 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20270 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20271 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20272 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20273 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20274 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20275 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20276 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20277 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20278 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
20279 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
20280 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
20281 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
20282 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
20283 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
20284 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
20285 | //SE_CAC_CGTT_CLK_CTRL |
20286 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20287 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20288 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG__SHIFT 0x1d |
20289 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20290 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20291 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20292 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20293 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DIDT_REG_MASK 0x20000000L |
20294 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20295 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20296 | //GC_CAC_CGTT_CLK_CTRL |
20297 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
20298 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
20299 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20300 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
20301 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
20302 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20303 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20304 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
20305 | //GRBM_CGTT_CLK_CNTL |
20306 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 |
20307 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 |
20308 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
20309 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
20310 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
20311 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
20312 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
20313 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
20314 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
20315 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
20316 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
20317 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL |
20318 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L |
20319 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
20320 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
20321 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
20322 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
20323 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
20324 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
20325 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
20326 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
20327 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
20328 | |
20329 | |
20330 | // addressBlock: gc_rbdec |
20331 | //DB_DEBUG |
20332 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 |
20333 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 |
20334 | #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 |
20335 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 |
20336 | #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 |
20337 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 |
20338 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 |
20339 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 |
20340 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa |
20341 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc |
20342 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe |
20343 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf |
20344 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 |
20345 | #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 |
20346 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 |
20347 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 |
20348 | #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 |
20349 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 |
20350 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 |
20351 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 |
20352 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c |
20353 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d |
20354 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e |
20355 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f |
20356 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L |
20357 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L |
20358 | #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L |
20359 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L |
20360 | #define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L |
20361 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L |
20362 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L |
20363 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L |
20364 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L |
20365 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L |
20366 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L |
20367 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L |
20368 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L |
20369 | #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L |
20370 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L |
20371 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L |
20372 | #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L |
20373 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L |
20374 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L |
20375 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L |
20376 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L |
20377 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L |
20378 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L |
20379 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L |
20380 | //DB_DEBUG2 |
20381 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 |
20382 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 |
20383 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 |
20384 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 |
20385 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 |
20386 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 |
20387 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 |
20388 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 |
20389 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 |
20390 | #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 |
20391 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe |
20392 | #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf |
20393 | #define DB_DEBUG2__RESERVED__SHIFT 0x10 |
20394 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 |
20395 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 |
20396 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 |
20397 | #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a |
20398 | #define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b |
20399 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c |
20400 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d |
20401 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e |
20402 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f |
20403 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L |
20404 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L |
20405 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L |
20406 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L |
20407 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L |
20408 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L |
20409 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L |
20410 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L |
20411 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L |
20412 | #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L |
20413 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L |
20414 | #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L |
20415 | #define DB_DEBUG2__RESERVED_MASK 0x00010000L |
20416 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L |
20417 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L |
20418 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L |
20419 | #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L |
20420 | #define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L |
20421 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L |
20422 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L |
20423 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L |
20424 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L |
20425 | //DB_DEBUG3 |
20426 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 |
20427 | #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 |
20428 | #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 |
20429 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 |
20430 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 |
20431 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 |
20432 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 |
20433 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 |
20434 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 |
20435 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 |
20436 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa |
20437 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb |
20438 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc |
20439 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd |
20440 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe |
20441 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf |
20442 | #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 |
20443 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 |
20444 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 |
20445 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 |
20446 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 |
20447 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 |
20448 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 |
20449 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 |
20450 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 |
20451 | #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 |
20452 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a |
20453 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b |
20454 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c |
20455 | #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d |
20456 | #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e |
20457 | #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f |
20458 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L |
20459 | #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L |
20460 | #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L |
20461 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L |
20462 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L |
20463 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L |
20464 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L |
20465 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L |
20466 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L |
20467 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L |
20468 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L |
20469 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L |
20470 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L |
20471 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L |
20472 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L |
20473 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L |
20474 | #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L |
20475 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L |
20476 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L |
20477 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L |
20478 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L |
20479 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L |
20480 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L |
20481 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L |
20482 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L |
20483 | #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L |
20484 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L |
20485 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L |
20486 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L |
20487 | #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L |
20488 | #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L |
20489 | #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L |
20490 | //DB_DEBUG4 |
20491 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 |
20492 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 |
20493 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 |
20494 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 |
20495 | #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 |
20496 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 |
20497 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 |
20498 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 |
20499 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 |
20500 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 |
20501 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa |
20502 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb |
20503 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc |
20504 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd |
20505 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe |
20506 | #define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf |
20507 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 |
20508 | #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 |
20509 | #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 |
20510 | #define 0x13 |
20511 | #define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e |
20512 | #define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f |
20513 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L |
20514 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L |
20515 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L |
20516 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L |
20517 | #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L |
20518 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L |
20519 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L |
20520 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L |
20521 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L |
20522 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L |
20523 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L |
20524 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L |
20525 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L |
20526 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L |
20527 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L |
20528 | #define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L |
20529 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L |
20530 | #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L |
20531 | #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L |
20532 | #define 0x3FF80000L |
20533 | #define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L |
20534 | #define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L |
20535 | //DB_CREDIT_LIMIT |
20536 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 |
20537 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 |
20538 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa |
20539 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 |
20540 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL |
20541 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L |
20542 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L |
20543 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L |
20544 | //DB_WATERMARKS |
20545 | #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 |
20546 | #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 |
20547 | #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb |
20548 | #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf |
20549 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 |
20550 | #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e |
20551 | #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f |
20552 | #define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL |
20553 | #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L |
20554 | #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L |
20555 | #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L |
20556 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L |
20557 | #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L |
20558 | #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L |
20559 | //DB_SUBTILE_CONTROL |
20560 | #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 |
20561 | #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 |
20562 | #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 |
20563 | #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 |
20564 | #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 |
20565 | #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa |
20566 | #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc |
20567 | #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe |
20568 | #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 |
20569 | #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 |
20570 | #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L |
20571 | #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL |
20572 | #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L |
20573 | #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L |
20574 | #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L |
20575 | #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L |
20576 | #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L |
20577 | #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L |
20578 | #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L |
20579 | #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L |
20580 | //DB_FREE_CACHELINES |
20581 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 |
20582 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 |
20583 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe |
20584 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 |
20585 | #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 |
20586 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL |
20587 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L |
20588 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L |
20589 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L |
20590 | #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L |
20591 | //DB_FIFO_DEPTH1 |
20592 | #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 |
20593 | #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 |
20594 | #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa |
20595 | #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 |
20596 | #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 |
20597 | #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL |
20598 | #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L |
20599 | #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L |
20600 | #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L |
20601 | #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L |
20602 | //DB_FIFO_DEPTH2 |
20603 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 |
20604 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 |
20605 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf |
20606 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 |
20607 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL |
20608 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L |
20609 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L |
20610 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L |
20611 | //DB_EXCEPTION_CONTROL |
20612 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 |
20613 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 |
20614 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 |
20615 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L |
20616 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L |
20617 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L |
20618 | //DB_RING_CONTROL |
20619 | #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 |
20620 | #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L |
20621 | //DB_MEM_ARB_WATERMARKS |
20622 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 |
20623 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 |
20624 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 |
20625 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 |
20626 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L |
20627 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L |
20628 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L |
20629 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L |
20630 | //DB_RMI_CACHE_POLICY |
20631 | #define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 |
20632 | #define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 |
20633 | #define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 |
20634 | #define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 |
20635 | #define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 |
20636 | #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa |
20637 | #define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb |
20638 | #define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 |
20639 | #define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 |
20640 | #define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 |
20641 | #define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 |
20642 | #define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 |
20643 | #define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 |
20644 | #define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a |
20645 | #define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b |
20646 | #define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L |
20647 | #define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L |
20648 | #define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L |
20649 | #define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L |
20650 | #define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L |
20651 | #define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L |
20652 | #define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L |
20653 | #define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L |
20654 | #define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L |
20655 | #define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L |
20656 | #define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L |
20657 | #define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L |
20658 | #define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L |
20659 | #define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L |
20660 | #define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L |
20661 | //DB_DFSM_CONFIG |
20662 | #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 |
20663 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 |
20664 | #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 |
20665 | #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 |
20666 | #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 |
20667 | #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L |
20668 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L |
20669 | #define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L |
20670 | #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L |
20671 | #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L |
20672 | //DB_DFSM_WATERMARK |
20673 | #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 |
20674 | #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 |
20675 | #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL |
20676 | #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L |
20677 | //DB_DFSM_TILES_IN_FLIGHT |
20678 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
20679 | #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 |
20680 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
20681 | #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L |
20682 | //DB_DFSM_PRIMS_IN_FLIGHT |
20683 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
20684 | #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 |
20685 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
20686 | #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L |
20687 | //DB_DFSM_WATCHDOG |
20688 | #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 |
20689 | #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL |
20690 | //DB_DFSM_FLUSH_ENABLE |
20691 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 |
20692 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 |
20693 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c |
20694 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL |
20695 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L |
20696 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L |
20697 | //DB_DFSM_FLUSH_AUX_EVENT |
20698 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 |
20699 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 |
20700 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 |
20701 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 |
20702 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL |
20703 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L |
20704 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L |
20705 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L |
20706 | //CC_RB_REDUNDANCY |
20707 | #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
20708 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
20709 | #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
20710 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
20711 | #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
20712 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
20713 | #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
20714 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
20715 | //CC_RB_BACKEND_DISABLE |
20716 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
20717 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
20718 | //GB_ADDR_CONFIG |
20719 | #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
20720 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
20721 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
20722 | #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
20723 | #define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
20724 | #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
20725 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
20726 | #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 |
20727 | #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
20728 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
20729 | #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
20730 | #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
20731 | #define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f |
20732 | #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
20733 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
20734 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
20735 | #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
20736 | #define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
20737 | #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
20738 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
20739 | #define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L |
20740 | #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
20741 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
20742 | #define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
20743 | #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
20744 | #define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L |
20745 | //GB_BACKEND_MAP |
20746 | #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 |
20747 | #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL |
20748 | //GB_GPU_ID |
20749 | #define GB_GPU_ID__GPU_ID__SHIFT 0x0 |
20750 | #define GB_GPU_ID__GPU_ID_MASK 0x0000000FL |
20751 | //CC_RB_DAISY_CHAIN |
20752 | #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 |
20753 | #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 |
20754 | #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 |
20755 | #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc |
20756 | #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 |
20757 | #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 |
20758 | #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 |
20759 | #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c |
20760 | #define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL |
20761 | #define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L |
20762 | #define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L |
20763 | #define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L |
20764 | #define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L |
20765 | #define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L |
20766 | #define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L |
20767 | #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L |
20768 | //GB_ADDR_CONFIG_READ |
20769 | #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
20770 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
20771 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
20772 | #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
20773 | #define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc |
20774 | #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
20775 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
20776 | #define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 |
20777 | #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
20778 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
20779 | #define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c |
20780 | #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e |
20781 | #define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f |
20782 | #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
20783 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
20784 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
20785 | #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
20786 | #define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L |
20787 | #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
20788 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
20789 | #define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L |
20790 | #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
20791 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
20792 | #define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L |
20793 | #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L |
20794 | #define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L |
20795 | //GB_TILE_MODE0 |
20796 | #define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 |
20797 | #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 |
20798 | #define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb |
20799 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20800 | #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 |
20801 | #define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL |
20802 | #define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L |
20803 | #define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L |
20804 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20805 | #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L |
20806 | //GB_TILE_MODE1 |
20807 | #define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 |
20808 | #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 |
20809 | #define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb |
20810 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20811 | #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 |
20812 | #define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL |
20813 | #define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L |
20814 | #define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L |
20815 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20816 | #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L |
20817 | //GB_TILE_MODE2 |
20818 | #define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 |
20819 | #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 |
20820 | #define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb |
20821 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20822 | #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 |
20823 | #define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL |
20824 | #define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L |
20825 | #define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L |
20826 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20827 | #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L |
20828 | //GB_TILE_MODE3 |
20829 | #define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 |
20830 | #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 |
20831 | #define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb |
20832 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20833 | #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 |
20834 | #define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL |
20835 | #define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L |
20836 | #define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L |
20837 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20838 | #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L |
20839 | //GB_TILE_MODE4 |
20840 | #define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 |
20841 | #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 |
20842 | #define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb |
20843 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20844 | #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 |
20845 | #define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL |
20846 | #define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L |
20847 | #define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L |
20848 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20849 | #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L |
20850 | //GB_TILE_MODE5 |
20851 | #define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 |
20852 | #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 |
20853 | #define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb |
20854 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20855 | #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 |
20856 | #define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL |
20857 | #define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L |
20858 | #define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L |
20859 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20860 | #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L |
20861 | //GB_TILE_MODE6 |
20862 | #define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 |
20863 | #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 |
20864 | #define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb |
20865 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20866 | #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 |
20867 | #define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL |
20868 | #define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L |
20869 | #define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L |
20870 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20871 | #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L |
20872 | //GB_TILE_MODE7 |
20873 | #define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 |
20874 | #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 |
20875 | #define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb |
20876 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20877 | #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 |
20878 | #define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL |
20879 | #define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L |
20880 | #define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L |
20881 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20882 | #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L |
20883 | //GB_TILE_MODE8 |
20884 | #define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 |
20885 | #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 |
20886 | #define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb |
20887 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20888 | #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 |
20889 | #define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL |
20890 | #define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L |
20891 | #define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L |
20892 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20893 | #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L |
20894 | //GB_TILE_MODE9 |
20895 | #define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 |
20896 | #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 |
20897 | #define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb |
20898 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20899 | #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 |
20900 | #define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL |
20901 | #define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L |
20902 | #define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L |
20903 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20904 | #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L |
20905 | //GB_TILE_MODE10 |
20906 | #define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 |
20907 | #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 |
20908 | #define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb |
20909 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20910 | #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 |
20911 | #define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL |
20912 | #define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L |
20913 | #define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L |
20914 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20915 | #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L |
20916 | //GB_TILE_MODE11 |
20917 | #define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 |
20918 | #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 |
20919 | #define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb |
20920 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20921 | #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 |
20922 | #define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL |
20923 | #define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L |
20924 | #define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L |
20925 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20926 | #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L |
20927 | //GB_TILE_MODE12 |
20928 | #define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 |
20929 | #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 |
20930 | #define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb |
20931 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20932 | #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 |
20933 | #define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL |
20934 | #define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L |
20935 | #define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L |
20936 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20937 | #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L |
20938 | //GB_TILE_MODE13 |
20939 | #define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 |
20940 | #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 |
20941 | #define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb |
20942 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20943 | #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 |
20944 | #define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL |
20945 | #define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L |
20946 | #define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L |
20947 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20948 | #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L |
20949 | //GB_TILE_MODE14 |
20950 | #define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 |
20951 | #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 |
20952 | #define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb |
20953 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20954 | #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 |
20955 | #define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL |
20956 | #define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L |
20957 | #define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L |
20958 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20959 | #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L |
20960 | //GB_TILE_MODE15 |
20961 | #define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 |
20962 | #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 |
20963 | #define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb |
20964 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20965 | #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 |
20966 | #define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL |
20967 | #define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L |
20968 | #define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L |
20969 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20970 | #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L |
20971 | //GB_TILE_MODE16 |
20972 | #define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 |
20973 | #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 |
20974 | #define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb |
20975 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20976 | #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 |
20977 | #define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL |
20978 | #define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L |
20979 | #define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L |
20980 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20981 | #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L |
20982 | //GB_TILE_MODE17 |
20983 | #define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 |
20984 | #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 |
20985 | #define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb |
20986 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20987 | #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 |
20988 | #define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL |
20989 | #define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L |
20990 | #define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L |
20991 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
20992 | #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L |
20993 | //GB_TILE_MODE18 |
20994 | #define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 |
20995 | #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 |
20996 | #define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb |
20997 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
20998 | #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 |
20999 | #define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL |
21000 | #define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L |
21001 | #define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L |
21002 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21003 | #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L |
21004 | //GB_TILE_MODE19 |
21005 | #define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 |
21006 | #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 |
21007 | #define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb |
21008 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21009 | #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 |
21010 | #define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL |
21011 | #define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L |
21012 | #define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L |
21013 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21014 | #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L |
21015 | //GB_TILE_MODE20 |
21016 | #define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 |
21017 | #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 |
21018 | #define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb |
21019 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21020 | #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 |
21021 | #define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL |
21022 | #define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L |
21023 | #define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L |
21024 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21025 | #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L |
21026 | //GB_TILE_MODE21 |
21027 | #define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 |
21028 | #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 |
21029 | #define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb |
21030 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21031 | #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 |
21032 | #define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL |
21033 | #define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L |
21034 | #define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L |
21035 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21036 | #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L |
21037 | //GB_TILE_MODE22 |
21038 | #define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 |
21039 | #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 |
21040 | #define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb |
21041 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21042 | #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 |
21043 | #define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL |
21044 | #define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L |
21045 | #define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L |
21046 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21047 | #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L |
21048 | //GB_TILE_MODE23 |
21049 | #define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 |
21050 | #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 |
21051 | #define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb |
21052 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21053 | #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 |
21054 | #define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL |
21055 | #define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L |
21056 | #define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L |
21057 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21058 | #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L |
21059 | //GB_TILE_MODE24 |
21060 | #define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 |
21061 | #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 |
21062 | #define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb |
21063 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21064 | #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 |
21065 | #define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL |
21066 | #define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L |
21067 | #define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L |
21068 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21069 | #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L |
21070 | //GB_TILE_MODE25 |
21071 | #define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 |
21072 | #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 |
21073 | #define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb |
21074 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21075 | #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 |
21076 | #define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL |
21077 | #define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L |
21078 | #define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L |
21079 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21080 | #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L |
21081 | //GB_TILE_MODE26 |
21082 | #define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 |
21083 | #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 |
21084 | #define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb |
21085 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21086 | #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 |
21087 | #define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL |
21088 | #define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L |
21089 | #define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L |
21090 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21091 | #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L |
21092 | //GB_TILE_MODE27 |
21093 | #define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 |
21094 | #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 |
21095 | #define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb |
21096 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21097 | #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 |
21098 | #define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL |
21099 | #define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L |
21100 | #define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L |
21101 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21102 | #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L |
21103 | //GB_TILE_MODE28 |
21104 | #define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 |
21105 | #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 |
21106 | #define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb |
21107 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21108 | #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 |
21109 | #define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL |
21110 | #define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L |
21111 | #define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L |
21112 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21113 | #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L |
21114 | //GB_TILE_MODE29 |
21115 | #define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 |
21116 | #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 |
21117 | #define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb |
21118 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21119 | #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 |
21120 | #define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL |
21121 | #define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L |
21122 | #define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L |
21123 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21124 | #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L |
21125 | //GB_TILE_MODE30 |
21126 | #define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 |
21127 | #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 |
21128 | #define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb |
21129 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21130 | #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 |
21131 | #define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL |
21132 | #define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L |
21133 | #define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L |
21134 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21135 | #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L |
21136 | //GB_TILE_MODE31 |
21137 | #define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 |
21138 | #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 |
21139 | #define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb |
21140 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
21141 | #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 |
21142 | #define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL |
21143 | #define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L |
21144 | #define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L |
21145 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
21146 | #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L |
21147 | //GB_MACROTILE_MODE0 |
21148 | #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 |
21149 | #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 |
21150 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 |
21151 | #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 |
21152 | #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L |
21153 | #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL |
21154 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L |
21155 | #define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L |
21156 | //GB_MACROTILE_MODE1 |
21157 | #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 |
21158 | #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 |
21159 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 |
21160 | #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 |
21161 | #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L |
21162 | #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL |
21163 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L |
21164 | #define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L |
21165 | //GB_MACROTILE_MODE2 |
21166 | #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 |
21167 | #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 |
21168 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 |
21169 | #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 |
21170 | #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L |
21171 | #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL |
21172 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L |
21173 | #define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L |
21174 | //GB_MACROTILE_MODE3 |
21175 | #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 |
21176 | #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 |
21177 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 |
21178 | #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 |
21179 | #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L |
21180 | #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL |
21181 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L |
21182 | #define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L |
21183 | //GB_MACROTILE_MODE4 |
21184 | #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 |
21185 | #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 |
21186 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 |
21187 | #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 |
21188 | #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L |
21189 | #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL |
21190 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L |
21191 | #define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L |
21192 | //GB_MACROTILE_MODE5 |
21193 | #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 |
21194 | #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 |
21195 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 |
21196 | #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 |
21197 | #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L |
21198 | #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL |
21199 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L |
21200 | #define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L |
21201 | //GB_MACROTILE_MODE6 |
21202 | #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 |
21203 | #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 |
21204 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 |
21205 | #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 |
21206 | #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L |
21207 | #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL |
21208 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L |
21209 | #define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L |
21210 | //GB_MACROTILE_MODE7 |
21211 | #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 |
21212 | #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 |
21213 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 |
21214 | #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 |
21215 | #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L |
21216 | #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL |
21217 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L |
21218 | #define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L |
21219 | //GB_MACROTILE_MODE8 |
21220 | #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 |
21221 | #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 |
21222 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 |
21223 | #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 |
21224 | #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L |
21225 | #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL |
21226 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L |
21227 | #define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L |
21228 | //GB_MACROTILE_MODE9 |
21229 | #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 |
21230 | #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 |
21231 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 |
21232 | #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 |
21233 | #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L |
21234 | #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL |
21235 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L |
21236 | #define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L |
21237 | //GB_MACROTILE_MODE10 |
21238 | #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 |
21239 | #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 |
21240 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 |
21241 | #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 |
21242 | #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L |
21243 | #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL |
21244 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L |
21245 | #define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L |
21246 | //GB_MACROTILE_MODE11 |
21247 | #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 |
21248 | #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 |
21249 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 |
21250 | #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 |
21251 | #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L |
21252 | #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL |
21253 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L |
21254 | #define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L |
21255 | //GB_MACROTILE_MODE12 |
21256 | #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 |
21257 | #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 |
21258 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 |
21259 | #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 |
21260 | #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L |
21261 | #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL |
21262 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L |
21263 | #define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L |
21264 | //GB_MACROTILE_MODE13 |
21265 | #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 |
21266 | #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 |
21267 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 |
21268 | #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 |
21269 | #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L |
21270 | #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL |
21271 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L |
21272 | #define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L |
21273 | //GB_MACROTILE_MODE14 |
21274 | #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 |
21275 | #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 |
21276 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 |
21277 | #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 |
21278 | #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L |
21279 | #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL |
21280 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L |
21281 | #define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L |
21282 | //GB_MACROTILE_MODE15 |
21283 | #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 |
21284 | #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 |
21285 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 |
21286 | #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 |
21287 | #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L |
21288 | #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL |
21289 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L |
21290 | #define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L |
21291 | //CB_HW_CONTROL |
21292 | #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 |
21293 | #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 |
21294 | #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc |
21295 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 |
21296 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 |
21297 | #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 |
21298 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 |
21299 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 |
21300 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 |
21301 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 |
21302 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 |
21303 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 |
21304 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a |
21305 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b |
21306 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c |
21307 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d |
21308 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e |
21309 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f |
21310 | #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL |
21311 | #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L |
21312 | #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L |
21313 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L |
21314 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L |
21315 | #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L |
21316 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L |
21317 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L |
21318 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L |
21319 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L |
21320 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L |
21321 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L |
21322 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L |
21323 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L |
21324 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L |
21325 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L |
21326 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L |
21327 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L |
21328 | //CB_HW_CONTROL_1 |
21329 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 |
21330 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 |
21331 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb |
21332 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 |
21333 | #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a |
21334 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL |
21335 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L |
21336 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L |
21337 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L |
21338 | #define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L |
21339 | //CB_HW_CONTROL_2 |
21340 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 |
21341 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 |
21342 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf |
21343 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 |
21344 | #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c |
21345 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL |
21346 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L |
21347 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L |
21348 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L |
21349 | #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L |
21350 | //CB_HW_CONTROL_3 |
21351 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 |
21352 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 |
21353 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 |
21354 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 |
21355 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 |
21356 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 |
21357 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 |
21358 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 |
21359 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 |
21360 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa |
21361 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb |
21362 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc |
21363 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd |
21364 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe |
21365 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf |
21366 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 |
21367 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 |
21368 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 |
21369 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 |
21370 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 |
21371 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 |
21372 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 |
21373 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 |
21374 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 |
21375 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 |
21376 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a |
21377 | #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b |
21378 | #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c |
21379 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L |
21380 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L |
21381 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L |
21382 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L |
21383 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L |
21384 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L |
21385 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L |
21386 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L |
21387 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L |
21388 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L |
21389 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L |
21390 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L |
21391 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L |
21392 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L |
21393 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L |
21394 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L |
21395 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L |
21396 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L |
21397 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L |
21398 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L |
21399 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L |
21400 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L |
21401 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L |
21402 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L |
21403 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L |
21404 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L |
21405 | #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L |
21406 | #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L |
21407 | //CB_HW_MEM_ARBITER_RD |
21408 | #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 |
21409 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 |
21410 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 |
21411 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa |
21412 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc |
21413 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe |
21414 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 |
21415 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 |
21416 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
21417 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 |
21418 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 |
21419 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a |
21420 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
21421 | #define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L |
21422 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL |
21423 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L |
21424 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L |
21425 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L |
21426 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L |
21427 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L |
21428 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
21429 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
21430 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L |
21431 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L |
21432 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L |
21433 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
21434 | //CB_HW_MEM_ARBITER_WR |
21435 | #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 |
21436 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 |
21437 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 |
21438 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa |
21439 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc |
21440 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe |
21441 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 |
21442 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 |
21443 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
21444 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 |
21445 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 |
21446 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a |
21447 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
21448 | #define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L |
21449 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL |
21450 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L |
21451 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L |
21452 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L |
21453 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L |
21454 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L |
21455 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
21456 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
21457 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L |
21458 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L |
21459 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L |
21460 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
21461 | //CB_DCC_CONFIG |
21462 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 |
21463 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 |
21464 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 |
21465 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 |
21466 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 |
21467 | #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 |
21468 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c |
21469 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL |
21470 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L |
21471 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L |
21472 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L |
21473 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L |
21474 | #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L |
21475 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L |
21476 | //GC_USER_RB_REDUNDANCY |
21477 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
21478 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
21479 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
21480 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
21481 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
21482 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
21483 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
21484 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
21485 | //GC_USER_RB_BACKEND_DISABLE |
21486 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
21487 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
21488 | |
21489 | |
21490 | // addressBlock: gc_rlcpdec |
21491 | //RLC_CNTL |
21492 | #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 |
21493 | #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 |
21494 | #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 |
21495 | #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 |
21496 | #define RLC_CNTL__RESERVED__SHIFT 0x4 |
21497 | #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L |
21498 | #define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L |
21499 | #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L |
21500 | #define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L |
21501 | #define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L |
21502 | //RLC_STAT |
21503 | #define RLC_STAT__RLC_BUSY__SHIFT 0x0 |
21504 | #define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 |
21505 | #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 |
21506 | #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 |
21507 | #define RLC_STAT__MC_BUSY__SHIFT 0x4 |
21508 | #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 |
21509 | #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 |
21510 | #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 |
21511 | #define RLC_STAT__RESERVED__SHIFT 0x8 |
21512 | #define RLC_STAT__RLC_BUSY_MASK 0x00000001L |
21513 | #define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L |
21514 | #define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L |
21515 | #define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L |
21516 | #define RLC_STAT__MC_BUSY_MASK 0x00000010L |
21517 | #define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L |
21518 | #define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L |
21519 | #define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L |
21520 | #define RLC_STAT__RESERVED_MASK 0xFFFFFF00L |
21521 | //RLC_SAFE_MODE |
21522 | #define RLC_SAFE_MODE__CMD__SHIFT 0x0 |
21523 | #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 |
21524 | #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 |
21525 | #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 |
21526 | #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc |
21527 | #define RLC_SAFE_MODE__CMD_MASK 0x00000001L |
21528 | #define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
21529 | #define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
21530 | #define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
21531 | #define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
21532 | //RLC_MEM_SLP_CNTL |
21533 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 |
21534 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 |
21535 | #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
21536 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
21537 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 |
21538 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 |
21539 | #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
21540 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L |
21541 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L |
21542 | #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
21543 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
21544 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
21545 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
21546 | #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
21547 | //RLC_RLCV_SAFE_MODE |
21548 | #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 |
21549 | #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 |
21550 | #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 |
21551 | #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 |
21552 | #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc |
21553 | #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L |
21554 | #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
21555 | #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
21556 | #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
21557 | #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
21558 | //RLC_RLCV_COMMAND |
21559 | #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 |
21560 | #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 |
21561 | #define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL |
21562 | #define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L |
21563 | //RLC_REFCLOCK_TIMESTAMP_LSB |
21564 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 |
21565 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL |
21566 | //RLC_REFCLOCK_TIMESTAMP_MSB |
21567 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 |
21568 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL |
21569 | //RLC_GPM_TIMER_INT_0 |
21570 | #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 |
21571 | #define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
21572 | //RLC_GPM_TIMER_INT_1 |
21573 | #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 |
21574 | #define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
21575 | //RLC_GPM_TIMER_INT_2 |
21576 | #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 |
21577 | #define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL |
21578 | //RLC_GPM_TIMER_CTRL |
21579 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
21580 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
21581 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 |
21582 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 |
21583 | #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 |
21584 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
21585 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
21586 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L |
21587 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L |
21588 | #define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L |
21589 | //RLC_LB_CNTR_MAX |
21590 | #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 |
21591 | #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL |
21592 | //RLC_GPM_TIMER_STAT |
21593 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
21594 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
21595 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 |
21596 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 |
21597 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
21598 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
21599 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa |
21600 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb |
21601 | #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc |
21602 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
21603 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
21604 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L |
21605 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L |
21606 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
21607 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
21608 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L |
21609 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L |
21610 | #define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L |
21611 | //RLC_GPM_TIMER_INT_3 |
21612 | #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 |
21613 | #define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL |
21614 | //RLC_SERDES_WR_NONCU_MASTER_MASK_1 |
21615 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 |
21616 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 |
21617 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 |
21618 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 |
21619 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 |
21620 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 |
21621 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 |
21622 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 |
21623 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 |
21624 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 |
21625 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 |
21626 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL |
21627 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L |
21628 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L |
21629 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L |
21630 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L |
21631 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L |
21632 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L |
21633 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L |
21634 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L |
21635 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L |
21636 | #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L |
21637 | //RLC_SERDES_NONCU_MASTER_BUSY_1 |
21638 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 |
21639 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 |
21640 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 |
21641 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 |
21642 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 |
21643 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 |
21644 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 |
21645 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 |
21646 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 |
21647 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 |
21648 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 |
21649 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL |
21650 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L |
21651 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L |
21652 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L |
21653 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L |
21654 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L |
21655 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L |
21656 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L |
21657 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L |
21658 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L |
21659 | #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L |
21660 | //RLC_INT_STAT |
21661 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 |
21662 | #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 |
21663 | #define RLC_INT_STAT__RESERVED__SHIFT 0x9 |
21664 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL |
21665 | #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L |
21666 | #define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L |
21667 | //RLC_LB_CNTL |
21668 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 |
21669 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 |
21670 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 |
21671 | #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 |
21672 | #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 |
21673 | #define RLC_LB_CNTL__RESERVED__SHIFT 0xc |
21674 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L |
21675 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L |
21676 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L |
21677 | #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L |
21678 | #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L |
21679 | #define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L |
21680 | //RLC_MGCG_CTRL |
21681 | #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 |
21682 | #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 |
21683 | #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 |
21684 | #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 |
21685 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 |
21686 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf |
21687 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 |
21688 | #define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 |
21689 | #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L |
21690 | #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L |
21691 | #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L |
21692 | #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L |
21693 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L |
21694 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L |
21695 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L |
21696 | #define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L |
21697 | //RLC_LB_CNTR_INIT |
21698 | #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 |
21699 | #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL |
21700 | //RLC_LOAD_BALANCE_CNTR |
21701 | #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 |
21702 | #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL |
21703 | //RLC_JUMP_TABLE_RESTORE |
21704 | #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 |
21705 | #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL |
21706 | //RLC_PG_DELAY_2 |
21707 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 |
21708 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 |
21709 | #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 |
21710 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL |
21711 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L |
21712 | #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L |
21713 | //RLC_GPU_CLOCK_COUNT_LSB |
21714 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
21715 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
21716 | //RLC_GPU_CLOCK_COUNT_MSB |
21717 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
21718 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
21719 | //RLC_CAPTURE_GPU_CLOCK_COUNT |
21720 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 |
21721 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 |
21722 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L |
21723 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL |
21724 | //RLC_UCODE_CNTL |
21725 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 |
21726 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL |
21727 | //RLC_GPM_THREAD_RESET |
21728 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 |
21729 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 |
21730 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 |
21731 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 |
21732 | #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 |
21733 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L |
21734 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L |
21735 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L |
21736 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L |
21737 | #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L |
21738 | //RLC_GPM_CP_DMA_COMPLETE_T0 |
21739 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 |
21740 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 |
21741 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L |
21742 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL |
21743 | //RLC_GPM_CP_DMA_COMPLETE_T1 |
21744 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 |
21745 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 |
21746 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L |
21747 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL |
21748 | //RLC_CLK_COUNT_GFXCLK_LSB |
21749 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 |
21750 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
21751 | //RLC_CLK_COUNT_GFXCLK_MSB |
21752 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 |
21753 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
21754 | //RLC_CLK_COUNT_REFCLK_LSB |
21755 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 |
21756 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
21757 | //RLC_CLK_COUNT_REFCLK_MSB |
21758 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 |
21759 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
21760 | //RLC_CLK_COUNT_CTRL |
21761 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 |
21762 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 |
21763 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 |
21764 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 |
21765 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 |
21766 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 |
21767 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L |
21768 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L |
21769 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L |
21770 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L |
21771 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L |
21772 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L |
21773 | //RLC_CLK_COUNT_STAT |
21774 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 |
21775 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 |
21776 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 |
21777 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 |
21778 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 |
21779 | #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 |
21780 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L |
21781 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L |
21782 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L |
21783 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L |
21784 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L |
21785 | #define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L |
21786 | //RLC_GPM_STAT |
21787 | #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
21788 | #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
21789 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
21790 | #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
21791 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
21792 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
21793 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
21794 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
21795 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
21796 | #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
21797 | #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
21798 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
21799 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
21800 | #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd |
21801 | #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe |
21802 | #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf |
21803 | #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 |
21804 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
21805 | #define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 |
21806 | #define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13 |
21807 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
21808 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
21809 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
21810 | #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
21811 | #define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
21812 | #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
21813 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
21814 | #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
21815 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
21816 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
21817 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
21818 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
21819 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
21820 | #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
21821 | #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
21822 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
21823 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
21824 | #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L |
21825 | #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L |
21826 | #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L |
21827 | #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L |
21828 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
21829 | #define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L |
21830 | #define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L |
21831 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
21832 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
21833 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
21834 | #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
21835 | //RLC_GPU_CLOCK_32_RES_SEL |
21836 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 |
21837 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 |
21838 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL |
21839 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L |
21840 | //RLC_GPU_CLOCK_32 |
21841 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 |
21842 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL |
21843 | //RLC_PG_CNTL |
21844 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 |
21845 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 |
21846 | #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 |
21847 | #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 |
21848 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 |
21849 | #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 |
21850 | #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe |
21851 | #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf |
21852 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 |
21853 | #define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 |
21854 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 |
21855 | #define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 |
21856 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L |
21857 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L |
21858 | #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L |
21859 | #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L |
21860 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L |
21861 | #define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L |
21862 | #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L |
21863 | #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L |
21864 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L |
21865 | #define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L |
21866 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L |
21867 | #define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L |
21868 | //RLC_GPM_THREAD_PRIORITY |
21869 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 |
21870 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 |
21871 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 |
21872 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 |
21873 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL |
21874 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L |
21875 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L |
21876 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L |
21877 | //RLC_GPM_THREAD_ENABLE |
21878 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 |
21879 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 |
21880 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 |
21881 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 |
21882 | #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 |
21883 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L |
21884 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L |
21885 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L |
21886 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L |
21887 | #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L |
21888 | //RLC_CGTT_MGCG_OVERRIDE |
21889 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 |
21890 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 |
21891 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 |
21892 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 |
21893 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 |
21894 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 |
21895 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 |
21896 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 |
21897 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 |
21898 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE__SHIFT 0x9 |
21899 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10__SHIFT 0xa |
21900 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 |
21901 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 |
21902 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L |
21903 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L |
21904 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L |
21905 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L |
21906 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L |
21907 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L |
21908 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L |
21909 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L |
21910 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L |
21911 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK 0x00000200L |
21912 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_10_MASK 0x0000FC00L |
21913 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L |
21914 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L |
21915 | //RLC_CGCG_CGLS_CTRL |
21916 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 |
21917 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 |
21918 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
21919 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
21920 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b |
21921 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c |
21922 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d |
21923 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f |
21924 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L |
21925 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L |
21926 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
21927 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
21928 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L |
21929 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L |
21930 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L |
21931 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L |
21932 | //RLC_CGCG_RAMP_CTRL |
21933 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 |
21934 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
21935 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 |
21936 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc |
21937 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 |
21938 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c |
21939 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
21940 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
21941 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L |
21942 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
21943 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L |
21944 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L |
21945 | //RLC_DYN_PG_STATUS |
21946 | #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 |
21947 | #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL |
21948 | //RLC_DYN_PG_REQUEST |
21949 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 |
21950 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL |
21951 | //RLC_PG_DELAY |
21952 | #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 |
21953 | #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 |
21954 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 |
21955 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 |
21956 | #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL |
21957 | #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L |
21958 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L |
21959 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L |
21960 | //RLC_CU_STATUS |
21961 | #define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 |
21962 | #define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL |
21963 | //RLC_LB_INIT_CU_MASK |
21964 | #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 |
21965 | #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL |
21966 | //RLC_LB_ALWAYS_ACTIVE_CU_MASK |
21967 | #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 |
21968 | #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL |
21969 | //RLC_LB_PARAMS |
21970 | #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 |
21971 | #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 |
21972 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 |
21973 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 |
21974 | #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L |
21975 | #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL |
21976 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L |
21977 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
21978 | //RLC_THREAD1_DELAY |
21979 | #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 |
21980 | #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 |
21981 | #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 |
21982 | #define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 |
21983 | #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL |
21984 | #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L |
21985 | #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L |
21986 | #define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L |
21987 | //RLC_PG_ALWAYS_ON_CU_MASK |
21988 | #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 |
21989 | #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL |
21990 | //RLC_MAX_PG_CU |
21991 | #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 |
21992 | #define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 |
21993 | #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL |
21994 | #define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L |
21995 | //RLC_AUTO_PG_CTRL |
21996 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 |
21997 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 |
21998 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 |
21999 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 |
22000 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 |
22001 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L |
22002 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L |
22003 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L |
22004 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L |
22005 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L |
22006 | //RLC_SERDES_RD_PENDING |
22007 | #define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0 |
22008 | #define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L |
22009 | //RLC_SERDES_RD_MASTER_INDEX |
22010 | #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 |
22011 | #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 |
22012 | #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 |
22013 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 |
22014 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc |
22015 | #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd |
22016 | #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 |
22017 | #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 |
22018 | #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL |
22019 | #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L |
22020 | #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L |
22021 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L |
22022 | #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L |
22023 | #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L |
22024 | #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L |
22025 | #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L |
22026 | //RLC_SERDES_RD_DATA_0 |
22027 | #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 |
22028 | #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL |
22029 | //RLC_SERDES_RD_DATA_1 |
22030 | #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 |
22031 | #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL |
22032 | //RLC_SERDES_RD_DATA_2 |
22033 | #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 |
22034 | #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL |
22035 | //RLC_SERDES_WR_CU_MASTER_MASK |
22036 | #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 |
22037 | #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL |
22038 | //RLC_SERDES_WR_NONCU_MASTER_MASK |
22039 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 |
22040 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 |
22041 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 |
22042 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 |
22043 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 |
22044 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 |
22045 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 |
22046 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 |
22047 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 |
22048 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 |
22049 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 |
22050 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a |
22051 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL |
22052 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L |
22053 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L |
22054 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L |
22055 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L |
22056 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L |
22057 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L |
22058 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L |
22059 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L |
22060 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L |
22061 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L |
22062 | #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L |
22063 | //RLC_SERDES_WR_CTRL |
22064 | #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 |
22065 | #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 |
22066 | #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 |
22067 | #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa |
22068 | #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb |
22069 | #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc |
22070 | #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd |
22071 | #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe |
22072 | #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf |
22073 | #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 |
22074 | #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a |
22075 | #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b |
22076 | #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c |
22077 | #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL |
22078 | #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L |
22079 | #define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L |
22080 | #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L |
22081 | #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L |
22082 | #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L |
22083 | #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L |
22084 | #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L |
22085 | #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L |
22086 | #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L |
22087 | #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L |
22088 | #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L |
22089 | #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L |
22090 | //RLC_SERDES_WR_DATA |
22091 | #define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 |
22092 | #define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL |
22093 | //RLC_SERDES_CU_MASTER_BUSY |
22094 | #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 |
22095 | #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL |
22096 | //RLC_SERDES_NONCU_MASTER_BUSY |
22097 | #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 |
22098 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 |
22099 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 |
22100 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 |
22101 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 |
22102 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 |
22103 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 |
22104 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 |
22105 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 |
22106 | #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 |
22107 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 |
22108 | #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a |
22109 | #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL |
22110 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L |
22111 | #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L |
22112 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L |
22113 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L |
22114 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L |
22115 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L |
22116 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L |
22117 | #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L |
22118 | #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L |
22119 | #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L |
22120 | #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L |
22121 | //RLC_GPM_GENERAL_0 |
22122 | #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 |
22123 | #define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
22124 | //RLC_GPM_GENERAL_1 |
22125 | #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 |
22126 | #define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
22127 | //RLC_GPM_GENERAL_2 |
22128 | #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 |
22129 | #define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
22130 | //RLC_GPM_GENERAL_3 |
22131 | #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 |
22132 | #define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
22133 | //RLC_GPM_GENERAL_4 |
22134 | #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 |
22135 | #define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
22136 | //RLC_GPM_GENERAL_5 |
22137 | #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 |
22138 | #define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
22139 | //RLC_GPM_GENERAL_6 |
22140 | #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 |
22141 | #define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
22142 | //RLC_GPM_GENERAL_7 |
22143 | #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 |
22144 | #define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
22145 | //RLC_GPM_SCRATCH_ADDR |
22146 | #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
22147 | #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 |
22148 | #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL |
22149 | #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L |
22150 | //RLC_GPM_SCRATCH_DATA |
22151 | #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 |
22152 | #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
22153 | //RLC_STATIC_PG_STATUS |
22154 | #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 |
22155 | #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL |
22156 | //RLC_SPM_MC_CNTL |
22157 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 |
22158 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 |
22159 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 |
22160 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 |
22161 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 |
22162 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 |
22163 | #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa |
22164 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL |
22165 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L |
22166 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L |
22167 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L |
22168 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L |
22169 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L |
22170 | #define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L |
22171 | //RLC_SPM_INT_CNTL |
22172 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 |
22173 | #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 |
22174 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L |
22175 | #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL |
22176 | //RLC_SPM_INT_STATUS |
22177 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 |
22178 | #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 |
22179 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L |
22180 | #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL |
22181 | //RLC_GPM_LOG_SIZE |
22182 | #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 |
22183 | #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL |
22184 | //RLC_PG_DELAY_3 |
22185 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 |
22186 | #define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 |
22187 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL |
22188 | #define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L |
22189 | //RLC_GPR_REG1 |
22190 | #define RLC_GPR_REG1__DATA__SHIFT 0x0 |
22191 | #define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL |
22192 | //RLC_GPR_REG2 |
22193 | #define RLC_GPR_REG2__DATA__SHIFT 0x0 |
22194 | #define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL |
22195 | //RLC_GPM_LOG_CONT |
22196 | #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 |
22197 | #define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL |
22198 | //RLC_GPM_INT_DISABLE_TH0 |
22199 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 |
22200 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL |
22201 | //RLC_GPM_INT_FORCE_TH0 |
22202 | #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 |
22203 | #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL |
22204 | //RLC_GPM_INT_FORCE_TH1 |
22205 | #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 |
22206 | #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL |
22207 | //RLC_SRM_CNTL |
22208 | #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 |
22209 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 |
22210 | #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 |
22211 | #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L |
22212 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L |
22213 | #define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL |
22214 | //RLC_SRM_ARAM_ADDR |
22215 | #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 |
22216 | #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc |
22217 | #define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL |
22218 | #define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L |
22219 | //RLC_SRM_ARAM_DATA |
22220 | #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 |
22221 | #define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL |
22222 | //RLC_SRM_DRAM_ADDR |
22223 | #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 |
22224 | #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc |
22225 | #define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL |
22226 | #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L |
22227 | //RLC_SRM_DRAM_DATA |
22228 | #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 |
22229 | #define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL |
22230 | //RLC_SRM_GPM_COMMAND |
22231 | #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 |
22232 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 |
22233 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 |
22234 | #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 |
22235 | #define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10 |
22236 | #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 |
22237 | #define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d |
22238 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f |
22239 | #define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L |
22240 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L |
22241 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL |
22242 | #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L |
22243 | #define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L |
22244 | #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L |
22245 | #define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L |
22246 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L |
22247 | //RLC_SRM_GPM_COMMAND_STATUS |
22248 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
22249 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
22250 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
22251 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
22252 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
22253 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
22254 | //RLC_SRM_RLCV_COMMAND |
22255 | #define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 |
22256 | #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 |
22257 | #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 |
22258 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 |
22259 | #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c |
22260 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f |
22261 | #define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L |
22262 | #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL |
22263 | #define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L |
22264 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L |
22265 | #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L |
22266 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L |
22267 | //RLC_SRM_RLCV_COMMAND_STATUS |
22268 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
22269 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
22270 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
22271 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
22272 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
22273 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
22274 | //RLC_SRM_INDEX_CNTL_ADDR_0 |
22275 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 |
22276 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 |
22277 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL |
22278 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L |
22279 | //RLC_SRM_INDEX_CNTL_ADDR_1 |
22280 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 |
22281 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 |
22282 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL |
22283 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L |
22284 | //RLC_SRM_INDEX_CNTL_ADDR_2 |
22285 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 |
22286 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 |
22287 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL |
22288 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L |
22289 | //RLC_SRM_INDEX_CNTL_ADDR_3 |
22290 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 |
22291 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 |
22292 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL |
22293 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L |
22294 | //RLC_SRM_INDEX_CNTL_ADDR_4 |
22295 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 |
22296 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 |
22297 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL |
22298 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L |
22299 | //RLC_SRM_INDEX_CNTL_ADDR_5 |
22300 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 |
22301 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 |
22302 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL |
22303 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L |
22304 | //RLC_SRM_INDEX_CNTL_ADDR_6 |
22305 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 |
22306 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 |
22307 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL |
22308 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L |
22309 | //RLC_SRM_INDEX_CNTL_ADDR_7 |
22310 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 |
22311 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 |
22312 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL |
22313 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L |
22314 | //RLC_SRM_INDEX_CNTL_DATA_0 |
22315 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 |
22316 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL |
22317 | //RLC_SRM_INDEX_CNTL_DATA_1 |
22318 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 |
22319 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL |
22320 | //RLC_SRM_INDEX_CNTL_DATA_2 |
22321 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 |
22322 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL |
22323 | //RLC_SRM_INDEX_CNTL_DATA_3 |
22324 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 |
22325 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL |
22326 | //RLC_SRM_INDEX_CNTL_DATA_4 |
22327 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 |
22328 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL |
22329 | //RLC_SRM_INDEX_CNTL_DATA_5 |
22330 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 |
22331 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL |
22332 | //RLC_SRM_INDEX_CNTL_DATA_6 |
22333 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 |
22334 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL |
22335 | //RLC_SRM_INDEX_CNTL_DATA_7 |
22336 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 |
22337 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL |
22338 | //RLC_SRM_STAT |
22339 | #define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 |
22340 | #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 |
22341 | #define RLC_SRM_STAT__RESERVED__SHIFT 0x2 |
22342 | #define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L |
22343 | #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L |
22344 | #define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL |
22345 | //RLC_SRM_GPM_ABORT |
22346 | #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 |
22347 | #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 |
22348 | #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L |
22349 | #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL |
22350 | //RLC_CSIB_ADDR_LO |
22351 | #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 |
22352 | #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL |
22353 | //RLC_CSIB_ADDR_HI |
22354 | #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 |
22355 | #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL |
22356 | //RLC_CSIB_LENGTH |
22357 | #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 |
22358 | #define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL |
22359 | //RLC_CP_SCHEDULERS |
22360 | #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 |
22361 | #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 |
22362 | #define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 |
22363 | #define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 |
22364 | #define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL |
22365 | #define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L |
22366 | #define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L |
22367 | #define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L |
22368 | //RLC_GPM_GENERAL_8 |
22369 | #define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 |
22370 | #define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL |
22371 | //RLC_GPM_GENERAL_9 |
22372 | #define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 |
22373 | #define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL |
22374 | //RLC_GPM_GENERAL_10 |
22375 | #define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 |
22376 | #define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL |
22377 | //RLC_GPM_GENERAL_11 |
22378 | #define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 |
22379 | #define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL |
22380 | //RLC_GPM_GENERAL_12 |
22381 | #define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 |
22382 | #define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL |
22383 | //RLC_GPM_UTCL1_CNTL_0 |
22384 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
22385 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 |
22386 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 |
22387 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a |
22388 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b |
22389 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c |
22390 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
22391 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e |
22392 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
22393 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L |
22394 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L |
22395 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L |
22396 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L |
22397 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L |
22398 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
22399 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L |
22400 | //RLC_GPM_UTCL1_CNTL_1 |
22401 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
22402 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 |
22403 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 |
22404 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a |
22405 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b |
22406 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c |
22407 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
22408 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e |
22409 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
22410 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L |
22411 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L |
22412 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L |
22413 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L |
22414 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L |
22415 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
22416 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L |
22417 | //RLC_GPM_UTCL1_CNTL_2 |
22418 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
22419 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 |
22420 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 |
22421 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a |
22422 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b |
22423 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c |
22424 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
22425 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e |
22426 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
22427 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L |
22428 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L |
22429 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L |
22430 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L |
22431 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L |
22432 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
22433 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L |
22434 | //RLC_SPM_UTCL1_CNTL |
22435 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
22436 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
22437 | #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
22438 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
22439 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
22440 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
22441 | #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
22442 | #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
22443 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
22444 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
22445 | #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
22446 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
22447 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
22448 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
22449 | #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
22450 | #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
22451 | //RLC_UTCL1_STATUS_2 |
22452 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 |
22453 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 |
22454 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 |
22455 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 |
22456 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 |
22457 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 |
22458 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 |
22459 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 |
22460 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 |
22461 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 |
22462 | #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa |
22463 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L |
22464 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L |
22465 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L |
22466 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L |
22467 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L |
22468 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L |
22469 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L |
22470 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L |
22471 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L |
22472 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L |
22473 | #define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L |
22474 | //RLC_LB_THR_CONFIG_2 |
22475 | #define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 |
22476 | #define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL |
22477 | //RLC_LB_THR_CONFIG_3 |
22478 | #define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 |
22479 | #define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL |
22480 | //RLC_LB_THR_CONFIG_4 |
22481 | #define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 |
22482 | #define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL |
22483 | //RLC_SPM_UTCL1_ERROR_1 |
22484 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
22485 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
22486 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
22487 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
22488 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
22489 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
22490 | //RLC_SPM_UTCL1_ERROR_2 |
22491 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
22492 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
22493 | //RLC_GPM_UTCL1_TH0_ERROR_1 |
22494 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 |
22495 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
22496 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
22497 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L |
22498 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
22499 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
22500 | //RLC_LB_THR_CONFIG_1 |
22501 | #define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 |
22502 | #define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL |
22503 | //RLC_GPM_UTCL1_TH0_ERROR_2 |
22504 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
22505 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
22506 | //RLC_GPM_UTCL1_TH1_ERROR_1 |
22507 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
22508 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
22509 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
22510 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
22511 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
22512 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
22513 | //RLC_GPM_UTCL1_TH1_ERROR_2 |
22514 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
22515 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
22516 | //RLC_GPM_UTCL1_TH2_ERROR_1 |
22517 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 |
22518 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
22519 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
22520 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L |
22521 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
22522 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
22523 | //RLC_GPM_UTCL1_TH2_ERROR_2 |
22524 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
22525 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
22526 | //RLC_SEMAPHORE_0 |
22527 | #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
22528 | #define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
22529 | #define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
22530 | #define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
22531 | //RLC_SEMAPHORE_1 |
22532 | #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
22533 | #define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
22534 | #define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
22535 | #define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
22536 | //RLC_CP_EOF_INT |
22537 | #define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 |
22538 | #define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 |
22539 | #define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L |
22540 | #define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL |
22541 | //RLC_CP_EOF_INT_CNT |
22542 | #define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 |
22543 | #define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL |
22544 | //RLC_SPARE_INT |
22545 | #define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 |
22546 | #define RLC_SPARE_INT__RESERVED__SHIFT 0x1 |
22547 | #define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L |
22548 | #define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
22549 | //RLC_PREWALKER_UTCL1_CNTL |
22550 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
22551 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
22552 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
22553 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
22554 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
22555 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
22556 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
22557 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
22558 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
22559 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
22560 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
22561 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
22562 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
22563 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
22564 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
22565 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
22566 | //RLC_PREWALKER_UTCL1_TRIG |
22567 | #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 |
22568 | #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 |
22569 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 |
22570 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 |
22571 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 |
22572 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 |
22573 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 |
22574 | #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f |
22575 | #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L |
22576 | #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL |
22577 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L |
22578 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L |
22579 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L |
22580 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L |
22581 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L |
22582 | #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L |
22583 | //RLC_PREWALKER_UTCL1_ADDR_LSB |
22584 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 |
22585 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL |
22586 | //RLC_PREWALKER_UTCL1_ADDR_MSB |
22587 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 |
22588 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL |
22589 | //RLC_PREWALKER_UTCL1_SIZE_LSB |
22590 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 |
22591 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL |
22592 | //RLC_PREWALKER_UTCL1_SIZE_MSB |
22593 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 |
22594 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L |
22595 | //RLC_DSM_TRIG |
22596 | #define RLC_DSM_TRIG__START__SHIFT 0x0 |
22597 | #define RLC_DSM_TRIG__START_MASK 0x00000001L |
22598 | //RLC_UTCL1_STATUS |
22599 | #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
22600 | #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
22601 | #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
22602 | #define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
22603 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
22604 | #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe |
22605 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
22606 | #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 |
22607 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
22608 | #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e |
22609 | #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
22610 | #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
22611 | #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
22612 | #define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L |
22613 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
22614 | #define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L |
22615 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
22616 | #define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L |
22617 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
22618 | #define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L |
22619 | //RLC_R2I_CNTL_0 |
22620 | #define RLC_R2I_CNTL_0__Data__SHIFT 0x0 |
22621 | #define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL |
22622 | //RLC_R2I_CNTL_1 |
22623 | #define RLC_R2I_CNTL_1__Data__SHIFT 0x0 |
22624 | #define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL |
22625 | //RLC_R2I_CNTL_2 |
22626 | #define RLC_R2I_CNTL_2__Data__SHIFT 0x0 |
22627 | #define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL |
22628 | //RLC_R2I_CNTL_3 |
22629 | #define RLC_R2I_CNTL_3__Data__SHIFT 0x0 |
22630 | #define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL |
22631 | //RLC_UTCL2_CNTL |
22632 | #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 |
22633 | #define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 |
22634 | #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L |
22635 | #define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL |
22636 | //RLC_LBPW_CU_STAT |
22637 | #define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 |
22638 | #define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 |
22639 | #define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL |
22640 | #define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L |
22641 | //RLC_DS_CNTL |
22642 | #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 |
22643 | #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 |
22644 | #define RLC_DS_CNTL__RESRVED__SHIFT 0x2 |
22645 | #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 |
22646 | #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 |
22647 | #define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 |
22648 | #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L |
22649 | #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L |
22650 | #define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL |
22651 | #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L |
22652 | #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L |
22653 | #define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L |
22654 | //RLC_GPM_INT_STAT_TH0 |
22655 | #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 |
22656 | #define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL |
22657 | //RLC_GPM_GENERAL_13 |
22658 | #define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 |
22659 | #define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL |
22660 | //RLC_GPM_GENERAL_14 |
22661 | #define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 |
22662 | #define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL |
22663 | //RLC_GPM_GENERAL_15 |
22664 | #define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 |
22665 | #define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL |
22666 | //RLC_SPARE_INT_1 |
22667 | #define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
22668 | #define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1 |
22669 | #define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
22670 | #define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
22671 | //RLC_RLCV_SPARE_INT_1 |
22672 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
22673 | #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 |
22674 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
22675 | #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
22676 | //RLC_SEMAPHORE_2 |
22677 | #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
22678 | #define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
22679 | #define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
22680 | #define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
22681 | //RLC_SEMAPHORE_3 |
22682 | #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
22683 | #define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
22684 | #define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
22685 | #define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
22686 | //RLC_GPU_CLOCK_COUNT_LSB_1 |
22687 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 |
22688 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
22689 | //RLC_GPU_CLOCK_COUNT_MSB_1 |
22690 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 |
22691 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
22692 | //RLC_CAPTURE_GPU_CLOCK_COUNT_1 |
22693 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 |
22694 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 |
22695 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L |
22696 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL |
22697 | //RLC_GPU_CLOCK_COUNT_LSB_2 |
22698 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 |
22699 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
22700 | //RLC_GPU_CLOCK_COUNT_MSB_2 |
22701 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 |
22702 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
22703 | //RLC_CAPTURE_GPU_CLOCK_COUNT_2 |
22704 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 |
22705 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 |
22706 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L |
22707 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL |
22708 | //RLC_CPG_STAT_INVAL |
22709 | #define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0 |
22710 | #define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L |
22711 | //RLC_EDC_CNT |
22712 | #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT 0x0 |
22713 | #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT 0x2 |
22714 | #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 |
22715 | #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 |
22716 | #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT 0x8 |
22717 | #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT 0xa |
22718 | #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc |
22719 | #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT 0xe |
22720 | #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT 0x10 |
22721 | #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT 0x12 |
22722 | #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 |
22723 | #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 |
22724 | #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT 0x18 |
22725 | #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT 0x1a |
22726 | #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT 0x1c |
22727 | #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT 0x1e |
22728 | #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK 0x00000003L |
22729 | #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK 0x0000000CL |
22730 | #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L |
22731 | #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L |
22732 | #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK 0x00000300L |
22733 | #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK 0x00000C00L |
22734 | #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L |
22735 | #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L |
22736 | #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK 0x00030000L |
22737 | #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK 0x000C0000L |
22738 | #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L |
22739 | #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L |
22740 | #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK 0x03000000L |
22741 | #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK 0x0C000000L |
22742 | #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK 0x30000000L |
22743 | #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK 0xC0000000L |
22744 | //RLC_EDC_CNT2 |
22745 | #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT 0x0 |
22746 | #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT 0x2 |
22747 | #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 |
22748 | #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 |
22749 | #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT 0x8 |
22750 | #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT 0xa |
22751 | #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc |
22752 | #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT 0xe |
22753 | #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT 0x10 |
22754 | #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT 0x12 |
22755 | #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 |
22756 | #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 |
22757 | #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT 0x18 |
22758 | #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT 0x1a |
22759 | #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT 0x1c |
22760 | #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT 0x1e |
22761 | #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK 0x00000003L |
22762 | #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK 0x0000000CL |
22763 | #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L |
22764 | #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L |
22765 | #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK 0x00000300L |
22766 | #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK 0x00000C00L |
22767 | #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L |
22768 | #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L |
22769 | #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK 0x00030000L |
22770 | #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK 0x000C0000L |
22771 | #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L |
22772 | #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L |
22773 | #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK 0x03000000L |
22774 | #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK 0x0C000000L |
22775 | #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK 0x30000000L |
22776 | #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK 0xC0000000L |
22777 | //RLC_DSM_CNTL |
22778 | #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 |
22779 | #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
22780 | #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 |
22781 | #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
22782 | #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 |
22783 | #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
22784 | #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 |
22785 | #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
22786 | #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc |
22787 | #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe |
22788 | #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf |
22789 | #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
22790 | #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12 |
22791 | #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 |
22792 | #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15 |
22793 | #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 |
22794 | #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L |
22795 | #define RLC_DSM_CNTL__RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
22796 | #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L |
22797 | #define RLC_DSM_CNTL__RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
22798 | #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
22799 | #define RLC_DSM_CNTL__RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
22800 | #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L |
22801 | #define RLC_DSM_CNTL__RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
22802 | #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L |
22803 | #define RLC_DSM_CNTL__RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L |
22804 | #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L |
22805 | #define RLC_DSM_CNTL__RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
22806 | #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
22807 | #define RLC_DSM_CNTL__RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L |
22808 | #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L |
22809 | #define RLC_DSM_CNTL__RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L |
22810 | //RLC_DSM_CNTLA |
22811 | #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 |
22812 | #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
22813 | #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 |
22814 | #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
22815 | #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x6 |
22816 | #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
22817 | #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x9 |
22818 | #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
22819 | #define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc |
22820 | #define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe |
22821 | #define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf |
22822 | #define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
22823 | #define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x12 |
22824 | #define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 |
22825 | #define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL__SHIFT 0x15 |
22826 | #define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 |
22827 | #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L |
22828 | #define RLC_DSM_CNTLA__RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
22829 | #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L |
22830 | #define RLC_DSM_CNTLA__RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
22831 | #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
22832 | #define RLC_DSM_CNTLA__RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
22833 | #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00000600L |
22834 | #define RLC_DSM_CNTLA__RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
22835 | #define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L |
22836 | #define RLC_DSM_CNTLA__RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L |
22837 | #define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L |
22838 | #define RLC_DSM_CNTLA__RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
22839 | #define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
22840 | #define RLC_DSM_CNTLA__RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L |
22841 | #define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL_MASK 0x00600000L |
22842 | #define RLC_DSM_CNTLA__RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L |
22843 | //RLC_DSM_CNTL2 |
22844 | #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
22845 | #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
22846 | #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
22847 | #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 |
22848 | #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
22849 | #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
22850 | #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
22851 | #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
22852 | #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
22853 | #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
22854 | #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf |
22855 | #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11 |
22856 | #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
22857 | #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0x14 |
22858 | #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
22859 | #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
22860 | #define RLC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
22861 | #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
22862 | #define RLC_DSM_CNTL2__RLCG_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
22863 | #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
22864 | #define RLC_DSM_CNTL2__RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L |
22865 | #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
22866 | #define RLC_DSM_CNTL2__RLCV_INSTR_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
22867 | #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
22868 | #define RLC_DSM_CNTL2__RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
22869 | #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
22870 | #define RLC_DSM_CNTL2__RLC_TCTAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
22871 | #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
22872 | #define RLC_DSM_CNTL2__RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L |
22873 | #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
22874 | #define RLC_DSM_CNTL2__RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L |
22875 | #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
22876 | #define RLC_DSM_CNTL2__RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
22877 | #define RLC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
22878 | //RLC_DSM_CNTL2A |
22879 | #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
22880 | #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
22881 | #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
22882 | #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 |
22883 | #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
22884 | #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
22885 | #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
22886 | #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
22887 | #define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
22888 | #define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
22889 | #define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0xf |
22890 | #define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x11 |
22891 | #define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
22892 | #define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x14 |
22893 | #define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
22894 | #define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
22895 | #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
22896 | #define RLC_DSM_CNTL2A__RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
22897 | #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
22898 | #define RLC_DSM_CNTL2A__RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L |
22899 | #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
22900 | #define RLC_DSM_CNTL2A__RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
22901 | #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
22902 | #define RLC_DSM_CNTL2A__RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
22903 | #define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
22904 | #define RLC_DSM_CNTL2A__RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
22905 | #define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
22906 | #define RLC_DSM_CNTL2A__RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00020000L |
22907 | #define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
22908 | #define RLC_DSM_CNTL2A__RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00100000L |
22909 | #define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
22910 | #define RLC_DSM_CNTL2A__RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
22911 | //RLC_RLCV_SPARE_INT |
22912 | #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 |
22913 | #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 |
22914 | #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L |
22915 | #define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
22916 | |
22917 | |
22918 | // addressBlock: gc_rmi_rmidec |
22919 | //RMI_GENERAL_CNTL |
22920 | #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 |
22921 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 |
22922 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 |
22923 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 |
22924 | #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 |
22925 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 |
22926 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 |
22927 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a |
22928 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b |
22929 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c |
22930 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d |
22931 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e |
22932 | #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L |
22933 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL |
22934 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L |
22935 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L |
22936 | #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L |
22937 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L |
22938 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L |
22939 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L |
22940 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L |
22941 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L |
22942 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L |
22943 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L |
22944 | //RMI_GENERAL_CNTL1 |
22945 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 |
22946 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 |
22947 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 |
22948 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 |
22949 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 |
22950 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa |
22951 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb |
22952 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc |
22953 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL |
22954 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L |
22955 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L |
22956 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L |
22957 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L |
22958 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L |
22959 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L |
22960 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L |
22961 | //RMI_GENERAL_STATUS |
22962 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 |
22963 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 |
22964 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 |
22965 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 |
22966 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 |
22967 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 |
22968 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 |
22969 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 |
22970 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 |
22971 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 |
22972 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa |
22973 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb |
22974 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc |
22975 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd |
22976 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe |
22977 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf |
22978 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 |
22979 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 |
22980 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 |
22981 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 |
22982 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 |
22983 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 |
22984 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d |
22985 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e |
22986 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f |
22987 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L |
22988 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L |
22989 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L |
22990 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L |
22991 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L |
22992 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L |
22993 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L |
22994 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L |
22995 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L |
22996 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L |
22997 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L |
22998 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L |
22999 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L |
23000 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L |
23001 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L |
23002 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L |
23003 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L |
23004 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L |
23005 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L |
23006 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L |
23007 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L |
23008 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L |
23009 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L |
23010 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L |
23011 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L |
23012 | //RMI_SUBBLOCK_STATUS0 |
23013 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 |
23014 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 |
23015 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 |
23016 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 |
23017 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 |
23018 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 |
23019 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 |
23020 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL |
23021 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L |
23022 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L |
23023 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L |
23024 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L |
23025 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L |
23026 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L |
23027 | //RMI_SUBBLOCK_STATUS1 |
23028 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 |
23029 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa |
23030 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 |
23031 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL |
23032 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L |
23033 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L |
23034 | //RMI_SUBBLOCK_STATUS2 |
23035 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 |
23036 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 |
23037 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL |
23038 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L |
23039 | //RMI_SUBBLOCK_STATUS3 |
23040 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 |
23041 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa |
23042 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL |
23043 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L |
23044 | //RMI_XBAR_CONFIG |
23045 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 |
23046 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 |
23047 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 |
23048 | #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 |
23049 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 |
23050 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc |
23051 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd |
23052 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe |
23053 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L |
23054 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL |
23055 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L |
23056 | #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L |
23057 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L |
23058 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L |
23059 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L |
23060 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L |
23061 | //RMI_PROBE_POP_LOGIC_CNTL |
23062 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 |
23063 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 |
23064 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 |
23065 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa |
23066 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 |
23067 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL |
23068 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L |
23069 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L |
23070 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L |
23071 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L |
23072 | //RMI_UTC_XNACK_N_MISC_CNTL |
23073 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 |
23074 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 |
23075 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc |
23076 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd |
23077 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL |
23078 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L |
23079 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L |
23080 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L |
23081 | //RMI_DEMUX_CNTL |
23082 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 |
23083 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 |
23084 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 |
23085 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 |
23086 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe |
23087 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 |
23088 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 |
23089 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 |
23090 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 |
23091 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e |
23092 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L |
23093 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L |
23094 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L |
23095 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L |
23096 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L |
23097 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L |
23098 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L |
23099 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L |
23100 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L |
23101 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L |
23102 | //RMI_UTCL1_CNTL1 |
23103 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
23104 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
23105 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
23106 | #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
23107 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
23108 | #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
23109 | #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
23110 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
23111 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
23112 | #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
23113 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
23114 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
23115 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
23116 | #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
23117 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
23118 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
23119 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
23120 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
23121 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
23122 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
23123 | #define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
23124 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
23125 | #define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
23126 | #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
23127 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
23128 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
23129 | #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
23130 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
23131 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
23132 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
23133 | #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
23134 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
23135 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
23136 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
23137 | //RMI_UTCL1_CNTL2 |
23138 | #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 |
23139 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
23140 | #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
23141 | #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
23142 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
23143 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
23144 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
23145 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
23146 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 |
23147 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
23148 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 |
23149 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
23150 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 |
23151 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 |
23152 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
23153 | #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL |
23154 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
23155 | #define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
23156 | #define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
23157 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
23158 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
23159 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
23160 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
23161 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L |
23162 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
23163 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L |
23164 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
23165 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L |
23166 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L |
23167 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
23168 | //RMI_UTC_UNIT_CONFIG |
23169 | #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 |
23170 | #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL |
23171 | //RMI_TCIW_FORMATTER0_CNTL |
23172 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 |
23173 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 |
23174 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
23175 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 |
23176 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
23177 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c |
23178 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d |
23179 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
23180 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f |
23181 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L |
23182 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL |
23183 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
23184 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L |
23185 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
23186 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L |
23187 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L |
23188 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
23189 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L |
23190 | //RMI_TCIW_FORMATTER1_CNTL |
23191 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 |
23192 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 |
23193 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
23194 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 |
23195 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
23196 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c |
23197 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d |
23198 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
23199 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f |
23200 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L |
23201 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL |
23202 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
23203 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L |
23204 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
23205 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L |
23206 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L |
23207 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
23208 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L |
23209 | //RMI_SCOREBOARD_CNTL |
23210 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 |
23211 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 |
23212 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 |
23213 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 |
23214 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 |
23215 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 |
23216 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 |
23217 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 |
23218 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 |
23219 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 |
23220 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L |
23221 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L |
23222 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L |
23223 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L |
23224 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L |
23225 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L |
23226 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L |
23227 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L |
23228 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L |
23229 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L |
23230 | //RMI_SCOREBOARD_STATUS0 |
23231 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 |
23232 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 |
23233 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 |
23234 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 |
23235 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 |
23236 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 |
23237 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 |
23238 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L |
23239 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L |
23240 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL |
23241 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L |
23242 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L |
23243 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L |
23244 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L |
23245 | //RMI_SCOREBOARD_STATUS1 |
23246 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 |
23247 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc |
23248 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd |
23249 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe |
23250 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf |
23251 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b |
23252 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c |
23253 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
23254 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e |
23255 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL |
23256 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
23257 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L |
23258 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L |
23259 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L |
23260 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L |
23261 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L |
23262 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
23263 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L |
23264 | //RMI_SCOREBOARD_STATUS2 |
23265 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 |
23266 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc |
23267 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd |
23268 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 |
23269 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a |
23270 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b |
23271 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c |
23272 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
23273 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e |
23274 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f |
23275 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL |
23276 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
23277 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L |
23278 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L |
23279 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L |
23280 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L |
23281 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L |
23282 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
23283 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L |
23284 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L |
23285 | //RMI_XBAR_ARBITER_CONFIG |
23286 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 |
23287 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 |
23288 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 |
23289 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 |
23290 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 |
23291 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 |
23292 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 |
23293 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 |
23294 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 |
23295 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 |
23296 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 |
23297 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 |
23298 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L |
23299 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L |
23300 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L |
23301 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L |
23302 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L |
23303 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L |
23304 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L |
23305 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L |
23306 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L |
23307 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L |
23308 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L |
23309 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L |
23310 | //RMI_XBAR_ARBITER_CONFIG_1 |
23311 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 |
23312 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 |
23313 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 |
23314 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 |
23315 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL |
23316 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L |
23317 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L |
23318 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L |
23319 | //RMI_CLOCK_CNTRL |
23320 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 |
23321 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 |
23322 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa |
23323 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf |
23324 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 |
23325 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 |
23326 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL |
23327 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L |
23328 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L |
23329 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L |
23330 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L |
23331 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L |
23332 | //RMI_UTCL1_STATUS |
23333 | #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
23334 | #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
23335 | #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
23336 | #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
23337 | #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
23338 | #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
23339 | //RMI_SPARE |
23340 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 |
23341 | #define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 |
23342 | #define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 |
23343 | #define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 |
23344 | #define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 |
23345 | #define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 |
23346 | #define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 |
23347 | #define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 |
23348 | #define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 |
23349 | #define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 |
23350 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L |
23351 | #define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L |
23352 | #define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L |
23353 | #define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L |
23354 | #define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L |
23355 | #define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L |
23356 | #define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L |
23357 | #define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L |
23358 | #define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L |
23359 | #define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L |
23360 | //RMI_SPARE_1 |
23361 | #define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 |
23362 | #define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 |
23363 | #define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 |
23364 | #define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 |
23365 | #define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 |
23366 | #define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 |
23367 | #define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 |
23368 | #define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 |
23369 | #define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 |
23370 | #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 |
23371 | #define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L |
23372 | #define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L |
23373 | #define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L |
23374 | #define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L |
23375 | #define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L |
23376 | #define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L |
23377 | #define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L |
23378 | #define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L |
23379 | #define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L |
23380 | #define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L |
23381 | //RMI_SPARE_2 |
23382 | #define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 |
23383 | #define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 |
23384 | #define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 |
23385 | #define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 |
23386 | #define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 |
23387 | #define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 |
23388 | #define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 |
23389 | #define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 |
23390 | #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 |
23391 | #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc |
23392 | #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 |
23393 | #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 |
23394 | #define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L |
23395 | #define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L |
23396 | #define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L |
23397 | #define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L |
23398 | #define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L |
23399 | #define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L |
23400 | #define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L |
23401 | #define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L |
23402 | #define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L |
23403 | #define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L |
23404 | #define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L |
23405 | #define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L |
23406 | |
23407 | |
23408 | // addressBlock: gc_shdec |
23409 | //SPI_SHADER_PGM_RSRC3_PS |
23410 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 |
23411 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 |
23412 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
23413 | #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a |
23414 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL |
23415 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L |
23416 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
23417 | #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L |
23418 | //SPI_SHADER_PGM_LO_PS |
23419 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 |
23420 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL |
23421 | //SPI_SHADER_PGM_HI_PS |
23422 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 |
23423 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL |
23424 | //SPI_SHADER_PGM_RSRC1_PS |
23425 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 |
23426 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 |
23427 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa |
23428 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc |
23429 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 |
23430 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 |
23431 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 |
23432 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 |
23433 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d |
23434 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL |
23435 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L |
23436 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L |
23437 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L |
23438 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L |
23439 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L |
23440 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L |
23441 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L |
23442 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L |
23443 | //SPI_SHADER_PGM_RSRC2_PS |
23444 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 |
23445 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 |
23446 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 |
23447 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 |
23448 | #define 0x8 |
23449 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 |
23450 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 |
23451 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a |
23452 | #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b |
23453 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c |
23454 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L |
23455 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL |
23456 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L |
23457 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L |
23458 | #define 0x0000FF00L |
23459 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L |
23460 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L |
23461 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L |
23462 | #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L |
23463 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L |
23464 | //SPI_SHADER_USER_DATA_PS_0 |
23465 | #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 |
23466 | #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL |
23467 | //SPI_SHADER_USER_DATA_PS_1 |
23468 | #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 |
23469 | #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL |
23470 | //SPI_SHADER_USER_DATA_PS_2 |
23471 | #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 |
23472 | #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL |
23473 | //SPI_SHADER_USER_DATA_PS_3 |
23474 | #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 |
23475 | #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL |
23476 | //SPI_SHADER_USER_DATA_PS_4 |
23477 | #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 |
23478 | #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL |
23479 | //SPI_SHADER_USER_DATA_PS_5 |
23480 | #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 |
23481 | #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL |
23482 | //SPI_SHADER_USER_DATA_PS_6 |
23483 | #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 |
23484 | #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL |
23485 | //SPI_SHADER_USER_DATA_PS_7 |
23486 | #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 |
23487 | #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL |
23488 | //SPI_SHADER_USER_DATA_PS_8 |
23489 | #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 |
23490 | #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL |
23491 | //SPI_SHADER_USER_DATA_PS_9 |
23492 | #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 |
23493 | #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL |
23494 | //SPI_SHADER_USER_DATA_PS_10 |
23495 | #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 |
23496 | #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL |
23497 | //SPI_SHADER_USER_DATA_PS_11 |
23498 | #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 |
23499 | #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL |
23500 | //SPI_SHADER_USER_DATA_PS_12 |
23501 | #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 |
23502 | #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL |
23503 | //SPI_SHADER_USER_DATA_PS_13 |
23504 | #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 |
23505 | #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL |
23506 | //SPI_SHADER_USER_DATA_PS_14 |
23507 | #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 |
23508 | #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL |
23509 | //SPI_SHADER_USER_DATA_PS_15 |
23510 | #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 |
23511 | #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL |
23512 | //SPI_SHADER_USER_DATA_PS_16 |
23513 | #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 |
23514 | #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL |
23515 | //SPI_SHADER_USER_DATA_PS_17 |
23516 | #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 |
23517 | #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL |
23518 | //SPI_SHADER_USER_DATA_PS_18 |
23519 | #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 |
23520 | #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL |
23521 | //SPI_SHADER_USER_DATA_PS_19 |
23522 | #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 |
23523 | #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL |
23524 | //SPI_SHADER_USER_DATA_PS_20 |
23525 | #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 |
23526 | #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL |
23527 | //SPI_SHADER_USER_DATA_PS_21 |
23528 | #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 |
23529 | #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL |
23530 | //SPI_SHADER_USER_DATA_PS_22 |
23531 | #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 |
23532 | #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL |
23533 | //SPI_SHADER_USER_DATA_PS_23 |
23534 | #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 |
23535 | #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL |
23536 | //SPI_SHADER_USER_DATA_PS_24 |
23537 | #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 |
23538 | #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL |
23539 | //SPI_SHADER_USER_DATA_PS_25 |
23540 | #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 |
23541 | #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL |
23542 | //SPI_SHADER_USER_DATA_PS_26 |
23543 | #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 |
23544 | #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL |
23545 | //SPI_SHADER_USER_DATA_PS_27 |
23546 | #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 |
23547 | #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL |
23548 | //SPI_SHADER_USER_DATA_PS_28 |
23549 | #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 |
23550 | #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL |
23551 | //SPI_SHADER_USER_DATA_PS_29 |
23552 | #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 |
23553 | #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL |
23554 | //SPI_SHADER_USER_DATA_PS_30 |
23555 | #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 |
23556 | #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL |
23557 | //SPI_SHADER_USER_DATA_PS_31 |
23558 | #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 |
23559 | #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL |
23560 | //SPI_SHADER_PGM_RSRC3_VS |
23561 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 |
23562 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 |
23563 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
23564 | #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a |
23565 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL |
23566 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L |
23567 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
23568 | #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L |
23569 | //SPI_SHADER_LATE_ALLOC_VS |
23570 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 |
23571 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL |
23572 | //SPI_SHADER_PGM_LO_VS |
23573 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 |
23574 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL |
23575 | //SPI_SHADER_PGM_HI_VS |
23576 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 |
23577 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL |
23578 | //SPI_SHADER_PGM_RSRC1_VS |
23579 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 |
23580 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 |
23581 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa |
23582 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc |
23583 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 |
23584 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 |
23585 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 |
23586 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 |
23587 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a |
23588 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f |
23589 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL |
23590 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L |
23591 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L |
23592 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L |
23593 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L |
23594 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L |
23595 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L |
23596 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L |
23597 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L |
23598 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L |
23599 | //SPI_SHADER_PGM_RSRC2_VS |
23600 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 |
23601 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 |
23602 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 |
23603 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 |
23604 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 |
23605 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 |
23606 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa |
23607 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb |
23608 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc |
23609 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd |
23610 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 |
23611 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 |
23612 | #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b |
23613 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c |
23614 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L |
23615 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL |
23616 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L |
23617 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L |
23618 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L |
23619 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L |
23620 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L |
23621 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L |
23622 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L |
23623 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L |
23624 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L |
23625 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L |
23626 | #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L |
23627 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L |
23628 | //SPI_SHADER_USER_DATA_VS_0 |
23629 | #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 |
23630 | #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL |
23631 | //SPI_SHADER_USER_DATA_VS_1 |
23632 | #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 |
23633 | #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL |
23634 | //SPI_SHADER_USER_DATA_VS_2 |
23635 | #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 |
23636 | #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL |
23637 | //SPI_SHADER_USER_DATA_VS_3 |
23638 | #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 |
23639 | #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL |
23640 | //SPI_SHADER_USER_DATA_VS_4 |
23641 | #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 |
23642 | #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL |
23643 | //SPI_SHADER_USER_DATA_VS_5 |
23644 | #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 |
23645 | #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL |
23646 | //SPI_SHADER_USER_DATA_VS_6 |
23647 | #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 |
23648 | #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL |
23649 | //SPI_SHADER_USER_DATA_VS_7 |
23650 | #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 |
23651 | #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL |
23652 | //SPI_SHADER_USER_DATA_VS_8 |
23653 | #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 |
23654 | #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL |
23655 | //SPI_SHADER_USER_DATA_VS_9 |
23656 | #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 |
23657 | #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL |
23658 | //SPI_SHADER_USER_DATA_VS_10 |
23659 | #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 |
23660 | #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL |
23661 | //SPI_SHADER_USER_DATA_VS_11 |
23662 | #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 |
23663 | #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL |
23664 | //SPI_SHADER_USER_DATA_VS_12 |
23665 | #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 |
23666 | #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL |
23667 | //SPI_SHADER_USER_DATA_VS_13 |
23668 | #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 |
23669 | #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL |
23670 | //SPI_SHADER_USER_DATA_VS_14 |
23671 | #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 |
23672 | #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL |
23673 | //SPI_SHADER_USER_DATA_VS_15 |
23674 | #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 |
23675 | #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL |
23676 | //SPI_SHADER_USER_DATA_VS_16 |
23677 | #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 |
23678 | #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL |
23679 | //SPI_SHADER_USER_DATA_VS_17 |
23680 | #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 |
23681 | #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL |
23682 | //SPI_SHADER_USER_DATA_VS_18 |
23683 | #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 |
23684 | #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL |
23685 | //SPI_SHADER_USER_DATA_VS_19 |
23686 | #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 |
23687 | #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL |
23688 | //SPI_SHADER_USER_DATA_VS_20 |
23689 | #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 |
23690 | #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL |
23691 | //SPI_SHADER_USER_DATA_VS_21 |
23692 | #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 |
23693 | #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL |
23694 | //SPI_SHADER_USER_DATA_VS_22 |
23695 | #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 |
23696 | #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL |
23697 | //SPI_SHADER_USER_DATA_VS_23 |
23698 | #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 |
23699 | #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL |
23700 | //SPI_SHADER_USER_DATA_VS_24 |
23701 | #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 |
23702 | #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL |
23703 | //SPI_SHADER_USER_DATA_VS_25 |
23704 | #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 |
23705 | #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL |
23706 | //SPI_SHADER_USER_DATA_VS_26 |
23707 | #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 |
23708 | #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL |
23709 | //SPI_SHADER_USER_DATA_VS_27 |
23710 | #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 |
23711 | #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL |
23712 | //SPI_SHADER_USER_DATA_VS_28 |
23713 | #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 |
23714 | #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL |
23715 | //SPI_SHADER_USER_DATA_VS_29 |
23716 | #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 |
23717 | #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL |
23718 | //SPI_SHADER_USER_DATA_VS_30 |
23719 | #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 |
23720 | #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL |
23721 | //SPI_SHADER_USER_DATA_VS_31 |
23722 | #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 |
23723 | #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL |
23724 | //SPI_SHADER_PGM_RSRC2_GS_VS |
23725 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 |
23726 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 |
23727 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 |
23728 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 |
23729 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 |
23730 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 |
23731 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 |
23732 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b |
23733 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c |
23734 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L |
23735 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL |
23736 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L |
23737 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L |
23738 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L |
23739 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L |
23740 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L |
23741 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L |
23742 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L |
23743 | //SPI_SHADER_PGM_RSRC4_GS |
23744 | #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 |
23745 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 |
23746 | #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL |
23747 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L |
23748 | //SPI_SHADER_USER_DATA_ADDR_LO_GS |
23749 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 |
23750 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
23751 | //SPI_SHADER_USER_DATA_ADDR_HI_GS |
23752 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 |
23753 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL |
23754 | //SPI_SHADER_PGM_LO_ES |
23755 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 |
23756 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL |
23757 | //SPI_SHADER_PGM_HI_ES |
23758 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 |
23759 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL |
23760 | //SPI_SHADER_PGM_RSRC3_GS |
23761 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 |
23762 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 |
23763 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
23764 | #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a |
23765 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL |
23766 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L |
23767 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
23768 | #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L |
23769 | //SPI_SHADER_PGM_LO_GS |
23770 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 |
23771 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
23772 | //SPI_SHADER_PGM_HI_GS |
23773 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 |
23774 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL |
23775 | //SPI_SHADER_PGM_RSRC1_GS |
23776 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 |
23777 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 |
23778 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa |
23779 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc |
23780 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 |
23781 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 |
23782 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 |
23783 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 |
23784 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d |
23785 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f |
23786 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL |
23787 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L |
23788 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L |
23789 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L |
23790 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L |
23791 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L |
23792 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L |
23793 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L |
23794 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L |
23795 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L |
23796 | //SPI_SHADER_PGM_RSRC2_GS |
23797 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 |
23798 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 |
23799 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 |
23800 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 |
23801 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 |
23802 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 |
23803 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 |
23804 | #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b |
23805 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c |
23806 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L |
23807 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL |
23808 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L |
23809 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L |
23810 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L |
23811 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L |
23812 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L |
23813 | #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L |
23814 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L |
23815 | //SPI_SHADER_USER_DATA_ES_0 |
23816 | #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 |
23817 | #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL |
23818 | //SPI_SHADER_USER_DATA_ES_1 |
23819 | #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 |
23820 | #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL |
23821 | //SPI_SHADER_USER_DATA_ES_2 |
23822 | #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 |
23823 | #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL |
23824 | //SPI_SHADER_USER_DATA_ES_3 |
23825 | #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 |
23826 | #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL |
23827 | //SPI_SHADER_USER_DATA_ES_4 |
23828 | #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 |
23829 | #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL |
23830 | //SPI_SHADER_USER_DATA_ES_5 |
23831 | #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 |
23832 | #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL |
23833 | //SPI_SHADER_USER_DATA_ES_6 |
23834 | #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 |
23835 | #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL |
23836 | //SPI_SHADER_USER_DATA_ES_7 |
23837 | #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 |
23838 | #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL |
23839 | //SPI_SHADER_USER_DATA_ES_8 |
23840 | #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 |
23841 | #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL |
23842 | //SPI_SHADER_USER_DATA_ES_9 |
23843 | #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 |
23844 | #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL |
23845 | //SPI_SHADER_USER_DATA_ES_10 |
23846 | #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 |
23847 | #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL |
23848 | //SPI_SHADER_USER_DATA_ES_11 |
23849 | #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 |
23850 | #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL |
23851 | //SPI_SHADER_USER_DATA_ES_12 |
23852 | #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 |
23853 | #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL |
23854 | //SPI_SHADER_USER_DATA_ES_13 |
23855 | #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 |
23856 | #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL |
23857 | //SPI_SHADER_USER_DATA_ES_14 |
23858 | #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 |
23859 | #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL |
23860 | //SPI_SHADER_USER_DATA_ES_15 |
23861 | #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 |
23862 | #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL |
23863 | //SPI_SHADER_USER_DATA_ES_16 |
23864 | #define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 |
23865 | #define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL |
23866 | //SPI_SHADER_USER_DATA_ES_17 |
23867 | #define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 |
23868 | #define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL |
23869 | //SPI_SHADER_USER_DATA_ES_18 |
23870 | #define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 |
23871 | #define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL |
23872 | //SPI_SHADER_USER_DATA_ES_19 |
23873 | #define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 |
23874 | #define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL |
23875 | //SPI_SHADER_USER_DATA_ES_20 |
23876 | #define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 |
23877 | #define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL |
23878 | //SPI_SHADER_USER_DATA_ES_21 |
23879 | #define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 |
23880 | #define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL |
23881 | //SPI_SHADER_USER_DATA_ES_22 |
23882 | #define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 |
23883 | #define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL |
23884 | //SPI_SHADER_USER_DATA_ES_23 |
23885 | #define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 |
23886 | #define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL |
23887 | //SPI_SHADER_USER_DATA_ES_24 |
23888 | #define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 |
23889 | #define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL |
23890 | //SPI_SHADER_USER_DATA_ES_25 |
23891 | #define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 |
23892 | #define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL |
23893 | //SPI_SHADER_USER_DATA_ES_26 |
23894 | #define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 |
23895 | #define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL |
23896 | //SPI_SHADER_USER_DATA_ES_27 |
23897 | #define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 |
23898 | #define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL |
23899 | //SPI_SHADER_USER_DATA_ES_28 |
23900 | #define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 |
23901 | #define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL |
23902 | //SPI_SHADER_USER_DATA_ES_29 |
23903 | #define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 |
23904 | #define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL |
23905 | //SPI_SHADER_USER_DATA_ES_30 |
23906 | #define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 |
23907 | #define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL |
23908 | //SPI_SHADER_USER_DATA_ES_31 |
23909 | #define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 |
23910 | #define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL |
23911 | //SPI_SHADER_PGM_RSRC4_HS |
23912 | #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 |
23913 | #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL |
23914 | //SPI_SHADER_USER_DATA_ADDR_LO_HS |
23915 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 |
23916 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
23917 | //SPI_SHADER_USER_DATA_ADDR_HI_HS |
23918 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 |
23919 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL |
23920 | //SPI_SHADER_PGM_LO_LS |
23921 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 |
23922 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL |
23923 | //SPI_SHADER_PGM_HI_LS |
23924 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 |
23925 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL |
23926 | //SPI_SHADER_PGM_RSRC3_HS |
23927 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 |
23928 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 |
23929 | #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa |
23930 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 |
23931 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL |
23932 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L |
23933 | #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L |
23934 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L |
23935 | //SPI_SHADER_PGM_LO_HS |
23936 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 |
23937 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
23938 | //SPI_SHADER_PGM_HI_HS |
23939 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 |
23940 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL |
23941 | //SPI_SHADER_PGM_RSRC1_HS |
23942 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 |
23943 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 |
23944 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa |
23945 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc |
23946 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 |
23947 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 |
23948 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 |
23949 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c |
23950 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e |
23951 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL |
23952 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L |
23953 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L |
23954 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L |
23955 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L |
23956 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L |
23957 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L |
23958 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L |
23959 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L |
23960 | //SPI_SHADER_PGM_RSRC2_HS |
23961 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 |
23962 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 |
23963 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 |
23964 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 |
23965 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 |
23966 | #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b |
23967 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c |
23968 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L |
23969 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL |
23970 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L |
23971 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L |
23972 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L |
23973 | #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L |
23974 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L |
23975 | //SPI_SHADER_USER_DATA_LS_0 |
23976 | #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 |
23977 | #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL |
23978 | //SPI_SHADER_USER_DATA_LS_1 |
23979 | #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 |
23980 | #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL |
23981 | //SPI_SHADER_USER_DATA_LS_2 |
23982 | #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 |
23983 | #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL |
23984 | //SPI_SHADER_USER_DATA_LS_3 |
23985 | #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 |
23986 | #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL |
23987 | //SPI_SHADER_USER_DATA_LS_4 |
23988 | #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 |
23989 | #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL |
23990 | //SPI_SHADER_USER_DATA_LS_5 |
23991 | #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 |
23992 | #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL |
23993 | //SPI_SHADER_USER_DATA_LS_6 |
23994 | #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 |
23995 | #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL |
23996 | //SPI_SHADER_USER_DATA_LS_7 |
23997 | #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 |
23998 | #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL |
23999 | //SPI_SHADER_USER_DATA_LS_8 |
24000 | #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 |
24001 | #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL |
24002 | //SPI_SHADER_USER_DATA_LS_9 |
24003 | #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 |
24004 | #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL |
24005 | //SPI_SHADER_USER_DATA_LS_10 |
24006 | #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 |
24007 | #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL |
24008 | //SPI_SHADER_USER_DATA_LS_11 |
24009 | #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 |
24010 | #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL |
24011 | //SPI_SHADER_USER_DATA_LS_12 |
24012 | #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 |
24013 | #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL |
24014 | //SPI_SHADER_USER_DATA_LS_13 |
24015 | #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 |
24016 | #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL |
24017 | //SPI_SHADER_USER_DATA_LS_14 |
24018 | #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 |
24019 | #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL |
24020 | //SPI_SHADER_USER_DATA_LS_15 |
24021 | #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 |
24022 | #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL |
24023 | //SPI_SHADER_USER_DATA_LS_16 |
24024 | #define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 |
24025 | #define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL |
24026 | //SPI_SHADER_USER_DATA_LS_17 |
24027 | #define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 |
24028 | #define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL |
24029 | //SPI_SHADER_USER_DATA_LS_18 |
24030 | #define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 |
24031 | #define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL |
24032 | //SPI_SHADER_USER_DATA_LS_19 |
24033 | #define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 |
24034 | #define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL |
24035 | //SPI_SHADER_USER_DATA_LS_20 |
24036 | #define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 |
24037 | #define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL |
24038 | //SPI_SHADER_USER_DATA_LS_21 |
24039 | #define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 |
24040 | #define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL |
24041 | //SPI_SHADER_USER_DATA_LS_22 |
24042 | #define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 |
24043 | #define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL |
24044 | //SPI_SHADER_USER_DATA_LS_23 |
24045 | #define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 |
24046 | #define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL |
24047 | //SPI_SHADER_USER_DATA_LS_24 |
24048 | #define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 |
24049 | #define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL |
24050 | //SPI_SHADER_USER_DATA_LS_25 |
24051 | #define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 |
24052 | #define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL |
24053 | //SPI_SHADER_USER_DATA_LS_26 |
24054 | #define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 |
24055 | #define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL |
24056 | //SPI_SHADER_USER_DATA_LS_27 |
24057 | #define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 |
24058 | #define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL |
24059 | //SPI_SHADER_USER_DATA_LS_28 |
24060 | #define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 |
24061 | #define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL |
24062 | //SPI_SHADER_USER_DATA_LS_29 |
24063 | #define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 |
24064 | #define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL |
24065 | //SPI_SHADER_USER_DATA_LS_30 |
24066 | #define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 |
24067 | #define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL |
24068 | //SPI_SHADER_USER_DATA_LS_31 |
24069 | #define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 |
24070 | #define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL |
24071 | //SPI_SHADER_USER_DATA_COMMON_0 |
24072 | #define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 |
24073 | #define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL |
24074 | //SPI_SHADER_USER_DATA_COMMON_1 |
24075 | #define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 |
24076 | #define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL |
24077 | //SPI_SHADER_USER_DATA_COMMON_2 |
24078 | #define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 |
24079 | #define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL |
24080 | //SPI_SHADER_USER_DATA_COMMON_3 |
24081 | #define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 |
24082 | #define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL |
24083 | //SPI_SHADER_USER_DATA_COMMON_4 |
24084 | #define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 |
24085 | #define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL |
24086 | //SPI_SHADER_USER_DATA_COMMON_5 |
24087 | #define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 |
24088 | #define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL |
24089 | //SPI_SHADER_USER_DATA_COMMON_6 |
24090 | #define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 |
24091 | #define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL |
24092 | //SPI_SHADER_USER_DATA_COMMON_7 |
24093 | #define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 |
24094 | #define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL |
24095 | //SPI_SHADER_USER_DATA_COMMON_8 |
24096 | #define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 |
24097 | #define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL |
24098 | //SPI_SHADER_USER_DATA_COMMON_9 |
24099 | #define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 |
24100 | #define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL |
24101 | //SPI_SHADER_USER_DATA_COMMON_10 |
24102 | #define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 |
24103 | #define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL |
24104 | //SPI_SHADER_USER_DATA_COMMON_11 |
24105 | #define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 |
24106 | #define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL |
24107 | //SPI_SHADER_USER_DATA_COMMON_12 |
24108 | #define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 |
24109 | #define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL |
24110 | //SPI_SHADER_USER_DATA_COMMON_13 |
24111 | #define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 |
24112 | #define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL |
24113 | //SPI_SHADER_USER_DATA_COMMON_14 |
24114 | #define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 |
24115 | #define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL |
24116 | //SPI_SHADER_USER_DATA_COMMON_15 |
24117 | #define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 |
24118 | #define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL |
24119 | //SPI_SHADER_USER_DATA_COMMON_16 |
24120 | #define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 |
24121 | #define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL |
24122 | //SPI_SHADER_USER_DATA_COMMON_17 |
24123 | #define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 |
24124 | #define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL |
24125 | //SPI_SHADER_USER_DATA_COMMON_18 |
24126 | #define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 |
24127 | #define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL |
24128 | //SPI_SHADER_USER_DATA_COMMON_19 |
24129 | #define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 |
24130 | #define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL |
24131 | //SPI_SHADER_USER_DATA_COMMON_20 |
24132 | #define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 |
24133 | #define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL |
24134 | //SPI_SHADER_USER_DATA_COMMON_21 |
24135 | #define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 |
24136 | #define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL |
24137 | //SPI_SHADER_USER_DATA_COMMON_22 |
24138 | #define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 |
24139 | #define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL |
24140 | //SPI_SHADER_USER_DATA_COMMON_23 |
24141 | #define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 |
24142 | #define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL |
24143 | //SPI_SHADER_USER_DATA_COMMON_24 |
24144 | #define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 |
24145 | #define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL |
24146 | //SPI_SHADER_USER_DATA_COMMON_25 |
24147 | #define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 |
24148 | #define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL |
24149 | //SPI_SHADER_USER_DATA_COMMON_26 |
24150 | #define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 |
24151 | #define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL |
24152 | //SPI_SHADER_USER_DATA_COMMON_27 |
24153 | #define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 |
24154 | #define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL |
24155 | //SPI_SHADER_USER_DATA_COMMON_28 |
24156 | #define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 |
24157 | #define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL |
24158 | //SPI_SHADER_USER_DATA_COMMON_29 |
24159 | #define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 |
24160 | #define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL |
24161 | //SPI_SHADER_USER_DATA_COMMON_30 |
24162 | #define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 |
24163 | #define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL |
24164 | //SPI_SHADER_USER_DATA_COMMON_31 |
24165 | #define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 |
24166 | #define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL |
24167 | //COMPUTE_DISPATCH_INITIATOR |
24168 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 |
24169 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 |
24170 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 |
24171 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 |
24172 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 |
24173 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 |
24174 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 |
24175 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa |
24176 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb |
24177 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc |
24178 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe |
24179 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L |
24180 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L |
24181 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L |
24182 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L |
24183 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L |
24184 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L |
24185 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L |
24186 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L |
24187 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L |
24188 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L |
24189 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L |
24190 | //COMPUTE_DIM_X |
24191 | #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 |
24192 | #define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL |
24193 | //COMPUTE_DIM_Y |
24194 | #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 |
24195 | #define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL |
24196 | //COMPUTE_DIM_Z |
24197 | #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 |
24198 | #define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL |
24199 | //COMPUTE_START_X |
24200 | #define COMPUTE_START_X__START__SHIFT 0x0 |
24201 | #define COMPUTE_START_X__START_MASK 0xFFFFFFFFL |
24202 | //COMPUTE_START_Y |
24203 | #define COMPUTE_START_Y__START__SHIFT 0x0 |
24204 | #define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL |
24205 | //COMPUTE_START_Z |
24206 | #define COMPUTE_START_Z__START__SHIFT 0x0 |
24207 | #define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL |
24208 | //COMPUTE_NUM_THREAD_X |
24209 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 |
24210 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 |
24211 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL |
24212 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
24213 | //COMPUTE_NUM_THREAD_Y |
24214 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 |
24215 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 |
24216 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL |
24217 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
24218 | //COMPUTE_NUM_THREAD_Z |
24219 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 |
24220 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 |
24221 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL |
24222 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
24223 | //COMPUTE_PIPELINESTAT_ENABLE |
24224 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 |
24225 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L |
24226 | //COMPUTE_PERFCOUNT_ENABLE |
24227 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 |
24228 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L |
24229 | //COMPUTE_PGM_LO |
24230 | #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 |
24231 | #define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL |
24232 | //COMPUTE_PGM_HI |
24233 | #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 |
24234 | #define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL |
24235 | //COMPUTE_DISPATCH_PKT_ADDR_LO |
24236 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 |
24237 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL |
24238 | //COMPUTE_DISPATCH_PKT_ADDR_HI |
24239 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 |
24240 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL |
24241 | //COMPUTE_DISPATCH_SCRATCH_BASE_LO |
24242 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 |
24243 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL |
24244 | //COMPUTE_DISPATCH_SCRATCH_BASE_HI |
24245 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 |
24246 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL |
24247 | //COMPUTE_PGM_RSRC1 |
24248 | #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 |
24249 | #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 |
24250 | #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa |
24251 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc |
24252 | #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 |
24253 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 |
24254 | #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 |
24255 | #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 |
24256 | #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a |
24257 | #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL |
24258 | #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L |
24259 | #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L |
24260 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L |
24261 | #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L |
24262 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L |
24263 | #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L |
24264 | #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L |
24265 | #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L |
24266 | //COMPUTE_PGM_RSRC2 |
24267 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 |
24268 | #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 |
24269 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 |
24270 | #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 |
24271 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 |
24272 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 |
24273 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa |
24274 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb |
24275 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd |
24276 | #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf |
24277 | #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 |
24278 | #define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f |
24279 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L |
24280 | #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL |
24281 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L |
24282 | #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L |
24283 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L |
24284 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L |
24285 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L |
24286 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L |
24287 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L |
24288 | #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L |
24289 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L |
24290 | #define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L |
24291 | //COMPUTE_VMID |
24292 | #define COMPUTE_VMID__DATA__SHIFT 0x0 |
24293 | #define COMPUTE_VMID__DATA_MASK 0x0000000FL |
24294 | //COMPUTE_RESOURCE_LIMITS |
24295 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 |
24296 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc |
24297 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 |
24298 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 |
24299 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 |
24300 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 |
24301 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b |
24302 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL |
24303 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L |
24304 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L |
24305 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L |
24306 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L |
24307 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L |
24308 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L |
24309 | //COMPUTE_STATIC_THREAD_MGMT_SE0 |
24310 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 |
24311 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 |
24312 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL |
24313 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L |
24314 | //COMPUTE_STATIC_THREAD_MGMT_SE1 |
24315 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 |
24316 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 |
24317 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL |
24318 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L |
24319 | //COMPUTE_TMPRING_SIZE |
24320 | #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 |
24321 | #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
24322 | #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
24323 | #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
24324 | //COMPUTE_STATIC_THREAD_MGMT_SE2 |
24325 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 |
24326 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 |
24327 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL |
24328 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L |
24329 | //COMPUTE_STATIC_THREAD_MGMT_SE3 |
24330 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 |
24331 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 |
24332 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL |
24333 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L |
24334 | //COMPUTE_RESTART_X |
24335 | #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 |
24336 | #define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL |
24337 | //COMPUTE_RESTART_Y |
24338 | #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 |
24339 | #define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL |
24340 | //COMPUTE_RESTART_Z |
24341 | #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 |
24342 | #define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL |
24343 | //COMPUTE_THREAD_TRACE_ENABLE |
24344 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 |
24345 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L |
24346 | //COMPUTE_MISC_RESERVED |
24347 | #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 |
24348 | #define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1__SHIFT 0x2 |
24349 | #define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID__SHIFT 0x4 |
24350 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 |
24351 | #define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0__SHIFT 0x11 |
24352 | #define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1__SHIFT 0x12 |
24353 | #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L |
24354 | #define COMPUTE_MISC_RESERVED__SEND_SEID_CORE1_MASK 0x0000000CL |
24355 | #define COMPUTE_MISC_RESERVED__RESTORE_CORE_ID_MASK 0x00000010L |
24356 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L |
24357 | #define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE0_MASK 0x00020000L |
24358 | #define COMPUTE_MISC_RESERVED__CRAWLER_DONE_CORE1_MASK 0x00040000L |
24359 | //COMPUTE_DISPATCH_ID |
24360 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 |
24361 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL |
24362 | //COMPUTE_THREADGROUP_ID |
24363 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 |
24364 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL |
24365 | //COMPUTE_RELAUNCH |
24366 | #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 |
24367 | #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e |
24368 | #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f |
24369 | #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL |
24370 | #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L |
24371 | #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L |
24372 | //COMPUTE_WAVE_RESTORE_ADDR_LO |
24373 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 |
24374 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL |
24375 | //COMPUTE_WAVE_RESTORE_ADDR_HI |
24376 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 |
24377 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL |
24378 | //COMPUTE_STATIC_THREAD_MGMT_SE4 |
24379 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN__SHIFT 0x0 |
24380 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN__SHIFT 0x10 |
24381 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SH0_CU_EN_MASK 0x0000FFFFL |
24382 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SH1_CU_EN_MASK 0xFFFF0000L |
24383 | //COMPUTE_STATIC_THREAD_MGMT_SE5 |
24384 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN__SHIFT 0x0 |
24385 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN__SHIFT 0x10 |
24386 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SH0_CU_EN_MASK 0x0000FFFFL |
24387 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SH1_CU_EN_MASK 0xFFFF0000L |
24388 | //COMPUTE_STATIC_THREAD_MGMT_SE6 |
24389 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN__SHIFT 0x0 |
24390 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN__SHIFT 0x10 |
24391 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SH0_CU_EN_MASK 0x0000FFFFL |
24392 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SH1_CU_EN_MASK 0xFFFF0000L |
24393 | //COMPUTE_STATIC_THREAD_MGMT_SE7 |
24394 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN__SHIFT 0x0 |
24395 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN__SHIFT 0x10 |
24396 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SH0_CU_EN_MASK 0x0000FFFFL |
24397 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SH1_CU_EN_MASK 0xFFFF0000L |
24398 | //COMPUTE_RESTART_X2 |
24399 | #define COMPUTE_RESTART_X2__RESTART__SHIFT 0x0 |
24400 | #define COMPUTE_RESTART_X2__RESTART_MASK 0xFFFFFFFFL |
24401 | //COMPUTE_RESTART_Y2 |
24402 | #define COMPUTE_RESTART_Y2__RESTART__SHIFT 0x0 |
24403 | #define COMPUTE_RESTART_Y2__RESTART_MASK 0xFFFFFFFFL |
24404 | //COMPUTE_RESTART_Z2 |
24405 | #define COMPUTE_RESTART_Z2__RESTART__SHIFT 0x0 |
24406 | #define COMPUTE_RESTART_Z2__RESTART_MASK 0xFFFFFFFFL |
24407 | //COMPUTE_SHADER_CHKSUM |
24408 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 |
24409 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL |
24410 | //COMPUTE_PGM_RSRC3 |
24411 | #define COMPUTE_PGM_RSRC3__ACCUM_OFFSET__SHIFT 0x0 |
24412 | #define COMPUTE_PGM_RSRC3__TG_SPLIT__SHIFT 0x10 |
24413 | #define COMPUTE_PGM_RSRC3__ACCUM_OFFSET_MASK 0x0000003FL |
24414 | #define COMPUTE_PGM_RSRC3__TG_SPLIT_MASK 0x00010000L |
24415 | //COMPUTE_USER_DATA_0 |
24416 | #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 |
24417 | #define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL |
24418 | //COMPUTE_USER_DATA_1 |
24419 | #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 |
24420 | #define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL |
24421 | //COMPUTE_USER_DATA_2 |
24422 | #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 |
24423 | #define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL |
24424 | //COMPUTE_USER_DATA_3 |
24425 | #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 |
24426 | #define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL |
24427 | //COMPUTE_USER_DATA_4 |
24428 | #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 |
24429 | #define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL |
24430 | //COMPUTE_USER_DATA_5 |
24431 | #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 |
24432 | #define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL |
24433 | //COMPUTE_USER_DATA_6 |
24434 | #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 |
24435 | #define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL |
24436 | //COMPUTE_USER_DATA_7 |
24437 | #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 |
24438 | #define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL |
24439 | //COMPUTE_USER_DATA_8 |
24440 | #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 |
24441 | #define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL |
24442 | //COMPUTE_USER_DATA_9 |
24443 | #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 |
24444 | #define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL |
24445 | //COMPUTE_USER_DATA_10 |
24446 | #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 |
24447 | #define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL |
24448 | //COMPUTE_USER_DATA_11 |
24449 | #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 |
24450 | #define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL |
24451 | //COMPUTE_USER_DATA_12 |
24452 | #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 |
24453 | #define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL |
24454 | //COMPUTE_USER_DATA_13 |
24455 | #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 |
24456 | #define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL |
24457 | //COMPUTE_USER_DATA_14 |
24458 | #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 |
24459 | #define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL |
24460 | //COMPUTE_USER_DATA_15 |
24461 | #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 |
24462 | #define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL |
24463 | //COMPUTE_DISPATCH_END |
24464 | #define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 |
24465 | #define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL |
24466 | //COMPUTE_NOWHERE |
24467 | #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 |
24468 | #define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL |
24469 | |
24470 | |
24471 | // addressBlock: gc_shsdec |
24472 | //SX_DEBUG_1 |
24473 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 |
24474 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 |
24475 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 |
24476 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa |
24477 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb |
24478 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc |
24479 | #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd |
24480 | #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe |
24481 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL |
24482 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L |
24483 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L |
24484 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L |
24485 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L |
24486 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L |
24487 | #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L |
24488 | #define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L |
24489 | //SPI_PS_MAX_WAVE_ID |
24490 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
24491 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 |
24492 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
24493 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L |
24494 | //SPI_START_PHASE |
24495 | #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 |
24496 | #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 |
24497 | #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 |
24498 | #define SPI_START_PHASE__SPI_TD_GAP__SHIFT 0x6 |
24499 | #define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L |
24500 | #define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL |
24501 | #define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L |
24502 | #define SPI_START_PHASE__SPI_TD_GAP_MASK 0x000003C0L |
24503 | //SPI_GFX_CNTL |
24504 | #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 |
24505 | #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L |
24506 | //SPI_DSM_CNTL |
24507 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
24508 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
24509 | #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
24510 | #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
24511 | #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
24512 | #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
24513 | #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
24514 | #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
24515 | #define SPI_DSM_CNTL__UNUSED__SHIFT 0xf |
24516 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
24517 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
24518 | #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
24519 | #define SPI_DSM_CNTL__SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
24520 | #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
24521 | #define SPI_DSM_CNTL__SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
24522 | #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
24523 | #define SPI_DSM_CNTL__SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
24524 | #define SPI_DSM_CNTL__UNUSED_MASK 0xFFFF8000L |
24525 | //SPI_DSM_CNTL2 |
24526 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
24527 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
24528 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 |
24529 | #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT__SHIFT 0xa |
24530 | #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY__SHIFT 0xc |
24531 | #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT__SHIFT 0xd |
24532 | #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY__SHIFT 0xf |
24533 | #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT__SHIFT 0x13 |
24534 | #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY__SHIFT 0x15 |
24535 | #define SPI_DSM_CNTL2__UNUSED__SHIFT 0x16 |
24536 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
24537 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
24538 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L |
24539 | #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT_MASK 0x00000C00L |
24540 | #define SPI_DSM_CNTL2__SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY_MASK 0x00001000L |
24541 | #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT_MASK 0x00006000L |
24542 | #define SPI_DSM_CNTL2__SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY_MASK 0x00008000L |
24543 | #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT_MASK 0x00180000L |
24544 | #define SPI_DSM_CNTL2__SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY_MASK 0x00200000L |
24545 | #define SPI_DSM_CNTL2__UNUSED_MASK 0xFFC00000L |
24546 | //SPI_EDC_CNT |
24547 | #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0 |
24548 | #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2 |
24549 | #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4 |
24550 | #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6 |
24551 | #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8 |
24552 | #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa |
24553 | #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10 |
24554 | #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12 |
24555 | #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L |
24556 | #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL |
24557 | #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L |
24558 | #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L |
24559 | #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L |
24560 | #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L |
24561 | #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L |
24562 | #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L |
24563 | //SPI_CONFIG_PS_CU_EN |
24564 | #define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 |
24565 | #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 |
24566 | #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 |
24567 | #define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L |
24568 | #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL |
24569 | #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L |
24570 | //SPI_WF_LIFETIME_CNTL |
24571 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 |
24572 | #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 |
24573 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL |
24574 | #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L |
24575 | //SPI_WF_LIFETIME_LIMIT_0 |
24576 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 |
24577 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f |
24578 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL |
24579 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L |
24580 | //SPI_WF_LIFETIME_LIMIT_1 |
24581 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 |
24582 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f |
24583 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL |
24584 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L |
24585 | //SPI_WF_LIFETIME_LIMIT_2 |
24586 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 |
24587 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f |
24588 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL |
24589 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L |
24590 | //SPI_WF_LIFETIME_LIMIT_3 |
24591 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 |
24592 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f |
24593 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL |
24594 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L |
24595 | //SPI_WF_LIFETIME_LIMIT_4 |
24596 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 |
24597 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f |
24598 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL |
24599 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L |
24600 | //SPI_WF_LIFETIME_LIMIT_5 |
24601 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 |
24602 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f |
24603 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL |
24604 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L |
24605 | //SPI_WF_LIFETIME_LIMIT_6 |
24606 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 |
24607 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f |
24608 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL |
24609 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L |
24610 | //SPI_WF_LIFETIME_LIMIT_7 |
24611 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 |
24612 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f |
24613 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL |
24614 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L |
24615 | //SPI_WF_LIFETIME_LIMIT_8 |
24616 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 |
24617 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f |
24618 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL |
24619 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L |
24620 | //SPI_WF_LIFETIME_LIMIT_9 |
24621 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 |
24622 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f |
24623 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL |
24624 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L |
24625 | //SPI_WF_LIFETIME_STATUS_0 |
24626 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 |
24627 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f |
24628 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL |
24629 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L |
24630 | //SPI_WF_LIFETIME_STATUS_1 |
24631 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 |
24632 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f |
24633 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL |
24634 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L |
24635 | //SPI_WF_LIFETIME_STATUS_2 |
24636 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 |
24637 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f |
24638 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL |
24639 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L |
24640 | //SPI_WF_LIFETIME_STATUS_3 |
24641 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 |
24642 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f |
24643 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL |
24644 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L |
24645 | //SPI_WF_LIFETIME_STATUS_4 |
24646 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 |
24647 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f |
24648 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL |
24649 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L |
24650 | //SPI_WF_LIFETIME_STATUS_5 |
24651 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 |
24652 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f |
24653 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL |
24654 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L |
24655 | //SPI_WF_LIFETIME_STATUS_6 |
24656 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 |
24657 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f |
24658 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL |
24659 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L |
24660 | //SPI_WF_LIFETIME_STATUS_7 |
24661 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 |
24662 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f |
24663 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL |
24664 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L |
24665 | //SPI_WF_LIFETIME_STATUS_8 |
24666 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 |
24667 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f |
24668 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL |
24669 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L |
24670 | //SPI_WF_LIFETIME_STATUS_9 |
24671 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 |
24672 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f |
24673 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL |
24674 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L |
24675 | //SPI_WF_LIFETIME_STATUS_10 |
24676 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 |
24677 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f |
24678 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL |
24679 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L |
24680 | //SPI_WF_LIFETIME_STATUS_11 |
24681 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 |
24682 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f |
24683 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL |
24684 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L |
24685 | //SPI_WF_LIFETIME_STATUS_12 |
24686 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 |
24687 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f |
24688 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL |
24689 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L |
24690 | //SPI_WF_LIFETIME_STATUS_13 |
24691 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 |
24692 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f |
24693 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL |
24694 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L |
24695 | //SPI_WF_LIFETIME_STATUS_14 |
24696 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 |
24697 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f |
24698 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL |
24699 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L |
24700 | //SPI_WF_LIFETIME_STATUS_15 |
24701 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 |
24702 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f |
24703 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL |
24704 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L |
24705 | //SPI_WF_LIFETIME_STATUS_16 |
24706 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 |
24707 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f |
24708 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL |
24709 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L |
24710 | //SPI_WF_LIFETIME_STATUS_17 |
24711 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 |
24712 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f |
24713 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL |
24714 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L |
24715 | //SPI_WF_LIFETIME_STATUS_18 |
24716 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 |
24717 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f |
24718 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL |
24719 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L |
24720 | //SPI_WF_LIFETIME_STATUS_19 |
24721 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 |
24722 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f |
24723 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL |
24724 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L |
24725 | //SPI_WF_LIFETIME_STATUS_20 |
24726 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 |
24727 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f |
24728 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL |
24729 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L |
24730 | //SPI_LB_CTR_CTRL |
24731 | #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 |
24732 | #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 |
24733 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 |
24734 | #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 |
24735 | #define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L |
24736 | #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L |
24737 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L |
24738 | #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L |
24739 | //SPI_LB_CU_MASK |
24740 | #define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 |
24741 | #define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL |
24742 | //SPI_LB_DATA_REG |
24743 | #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 |
24744 | #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL |
24745 | //SPI_PG_ENABLE_STATIC_CU_MASK |
24746 | #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 |
24747 | #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL |
24748 | //SPI_GDS_CREDITS |
24749 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 |
24750 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 |
24751 | #define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 |
24752 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL |
24753 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L |
24754 | #define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L |
24755 | //SPI_SX_EXPORT_BUFFER_SIZES |
24756 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 |
24757 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 |
24758 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL |
24759 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L |
24760 | //SPI_SX_SCOREBOARD_BUFFER_SIZES |
24761 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 |
24762 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 |
24763 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL |
24764 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L |
24765 | //SPI_CSQ_WF_ACTIVE_STATUS |
24766 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 |
24767 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL |
24768 | //SPI_CSQ_WF_ACTIVE_COUNT_0 |
24769 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 |
24770 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 |
24771 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000001FFL |
24772 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x01FF0000L |
24773 | //SPI_CSQ_WF_ACTIVE_COUNT_1 |
24774 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 |
24775 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 |
24776 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000001FFL |
24777 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x01FF0000L |
24778 | //SPI_CSQ_WF_ACTIVE_COUNT_2 |
24779 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 |
24780 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 |
24781 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000001FFL |
24782 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x01FF0000L |
24783 | //SPI_CSQ_WF_ACTIVE_COUNT_3 |
24784 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 |
24785 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 |
24786 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000001FFL |
24787 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x01FF0000L |
24788 | //SPI_CSQ_WF_ACTIVE_COUNT_4 |
24789 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 |
24790 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 |
24791 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000001FFL |
24792 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x01FF0000L |
24793 | //SPI_CSQ_WF_ACTIVE_COUNT_5 |
24794 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 |
24795 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 |
24796 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000001FFL |
24797 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x01FF0000L |
24798 | //SPI_CSQ_WF_ACTIVE_COUNT_6 |
24799 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 |
24800 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 |
24801 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000001FFL |
24802 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x01FF0000L |
24803 | //SPI_CSQ_WF_ACTIVE_COUNT_7 |
24804 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 |
24805 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 |
24806 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000001FFL |
24807 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x01FF0000L |
24808 | //SPI_LB_DATA_WAVES |
24809 | #define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 |
24810 | #define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 |
24811 | #define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL |
24812 | #define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L |
24813 | //SPI_LB_DATA_PERCU_WAVE_HSGS |
24814 | #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 |
24815 | #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 |
24816 | #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL |
24817 | #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L |
24818 | //SPI_LB_DATA_PERCU_WAVE_VSPS |
24819 | #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 |
24820 | #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 |
24821 | #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL |
24822 | #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L |
24823 | //SPI_LB_DATA_PERCU_WAVE_CS |
24824 | #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 |
24825 | #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL |
24826 | //SPI_P0_TRAP_SCREEN_PSBA_LO |
24827 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
24828 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
24829 | //SPI_P0_TRAP_SCREEN_PSBA_HI |
24830 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
24831 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
24832 | //SPI_P0_TRAP_SCREEN_PSMA_LO |
24833 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
24834 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
24835 | //SPI_P0_TRAP_SCREEN_PSMA_HI |
24836 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
24837 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
24838 | //SPI_P0_TRAP_SCREEN_GPR_MIN |
24839 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
24840 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
24841 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
24842 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
24843 | //SPI_P1_TRAP_SCREEN_PSBA_LO |
24844 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
24845 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
24846 | //SPI_P1_TRAP_SCREEN_PSBA_HI |
24847 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
24848 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
24849 | //SPI_P1_TRAP_SCREEN_PSMA_LO |
24850 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
24851 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
24852 | //SPI_P1_TRAP_SCREEN_PSMA_HI |
24853 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
24854 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
24855 | //SPI_P1_TRAP_SCREEN_GPR_MIN |
24856 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
24857 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
24858 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
24859 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
24860 | |
24861 | |
24862 | // addressBlock: gc_spipdec |
24863 | //SPI_ARB_PRIORITY |
24864 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 |
24865 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 |
24866 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 |
24867 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 |
24868 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc |
24869 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe |
24870 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 |
24871 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 |
24872 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L |
24873 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L |
24874 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L |
24875 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L |
24876 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L |
24877 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L |
24878 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L |
24879 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L |
24880 | //SPI_ARB_CYCLES_0 |
24881 | #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 |
24882 | #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 |
24883 | #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL |
24884 | #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L |
24885 | //SPI_ARB_CYCLES_1 |
24886 | #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 |
24887 | #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 |
24888 | #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL |
24889 | #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L |
24890 | //SPI_WCL_PIPE_PERCENT_GFX |
24891 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 |
24892 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 |
24893 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc |
24894 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 |
24895 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 |
24896 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL |
24897 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L |
24898 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L |
24899 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L |
24900 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L |
24901 | //SPI_WCL_PIPE_PERCENT_HP3D |
24902 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 |
24903 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc |
24904 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 |
24905 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL |
24906 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L |
24907 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L |
24908 | //SPI_WCL_PIPE_PERCENT_CS0 |
24909 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 |
24910 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL |
24911 | //SPI_WCL_PIPE_PERCENT_CS1 |
24912 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 |
24913 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL |
24914 | //SPI_WCL_PIPE_PERCENT_CS2 |
24915 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 |
24916 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL |
24917 | //SPI_WCL_PIPE_PERCENT_CS3 |
24918 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 |
24919 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL |
24920 | //SPI_WCL_PIPE_PERCENT_CS4 |
24921 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 |
24922 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL |
24923 | //SPI_WCL_PIPE_PERCENT_CS5 |
24924 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 |
24925 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL |
24926 | //SPI_WCL_PIPE_PERCENT_CS6 |
24927 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 |
24928 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL |
24929 | //SPI_WCL_PIPE_PERCENT_CS7 |
24930 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 |
24931 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL |
24932 | //SPI_GDBG_WAVE_CNTL |
24933 | #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 |
24934 | #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x01L |
24935 | //SPI_GDBG_TRAP_CONFIG |
24936 | #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 |
24937 | #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 |
24938 | #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 |
24939 | #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 |
24940 | #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL |
24941 | #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L |
24942 | #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L |
24943 | #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L |
24944 | //SPI_GDBG_PER_VMID_CNTL |
24945 | #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 |
24946 | #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 |
24947 | #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 |
24948 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 |
24949 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd |
24950 | #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x0001L |
24951 | #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x0006L |
24952 | #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x0008L |
24953 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x1FF0L |
24954 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x2000L |
24955 | //SPI_GDBG_WAVE_CNTL3 |
24956 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 |
24957 | #define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 |
24958 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 |
24959 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 |
24960 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 |
24961 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 |
24962 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 |
24963 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 |
24964 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 |
24965 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 |
24966 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa |
24967 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb |
24968 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc |
24969 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd |
24970 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c |
24971 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L |
24972 | #define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L |
24973 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L |
24974 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L |
24975 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L |
24976 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L |
24977 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L |
24978 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L |
24979 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L |
24980 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L |
24981 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L |
24982 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L |
24983 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L |
24984 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L |
24985 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L |
24986 | //SPI_GDBG_TRAP_DATA0 |
24987 | #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 |
24988 | #define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL |
24989 | //SPI_GDBG_TRAP_DATA1 |
24990 | #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 |
24991 | #define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL |
24992 | //SPI_COMPUTE_QUEUE_RESET |
24993 | #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 |
24994 | #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L |
24995 | //SPI_RESOURCE_RESERVE_CU_0 |
24996 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 |
24997 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 |
24998 | #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 |
24999 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc |
25000 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf |
25001 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL |
25002 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L |
25003 | #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L |
25004 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L |
25005 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L |
25006 | //SPI_RESOURCE_RESERVE_CU_1 |
25007 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 |
25008 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 |
25009 | #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 |
25010 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc |
25011 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf |
25012 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL |
25013 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L |
25014 | #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L |
25015 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L |
25016 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L |
25017 | //SPI_RESOURCE_RESERVE_CU_2 |
25018 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 |
25019 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 |
25020 | #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 |
25021 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc |
25022 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf |
25023 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL |
25024 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L |
25025 | #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L |
25026 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L |
25027 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L |
25028 | //SPI_RESOURCE_RESERVE_CU_3 |
25029 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 |
25030 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 |
25031 | #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 |
25032 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc |
25033 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf |
25034 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL |
25035 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L |
25036 | #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L |
25037 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L |
25038 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L |
25039 | //SPI_RESOURCE_RESERVE_CU_4 |
25040 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 |
25041 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 |
25042 | #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 |
25043 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc |
25044 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf |
25045 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL |
25046 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L |
25047 | #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L |
25048 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L |
25049 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L |
25050 | //SPI_RESOURCE_RESERVE_CU_5 |
25051 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 |
25052 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 |
25053 | #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 |
25054 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc |
25055 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf |
25056 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL |
25057 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L |
25058 | #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L |
25059 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L |
25060 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L |
25061 | //SPI_RESOURCE_RESERVE_CU_6 |
25062 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 |
25063 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 |
25064 | #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 |
25065 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc |
25066 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf |
25067 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL |
25068 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L |
25069 | #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L |
25070 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L |
25071 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L |
25072 | //SPI_RESOURCE_RESERVE_CU_7 |
25073 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 |
25074 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 |
25075 | #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 |
25076 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc |
25077 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf |
25078 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL |
25079 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L |
25080 | #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L |
25081 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L |
25082 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L |
25083 | //SPI_RESOURCE_RESERVE_CU_8 |
25084 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 |
25085 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 |
25086 | #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 |
25087 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc |
25088 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf |
25089 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL |
25090 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L |
25091 | #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L |
25092 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L |
25093 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L |
25094 | //SPI_RESOURCE_RESERVE_CU_9 |
25095 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 |
25096 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 |
25097 | #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 |
25098 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc |
25099 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf |
25100 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL |
25101 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L |
25102 | #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L |
25103 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L |
25104 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L |
25105 | //SPI_RESOURCE_RESERVE_EN_CU_0 |
25106 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 |
25107 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 |
25108 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 |
25109 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25110 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L |
25111 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL |
25112 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L |
25113 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25114 | //SPI_RESOURCE_RESERVE_EN_CU_1 |
25115 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 |
25116 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 |
25117 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 |
25118 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25119 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L |
25120 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL |
25121 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L |
25122 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25123 | //SPI_RESOURCE_RESERVE_EN_CU_2 |
25124 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 |
25125 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 |
25126 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 |
25127 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25128 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L |
25129 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL |
25130 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L |
25131 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25132 | //SPI_RESOURCE_RESERVE_EN_CU_3 |
25133 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 |
25134 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 |
25135 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 |
25136 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25137 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L |
25138 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL |
25139 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L |
25140 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25141 | //SPI_RESOURCE_RESERVE_EN_CU_4 |
25142 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 |
25143 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 |
25144 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 |
25145 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25146 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L |
25147 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL |
25148 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L |
25149 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25150 | //SPI_RESOURCE_RESERVE_EN_CU_5 |
25151 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 |
25152 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 |
25153 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 |
25154 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25155 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L |
25156 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL |
25157 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L |
25158 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25159 | //SPI_RESOURCE_RESERVE_EN_CU_6 |
25160 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 |
25161 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 |
25162 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 |
25163 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25164 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L |
25165 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL |
25166 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L |
25167 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25168 | //SPI_RESOURCE_RESERVE_EN_CU_7 |
25169 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 |
25170 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 |
25171 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 |
25172 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25173 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L |
25174 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL |
25175 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L |
25176 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25177 | //SPI_RESOURCE_RESERVE_EN_CU_8 |
25178 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 |
25179 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 |
25180 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 |
25181 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25182 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L |
25183 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL |
25184 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L |
25185 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25186 | //SPI_RESOURCE_RESERVE_EN_CU_9 |
25187 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 |
25188 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 |
25189 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 |
25190 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25191 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L |
25192 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL |
25193 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L |
25194 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25195 | //SPI_RESOURCE_RESERVE_CU_10 |
25196 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 |
25197 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 |
25198 | #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 |
25199 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc |
25200 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf |
25201 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL |
25202 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L |
25203 | #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L |
25204 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L |
25205 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L |
25206 | //SPI_RESOURCE_RESERVE_CU_11 |
25207 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 |
25208 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 |
25209 | #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 |
25210 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc |
25211 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf |
25212 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL |
25213 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L |
25214 | #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L |
25215 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L |
25216 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L |
25217 | //SPI_RESOURCE_RESERVE_EN_CU_10 |
25218 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 |
25219 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 |
25220 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 |
25221 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25222 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L |
25223 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL |
25224 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L |
25225 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25226 | //SPI_RESOURCE_RESERVE_EN_CU_11 |
25227 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 |
25228 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 |
25229 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 |
25230 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25231 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L |
25232 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL |
25233 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L |
25234 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25235 | //SPI_RESOURCE_RESERVE_CU_12 |
25236 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 |
25237 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 |
25238 | #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 |
25239 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc |
25240 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf |
25241 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL |
25242 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L |
25243 | #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L |
25244 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L |
25245 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L |
25246 | //SPI_RESOURCE_RESERVE_CU_13 |
25247 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 |
25248 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 |
25249 | #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 |
25250 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc |
25251 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf |
25252 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL |
25253 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L |
25254 | #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L |
25255 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L |
25256 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L |
25257 | //SPI_RESOURCE_RESERVE_CU_14 |
25258 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 |
25259 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 |
25260 | #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 |
25261 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc |
25262 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf |
25263 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL |
25264 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L |
25265 | #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L |
25266 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L |
25267 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L |
25268 | //SPI_RESOURCE_RESERVE_CU_15 |
25269 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 |
25270 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 |
25271 | #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 |
25272 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc |
25273 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf |
25274 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL |
25275 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L |
25276 | #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L |
25277 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L |
25278 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L |
25279 | //SPI_RESOURCE_RESERVE_EN_CU_12 |
25280 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 |
25281 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 |
25282 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 |
25283 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25284 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L |
25285 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL |
25286 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L |
25287 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25288 | //SPI_RESOURCE_RESERVE_EN_CU_13 |
25289 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 |
25290 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 |
25291 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 |
25292 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25293 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L |
25294 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL |
25295 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L |
25296 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25297 | //SPI_RESOURCE_RESERVE_EN_CU_14 |
25298 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 |
25299 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 |
25300 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 |
25301 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25302 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L |
25303 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL |
25304 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L |
25305 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25306 | //SPI_RESOURCE_RESERVE_EN_CU_15 |
25307 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 |
25308 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 |
25309 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 |
25310 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 |
25311 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L |
25312 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL |
25313 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L |
25314 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L |
25315 | //SPI_COMPUTE_WF_CTX_SAVE |
25316 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 |
25317 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 |
25318 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 |
25319 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e |
25320 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f |
25321 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L |
25322 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L |
25323 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L |
25324 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L |
25325 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L |
25326 | //SPI_ARB_CNTL_0 |
25327 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 |
25328 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 |
25329 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 |
25330 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL |
25331 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L |
25332 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L |
25333 | |
25334 | |
25335 | // addressBlock: gc_sqdec |
25336 | //SQ_CONFIG |
25337 | #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0 |
25338 | #define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING__SHIFT 0x1 |
25339 | #define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO__SHIFT 0x2 |
25340 | #define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY__SHIFT 0x3 |
25341 | #define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x4 |
25342 | #define SQ_CONFIG__DISABLE_MAI_CO_EXEC__SHIFT 0x5 |
25343 | #define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY__SHIFT 0x6 |
25344 | #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 |
25345 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb |
25346 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc |
25347 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd |
25348 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe |
25349 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf |
25350 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 |
25351 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 |
25352 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 |
25353 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 |
25354 | #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 |
25355 | #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c |
25356 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d |
25357 | #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e |
25358 | #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f |
25359 | #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L |
25360 | #define SQ_CONFIG__DISABLE_REPEATER_FGCG_CLOCK_GATING_MASK 0x00000002L |
25361 | #define SQ_CONFIG__DISABLE_SPIPRIO_OVER_USERPRIO_MASK 0x00000004L |
25362 | #define SQ_CONFIG__OVERRIDE_SP_MAI_ALU_BUSY_MASK 0x00000008L |
25363 | #define SQ_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000010L |
25364 | #define SQ_CONFIG__DISABLE_MAI_CO_EXEC_MASK 0x00000020L |
25365 | #define SQ_CONFIG__OVERRIDE_MAI_ALU_BUSY_MASK 0x00000040L |
25366 | #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L |
25367 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L |
25368 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L |
25369 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L |
25370 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L |
25371 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L |
25372 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L |
25373 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L |
25374 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L |
25375 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L |
25376 | #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L |
25377 | #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L |
25378 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L |
25379 | #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L |
25380 | #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L |
25381 | //SQC_CONFIG |
25382 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 |
25383 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 |
25384 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 |
25385 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 |
25386 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 |
25387 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 |
25388 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb |
25389 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc |
25390 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe |
25391 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf |
25392 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 |
25393 | #define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 |
25394 | #define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1d |
25395 | #define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK__SHIFT 0x1e |
25396 | #define SQC_CONFIG__MEM_LS_DISABLE__SHIFT 0x1f |
25397 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L |
25398 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL |
25399 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L |
25400 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L |
25401 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L |
25402 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L |
25403 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L |
25404 | #define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L |
25405 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L |
25406 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L |
25407 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L |
25408 | #define SQC_CONFIG__INST_PRF_COUNT_MASK 0x1F000000L |
25409 | #define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x20000000L |
25410 | #define SQC_CONFIG__DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK_MASK 0x40000000L |
25411 | #define SQC_CONFIG__MEM_LS_DISABLE_MASK 0x80000000L |
25412 | //LDS_CONFIG |
25413 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 |
25414 | #define LDS_CONFIG__TMZ_VIOLATION_REPORTING__SHIFT 0x1 |
25415 | #define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2 |
25416 | #define LDS_CONFIG__DISABLE_IDXCLK_MGCG__SHIFT 0x3 |
25417 | #define LDS_CONFIG__DISABLE_MEMCLK_MGCG__SHIFT 0x4 |
25418 | #define LDS_CONFIG__DISABLE_ATTRCLK_MGCG__SHIFT 0x5 |
25419 | #define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG__SHIFT 0x6 |
25420 | #define LDS_CONFIG__DISABLE_PHASE_FGCG__SHIFT 0x7 |
25421 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L |
25422 | #define LDS_CONFIG__TMZ_VIOLATION_REPORTING_MASK 0x00000002L |
25423 | #define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L |
25424 | #define LDS_CONFIG__DISABLE_IDXCLK_MGCG_MASK 0x00000008L |
25425 | #define LDS_CONFIG__DISABLE_MEMCLK_MGCG_MASK 0x00000010L |
25426 | #define LDS_CONFIG__DISABLE_ATTRCLK_MGCG_MASK 0x00000020L |
25427 | #define LDS_CONFIG__DISABLE_ATODFPCLK_MGCG_MASK 0x00000040L |
25428 | #define LDS_CONFIG__DISABLE_PHASE_FGCG_MASK 0x00000080L |
25429 | //SQ_RANDOM_WAVE_PRI |
25430 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 |
25431 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 |
25432 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa |
25433 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL |
25434 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L |
25435 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L |
25436 | //SQ_REG_CREDITS |
25437 | #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 |
25438 | #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 |
25439 | #define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c |
25440 | #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d |
25441 | #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e |
25442 | #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f |
25443 | #define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL |
25444 | #define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L |
25445 | #define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L |
25446 | #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L |
25447 | #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L |
25448 | #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L |
25449 | //SQ_FIFO_SIZES |
25450 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 |
25451 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 |
25452 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 |
25453 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 |
25454 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL |
25455 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L |
25456 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L |
25457 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L |
25458 | //SQ_DSM_CNTL |
25459 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 |
25460 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 |
25461 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 |
25462 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 |
25463 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 |
25464 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 |
25465 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa |
25466 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 |
25467 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 |
25468 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 |
25469 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 |
25470 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 |
25471 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 |
25472 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 |
25473 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 |
25474 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
25475 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L |
25476 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L |
25477 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L |
25478 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L |
25479 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L |
25480 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L |
25481 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L |
25482 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L |
25483 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L |
25484 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L |
25485 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L |
25486 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L |
25487 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L |
25488 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L |
25489 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L |
25490 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
25491 | //SQ_DSM_CNTL2 |
25492 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 |
25493 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 |
25494 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 |
25495 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 |
25496 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 |
25497 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 |
25498 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 |
25499 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb |
25500 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe |
25501 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 |
25502 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a |
25503 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L |
25504 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L |
25505 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L |
25506 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L |
25507 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
25508 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L |
25509 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L |
25510 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L |
25511 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L |
25512 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L |
25513 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L |
25514 | //SQ_RUNTIME_CONFIG |
25515 | #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 |
25516 | #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L |
25517 | //SQ_DEBUG_STS_GLOBAL |
25518 | #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 |
25519 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 |
25520 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 |
25521 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 |
25522 | #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L |
25523 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L |
25524 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000FFF0L |
25525 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0FFF0000L |
25526 | //SH_MEM_BASES |
25527 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 |
25528 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 |
25529 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL |
25530 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L |
25531 | //SQ_TIMEOUT_CONFIG |
25532 | #define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0 |
25533 | #define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6 |
25534 | #define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL |
25535 | #define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L |
25536 | //SQ_TIMEOUT_STATUS |
25537 | #define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT__SHIFT 0x0 |
25538 | #define SQ_TIMEOUT_STATUS__WAVE_TIMEOUT_MASK 0xFFFFFFFFL |
25539 | //SH_MEM_CONFIG |
25540 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 |
25541 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 |
25542 | #define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc |
25543 | #define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd |
25544 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L |
25545 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L |
25546 | #define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L |
25547 | #define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L |
25548 | //SP_MFMA_PORTD_RD_CONFIG |
25549 | #define SP_MFMA_PORTD_RD_CONFIG__SET__SHIFT 0x0 |
25550 | #define SP_MFMA_PORTD_RD_CONFIG__TYPE__SHIFT 0x1 |
25551 | #define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS__SHIFT 0x4 |
25552 | #define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN__SHIFT 0x9 |
25553 | #define SP_MFMA_PORTD_RD_CONFIG__SET_MASK 0x00000001L |
25554 | #define SP_MFMA_PORTD_RD_CONFIG__TYPE_MASK 0x0000000EL |
25555 | #define SP_MFMA_PORTD_RD_CONFIG__LAST_PASS_MASK 0x000001F0L |
25556 | #define SP_MFMA_PORTD_RD_CONFIG__PORTD_PATTERN_MASK 0x1FFFFE00L |
25557 | //SH_CAC_CONFIG |
25558 | #define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x0 |
25559 | #define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE__SHIFT 0x1 |
25560 | #define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE__SHIFT 0x2 |
25561 | #define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE__SHIFT 0x3 |
25562 | #define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE__SHIFT 0x4 |
25563 | #define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE__SHIFT 0x5 |
25564 | #define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE__SHIFT 0x6 |
25565 | #define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING__SHIFT 0x8 |
25566 | #define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING__SHIFT 0x9 |
25567 | #define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT__SHIFT 0x10 |
25568 | #define SH_CAC_CONFIG__SQC_MGCG_DISABLE__SHIFT 0x14 |
25569 | #define SH_CAC_CONFIG__SQG_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000001L |
25570 | #define SH_CAC_CONFIG__SQC_UTCL1_REPEATER_FGCG_DISABLE_MASK 0x00000002L |
25571 | #define SH_CAC_CONFIG__SPI_SQ_CMD_REPEATER_FGCG_DISABLE_MASK 0x00000004L |
25572 | #define SH_CAC_CONFIG__SQ_MSG_REPEATER_FGCG_DISABLE_MASK 0x00000008L |
25573 | #define SH_CAC_CONFIG__SQC_TC_REPEATER_FGCG_DISABLE_MASK 0x00000010L |
25574 | #define SH_CAC_CONFIG__SQC_SQ_REPEATER_FGCG_DISABLE_MASK 0x00000020L |
25575 | #define SH_CAC_CONFIG__SQG_TC_REPEATER_FGCG_DISABLE_MASK 0x00000040L |
25576 | #define SH_CAC_CONFIG__SQC_DISABLE_RAM_CLOCK_GATING_MASK 0x00000100L |
25577 | #define SH_CAC_CONFIG__SQG_DISABLE_RAM_CLOCK_GATING_MASK 0x00000200L |
25578 | #define SH_CAC_CONFIG__SQC_MGCG_CLOCK_OFF_DELAY_CNT_MASK 0x000F0000L |
25579 | #define SH_CAC_CONFIG__SQC_MGCG_DISABLE_MASK 0x0FF00000L |
25580 | //SQ_DEBUG_STS_GLOBAL2 |
25581 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 |
25582 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 |
25583 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 |
25584 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 |
25585 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000FFL |
25586 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000FF00L |
25587 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00FF0000L |
25588 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xFF000000L |
25589 | //SQ_DEBUG_STS_GLOBAL3 |
25590 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 |
25591 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 |
25592 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000FL |
25593 | #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000003F0L |
25594 | //CC_GC_SHADER_RATE_CONFIG |
25595 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
25596 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
25597 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 |
25598 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
25599 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
25600 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L |
25601 | //GC_USER_SHADER_RATE_CONFIG |
25602 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
25603 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
25604 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 |
25605 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
25606 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
25607 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L |
25608 | //SQ_INTERRUPT_AUTO_MASK |
25609 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 |
25610 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL |
25611 | //SQ_INTERRUPT_MSG_CTRL |
25612 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 |
25613 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L |
25614 | //SQ_DEBUG_PERFCOUNT_TRAP |
25615 | #define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE__SHIFT 0x0 |
25616 | #define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER__SHIFT 0x1 |
25617 | #define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT__SHIFT 0x4 |
25618 | #define SQ_DEBUG_PERFCOUNT_TRAP__ENABLE_MASK 0x00000001L |
25619 | #define SQ_DEBUG_PERFCOUNT_TRAP__COUNTER_MASK 0x0000000EL |
25620 | #define SQ_DEBUG_PERFCOUNT_TRAP__LIMIT_MASK 0x0FFFFFF0L |
25621 | //SQ_UTCL1_CNTL1 |
25622 | #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
25623 | #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
25624 | #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
25625 | #define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
25626 | #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
25627 | #define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
25628 | #define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
25629 | #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
25630 | #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
25631 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
25632 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
25633 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
25634 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 |
25635 | #define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
25636 | #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
25637 | #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
25638 | #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
25639 | #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
25640 | #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
25641 | #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
25642 | #define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
25643 | #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
25644 | #define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
25645 | #define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
25646 | #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
25647 | #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
25648 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
25649 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
25650 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
25651 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L |
25652 | #define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
25653 | #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
25654 | #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
25655 | #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
25656 | //SQ_UTCL1_CNTL2 |
25657 | #define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
25658 | #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
25659 | #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
25660 | #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
25661 | #define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
25662 | #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
25663 | #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
25664 | #define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
25665 | #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
25666 | #define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 |
25667 | #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
25668 | #define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c |
25669 | #define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
25670 | #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
25671 | #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
25672 | #define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
25673 | #define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
25674 | #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
25675 | #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
25676 | #define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
25677 | #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
25678 | #define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L |
25679 | #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
25680 | #define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L |
25681 | //SQ_UTCL1_STATUS |
25682 | #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
25683 | #define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
25684 | #define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
25685 | #define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
25686 | #define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 |
25687 | #define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
25688 | #define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
25689 | #define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
25690 | #define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L |
25691 | #define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L |
25692 | //SQ_FED_INTERRUPT_STATUS |
25693 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS__SHIFT 0x0 |
25694 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID__SHIFT 0x2 |
25695 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID__SHIFT 0x4 |
25696 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID__SHIFT 0x8 |
25697 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID__SHIFT 0xc |
25698 | #define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE__SHIFT 0x11 |
25699 | #define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE__SHIFT 0x12 |
25700 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_STATUS_MASK 0x00000001L |
25701 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_SIMD_ID_MASK 0x0000000CL |
25702 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_WAVE_ID_MASK 0x000000F0L |
25703 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_CU_ID_MASK 0x00000F00L |
25704 | #define SQ_FED_INTERRUPT_STATUS__INTERRUPT_VM_ID_MASK 0x0000F000L |
25705 | #define SQ_FED_INTERRUPT_STATUS__TO_IH_DISABLE_MASK 0x00020000L |
25706 | #define SQ_FED_INTERRUPT_STATUS__FED_HALT_DISABLE_MASK 0x00040000L |
25707 | //SQ_CGTS_CONFIG |
25708 | #define 0x0 |
25709 | #define 0x4 |
25710 | #define 0x8 |
25711 | #define 0xc |
25712 | #define 0x10 |
25713 | #define 0x12 |
25714 | #define 0x0000000FL |
25715 | #define 0x000000F0L |
25716 | #define 0x00000F00L |
25717 | #define 0x0000F000L |
25718 | #define 0x00030000L |
25719 | #define 0x000C0000L |
25720 | //SQ_SHADER_TBA_LO |
25721 | #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 |
25722 | #define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
25723 | //SQ_SHADER_TBA_HI |
25724 | #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 |
25725 | #define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL |
25726 | //SQ_SHADER_TMA_LO |
25727 | #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 |
25728 | #define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
25729 | //SQ_SHADER_TMA_HI |
25730 | #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 |
25731 | #define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL |
25732 | //SQC_DSM_CNTL |
25733 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
25734 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
25735 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 |
25736 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
25737 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
25738 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
25739 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 |
25740 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb |
25741 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc |
25742 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe |
25743 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf |
25744 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
25745 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
25746 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
25747 | #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x15 |
25748 | #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
25749 | #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x18 |
25750 | #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
25751 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
25752 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
25753 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L |
25754 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
25755 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
25756 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
25757 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L |
25758 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
25759 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L |
25760 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
25761 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L |
25762 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
25763 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
25764 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
25765 | #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00600000L |
25766 | #define SQC_DSM_CNTL__DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
25767 | #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x03000000L |
25768 | #define SQC_DSM_CNTL__DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
25769 | //SQC_DSM_CNTLA |
25770 | #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
25771 | #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
25772 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 |
25773 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
25774 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
25775 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
25776 | #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
25777 | #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
25778 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc |
25779 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
25780 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf |
25781 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
25782 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
25783 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
25784 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
25785 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
25786 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 |
25787 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
25788 | #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
25789 | #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
25790 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L |
25791 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
25792 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
25793 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
25794 | #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
25795 | #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
25796 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
25797 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
25798 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L |
25799 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
25800 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
25801 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
25802 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
25803 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
25804 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L |
25805 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
25806 | //SQC_DSM_CNTLB |
25807 | #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
25808 | #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
25809 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 |
25810 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
25811 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
25812 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
25813 | #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
25814 | #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
25815 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc |
25816 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
25817 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf |
25818 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
25819 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
25820 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
25821 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
25822 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
25823 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 |
25824 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
25825 | #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
25826 | #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
25827 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L |
25828 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
25829 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
25830 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
25831 | #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
25832 | #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
25833 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
25834 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
25835 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L |
25836 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
25837 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
25838 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
25839 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
25840 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
25841 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L |
25842 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
25843 | //SQC_DSM_CNTL2 |
25844 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
25845 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 |
25846 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 |
25847 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 |
25848 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
25849 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
25850 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 |
25851 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb |
25852 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc |
25853 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe |
25854 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf |
25855 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 |
25856 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
25857 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
25858 | #define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
25859 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
25860 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L |
25861 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L |
25862 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L |
25863 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
25864 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
25865 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L |
25866 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L |
25867 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L |
25868 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L |
25869 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L |
25870 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L |
25871 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
25872 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
25873 | #define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
25874 | //SQC_DSM_CNTL2A |
25875 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
25876 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
25877 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 |
25878 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 |
25879 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
25880 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
25881 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
25882 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
25883 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
25884 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
25885 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf |
25886 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 |
25887 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
25888 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
25889 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
25890 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
25891 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 |
25892 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a |
25893 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
25894 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
25895 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L |
25896 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L |
25897 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
25898 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
25899 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
25900 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
25901 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
25902 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
25903 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L |
25904 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L |
25905 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
25906 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
25907 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
25908 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
25909 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L |
25910 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L |
25911 | //SQC_DSM_CNTL2B |
25912 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
25913 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
25914 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 |
25915 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 |
25916 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
25917 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
25918 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
25919 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
25920 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
25921 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
25922 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf |
25923 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 |
25924 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
25925 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
25926 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
25927 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
25928 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 |
25929 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a |
25930 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
25931 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
25932 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L |
25933 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L |
25934 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
25935 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
25936 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
25937 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
25938 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
25939 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
25940 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L |
25941 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L |
25942 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
25943 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
25944 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
25945 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
25946 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L |
25947 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L |
25948 | //SQC_DSM_CNTL2E |
25949 | #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x0 |
25950 | #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x2 |
25951 | #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 |
25952 | #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x5 |
25953 | #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000003L |
25954 | #define SQC_DSM_CNTL2E__DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000004L |
25955 | #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L |
25956 | #define SQC_DSM_CNTL2E__DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000020L |
25957 | //SQC_EDC_FUE_CNTL |
25958 | #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
25959 | #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
25960 | #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
25961 | #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
25962 | //SQC_EDC_CNT2 |
25963 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 |
25964 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 |
25965 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 |
25966 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 |
25967 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 |
25968 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa |
25969 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc |
25970 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe |
25971 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10 |
25972 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12 |
25973 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x14 |
25974 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x16 |
25975 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L |
25976 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL |
25977 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L |
25978 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L |
25979 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L |
25980 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L |
25981 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L |
25982 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L |
25983 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L |
25984 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L |
25985 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00300000L |
25986 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT_MASK 0x00C00000L |
25987 | //SQC_EDC_CNT3 |
25988 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 |
25989 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 |
25990 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 |
25991 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 |
25992 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 |
25993 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa |
25994 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc |
25995 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe |
25996 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT__SHIFT 0x10 |
25997 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT__SHIFT 0x12 |
25998 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L |
25999 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL |
26000 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L |
26001 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L |
26002 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L |
26003 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L |
26004 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L |
26005 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L |
26006 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT_MASK 0x00030000L |
26007 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT_MASK 0x000C0000L |
26008 | //SQC_EDC_PARITY_CNT3 |
26009 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0 |
26010 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2 |
26011 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4 |
26012 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6 |
26013 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8 |
26014 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa |
26015 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc |
26016 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe |
26017 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10 |
26018 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12 |
26019 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14 |
26020 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16 |
26021 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18 |
26022 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a |
26023 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c |
26024 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e |
26025 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L |
26026 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL |
26027 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L |
26028 | #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L |
26029 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L |
26030 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L |
26031 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L |
26032 | #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L |
26033 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L |
26034 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L |
26035 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L |
26036 | #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L |
26037 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L |
26038 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L |
26039 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L |
26040 | #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L |
26041 | //SQ_DEBUG |
26042 | #define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 |
26043 | #define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L |
26044 | //SQ_REG_TIMESTAMP |
26045 | #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 |
26046 | #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL |
26047 | //SQ_CMD_TIMESTAMP |
26048 | #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 |
26049 | #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL |
26050 | //SQ_HOSTTRAP_STATUS |
26051 | #define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 |
26052 | #define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 |
26053 | #define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL |
26054 | #define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L |
26055 | //SQ_IND_INDEX |
26056 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 |
26057 | #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 |
26058 | #define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 |
26059 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc |
26060 | #define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd |
26061 | #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe |
26062 | #define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf |
26063 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 |
26064 | #define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL |
26065 | #define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L |
26066 | #define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L |
26067 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L |
26068 | #define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L |
26069 | #define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L |
26070 | #define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L |
26071 | #define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L |
26072 | //SQ_IND_DATA |
26073 | #define SQ_IND_DATA__DATA__SHIFT 0x0 |
26074 | #define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL |
26075 | //SQ_CONFIG1 |
26076 | #define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC__SHIFT 0x0 |
26077 | #define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF__SHIFT 0x1 |
26078 | #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF__SHIFT 0x2 |
26079 | #define SQ_CONFIG1__DISABLE_MGCG_ON_EXP__SHIFT 0x3 |
26080 | #define SQ_CONFIG1__DISABLE_MGCG_ON_SCA__SHIFT 0x4 |
26081 | #define SQ_CONFIG1__DISABLE_MGCG_ON_SREG__SHIFT 0x5 |
26082 | #define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC__SHIFT 0x6 |
26083 | #define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE__SHIFT 0xc |
26084 | #define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH__SHIFT 0xd |
26085 | #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT__SHIFT 0xe |
26086 | #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF__SHIFT 0xf |
26087 | #define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE__SHIFT 0x18 |
26088 | #define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE__SHIFT 0x19 |
26089 | #define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE__SHIFT 0x1a |
26090 | #define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE__SHIFT 0x1b |
26091 | #define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE__SHIFT 0x1c |
26092 | #define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE__SHIFT 0x1d |
26093 | #define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP__SHIFT 0x1e |
26094 | #define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE__SHIFT 0x1f |
26095 | #define SQ_CONFIG1__DISABLE_XDL_PORTD_CO_EXEC_MASK 0x00000001L |
26096 | #define SQ_CONFIG1__DISABLE_MGCG_ON_IBUF_MASK 0x00000002L |
26097 | #define SQ_CONFIG1__DISABLE_MGCG_ON_PERF_MASK 0x00000004L |
26098 | #define SQ_CONFIG1__DISABLE_MGCG_ON_EXP_MASK 0x00000008L |
26099 | #define SQ_CONFIG1__DISABLE_MGCG_ON_SCA_MASK 0x00000010L |
26100 | #define SQ_CONFIG1__DISABLE_MGCG_ON_SREG_MASK 0x00000020L |
26101 | #define SQ_CONFIG1__DISABLE_MGCG_ON_VDEC_MASK 0x00000040L |
26102 | #define SQ_CONFIG1__DISABLE_XNACK_CHECK_IN_RETRY_DISABLE_MASK 0x00001000L |
26103 | #define SQ_CONFIG1__DISABLE_BARRIER_ADDR_WATCH_MASK 0x00002000L |
26104 | #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_WAIT_MASK 0x00004000L |
26105 | #define SQ_CONFIG1__DISABLE_BARRIER_MEMVIOL_BACKOFF_MASK 0x00008000L |
26106 | #define SQ_CONFIG1__SP_FGCG_REP_OVERRIDE_MASK 0x01000000L |
26107 | #define SQ_CONFIG1__DPMACC_MGCG_OVERRIDE_MASK 0x02000000L |
26108 | #define SQ_CONFIG1__XDLMACC_MGCG_OVERRIDE_MASK 0x04000000L |
26109 | #define SQ_CONFIG1__TRANSMACC_MGCG_OVERRIDE_MASK 0x08000000L |
26110 | #define SQ_CONFIG1__SPMACC_MGCG_OVERRIDE_MASK 0x10000000L |
26111 | #define SQ_CONFIG1__DPMACC_DGEMM2X_MGCG_OVERRIDE_MASK 0x20000000L |
26112 | #define SQ_CONFIG1__DISABLE_SP_VGPR_READ_SKIP_MASK 0x40000000L |
26113 | #define SQ_CONFIG1__SP_SRC_1ST_BUFFER_MGCG_OVERRIDE_MASK 0x80000000L |
26114 | //SQ_CMD |
26115 | #define SQ_CMD__CMD__SHIFT 0x0 |
26116 | #define SQ_CMD__MODE__SHIFT 0x4 |
26117 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 |
26118 | #define SQ_CMD__DATA__SHIFT 0x8 |
26119 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 |
26120 | #define SQ_CMD__SIMD_ID__SHIFT 0x14 |
26121 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 |
26122 | #define SQ_CMD__VM_ID__SHIFT 0x1c |
26123 | #define SQ_CMD__CMD_MASK 0x00000007L |
26124 | #define SQ_CMD__MODE_MASK 0x00000070L |
26125 | #define SQ_CMD__CHECK_VMID_MASK 0x00000080L |
26126 | #define SQ_CMD__DATA_MASK 0x00000F00L |
26127 | #define SQ_CMD__WAVE_ID_MASK 0x000F0000L |
26128 | #define SQ_CMD__SIMD_ID_MASK 0x00300000L |
26129 | #define SQ_CMD__QUEUE_ID_MASK 0x07000000L |
26130 | #define SQ_CMD__VM_ID_MASK 0xF0000000L |
26131 | //SQ_TIME_HI |
26132 | #define SQ_TIME_HI__TIME__SHIFT 0x0 |
26133 | #define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL |
26134 | //SQ_TIME_LO |
26135 | #define SQ_TIME_LO__TIME__SHIFT 0x0 |
26136 | #define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL |
26137 | //SQ_DS_0 |
26138 | #define SQ_DS_0__OFFSET0__SHIFT 0x0 |
26139 | #define SQ_DS_0__OFFSET1__SHIFT 0x8 |
26140 | #define SQ_DS_0__GDS__SHIFT 0x10 |
26141 | #define SQ_DS_0__OP__SHIFT 0x11 |
26142 | #define SQ_DS_0__ACC__SHIFT 0x19 |
26143 | #define SQ_DS_0__ENCODING__SHIFT 0x1a |
26144 | #define SQ_DS_0__OFFSET0_MASK 0x000000FFL |
26145 | #define SQ_DS_0__OFFSET1_MASK 0x0000FF00L |
26146 | #define SQ_DS_0__GDS_MASK 0x00010000L |
26147 | #define SQ_DS_0__OP_MASK 0x01FE0000L |
26148 | #define SQ_DS_0__ACC_MASK 0x02000000L |
26149 | #define SQ_DS_0__ENCODING_MASK 0xFC000000L |
26150 | //SQ_DS_1 |
26151 | #define SQ_DS_1__ADDR__SHIFT 0x0 |
26152 | #define SQ_DS_1__DATA0__SHIFT 0x8 |
26153 | #define SQ_DS_1__DATA1__SHIFT 0x10 |
26154 | #define SQ_DS_1__VDST__SHIFT 0x18 |
26155 | #define SQ_DS_1__ADDR_MASK 0x000000FFL |
26156 | #define SQ_DS_1__DATA0_MASK 0x0000FF00L |
26157 | #define SQ_DS_1__DATA1_MASK 0x00FF0000L |
26158 | #define SQ_DS_1__VDST_MASK 0xFF000000L |
26159 | //SQ_EXP_0 |
26160 | #define SQ_EXP_0__EN__SHIFT 0x0 |
26161 | #define SQ_EXP_0__TGT__SHIFT 0x4 |
26162 | #define SQ_EXP_0__COMPR__SHIFT 0xa |
26163 | #define SQ_EXP_0__DONE__SHIFT 0xb |
26164 | #define SQ_EXP_0__VM__SHIFT 0xc |
26165 | #define SQ_EXP_0__ENCODING__SHIFT 0x1a |
26166 | #define SQ_EXP_0__EN_MASK 0x0000000FL |
26167 | #define SQ_EXP_0__TGT_MASK 0x000003F0L |
26168 | #define SQ_EXP_0__COMPR_MASK 0x00000400L |
26169 | #define SQ_EXP_0__DONE_MASK 0x00000800L |
26170 | #define SQ_EXP_0__VM_MASK 0x00001000L |
26171 | #define SQ_EXP_0__ENCODING_MASK 0xFC000000L |
26172 | //SQ_EXP_1 |
26173 | #define SQ_EXP_1__VSRC0__SHIFT 0x0 |
26174 | #define SQ_EXP_1__VSRC1__SHIFT 0x8 |
26175 | #define SQ_EXP_1__VSRC2__SHIFT 0x10 |
26176 | #define SQ_EXP_1__VSRC3__SHIFT 0x18 |
26177 | #define SQ_EXP_1__VSRC0_MASK 0x000000FFL |
26178 | #define SQ_EXP_1__VSRC1_MASK 0x0000FF00L |
26179 | #define SQ_EXP_1__VSRC2_MASK 0x00FF0000L |
26180 | #define SQ_EXP_1__VSRC3_MASK 0xFF000000L |
26181 | //SQ_FLAT_0 |
26182 | #define SQ_FLAT_0__OFFSET__SHIFT 0x0 |
26183 | #define SQ_FLAT_0__LDS__SHIFT 0xd |
26184 | #define SQ_FLAT_0__SEG__SHIFT 0xe |
26185 | #define SQ_FLAT_0__GLC__SHIFT 0x10 |
26186 | #define SQ_FLAT_0__SLC__SHIFT 0x11 |
26187 | #define SQ_FLAT_0__OP__SHIFT 0x12 |
26188 | #define SQ_FLAT_0__SCC__SHIFT 0x19 |
26189 | #define SQ_FLAT_0__ENCODING__SHIFT 0x1a |
26190 | #define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL |
26191 | #define SQ_FLAT_0__LDS_MASK 0x00002000L |
26192 | #define SQ_FLAT_0__SEG_MASK 0x0000C000L |
26193 | #define SQ_FLAT_0__GLC_MASK 0x00010000L |
26194 | #define SQ_FLAT_0__SLC_MASK 0x00020000L |
26195 | #define SQ_FLAT_0__OP_MASK 0x01FC0000L |
26196 | #define SQ_FLAT_0__SCC_MASK 0x02000000L |
26197 | #define SQ_FLAT_0__ENCODING_MASK 0xFC000000L |
26198 | //SQ_FLAT_1 |
26199 | #define SQ_FLAT_1__ADDR__SHIFT 0x0 |
26200 | #define SQ_FLAT_1__DATA__SHIFT 0x8 |
26201 | #define SQ_FLAT_1__SADDR__SHIFT 0x10 |
26202 | #define SQ_FLAT_1__ACC__SHIFT 0x17 |
26203 | #define SQ_FLAT_1__VDST__SHIFT 0x18 |
26204 | #define SQ_FLAT_1__ADDR_MASK 0x000000FFL |
26205 | #define SQ_FLAT_1__DATA_MASK 0x0000FF00L |
26206 | #define SQ_FLAT_1__SADDR_MASK 0x007F0000L |
26207 | #define SQ_FLAT_1__ACC_MASK 0x00800000L |
26208 | #define SQ_FLAT_1__VDST_MASK 0xFF000000L |
26209 | //SQ_GLBL_0 |
26210 | #define SQ_GLBL_0__OFFSET__SHIFT 0x0 |
26211 | #define SQ_GLBL_0__LDS__SHIFT 0xd |
26212 | #define SQ_GLBL_0__SEG__SHIFT 0xe |
26213 | #define SQ_GLBL_0__GLC__SHIFT 0x10 |
26214 | #define SQ_GLBL_0__SLC__SHIFT 0x11 |
26215 | #define SQ_GLBL_0__OP__SHIFT 0x12 |
26216 | #define SQ_GLBL_0__SCC__SHIFT 0x19 |
26217 | #define SQ_GLBL_0__ENCODING__SHIFT 0x1a |
26218 | #define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL |
26219 | #define SQ_GLBL_0__LDS_MASK 0x00002000L |
26220 | #define SQ_GLBL_0__SEG_MASK 0x0000C000L |
26221 | #define SQ_GLBL_0__GLC_MASK 0x00010000L |
26222 | #define SQ_GLBL_0__SLC_MASK 0x00020000L |
26223 | #define SQ_GLBL_0__OP_MASK 0x01FC0000L |
26224 | #define SQ_GLBL_0__SCC_MASK 0x02000000L |
26225 | #define SQ_GLBL_0__ENCODING_MASK 0xFC000000L |
26226 | //SQ_GLBL_1 |
26227 | #define SQ_GLBL_1__ADDR__SHIFT 0x0 |
26228 | #define SQ_GLBL_1__DATA__SHIFT 0x8 |
26229 | #define SQ_GLBL_1__SADDR__SHIFT 0x10 |
26230 | #define SQ_GLBL_1__ACC__SHIFT 0x17 |
26231 | #define SQ_GLBL_1__VDST__SHIFT 0x18 |
26232 | #define SQ_GLBL_1__ADDR_MASK 0x000000FFL |
26233 | #define SQ_GLBL_1__DATA_MASK 0x0000FF00L |
26234 | #define SQ_GLBL_1__SADDR_MASK 0x007F0000L |
26235 | #define SQ_GLBL_1__ACC_MASK 0x00800000L |
26236 | #define SQ_GLBL_1__VDST_MASK 0xFF000000L |
26237 | //SQ_INST |
26238 | #define SQ_INST__ENCODING__SHIFT 0x0 |
26239 | #define SQ_INST__ENCODING_MASK 0xFFFFFFFFL |
26240 | //SQ_MIMG_0 |
26241 | #define SQ_MIMG_0__OPM__SHIFT 0x0 |
26242 | #define SQ_MIMG_0__SCC__SHIFT 0x7 |
26243 | #define SQ_MIMG_0__DMASK__SHIFT 0x8 |
26244 | #define SQ_MIMG_0__UNORM__SHIFT 0xc |
26245 | #define SQ_MIMG_0__GLC__SHIFT 0xd |
26246 | #define SQ_MIMG_0__DA__SHIFT 0xe |
26247 | #define SQ_MIMG_0__A16__SHIFT 0xf |
26248 | #define SQ_MIMG_0__ACC__SHIFT 0x10 |
26249 | #define SQ_MIMG_0__LWE__SHIFT 0x11 |
26250 | #define SQ_MIMG_0__OP__SHIFT 0x12 |
26251 | #define SQ_MIMG_0__SLC__SHIFT 0x19 |
26252 | #define SQ_MIMG_0__ENCODING__SHIFT 0x1a |
26253 | #define SQ_MIMG_0__OPM_MASK 0x00000001L |
26254 | #define SQ_MIMG_0__SCC_MASK 0x00000080L |
26255 | #define SQ_MIMG_0__DMASK_MASK 0x00000F00L |
26256 | #define SQ_MIMG_0__UNORM_MASK 0x00001000L |
26257 | #define SQ_MIMG_0__GLC_MASK 0x00002000L |
26258 | #define SQ_MIMG_0__DA_MASK 0x00004000L |
26259 | #define SQ_MIMG_0__A16_MASK 0x00008000L |
26260 | #define SQ_MIMG_0__ACC_MASK 0x00010000L |
26261 | #define SQ_MIMG_0__LWE_MASK 0x00020000L |
26262 | #define SQ_MIMG_0__OP_MASK 0x01FC0000L |
26263 | #define SQ_MIMG_0__SLC_MASK 0x02000000L |
26264 | #define SQ_MIMG_0__ENCODING_MASK 0xFC000000L |
26265 | //SQ_MIMG_1 |
26266 | #define SQ_MIMG_1__VADDR__SHIFT 0x0 |
26267 | #define SQ_MIMG_1__VDATA__SHIFT 0x8 |
26268 | #define SQ_MIMG_1__SRSRC__SHIFT 0x10 |
26269 | #define SQ_MIMG_1__SSAMP__SHIFT 0x15 |
26270 | #define SQ_MIMG_1__D16__SHIFT 0x1f |
26271 | #define SQ_MIMG_1__VADDR_MASK 0x000000FFL |
26272 | #define SQ_MIMG_1__VDATA_MASK 0x0000FF00L |
26273 | #define SQ_MIMG_1__SRSRC_MASK 0x001F0000L |
26274 | #define SQ_MIMG_1__SSAMP_MASK 0x03E00000L |
26275 | #define SQ_MIMG_1__D16_MASK 0x80000000L |
26276 | //SQ_MTBUF_0 |
26277 | #define SQ_MTBUF_0__OFFSET__SHIFT 0x0 |
26278 | #define SQ_MTBUF_0__OFFEN__SHIFT 0xc |
26279 | #define SQ_MTBUF_0__IDXEN__SHIFT 0xd |
26280 | #define SQ_MTBUF_0__GLC__SHIFT 0xe |
26281 | #define SQ_MTBUF_0__OP__SHIFT 0xf |
26282 | #define SQ_MTBUF_0__DFMT__SHIFT 0x13 |
26283 | #define SQ_MTBUF_0__NFMT__SHIFT 0x17 |
26284 | #define SQ_MTBUF_0__ENCODING__SHIFT 0x1a |
26285 | #define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL |
26286 | #define SQ_MTBUF_0__OFFEN_MASK 0x00001000L |
26287 | #define SQ_MTBUF_0__IDXEN_MASK 0x00002000L |
26288 | #define SQ_MTBUF_0__GLC_MASK 0x00004000L |
26289 | #define SQ_MTBUF_0__OP_MASK 0x00078000L |
26290 | #define SQ_MTBUF_0__DFMT_MASK 0x00780000L |
26291 | #define SQ_MTBUF_0__NFMT_MASK 0x03800000L |
26292 | #define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L |
26293 | //SQ_MTBUF_1 |
26294 | #define SQ_MTBUF_1__VADDR__SHIFT 0x0 |
26295 | #define SQ_MTBUF_1__VDATA__SHIFT 0x8 |
26296 | #define SQ_MTBUF_1__SRSRC__SHIFT 0x10 |
26297 | #define SQ_MTBUF_1__SCC__SHIFT 0x15 |
26298 | #define SQ_MTBUF_1__SLC__SHIFT 0x16 |
26299 | #define SQ_MTBUF_1__ACC__SHIFT 0x17 |
26300 | #define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 |
26301 | #define SQ_MTBUF_1__VADDR_MASK 0x000000FFL |
26302 | #define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L |
26303 | #define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L |
26304 | #define SQ_MTBUF_1__SCC_MASK 0x00200000L |
26305 | #define SQ_MTBUF_1__SLC_MASK 0x00400000L |
26306 | #define SQ_MTBUF_1__ACC_MASK 0x00800000L |
26307 | #define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L |
26308 | //SQ_MUBUF_0 |
26309 | #define SQ_MUBUF_0__OFFSET__SHIFT 0x0 |
26310 | #define SQ_MUBUF_0__OFFEN__SHIFT 0xc |
26311 | #define SQ_MUBUF_0__IDXEN__SHIFT 0xd |
26312 | #define SQ_MUBUF_0__GLC__SHIFT 0xe |
26313 | #define SQ_MUBUF_0__SCC__SHIFT 0xf |
26314 | #define SQ_MUBUF_0__LDS__SHIFT 0x10 |
26315 | #define SQ_MUBUF_0__SLC__SHIFT 0x11 |
26316 | #define SQ_MUBUF_0__OP__SHIFT 0x12 |
26317 | #define SQ_MUBUF_0__ENCODING__SHIFT 0x1a |
26318 | #define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL |
26319 | #define SQ_MUBUF_0__OFFEN_MASK 0x00001000L |
26320 | #define SQ_MUBUF_0__IDXEN_MASK 0x00002000L |
26321 | #define SQ_MUBUF_0__GLC_MASK 0x00004000L |
26322 | #define SQ_MUBUF_0__SCC_MASK 0x00008000L |
26323 | #define SQ_MUBUF_0__LDS_MASK 0x00010000L |
26324 | #define SQ_MUBUF_0__SLC_MASK 0x00020000L |
26325 | #define SQ_MUBUF_0__OP_MASK 0x01FC0000L |
26326 | #define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L |
26327 | //SQ_MUBUF_1 |
26328 | #define SQ_MUBUF_1__VADDR__SHIFT 0x0 |
26329 | #define SQ_MUBUF_1__VDATA__SHIFT 0x8 |
26330 | #define SQ_MUBUF_1__SRSRC__SHIFT 0x10 |
26331 | #define SQ_MUBUF_1__ACC__SHIFT 0x17 |
26332 | #define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 |
26333 | #define SQ_MUBUF_1__VADDR_MASK 0x000000FFL |
26334 | #define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L |
26335 | #define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L |
26336 | #define SQ_MUBUF_1__ACC_MASK 0x00800000L |
26337 | #define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L |
26338 | //SQ_SCRATCH_0 |
26339 | #define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 |
26340 | #define SQ_SCRATCH_0__LDS__SHIFT 0xd |
26341 | #define SQ_SCRATCH_0__SEG__SHIFT 0xe |
26342 | #define SQ_SCRATCH_0__GLC__SHIFT 0x10 |
26343 | #define SQ_SCRATCH_0__SLC__SHIFT 0x11 |
26344 | #define SQ_SCRATCH_0__OP__SHIFT 0x12 |
26345 | #define SQ_SCRATCH_0__SCC__SHIFT 0x19 |
26346 | #define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a |
26347 | #define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL |
26348 | #define SQ_SCRATCH_0__LDS_MASK 0x00002000L |
26349 | #define SQ_SCRATCH_0__SEG_MASK 0x0000C000L |
26350 | #define SQ_SCRATCH_0__GLC_MASK 0x00010000L |
26351 | #define SQ_SCRATCH_0__SLC_MASK 0x00020000L |
26352 | #define SQ_SCRATCH_0__OP_MASK 0x01FC0000L |
26353 | #define SQ_SCRATCH_0__SCC_MASK 0x02000000L |
26354 | #define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L |
26355 | //SQ_SCRATCH_1 |
26356 | #define SQ_SCRATCH_1__ADDR__SHIFT 0x0 |
26357 | #define SQ_SCRATCH_1__DATA__SHIFT 0x8 |
26358 | #define SQ_SCRATCH_1__SADDR__SHIFT 0x10 |
26359 | #define SQ_SCRATCH_1__ACC__SHIFT 0x17 |
26360 | #define SQ_SCRATCH_1__VDST__SHIFT 0x18 |
26361 | #define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL |
26362 | #define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L |
26363 | #define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L |
26364 | #define SQ_SCRATCH_1__ACC_MASK 0x00800000L |
26365 | #define SQ_SCRATCH_1__VDST_MASK 0xFF000000L |
26366 | //SQ_SMEM_0 |
26367 | #define SQ_SMEM_0__SBASE__SHIFT 0x0 |
26368 | #define SQ_SMEM_0__SDATA__SHIFT 0x6 |
26369 | #define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe |
26370 | #define SQ_SMEM_0__NV__SHIFT 0xf |
26371 | #define SQ_SMEM_0__GLC__SHIFT 0x10 |
26372 | #define SQ_SMEM_0__IMM__SHIFT 0x11 |
26373 | #define SQ_SMEM_0__OP__SHIFT 0x12 |
26374 | #define SQ_SMEM_0__ENCODING__SHIFT 0x1a |
26375 | #define SQ_SMEM_0__SBASE_MASK 0x0000003FL |
26376 | #define SQ_SMEM_0__SDATA_MASK 0x00001FC0L |
26377 | #define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L |
26378 | #define SQ_SMEM_0__NV_MASK 0x00008000L |
26379 | #define SQ_SMEM_0__GLC_MASK 0x00010000L |
26380 | #define SQ_SMEM_0__IMM_MASK 0x00020000L |
26381 | #define SQ_SMEM_0__OP_MASK 0x03FC0000L |
26382 | #define SQ_SMEM_0__ENCODING_MASK 0xFC000000L |
26383 | //SQ_SMEM_1 |
26384 | #define SQ_SMEM_1__OFFSET__SHIFT 0x0 |
26385 | #define SQ_SMEM_1__SOFFSET__SHIFT 0x19 |
26386 | #define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL |
26387 | #define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L |
26388 | //SQ_SOP1 |
26389 | #define SQ_SOP1__SSRC0__SHIFT 0x0 |
26390 | #define SQ_SOP1__OP__SHIFT 0x8 |
26391 | #define SQ_SOP1__SDST__SHIFT 0x10 |
26392 | #define SQ_SOP1__ENCODING__SHIFT 0x17 |
26393 | #define SQ_SOP1__SSRC0_MASK 0x000000FFL |
26394 | #define SQ_SOP1__OP_MASK 0x0000FF00L |
26395 | #define SQ_SOP1__SDST_MASK 0x007F0000L |
26396 | #define SQ_SOP1__ENCODING_MASK 0xFF800000L |
26397 | //SQ_SOP2 |
26398 | #define SQ_SOP2__SSRC0__SHIFT 0x0 |
26399 | #define SQ_SOP2__SSRC1__SHIFT 0x8 |
26400 | #define SQ_SOP2__SDST__SHIFT 0x10 |
26401 | #define SQ_SOP2__OP__SHIFT 0x17 |
26402 | #define SQ_SOP2__ENCODING__SHIFT 0x1e |
26403 | #define SQ_SOP2__SSRC0_MASK 0x000000FFL |
26404 | #define SQ_SOP2__SSRC1_MASK 0x0000FF00L |
26405 | #define SQ_SOP2__SDST_MASK 0x007F0000L |
26406 | #define SQ_SOP2__OP_MASK 0x3F800000L |
26407 | #define SQ_SOP2__ENCODING_MASK 0xC0000000L |
26408 | //SQ_SOPC |
26409 | #define SQ_SOPC__SSRC0__SHIFT 0x0 |
26410 | #define SQ_SOPC__SSRC1__SHIFT 0x8 |
26411 | #define SQ_SOPC__OP__SHIFT 0x10 |
26412 | #define SQ_SOPC__ENCODING__SHIFT 0x17 |
26413 | #define SQ_SOPC__SSRC0_MASK 0x000000FFL |
26414 | #define SQ_SOPC__SSRC1_MASK 0x0000FF00L |
26415 | #define SQ_SOPC__OP_MASK 0x007F0000L |
26416 | #define SQ_SOPC__ENCODING_MASK 0xFF800000L |
26417 | //SQ_SOPK |
26418 | #define SQ_SOPK__SIMM16__SHIFT 0x0 |
26419 | #define SQ_SOPK__SDST__SHIFT 0x10 |
26420 | #define SQ_SOPK__OP__SHIFT 0x17 |
26421 | #define SQ_SOPK__ENCODING__SHIFT 0x1c |
26422 | #define SQ_SOPK__SIMM16_MASK 0x0000FFFFL |
26423 | #define SQ_SOPK__SDST_MASK 0x007F0000L |
26424 | #define SQ_SOPK__OP_MASK 0x0F800000L |
26425 | #define SQ_SOPK__ENCODING_MASK 0xF0000000L |
26426 | //SQ_SOPP |
26427 | #define SQ_SOPP__SIMM16__SHIFT 0x0 |
26428 | #define SQ_SOPP__OP__SHIFT 0x10 |
26429 | #define SQ_SOPP__ENCODING__SHIFT 0x17 |
26430 | #define SQ_SOPP__SIMM16_MASK 0x0000FFFFL |
26431 | #define SQ_SOPP__OP_MASK 0x007F0000L |
26432 | #define SQ_SOPP__ENCODING_MASK 0xFF800000L |
26433 | //SQ_VINTRP |
26434 | #define SQ_VINTRP__VSRC__SHIFT 0x0 |
26435 | #define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 |
26436 | #define SQ_VINTRP__ATTR__SHIFT 0xa |
26437 | #define SQ_VINTRP__OP__SHIFT 0x10 |
26438 | #define SQ_VINTRP__VDST__SHIFT 0x12 |
26439 | #define SQ_VINTRP__ENCODING__SHIFT 0x1a |
26440 | #define SQ_VINTRP__VSRC_MASK 0x000000FFL |
26441 | #define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L |
26442 | #define SQ_VINTRP__ATTR_MASK 0x0000FC00L |
26443 | #define SQ_VINTRP__OP_MASK 0x00030000L |
26444 | #define SQ_VINTRP__VDST_MASK 0x03FC0000L |
26445 | #define SQ_VINTRP__ENCODING_MASK 0xFC000000L |
26446 | //SQ_VOP1 |
26447 | #define SQ_VOP1__SRC0__SHIFT 0x0 |
26448 | #define SQ_VOP1__OP__SHIFT 0x9 |
26449 | #define SQ_VOP1__VDST__SHIFT 0x11 |
26450 | #define SQ_VOP1__ENCODING__SHIFT 0x19 |
26451 | #define SQ_VOP1__SRC0_MASK 0x000001FFL |
26452 | #define SQ_VOP1__OP_MASK 0x0001FE00L |
26453 | #define SQ_VOP1__VDST_MASK 0x01FE0000L |
26454 | #define SQ_VOP1__ENCODING_MASK 0xFE000000L |
26455 | //SQ_VOP2 |
26456 | #define SQ_VOP2__SRC0__SHIFT 0x0 |
26457 | #define SQ_VOP2__VSRC1__SHIFT 0x9 |
26458 | #define SQ_VOP2__VDST__SHIFT 0x11 |
26459 | #define SQ_VOP2__OP__SHIFT 0x19 |
26460 | #define SQ_VOP2__ENCODING__SHIFT 0x1f |
26461 | #define SQ_VOP2__SRC0_MASK 0x000001FFL |
26462 | #define SQ_VOP2__VSRC1_MASK 0x0001FE00L |
26463 | #define SQ_VOP2__VDST_MASK 0x01FE0000L |
26464 | #define SQ_VOP2__OP_MASK 0x7E000000L |
26465 | #define SQ_VOP2__ENCODING_MASK 0x80000000L |
26466 | //SQ_VOP3P_0 |
26467 | #define SQ_VOP3P_0__VDST__SHIFT 0x0 |
26468 | #define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 |
26469 | #define SQ_VOP3P_0__OP_SEL__SHIFT 0xb |
26470 | #define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe |
26471 | #define SQ_VOP3P_0__CLAMP__SHIFT 0xf |
26472 | #define SQ_VOP3P_0__OP__SHIFT 0x10 |
26473 | #define SQ_VOP3P_0__ENCODING__SHIFT 0x17 |
26474 | #define SQ_VOP3P_0__VDST_MASK 0x000000FFL |
26475 | #define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L |
26476 | #define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L |
26477 | #define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L |
26478 | #define SQ_VOP3P_0__CLAMP_MASK 0x00008000L |
26479 | #define SQ_VOP3P_0__OP_MASK 0x007F0000L |
26480 | #define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L |
26481 | //SQ_VOP3P_1 |
26482 | #define SQ_VOP3P_1__SRC0__SHIFT 0x0 |
26483 | #define SQ_VOP3P_1__SRC1__SHIFT 0x9 |
26484 | #define SQ_VOP3P_1__SRC2__SHIFT 0x12 |
26485 | #define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b |
26486 | #define SQ_VOP3P_1__NEG__SHIFT 0x1d |
26487 | #define SQ_VOP3P_1__SRC0_MASK 0x000001FFL |
26488 | #define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L |
26489 | #define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L |
26490 | #define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L |
26491 | #define SQ_VOP3P_1__NEG_MASK 0xE0000000L |
26492 | //SQ_VOP3P_MFMA_0 |
26493 | #define SQ_VOP3P_MFMA_0__VDST__SHIFT 0x0 |
26494 | #define SQ_VOP3P_MFMA_0__CBSZ__SHIFT 0x8 |
26495 | #define SQ_VOP3P_MFMA_0__ABID__SHIFT 0xb |
26496 | #define SQ_VOP3P_MFMA_0__ACC_CD__SHIFT 0xf |
26497 | #define SQ_VOP3P_MFMA_0__OP__SHIFT 0x10 |
26498 | #define SQ_VOP3P_MFMA_0__ENCODING__SHIFT 0x17 |
26499 | #define SQ_VOP3P_MFMA_0__VDST_MASK 0x000000FFL |
26500 | #define SQ_VOP3P_MFMA_0__CBSZ_MASK 0x00000700L |
26501 | #define SQ_VOP3P_MFMA_0__ABID_MASK 0x00007800L |
26502 | #define SQ_VOP3P_MFMA_0__ACC_CD_MASK 0x00008000L |
26503 | #define SQ_VOP3P_MFMA_0__OP_MASK 0x007F0000L |
26504 | #define SQ_VOP3P_MFMA_0__ENCODING_MASK 0xFF800000L |
26505 | //SQ_VOP3P_MFMA_1 |
26506 | #define SQ_VOP3P_MFMA_1__SRC0__SHIFT 0x0 |
26507 | #define SQ_VOP3P_MFMA_1__SRC1__SHIFT 0x9 |
26508 | #define SQ_VOP3P_MFMA_1__SRC2__SHIFT 0x12 |
26509 | #define SQ_VOP3P_MFMA_1__ACC__SHIFT 0x1b |
26510 | #define SQ_VOP3P_MFMA_1__BLGP__SHIFT 0x1d |
26511 | #define SQ_VOP3P_MFMA_1__SRC0_MASK 0x000001FFL |
26512 | #define SQ_VOP3P_MFMA_1__SRC1_MASK 0x0003FE00L |
26513 | #define SQ_VOP3P_MFMA_1__SRC2_MASK 0x07FC0000L |
26514 | #define SQ_VOP3P_MFMA_1__ACC_MASK 0x18000000L |
26515 | #define SQ_VOP3P_MFMA_1__BLGP_MASK 0xE0000000L |
26516 | //SQ_VOP3_0 |
26517 | #define SQ_VOP3_0__VDST__SHIFT 0x0 |
26518 | #define SQ_VOP3_0__ABS__SHIFT 0x8 |
26519 | #define SQ_VOP3_0__OP_SEL__SHIFT 0xb |
26520 | #define SQ_VOP3_0__CLAMP__SHIFT 0xf |
26521 | #define SQ_VOP3_0__OP__SHIFT 0x10 |
26522 | #define SQ_VOP3_0__ENCODING__SHIFT 0x1a |
26523 | #define SQ_VOP3_0__VDST_MASK 0x000000FFL |
26524 | #define SQ_VOP3_0__ABS_MASK 0x00000700L |
26525 | #define SQ_VOP3_0__OP_SEL_MASK 0x00007800L |
26526 | #define SQ_VOP3_0__CLAMP_MASK 0x00008000L |
26527 | #define SQ_VOP3_0__OP_MASK 0x03FF0000L |
26528 | #define SQ_VOP3_0__ENCODING_MASK 0xFC000000L |
26529 | //SQ_VOP3_0_SDST_ENC |
26530 | #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 |
26531 | #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 |
26532 | #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf |
26533 | #define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 |
26534 | #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a |
26535 | #define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL |
26536 | #define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L |
26537 | #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L |
26538 | #define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L |
26539 | #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L |
26540 | //SQ_VOP3_1 |
26541 | #define SQ_VOP3_1__SRC0__SHIFT 0x0 |
26542 | #define SQ_VOP3_1__SRC1__SHIFT 0x9 |
26543 | #define SQ_VOP3_1__SRC2__SHIFT 0x12 |
26544 | #define SQ_VOP3_1__OMOD__SHIFT 0x1b |
26545 | #define SQ_VOP3_1__NEG__SHIFT 0x1d |
26546 | #define SQ_VOP3_1__SRC0_MASK 0x000001FFL |
26547 | #define SQ_VOP3_1__SRC1_MASK 0x0003FE00L |
26548 | #define SQ_VOP3_1__SRC2_MASK 0x07FC0000L |
26549 | #define SQ_VOP3_1__OMOD_MASK 0x18000000L |
26550 | #define SQ_VOP3_1__NEG_MASK 0xE0000000L |
26551 | //SQ_VOPC |
26552 | #define SQ_VOPC__SRC0__SHIFT 0x0 |
26553 | #define SQ_VOPC__VSRC1__SHIFT 0x9 |
26554 | #define SQ_VOPC__OP__SHIFT 0x11 |
26555 | #define SQ_VOPC__ENCODING__SHIFT 0x19 |
26556 | #define SQ_VOPC__SRC0_MASK 0x000001FFL |
26557 | #define SQ_VOPC__VSRC1_MASK 0x0001FE00L |
26558 | #define SQ_VOPC__OP_MASK 0x01FE0000L |
26559 | #define SQ_VOPC__ENCODING_MASK 0xFE000000L |
26560 | //SQ_VOP_DPP |
26561 | #define SQ_VOP_DPP__SRC0__SHIFT 0x0 |
26562 | #define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 |
26563 | #define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 |
26564 | #define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 |
26565 | #define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 |
26566 | #define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 |
26567 | #define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 |
26568 | #define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 |
26569 | #define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c |
26570 | #define SQ_VOP_DPP__SRC0_MASK 0x000000FFL |
26571 | #define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L |
26572 | #define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L |
26573 | #define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L |
26574 | #define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L |
26575 | #define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L |
26576 | #define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L |
26577 | #define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L |
26578 | #define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L |
26579 | //SQ_VOP_SDWA |
26580 | #define SQ_VOP_SDWA__SRC0__SHIFT 0x0 |
26581 | #define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 |
26582 | #define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb |
26583 | #define SQ_VOP_SDWA__CLAMP__SHIFT 0xd |
26584 | #define SQ_VOP_SDWA__OMOD__SHIFT 0xe |
26585 | #define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 |
26586 | #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 |
26587 | #define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 |
26588 | #define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 |
26589 | #define SQ_VOP_SDWA__S0__SHIFT 0x17 |
26590 | #define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 |
26591 | #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b |
26592 | #define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c |
26593 | #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d |
26594 | #define SQ_VOP_SDWA__S1__SHIFT 0x1f |
26595 | #define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL |
26596 | #define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L |
26597 | #define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L |
26598 | #define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L |
26599 | #define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L |
26600 | #define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L |
26601 | #define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L |
26602 | #define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L |
26603 | #define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L |
26604 | #define SQ_VOP_SDWA__S0_MASK 0x00800000L |
26605 | #define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L |
26606 | #define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L |
26607 | #define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L |
26608 | #define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L |
26609 | #define SQ_VOP_SDWA__S1_MASK 0x80000000L |
26610 | //SQ_VOP_SDWA_SDST_ENC |
26611 | #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 |
26612 | #define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 |
26613 | #define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf |
26614 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 |
26615 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 |
26616 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 |
26617 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 |
26618 | #define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 |
26619 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 |
26620 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b |
26621 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c |
26622 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d |
26623 | #define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f |
26624 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL |
26625 | #define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L |
26626 | #define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L |
26627 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L |
26628 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L |
26629 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L |
26630 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L |
26631 | #define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L |
26632 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L |
26633 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L |
26634 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L |
26635 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L |
26636 | #define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L |
26637 | //SQ_LB_CTR_CTRL |
26638 | #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 |
26639 | #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
26640 | #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
26641 | #define SQ_LB_CTR_CTRL__START_MASK 0x00000001L |
26642 | #define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
26643 | #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
26644 | //SQ_LB_DATA0 |
26645 | #define SQ_LB_DATA0__DATA__SHIFT 0x0 |
26646 | #define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
26647 | //SQ_LB_DATA1 |
26648 | #define SQ_LB_DATA1__DATA__SHIFT 0x0 |
26649 | #define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
26650 | //SQ_LB_DATA2 |
26651 | #define SQ_LB_DATA2__DATA__SHIFT 0x0 |
26652 | #define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
26653 | //SQ_LB_DATA3 |
26654 | #define SQ_LB_DATA3__DATA__SHIFT 0x0 |
26655 | #define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
26656 | //SQ_LB_CTR_SEL |
26657 | #define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 |
26658 | #define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 |
26659 | #define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 |
26660 | #define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc |
26661 | #define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL |
26662 | #define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L |
26663 | #define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L |
26664 | #define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L |
26665 | //SQ_LB_CTR0_CU |
26666 | #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 |
26667 | #define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 |
26668 | #define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL |
26669 | #define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L |
26670 | //SQ_LB_CTR1_CU |
26671 | #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 |
26672 | #define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 |
26673 | #define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL |
26674 | #define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L |
26675 | //SQ_LB_CTR2_CU |
26676 | #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 |
26677 | #define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 |
26678 | #define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL |
26679 | #define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L |
26680 | //SQ_LB_CTR3_CU |
26681 | #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 |
26682 | #define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 |
26683 | #define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL |
26684 | #define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L |
26685 | //SQC_EDC_CNT |
26686 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 |
26687 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 |
26688 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 |
26689 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 |
26690 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 |
26691 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa |
26692 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc |
26693 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe |
26694 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 |
26695 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 |
26696 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 |
26697 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 |
26698 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 |
26699 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a |
26700 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c |
26701 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e |
26702 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L |
26703 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL |
26704 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L |
26705 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L |
26706 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L |
26707 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L |
26708 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L |
26709 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L |
26710 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L |
26711 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L |
26712 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L |
26713 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L |
26714 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L |
26715 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L |
26716 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L |
26717 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L |
26718 | //SQ_EDC_SEC_CNT |
26719 | #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 |
26720 | #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 |
26721 | #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 |
26722 | #define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL |
26723 | #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L |
26724 | #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L |
26725 | //SQ_EDC_DED_CNT |
26726 | #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 |
26727 | #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 |
26728 | #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 |
26729 | #define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL |
26730 | #define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L |
26731 | #define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L |
26732 | //SQ_EDC_INFO |
26733 | #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 |
26734 | #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 |
26735 | #define SQ_EDC_INFO__SOURCE__SHIFT 0x6 |
26736 | #define SQ_EDC_INFO__VM_ID__SHIFT 0x9 |
26737 | #define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL |
26738 | #define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L |
26739 | #define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L |
26740 | #define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L |
26741 | //SQ_EDC_CNT |
26742 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 |
26743 | #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 |
26744 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 |
26745 | #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 |
26746 | #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 |
26747 | #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa |
26748 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc |
26749 | #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe |
26750 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 |
26751 | #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 |
26752 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 |
26753 | #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 |
26754 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 |
26755 | #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a |
26756 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L |
26757 | #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL |
26758 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L |
26759 | #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L |
26760 | #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L |
26761 | #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L |
26762 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L |
26763 | #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L |
26764 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L |
26765 | #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L |
26766 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L |
26767 | #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L |
26768 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L |
26769 | #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L |
26770 | //SQ_EDC_FUE_CNTL |
26771 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
26772 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
26773 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
26774 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
26775 | //SQ_THREAD_TRACE_WORD_CMN |
26776 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 |
26777 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 |
26778 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL |
26779 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L |
26780 | //SQ_THREAD_TRACE_WORD_EVENT |
26781 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 |
26782 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 |
26783 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 |
26784 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 |
26785 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa |
26786 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL |
26787 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L |
26788 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L |
26789 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L |
26790 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L |
26791 | //SQ_THREAD_TRACE_WORD_INST |
26792 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 |
26793 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 |
26794 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 |
26795 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 |
26796 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb |
26797 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL |
26798 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L |
26799 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L |
26800 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L |
26801 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L |
26802 | //SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 |
26803 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26804 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 |
26805 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 |
26806 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 |
26807 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf |
26808 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 |
26809 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26810 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L |
26811 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L |
26812 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L |
26813 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L |
26814 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L |
26815 | //SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 |
26816 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26817 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 |
26818 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 |
26819 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 |
26820 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa |
26821 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe |
26822 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 |
26823 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26824 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L |
26825 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L |
26826 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L |
26827 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L |
26828 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L |
26829 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L |
26830 | //SQ_THREAD_TRACE_WORD_ISSUE |
26831 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 |
26832 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 |
26833 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 |
26834 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 |
26835 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa |
26836 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc |
26837 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe |
26838 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 |
26839 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 |
26840 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 |
26841 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 |
26842 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 |
26843 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a |
26844 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL |
26845 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L |
26846 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L |
26847 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L |
26848 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L |
26849 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L |
26850 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L |
26851 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L |
26852 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L |
26853 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L |
26854 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L |
26855 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L |
26856 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L |
26857 | //SQ_THREAD_TRACE_WORD_MISC |
26858 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 |
26859 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 |
26860 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc |
26861 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd |
26862 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL |
26863 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L |
26864 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L |
26865 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L |
26866 | //SQ_THREAD_TRACE_WORD_PERF_1_OF_2 |
26867 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26868 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 |
26869 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 |
26870 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 |
26871 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa |
26872 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc |
26873 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 |
26874 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26875 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L |
26876 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L |
26877 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L |
26878 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L |
26879 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L |
26880 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L |
26881 | //SQ_THREAD_TRACE_WORD_REG_1_OF_2 |
26882 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26883 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 |
26884 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 |
26885 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 |
26886 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 |
26887 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa |
26888 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe |
26889 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf |
26890 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 |
26891 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26892 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L |
26893 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L |
26894 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L |
26895 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L |
26896 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L |
26897 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L |
26898 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L |
26899 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L |
26900 | //SQ_THREAD_TRACE_WORD_REG_2_OF_2 |
26901 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 |
26902 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL |
26903 | //SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 |
26904 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26905 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 |
26906 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 |
26907 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 |
26908 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 |
26909 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 |
26910 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26911 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L |
26912 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L |
26913 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L |
26914 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L |
26915 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L |
26916 | //SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 |
26917 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 |
26918 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL |
26919 | //SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 |
26920 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
26921 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 |
26922 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
26923 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L |
26924 | //SQ_THREAD_TRACE_WORD_WAVE |
26925 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 |
26926 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 |
26927 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 |
26928 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 |
26929 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa |
26930 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe |
26931 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL |
26932 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L |
26933 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L |
26934 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L |
26935 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L |
26936 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L |
26937 | //SQ_THREAD_TRACE_WORD_WAVE_START |
26938 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 |
26939 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 |
26940 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 |
26941 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 |
26942 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa |
26943 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe |
26944 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 |
26945 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 |
26946 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 |
26947 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d |
26948 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL |
26949 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L |
26950 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L |
26951 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L |
26952 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L |
26953 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L |
26954 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L |
26955 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L |
26956 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L |
26957 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L |
26958 | //SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 |
26959 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 |
26960 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL |
26961 | //SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 |
26962 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 |
26963 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL |
26964 | //SQ_THREAD_TRACE_WORD_PERF_2_OF_2 |
26965 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 |
26966 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 |
26967 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 |
26968 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL |
26969 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L |
26970 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L |
26971 | //SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 |
26972 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 |
26973 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL |
26974 | //SQ_WREXEC_EXEC_HI |
26975 | #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 |
26976 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a |
26977 | #define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b |
26978 | #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c |
26979 | #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f |
26980 | #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL |
26981 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L |
26982 | #define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L |
26983 | #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L |
26984 | #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L |
26985 | //SQ_WREXEC_EXEC_LO |
26986 | #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 |
26987 | #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
26988 | //SQ_BUF_RSRC_WORD0 |
26989 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 |
26990 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL |
26991 | //SQ_BUF_RSRC_WORD1 |
26992 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 |
26993 | #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 |
26994 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e |
26995 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f |
26996 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL |
26997 | #define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L |
26998 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L |
26999 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L |
27000 | //SQ_BUF_RSRC_WORD2 |
27001 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 |
27002 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL |
27003 | //SQ_BUF_RSRC_WORD3 |
27004 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 |
27005 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 |
27006 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 |
27007 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 |
27008 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc |
27009 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf |
27010 | #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 |
27011 | #define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 |
27012 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 |
27013 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 |
27014 | #define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b |
27015 | #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e |
27016 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L |
27017 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L |
27018 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L |
27019 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L |
27020 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L |
27021 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L |
27022 | #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L |
27023 | #define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L |
27024 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L |
27025 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L |
27026 | #define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L |
27027 | #define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L |
27028 | //SQ_IMG_RSRC_WORD0 |
27029 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 |
27030 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL |
27031 | //SQ_IMG_RSRC_WORD1 |
27032 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 |
27033 | #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 |
27034 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 |
27035 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a |
27036 | #define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e |
27037 | #define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f |
27038 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL |
27039 | #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L |
27040 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L |
27041 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L |
27042 | #define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L |
27043 | #define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L |
27044 | //SQ_IMG_RSRC_WORD2 |
27045 | #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 |
27046 | #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe |
27047 | #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c |
27048 | #define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL |
27049 | #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L |
27050 | #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L |
27051 | //SQ_IMG_RSRC_WORD3 |
27052 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 |
27053 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 |
27054 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 |
27055 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 |
27056 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc |
27057 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 |
27058 | #define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 |
27059 | #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c |
27060 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L |
27061 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L |
27062 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L |
27063 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L |
27064 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L |
27065 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L |
27066 | #define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L |
27067 | #define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L |
27068 | //SQ_IMG_RSRC_WORD4 |
27069 | #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 |
27070 | #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd |
27071 | #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d |
27072 | #define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL |
27073 | #define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L |
27074 | #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L |
27075 | //SQ_IMG_RSRC_WORD5 |
27076 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 |
27077 | #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd |
27078 | #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 |
27079 | #define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 |
27080 | #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a |
27081 | #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b |
27082 | #define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c |
27083 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL |
27084 | #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L |
27085 | #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L |
27086 | #define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L |
27087 | #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L |
27088 | #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L |
27089 | #define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L |
27090 | //SQ_IMG_RSRC_WORD6 |
27091 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 |
27092 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc |
27093 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 |
27094 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 |
27095 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 |
27096 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 |
27097 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 |
27098 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c |
27099 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL |
27100 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L |
27101 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L |
27102 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L |
27103 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L |
27104 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L |
27105 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L |
27106 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L |
27107 | //SQ_IMG_RSRC_WORD7 |
27108 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 |
27109 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL |
27110 | //SQ_IMG_SAMP_WORD0 |
27111 | #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 |
27112 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 |
27113 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 |
27114 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 |
27115 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc |
27116 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf |
27117 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 |
27118 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 |
27119 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 |
27120 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 |
27121 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b |
27122 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c |
27123 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d |
27124 | #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L |
27125 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L |
27126 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L |
27127 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L |
27128 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L |
27129 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L |
27130 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L |
27131 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L |
27132 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L |
27133 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L |
27134 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L |
27135 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L |
27136 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L |
27137 | //SQ_IMG_SAMP_WORD1 |
27138 | #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 |
27139 | #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc |
27140 | #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 |
27141 | #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c |
27142 | #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL |
27143 | #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L |
27144 | #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L |
27145 | #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L |
27146 | //SQ_IMG_SAMP_WORD2 |
27147 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 |
27148 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe |
27149 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 |
27150 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 |
27151 | #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 |
27152 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a |
27153 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c |
27154 | #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d |
27155 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e |
27156 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f |
27157 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL |
27158 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L |
27159 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L |
27160 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L |
27161 | #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L |
27162 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L |
27163 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L |
27164 | #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L |
27165 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L |
27166 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L |
27167 | //SQ_IMG_SAMP_WORD3 |
27168 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 |
27169 | #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc |
27170 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e |
27171 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL |
27172 | #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L |
27173 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L |
27174 | //SQ_FLAT_SCRATCH_WORD0 |
27175 | #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 |
27176 | #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL |
27177 | //SQ_FLAT_SCRATCH_WORD1 |
27178 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 |
27179 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL |
27180 | //SQ_M0_GPR_IDX_WORD |
27181 | #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 |
27182 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc |
27183 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd |
27184 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe |
27185 | #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf |
27186 | #define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL |
27187 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L |
27188 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L |
27189 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L |
27190 | #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L |
27191 | //SQC_ICACHE_UTCL1_CNTL1 |
27192 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
27193 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
27194 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
27195 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
27196 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
27197 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
27198 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
27199 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
27200 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
27201 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
27202 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
27203 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
27204 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
27205 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
27206 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
27207 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
27208 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
27209 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
27210 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
27211 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
27212 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
27213 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
27214 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
27215 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
27216 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
27217 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
27218 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
27219 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
27220 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
27221 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
27222 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
27223 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
27224 | //SQC_ICACHE_UTCL1_CNTL2 |
27225 | #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
27226 | #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
27227 | #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
27228 | #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
27229 | #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
27230 | #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
27231 | #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
27232 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
27233 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
27234 | #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
27235 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
27236 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
27237 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
27238 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
27239 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
27240 | #define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
27241 | #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
27242 | #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
27243 | #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
27244 | #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
27245 | #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
27246 | #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
27247 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
27248 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
27249 | #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
27250 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
27251 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
27252 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
27253 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
27254 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
27255 | //SQC_DCACHE_UTCL1_CNTL1 |
27256 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
27257 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
27258 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
27259 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
27260 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
27261 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
27262 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
27263 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
27264 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
27265 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
27266 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
27267 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
27268 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
27269 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
27270 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
27271 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
27272 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
27273 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
27274 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
27275 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
27276 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
27277 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
27278 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
27279 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
27280 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
27281 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
27282 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
27283 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
27284 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
27285 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
27286 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
27287 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
27288 | //SQC_DCACHE_UTCL1_CNTL2 |
27289 | #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
27290 | #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
27291 | #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
27292 | #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
27293 | #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
27294 | #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
27295 | #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
27296 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
27297 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
27298 | #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
27299 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
27300 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
27301 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
27302 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
27303 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
27304 | #define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
27305 | #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
27306 | #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
27307 | #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
27308 | #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
27309 | #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
27310 | #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
27311 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
27312 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
27313 | #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
27314 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
27315 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
27316 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
27317 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
27318 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
27319 | //SQC_ICACHE_UTCL1_STATUS |
27320 | #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
27321 | #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
27322 | #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
27323 | #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
27324 | #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
27325 | #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
27326 | //SQC_DCACHE_UTCL1_STATUS |
27327 | #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
27328 | #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
27329 | #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
27330 | #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
27331 | #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
27332 | #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
27333 | |
27334 | |
27335 | // addressBlock: gc_tcdec |
27336 | //TCP_INVALIDATE |
27337 | #define TCP_INVALIDATE__START__SHIFT 0x0 |
27338 | #define TCP_INVALIDATE__START_MASK 0x00000001L |
27339 | //TCP_STATUS |
27340 | #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 |
27341 | #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 |
27342 | #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 |
27343 | #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 |
27344 | #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 |
27345 | #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 |
27346 | #define TCP_STATUS__READ_BUSY__SHIFT 0x6 |
27347 | #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 |
27348 | #define TCP_STATUS__VM_BUSY__SHIFT 0x8 |
27349 | #define TCP_STATUS__TCP_BUSY_MASK 0x00000001L |
27350 | #define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L |
27351 | #define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L |
27352 | #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L |
27353 | #define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L |
27354 | #define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L |
27355 | #define TCP_STATUS__READ_BUSY_MASK 0x00000040L |
27356 | #define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L |
27357 | #define TCP_STATUS__VM_BUSY_MASK 0x00000100L |
27358 | //TCP_CHAN_STEER_0 |
27359 | #define TCP_CHAN_STEER_0__CHAN0__SHIFT 0x0 |
27360 | #define TCP_CHAN_STEER_0__CHAN1__SHIFT 0x5 |
27361 | #define TCP_CHAN_STEER_0__CHAN2__SHIFT 0xa |
27362 | #define TCP_CHAN_STEER_0__CHAN3__SHIFT 0xf |
27363 | #define TCP_CHAN_STEER_0__CHAN4__SHIFT 0x14 |
27364 | #define TCP_CHAN_STEER_0__CHAN5__SHIFT 0x19 |
27365 | #define TCP_CHAN_STEER_0__CHAN0_MASK 0x0000001FL |
27366 | #define TCP_CHAN_STEER_0__CHAN1_MASK 0x000003E0L |
27367 | #define TCP_CHAN_STEER_0__CHAN2_MASK 0x00007C00L |
27368 | #define TCP_CHAN_STEER_0__CHAN3_MASK 0x000F8000L |
27369 | #define TCP_CHAN_STEER_0__CHAN4_MASK 0x01F00000L |
27370 | #define TCP_CHAN_STEER_0__CHAN5_MASK 0x3E000000L |
27371 | //TCP_CHAN_STEER_1 |
27372 | #define TCP_CHAN_STEER_1__CHAN6__SHIFT 0x0 |
27373 | #define TCP_CHAN_STEER_1__CHAN7__SHIFT 0x5 |
27374 | #define TCP_CHAN_STEER_1__CHAN8__SHIFT 0xa |
27375 | #define TCP_CHAN_STEER_1__CHAN9__SHIFT 0xf |
27376 | #define TCP_CHAN_STEER_1__CHANA__SHIFT 0x14 |
27377 | #define TCP_CHAN_STEER_1__CHAN6_MASK 0x0000001FL |
27378 | #define TCP_CHAN_STEER_1__CHAN7_MASK 0x000003E0L |
27379 | #define TCP_CHAN_STEER_1__CHAN8_MASK 0x00007C00L |
27380 | #define TCP_CHAN_STEER_1__CHAN9_MASK 0x000F8000L |
27381 | #define TCP_CHAN_STEER_1__CHANA_MASK 0x01F00000L |
27382 | //TCP_ADDR_CONFIG |
27383 | #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 |
27384 | #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x5 |
27385 | #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x7 |
27386 | #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0xa |
27387 | #define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT 0xb |
27388 | #define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT 0xc |
27389 | #define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT 0xd |
27390 | #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000001FL |
27391 | #define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000060L |
27392 | #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x00000380L |
27393 | #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000400L |
27394 | #define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK 0x00000800L |
27395 | #define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK 0x00001000L |
27396 | #define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK 0x00002000L |
27397 | //TCP_CHAN_STEER_2 |
27398 | #define TCP_CHAN_STEER_2__CHANC__SHIFT 0x0 |
27399 | #define TCP_CHAN_STEER_2__CHAND__SHIFT 0x5 |
27400 | #define TCP_CHAN_STEER_2__CHANE__SHIFT 0xa |
27401 | #define TCP_CHAN_STEER_2__CHANF__SHIFT 0xf |
27402 | #define TCP_CHAN_STEER_2__CHAN10__SHIFT 0x14 |
27403 | #define TCP_CHAN_STEER_2__CHAN11__SHIFT 0x19 |
27404 | #define TCP_CHAN_STEER_2__CHANC_MASK 0x0000001FL |
27405 | #define TCP_CHAN_STEER_2__CHAND_MASK 0x000003E0L |
27406 | #define TCP_CHAN_STEER_2__CHANE_MASK 0x00007C00L |
27407 | #define TCP_CHAN_STEER_2__CHANF_MASK 0x000F8000L |
27408 | #define TCP_CHAN_STEER_2__CHAN10_MASK 0x01F00000L |
27409 | #define TCP_CHAN_STEER_2__CHAN11_MASK 0x3E000000L |
27410 | //TCP_CHAN_STEER_3 |
27411 | #define TCP_CHAN_STEER_3__CHAN12__SHIFT 0x0 |
27412 | #define TCP_CHAN_STEER_3__CHAN13__SHIFT 0x5 |
27413 | #define TCP_CHAN_STEER_3__CHAN14__SHIFT 0xa |
27414 | #define TCP_CHAN_STEER_3__CHAN15__SHIFT 0xf |
27415 | #define TCP_CHAN_STEER_3__CHAN16__SHIFT 0x14 |
27416 | #define TCP_CHAN_STEER_3__CHAN17__SHIFT 0x19 |
27417 | #define TCP_CHAN_STEER_3__CHAN12_MASK 0x0000001FL |
27418 | #define TCP_CHAN_STEER_3__CHAN13_MASK 0x000003E0L |
27419 | #define TCP_CHAN_STEER_3__CHAN14_MASK 0x00007C00L |
27420 | #define TCP_CHAN_STEER_3__CHAN15_MASK 0x000F8000L |
27421 | #define TCP_CHAN_STEER_3__CHAN16_MASK 0x01F00000L |
27422 | #define TCP_CHAN_STEER_3__CHAN17_MASK 0x3E000000L |
27423 | //TCP_CHAN_STEER_4 |
27424 | #define TCP_CHAN_STEER_4__CHAN18__SHIFT 0x0 |
27425 | #define TCP_CHAN_STEER_4__CHAN19__SHIFT 0x5 |
27426 | #define TCP_CHAN_STEER_4__CHAN1A__SHIFT 0xa |
27427 | #define TCP_CHAN_STEER_4__CHAN1B__SHIFT 0xf |
27428 | #define TCP_CHAN_STEER_4__CHAN1C__SHIFT 0x14 |
27429 | #define TCP_CHAN_STEER_4__CHAN1D__SHIFT 0x19 |
27430 | #define TCP_CHAN_STEER_4__CHAN18_MASK 0x0000001FL |
27431 | #define TCP_CHAN_STEER_4__CHAN19_MASK 0x000003E0L |
27432 | #define TCP_CHAN_STEER_4__CHAN1A_MASK 0x00007C00L |
27433 | #define TCP_CHAN_STEER_4__CHAN1B_MASK 0x000F8000L |
27434 | #define TCP_CHAN_STEER_4__CHAN1C_MASK 0x01F00000L |
27435 | #define TCP_CHAN_STEER_4__CHAN1D_MASK 0x3E000000L |
27436 | //TCP_CHAN_STEER_5 |
27437 | #define TCP_CHAN_STEER_5__CHAN1E__SHIFT 0x0 |
27438 | #define TCP_CHAN_STEER_5__CHAN1F__SHIFT 0x5 |
27439 | #define TCP_CHAN_STEER_5__CHAN1E_MASK 0x0000001FL |
27440 | #define TCP_CHAN_STEER_5__CHAN1F_MASK 0x000003E0L |
27441 | //TCP_EDC_CNT |
27442 | #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 |
27443 | #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 |
27444 | #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 |
27445 | #define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL |
27446 | #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L |
27447 | #define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L |
27448 | //TCP_EDC_CNT_NEW |
27449 | #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0 |
27450 | #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2 |
27451 | #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4 |
27452 | #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6 |
27453 | #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT 0x8 |
27454 | #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT 0xa |
27455 | #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xc |
27456 | #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xe |
27457 | #define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT__SHIFT 0x10 |
27458 | #define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT__SHIFT 0x12 |
27459 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x14 |
27460 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x16 |
27461 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x18 |
27462 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x1a |
27463 | #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L |
27464 | #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL |
27465 | #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L |
27466 | #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L |
27467 | #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK 0x00000300L |
27468 | #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK 0x00000C00L |
27469 | #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00003000L |
27470 | #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x0000C000L |
27471 | #define TCP_EDC_CNT_NEW__DB_RAM_SEC_COUNT_MASK 0x00030000L |
27472 | #define TCP_EDC_CNT_NEW__DB_RAM_DED_COUNT_MASK 0x000C0000L |
27473 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00300000L |
27474 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x00C00000L |
27475 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x03000000L |
27476 | #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x0C000000L |
27477 | //TC_CFG_L1_LOAD_POLICY0 |
27478 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 |
27479 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 |
27480 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 |
27481 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 |
27482 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 |
27483 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa |
27484 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc |
27485 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe |
27486 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 |
27487 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 |
27488 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 |
27489 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 |
27490 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 |
27491 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a |
27492 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c |
27493 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e |
27494 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L |
27495 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL |
27496 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L |
27497 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L |
27498 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L |
27499 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L |
27500 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L |
27501 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L |
27502 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L |
27503 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L |
27504 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L |
27505 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L |
27506 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L |
27507 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L |
27508 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L |
27509 | #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L |
27510 | //TC_CFG_L1_LOAD_POLICY1 |
27511 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 |
27512 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 |
27513 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 |
27514 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 |
27515 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 |
27516 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa |
27517 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc |
27518 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe |
27519 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 |
27520 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 |
27521 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 |
27522 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 |
27523 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 |
27524 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a |
27525 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c |
27526 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e |
27527 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L |
27528 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL |
27529 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L |
27530 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L |
27531 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L |
27532 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L |
27533 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L |
27534 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L |
27535 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L |
27536 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L |
27537 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L |
27538 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L |
27539 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L |
27540 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L |
27541 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L |
27542 | #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L |
27543 | //TC_CFG_L1_STORE_POLICY |
27544 | #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 |
27545 | #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 |
27546 | #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 |
27547 | #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 |
27548 | #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 |
27549 | #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 |
27550 | #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 |
27551 | #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 |
27552 | #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 |
27553 | #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 |
27554 | #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa |
27555 | #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb |
27556 | #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc |
27557 | #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd |
27558 | #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe |
27559 | #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf |
27560 | #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 |
27561 | #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 |
27562 | #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 |
27563 | #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 |
27564 | #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 |
27565 | #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 |
27566 | #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 |
27567 | #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 |
27568 | #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 |
27569 | #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 |
27570 | #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a |
27571 | #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b |
27572 | #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c |
27573 | #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d |
27574 | #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e |
27575 | #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f |
27576 | #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L |
27577 | #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L |
27578 | #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L |
27579 | #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L |
27580 | #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L |
27581 | #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L |
27582 | #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L |
27583 | #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L |
27584 | #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L |
27585 | #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L |
27586 | #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L |
27587 | #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L |
27588 | #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L |
27589 | #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L |
27590 | #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L |
27591 | #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L |
27592 | #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L |
27593 | #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L |
27594 | #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L |
27595 | #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L |
27596 | #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L |
27597 | #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L |
27598 | #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L |
27599 | #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L |
27600 | #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L |
27601 | #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L |
27602 | #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L |
27603 | #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L |
27604 | #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L |
27605 | #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L |
27606 | #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L |
27607 | #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L |
27608 | //TC_CFG_L2_LOAD_POLICY0 |
27609 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 |
27610 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 |
27611 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 |
27612 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 |
27613 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 |
27614 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa |
27615 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc |
27616 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe |
27617 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 |
27618 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 |
27619 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 |
27620 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 |
27621 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 |
27622 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a |
27623 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c |
27624 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e |
27625 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L |
27626 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL |
27627 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L |
27628 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L |
27629 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L |
27630 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L |
27631 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L |
27632 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L |
27633 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L |
27634 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L |
27635 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L |
27636 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L |
27637 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L |
27638 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L |
27639 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L |
27640 | #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L |
27641 | //TC_CFG_L2_LOAD_POLICY1 |
27642 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 |
27643 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 |
27644 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 |
27645 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 |
27646 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 |
27647 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa |
27648 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc |
27649 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe |
27650 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 |
27651 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 |
27652 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 |
27653 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 |
27654 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 |
27655 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a |
27656 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c |
27657 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e |
27658 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L |
27659 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL |
27660 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L |
27661 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L |
27662 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L |
27663 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L |
27664 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L |
27665 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L |
27666 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L |
27667 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L |
27668 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L |
27669 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L |
27670 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L |
27671 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L |
27672 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L |
27673 | #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L |
27674 | //TC_CFG_L2_STORE_POLICY0 |
27675 | #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 |
27676 | #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 |
27677 | #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 |
27678 | #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 |
27679 | #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 |
27680 | #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa |
27681 | #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc |
27682 | #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe |
27683 | #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 |
27684 | #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 |
27685 | #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 |
27686 | #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 |
27687 | #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 |
27688 | #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a |
27689 | #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c |
27690 | #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e |
27691 | #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L |
27692 | #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL |
27693 | #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L |
27694 | #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L |
27695 | #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L |
27696 | #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L |
27697 | #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L |
27698 | #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L |
27699 | #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L |
27700 | #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L |
27701 | #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L |
27702 | #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L |
27703 | #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L |
27704 | #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L |
27705 | #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L |
27706 | #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L |
27707 | //TC_CFG_L2_STORE_POLICY1 |
27708 | #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 |
27709 | #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 |
27710 | #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 |
27711 | #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 |
27712 | #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 |
27713 | #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa |
27714 | #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc |
27715 | #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe |
27716 | #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 |
27717 | #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 |
27718 | #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 |
27719 | #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 |
27720 | #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 |
27721 | #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a |
27722 | #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c |
27723 | #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e |
27724 | #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L |
27725 | #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL |
27726 | #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L |
27727 | #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L |
27728 | #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L |
27729 | #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L |
27730 | #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L |
27731 | #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L |
27732 | #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L |
27733 | #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L |
27734 | #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L |
27735 | #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L |
27736 | #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L |
27737 | #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L |
27738 | #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L |
27739 | #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L |
27740 | //TC_CFG_L2_ATOMIC_POLICY |
27741 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 |
27742 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 |
27743 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 |
27744 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 |
27745 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 |
27746 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa |
27747 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc |
27748 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe |
27749 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 |
27750 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 |
27751 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 |
27752 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 |
27753 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 |
27754 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a |
27755 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c |
27756 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e |
27757 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L |
27758 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL |
27759 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L |
27760 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L |
27761 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L |
27762 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L |
27763 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L |
27764 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L |
27765 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L |
27766 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L |
27767 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L |
27768 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L |
27769 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L |
27770 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L |
27771 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L |
27772 | #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L |
27773 | //TC_CFG_L1_VOLATILE |
27774 | #define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 |
27775 | #define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL |
27776 | //TC_CFG_L2_VOLATILE |
27777 | #define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 |
27778 | #define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL |
27779 | //TCI_MISC |
27780 | #define TCI_MISC__FGCG_REPEATER_DISABLE__SHIFT 0x0 |
27781 | #define TCI_MISC__LEGACY_MGCG_DISABLE__SHIFT 0x1 |
27782 | #define TCI_MISC__FGCG_REPEATER_DISABLE_MASK 0x00000001L |
27783 | #define TCI_MISC__LEGACY_MGCG_DISABLE_MASK 0x00000002L |
27784 | //TCI_CNTL_3 |
27785 | #define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH__SHIFT 0x0 |
27786 | #define TCI_CNTL_3__COMBINING_DELAY_WINDOW__SHIFT 0x2 |
27787 | #define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG__SHIFT 0x4 |
27788 | #define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE__SHIFT 0x7 |
27789 | #define TCI_CNTL_3__DISABLE_DOUBLING_L2_BANDWIDTH_MASK 0x00000003L |
27790 | #define TCI_CNTL_3__COMBINING_DELAY_WINDOW_MASK 0x0000000CL |
27791 | #define TCI_CNTL_3__CHICKEN_BIT_TCR_MGCG_MASK 0x00000070L |
27792 | #define TCI_CNTL_3__TCR_FGCG_REPEATER_DISABLE_MASK 0x00000080L |
27793 | //TCI_DSM_CNTL |
27794 | #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 |
27795 | #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
27796 | #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L |
27797 | #define TCI_DSM_CNTL__WRITE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
27798 | //TCI_DSM_CNTL2 |
27799 | #define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
27800 | #define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
27801 | #define TCI_DSM_CNTL2__TCI_INJECT_DELAY__SHIFT 0x1a |
27802 | #define TCI_DSM_CNTL2__WRITE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
27803 | #define TCI_DSM_CNTL2__WRITE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
27804 | #define TCI_DSM_CNTL2__TCI_INJECT_DELAY_MASK 0xFC000000L |
27805 | //TCI_EDC_CNT |
27806 | #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT 0x0 |
27807 | #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT 0x2 |
27808 | #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK 0x00000003L |
27809 | #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK 0x0000000CL |
27810 | //TCI_STATUS |
27811 | #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 |
27812 | #define TCI_STATUS__TCI_BUSY_MASK 0x00000001L |
27813 | //TCI_CNTL_1 |
27814 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 |
27815 | #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 |
27816 | #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 |
27817 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL |
27818 | #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L |
27819 | #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L |
27820 | //TCI_CNTL_2 |
27821 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 |
27822 | #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 |
27823 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L |
27824 | #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL |
27825 | //TCC_CTRL |
27826 | #define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 |
27827 | #define TCC_CTRL__RATE__SHIFT 0x2 |
27828 | #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 |
27829 | #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc |
27830 | #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 |
27831 | #define TCC_CTRL__OUTPUT_FIFO_CLK_MODE__SHIFT 0x16 |
27832 | #define TCC_CTRL__EXECUTE_CLK_MODE__SHIFT 0x17 |
27833 | #define TCC_CTRL__RETURN_BUFFER_CLK_MODE__SHIFT 0x19 |
27834 | #define TCC_CTRL__SRC_FIFO_CLK_MODE__SHIFT 0x1a |
27835 | #define TCC_CTRL__MC_WRITE_CLK_MODE__SHIFT 0x1b |
27836 | #define TCC_CTRL__LATENCY_FIFO_CLK_MODE__SHIFT 0x1c |
27837 | #define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L |
27838 | #define TCC_CTRL__RATE_MASK 0x0000000CL |
27839 | #define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L |
27840 | #define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L |
27841 | #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L |
27842 | #define TCC_CTRL__OUTPUT_FIFO_CLK_MODE_MASK 0x00400000L |
27843 | #define TCC_CTRL__EXECUTE_CLK_MODE_MASK 0x01800000L |
27844 | #define TCC_CTRL__RETURN_BUFFER_CLK_MODE_MASK 0x02000000L |
27845 | #define TCC_CTRL__SRC_FIFO_CLK_MODE_MASK 0x04000000L |
27846 | #define TCC_CTRL__MC_WRITE_CLK_MODE_MASK 0x08000000L |
27847 | #define TCC_CTRL__LATENCY_FIFO_CLK_MODE_MASK 0x10000000L |
27848 | //TCC_CTRL2 |
27849 | #define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 |
27850 | #define TCC_CTRL2__INF_NAN_CLAMP__SHIFT 0x10 |
27851 | #define TCC_CTRL2__PROBE_FILTER_CTRL__SHIFT 0x11 |
27852 | #define TCC_CTRL2__WAIT_CLK_STABLE_CNT__SHIFT 0x12 |
27853 | #define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE__SHIFT 0x17 |
27854 | #define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE__SHIFT 0x18 |
27855 | #define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE__SHIFT 0x19 |
27856 | #define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE__SHIFT 0x1a |
27857 | #define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE__SHIFT 0x1b |
27858 | #define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE__SHIFT 0x1c |
27859 | #define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x1d |
27860 | #define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL |
27861 | #define TCC_CTRL2__INF_NAN_CLAMP_MASK 0x00010000L |
27862 | #define TCC_CTRL2__PROBE_FILTER_CTRL_MASK 0x00020000L |
27863 | #define TCC_CTRL2__WAIT_CLK_STABLE_CNT_MASK 0x007C0000L |
27864 | #define TCC_CTRL2__TCC_TCX_REPEATER_FGCG_DISABLE_MASK 0x00800000L |
27865 | #define TCC_CTRL2__TCC_EA0_RDREQ_FGCG_DISABLE_MASK 0x01000000L |
27866 | #define TCC_CTRL2__TCC_EA0_WRREQ_FGCG_DISABLE_MASK 0x02000000L |
27867 | #define TCC_CTRL2__TCC_TCX_ACK_REPEATER_FGCG_DISABLE_MASK 0x04000000L |
27868 | #define TCC_CTRL2__TCC_TCA_HOLE_REPEATER_FGCG_DISABLE_MASK 0x08000000L |
27869 | #define TCC_CTRL2__TCC_TCA_RTN_REPEATER_FGCG_DISABLE_MASK 0x10000000L |
27870 | #define TCC_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x20000000L |
27871 | //TCC_EDC_CNT |
27872 | #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 |
27873 | #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 |
27874 | #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 |
27875 | #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 |
27876 | #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 |
27877 | #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa |
27878 | #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc |
27879 | #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe |
27880 | #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 |
27881 | #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 |
27882 | #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14 |
27883 | #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT 0x16 |
27884 | #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT 0x18 |
27885 | #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT 0x1a |
27886 | #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L |
27887 | #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL |
27888 | #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L |
27889 | #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L |
27890 | #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L |
27891 | #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L |
27892 | #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L |
27893 | #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L |
27894 | #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L |
27895 | #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L |
27896 | #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK 0x00300000L |
27897 | #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK 0x00C00000L |
27898 | #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK 0x03000000L |
27899 | #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK 0x0C000000L |
27900 | //TCC_EDC_CNT2 |
27901 | #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT 0x0 |
27902 | #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT 0x2 |
27903 | #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT 0x4 |
27904 | #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT 0x6 |
27905 | #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT 0x8 |
27906 | #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT 0xa |
27907 | #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT 0xc |
27908 | #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT 0xe |
27909 | #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT 0x10 |
27910 | #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT 0x12 |
27911 | #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14 |
27912 | #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT 0x16 |
27913 | #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT 0x18 |
27914 | #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT 0x1a |
27915 | #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT 0x1c |
27916 | #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT 0x1e |
27917 | #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK 0x00000003L |
27918 | #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK 0x0000000CL |
27919 | #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK 0x00000030L |
27920 | #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK 0x000000C0L |
27921 | #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK 0x00000300L |
27922 | #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK 0x00000C00L |
27923 | #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK 0x00003000L |
27924 | #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK 0x0000C000L |
27925 | #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK 0x00030000L |
27926 | #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK 0x000C0000L |
27927 | #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK 0x00300000L |
27928 | #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK 0x00C00000L |
27929 | #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK 0x03000000L |
27930 | #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK 0x0C000000L |
27931 | #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK 0x30000000L |
27932 | #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK 0xC0000000L |
27933 | //TCC_REDUNDANCY |
27934 | #define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 |
27935 | #define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 |
27936 | #define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L |
27937 | #define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L |
27938 | //TCC_EXE_DISABLE |
27939 | #define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 |
27940 | #define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L |
27941 | //TCC_DSM_CNTL |
27942 | #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 |
27943 | #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
27944 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 |
27945 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
27946 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 |
27947 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
27948 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 |
27949 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
27950 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc |
27951 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe |
27952 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf |
27953 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
27954 | #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 |
27955 | #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 |
27956 | #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 |
27957 | #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 |
27958 | #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 |
27959 | #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a |
27960 | #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b |
27961 | #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d |
27962 | #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L |
27963 | #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
27964 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L |
27965 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
27966 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
27967 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
27968 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L |
27969 | #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
27970 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L |
27971 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L |
27972 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L |
27973 | #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
27974 | #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
27975 | #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L |
27976 | #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L |
27977 | #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L |
27978 | #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L |
27979 | #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L |
27980 | #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L |
27981 | #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L |
27982 | //TCC_DSM_CNTLA |
27983 | #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 |
27984 | #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
27985 | #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 |
27986 | #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
27987 | #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 |
27988 | #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
27989 | #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 |
27990 | #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
27991 | #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc |
27992 | #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe |
27993 | #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0xf |
27994 | #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
27995 | #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 |
27996 | #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 |
27997 | #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x15 |
27998 | #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 |
27999 | #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x18 |
28000 | #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a |
28001 | #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL__SHIFT 0x1b |
28002 | #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d |
28003 | #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L |
28004 | #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
28005 | #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L |
28006 | #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
28007 | #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
28008 | #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
28009 | #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L |
28010 | #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
28011 | #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L |
28012 | #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L |
28013 | #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x00018000L |
28014 | #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
28015 | #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
28016 | #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L |
28017 | #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x00600000L |
28018 | #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L |
28019 | #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x03000000L |
28020 | #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L |
28021 | #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_DATA_SEL_MASK 0x18000000L |
28022 | #define TCC_DSM_CNTLA__OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L |
28023 | //TCC_DSM_CNTL2 |
28024 | #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28025 | #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 |
28026 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28027 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 |
28028 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 |
28029 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 |
28030 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 |
28031 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb |
28032 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc |
28033 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe |
28034 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf |
28035 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 |
28036 | #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 |
28037 | #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 |
28038 | #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 |
28039 | #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 |
28040 | #define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
28041 | #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28042 | #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L |
28043 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28044 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L |
28045 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
28046 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L |
28047 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L |
28048 | #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L |
28049 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28050 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L |
28051 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L |
28052 | #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L |
28053 | #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
28054 | #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L |
28055 | #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L |
28056 | #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L |
28057 | #define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
28058 | //TCC_DSM_CNTL2A |
28059 | #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28060 | #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 |
28061 | #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28062 | #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 |
28063 | #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 |
28064 | #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 |
28065 | #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 |
28066 | #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb |
28067 | #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc |
28068 | #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe |
28069 | #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf |
28070 | #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 |
28071 | #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 |
28072 | #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 |
28073 | #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 |
28074 | #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 |
28075 | #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x18 |
28076 | #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1a |
28077 | #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT__SHIFT 0x1b |
28078 | #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY__SHIFT 0x1d |
28079 | #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28080 | #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L |
28081 | #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28082 | #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L |
28083 | #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
28084 | #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L |
28085 | #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L |
28086 | #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L |
28087 | #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28088 | #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L |
28089 | #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L |
28090 | #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L |
28091 | #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
28092 | #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L |
28093 | #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L |
28094 | #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L |
28095 | #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x03000000L |
28096 | #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x04000000L |
28097 | #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_ENABLE_ERROR_INJECT_MASK 0x18000000L |
28098 | #define TCC_DSM_CNTL2A__OUTPUT_FIFOS_SELECT_INJECT_DELAY_MASK 0x20000000L |
28099 | //TCC_DSM_CNTL2B |
28100 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28101 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 |
28102 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28103 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 |
28104 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xc |
28105 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY__SHIFT 0xe |
28106 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL__SHIFT 0xf |
28107 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
28108 | #define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD__SHIFT 0x12 |
28109 | #define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD__SHIFT 0x18 |
28110 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28111 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L |
28112 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28113 | #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L |
28114 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28115 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_SELECT_INJECT_DELAY_MASK 0x00004000L |
28116 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL_MASK 0x00018000L |
28117 | #define TCC_DSM_CNTL2B__WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
28118 | #define TCC_DSM_CNTL2B__RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD_MASK 0x00FC0000L |
28119 | #define TCC_DSM_CNTL2B__RTN_GO_FIFO_BUBBLE_THRESHOLD_MASK 0x1F000000L |
28120 | //TCC_WBINVL2 |
28121 | #define TCC_WBINVL2__DONE__SHIFT 0x4 |
28122 | #define TCC_WBINVL2__DONE_MASK 0x00000010L |
28123 | //TCC_SOFT_RESET |
28124 | #define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 |
28125 | #define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L |
28126 | //TCC_DSM_CNTL3 |
28127 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL__SHIFT 0x0 |
28128 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
28129 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL__SHIFT 0x3 |
28130 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
28131 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL__SHIFT 0x6 |
28132 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
28133 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL__SHIFT 0x9 |
28134 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
28135 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT__SHIFT 0xc |
28136 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY__SHIFT 0xe |
28137 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT__SHIFT 0xf |
28138 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY__SHIFT 0x11 |
28139 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT__SHIFT 0x12 |
28140 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY__SHIFT 0x14 |
28141 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT__SHIFT 0x15 |
28142 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY__SHIFT 0x17 |
28143 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL_MASK 0x00000003L |
28144 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
28145 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL_MASK 0x00000018L |
28146 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
28147 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
28148 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
28149 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL_MASK 0x00000600L |
28150 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
28151 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28152 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY_MASK 0x00004000L |
28153 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT_MASK 0x00018000L |
28154 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY_MASK 0x00020000L |
28155 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
28156 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY_MASK 0x00100000L |
28157 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT_MASK 0x00600000L |
28158 | #define TCC_DSM_CNTL3__CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY_MASK 0x00800000L |
28159 | //TCA_CTRL |
28160 | #define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 |
28161 | #define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 |
28162 | #define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 |
28163 | #define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 |
28164 | #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 |
28165 | #define TCA_CTRL__TCA_TCC_FGCG_DISABLE__SHIFT 0x8 |
28166 | #define TCA_CTRL__TCA_TCA_FGCG_DISABLE__SHIFT 0x9 |
28167 | #define TCA_CTRL__TCA_TCH_FGCG_DISABLE__SHIFT 0xa |
28168 | #define TCA_CTRL__TCA_TCX_FGCG_DISABLE__SHIFT 0xb |
28169 | #define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE__SHIFT 0xc |
28170 | #define TCA_CTRL__RTN_CREDIT_THRESHOLD__SHIFT 0xd |
28171 | #define TCA_CTRL__ACK_CREDIT_THRESHOLD__SHIFT 0x10 |
28172 | #define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL |
28173 | #define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L |
28174 | #define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L |
28175 | #define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L |
28176 | #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L |
28177 | #define TCA_CTRL__TCA_TCC_FGCG_DISABLE_MASK 0x00000100L |
28178 | #define TCA_CTRL__TCA_TCA_FGCG_DISABLE_MASK 0x00000200L |
28179 | #define TCA_CTRL__TCA_TCH_FGCG_DISABLE_MASK 0x00000400L |
28180 | #define TCA_CTRL__TCA_TCX_FGCG_DISABLE_MASK 0x00000800L |
28181 | #define TCA_CTRL__TCA_RANDOM_REVERSE_PRIORITY_ENABLE_MASK 0x00001000L |
28182 | #define TCA_CTRL__RTN_CREDIT_THRESHOLD_MASK 0x0000E000L |
28183 | #define TCA_CTRL__ACK_CREDIT_THRESHOLD_MASK 0x00070000L |
28184 | //TCA_BURST_MASK |
28185 | #define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 |
28186 | #define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
28187 | //TCA_BURST_CTRL |
28188 | #define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 |
28189 | #define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 |
28190 | #define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 |
28191 | #define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 |
28192 | #define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 |
28193 | #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa |
28194 | #define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb |
28195 | #define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc |
28196 | #define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd |
28197 | #define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L |
28198 | #define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L |
28199 | #define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L |
28200 | #define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L |
28201 | #define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L |
28202 | #define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L |
28203 | #define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L |
28204 | #define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L |
28205 | #define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L |
28206 | //TCA_DSM_CNTL |
28207 | #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 |
28208 | #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
28209 | #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 |
28210 | #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
28211 | #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L |
28212 | #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
28213 | #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L |
28214 | #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
28215 | //TCA_DSM_CNTL2 |
28216 | #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28217 | #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 |
28218 | #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28219 | #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 |
28220 | #define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
28221 | #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28222 | #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L |
28223 | #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28224 | #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L |
28225 | #define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
28226 | //TCA_EDC_CNT |
28227 | #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT 0x0 |
28228 | #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT 0x2 |
28229 | #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT 0x4 |
28230 | #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT 0x6 |
28231 | #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK 0x00000003L |
28232 | #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK 0x0000000CL |
28233 | #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK 0x00000030L |
28234 | #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK 0x000000C0L |
28235 | //TCX_CTRL |
28236 | #define TCX_CTRL__TCX_TCX_FGCG_DISABLE__SHIFT 0x0 |
28237 | #define TCX_CTRL__TCX_TCR_FGCG_DISABLE__SHIFT 0x1 |
28238 | #define TCX_CTRL__TCX_TCC_FGCG_DISABLE__SHIFT 0x2 |
28239 | #define TCX_CTRL__TCX_TCX_FGCG_DISABLE_MASK 0x00000001L |
28240 | #define TCX_CTRL__TCX_TCR_FGCG_DISABLE_MASK 0x00000002L |
28241 | #define TCX_CTRL__TCX_TCC_FGCG_DISABLE_MASK 0x00000004L |
28242 | //TCX_DSM_CNTL |
28243 | #define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 |
28244 | #define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL__SHIFT 0x2 |
28245 | #define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL__SHIFT 0x4 |
28246 | #define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL__SHIFT 0x6 |
28247 | #define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL__SHIFT 0x8 |
28248 | #define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL__SHIFT 0xa |
28249 | #define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL__SHIFT 0xc |
28250 | #define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL__SHIFT 0xe |
28251 | #define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL__SHIFT 0x10 |
28252 | #define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL__SHIFT 0x12 |
28253 | #define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL__SHIFT 0x14 |
28254 | #define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL__SHIFT 0x16 |
28255 | #define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL__SHIFT 0x18 |
28256 | #define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL__SHIFT 0x1a |
28257 | #define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL__SHIFT 0x1c |
28258 | #define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x1e |
28259 | #define TCX_DSM_CNTL__GROUP0_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L |
28260 | #define TCX_DSM_CNTL__GROUP1_SED_IRRITATOR_DATA_SEL_MASK 0x0000000CL |
28261 | #define TCX_DSM_CNTL__GROUP2_SED_IRRITATOR_DATA_SEL_MASK 0x00000030L |
28262 | #define TCX_DSM_CNTL__GROUP3_SED_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
28263 | #define TCX_DSM_CNTL__GROUP4_SED_IRRITATOR_DATA_SEL_MASK 0x00000300L |
28264 | #define TCX_DSM_CNTL__GROUP5_SED_IRRITATOR_DATA_SEL_MASK 0x00000C00L |
28265 | #define TCX_DSM_CNTL__GROUP6_SED_IRRITATOR_DATA_SEL_MASK 0x00003000L |
28266 | #define TCX_DSM_CNTL__GROUP7_SED_IRRITATOR_DATA_SEL_MASK 0x0000C000L |
28267 | #define TCX_DSM_CNTL__GROUP8_SED_IRRITATOR_DATA_SEL_MASK 0x00030000L |
28268 | #define TCX_DSM_CNTL__GROUP9_SED_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
28269 | #define TCX_DSM_CNTL__GROUP10_SED_IRRITATOR_DATA_SEL_MASK 0x00300000L |
28270 | #define TCX_DSM_CNTL__GROUP11_SED_IRRITATOR_DATA_SEL_MASK 0x00C00000L |
28271 | #define TCX_DSM_CNTL__GROUP12_SED_IRRITATOR_DATA_SEL_MASK 0x03000000L |
28272 | #define TCX_DSM_CNTL__GROUP13_SED_IRRITATOR_DATA_SEL_MASK 0x0C000000L |
28273 | #define TCX_DSM_CNTL__GROUP14_SED_IRRITATOR_DATA_SEL_MASK 0x30000000L |
28274 | #define TCX_DSM_CNTL__SED_IRRITATOR_SINGLE_WRITE_MASK 0x40000000L |
28275 | //TCX_DSM_CNTL2 |
28276 | #define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28277 | #define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY__SHIFT 0x2 |
28278 | #define TCX_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
28279 | #define TCX_DSM_CNTL2__SED_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28280 | #define TCX_DSM_CNTL2__SED_SELECT_INJECT_DELAY_MASK 0x00000004L |
28281 | #define TCX_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
28282 | //TCX_EDC_CNT |
28283 | #define TCX_EDC_CNT__GROUP0_SEC_COUNT__SHIFT 0x0 |
28284 | #define TCX_EDC_CNT__GROUP0_DED_COUNT__SHIFT 0x2 |
28285 | #define TCX_EDC_CNT__GROUP1_SEC_COUNT__SHIFT 0x4 |
28286 | #define TCX_EDC_CNT__GROUP1_DED_COUNT__SHIFT 0x6 |
28287 | #define TCX_EDC_CNT__GROUP2_SEC_COUNT__SHIFT 0x8 |
28288 | #define TCX_EDC_CNT__GROUP2_DED_COUNT__SHIFT 0xa |
28289 | #define TCX_EDC_CNT__GROUP3_SEC_COUNT__SHIFT 0xc |
28290 | #define TCX_EDC_CNT__GROUP3_DED_COUNT__SHIFT 0xe |
28291 | #define TCX_EDC_CNT__GROUP4_SEC_COUNT__SHIFT 0x10 |
28292 | #define TCX_EDC_CNT__GROUP4_DED_COUNT__SHIFT 0x12 |
28293 | #define TCX_EDC_CNT__GROUP5_SED_COUNT__SHIFT 0x14 |
28294 | #define TCX_EDC_CNT__GROUP6_SED_COUNT__SHIFT 0x16 |
28295 | #define TCX_EDC_CNT__GROUP7_SED_COUNT__SHIFT 0x18 |
28296 | #define TCX_EDC_CNT__GROUP8_SED_COUNT__SHIFT 0x1a |
28297 | #define TCX_EDC_CNT__GROUP9_SED_COUNT__SHIFT 0x1c |
28298 | #define TCX_EDC_CNT__GROUP10_SED_COUNT__SHIFT 0x1e |
28299 | #define TCX_EDC_CNT__GROUP0_SEC_COUNT_MASK 0x00000003L |
28300 | #define TCX_EDC_CNT__GROUP0_DED_COUNT_MASK 0x0000000CL |
28301 | #define TCX_EDC_CNT__GROUP1_SEC_COUNT_MASK 0x00000030L |
28302 | #define TCX_EDC_CNT__GROUP1_DED_COUNT_MASK 0x000000C0L |
28303 | #define TCX_EDC_CNT__GROUP2_SEC_COUNT_MASK 0x00000300L |
28304 | #define TCX_EDC_CNT__GROUP2_DED_COUNT_MASK 0x00000C00L |
28305 | #define TCX_EDC_CNT__GROUP3_SEC_COUNT_MASK 0x00003000L |
28306 | #define TCX_EDC_CNT__GROUP3_DED_COUNT_MASK 0x0000C000L |
28307 | #define TCX_EDC_CNT__GROUP4_SEC_COUNT_MASK 0x00030000L |
28308 | #define TCX_EDC_CNT__GROUP4_DED_COUNT_MASK 0x000C0000L |
28309 | #define TCX_EDC_CNT__GROUP5_SED_COUNT_MASK 0x00300000L |
28310 | #define TCX_EDC_CNT__GROUP6_SED_COUNT_MASK 0x00C00000L |
28311 | #define TCX_EDC_CNT__GROUP7_SED_COUNT_MASK 0x03000000L |
28312 | #define TCX_EDC_CNT__GROUP8_SED_COUNT_MASK 0x0C000000L |
28313 | #define TCX_EDC_CNT__GROUP9_SED_COUNT_MASK 0x30000000L |
28314 | #define TCX_EDC_CNT__GROUP10_SED_COUNT_MASK 0xC0000000L |
28315 | //TCX_EDC_CNT2 |
28316 | #define TCX_EDC_CNT2__GROUP11_SED_COUNT__SHIFT 0x0 |
28317 | #define TCX_EDC_CNT2__GROUP12_SED_COUNT__SHIFT 0x2 |
28318 | #define TCX_EDC_CNT2__GROUP13_SED_COUNT__SHIFT 0x4 |
28319 | #define TCX_EDC_CNT2__GROUP14_SED_COUNT__SHIFT 0x6 |
28320 | #define TCX_EDC_CNT2__GROUP11_SED_COUNT_MASK 0x00000003L |
28321 | #define TCX_EDC_CNT2__GROUP12_SED_COUNT_MASK 0x0000000CL |
28322 | #define TCX_EDC_CNT2__GROUP13_SED_COUNT_MASK 0x00000030L |
28323 | #define TCX_EDC_CNT2__GROUP14_SED_COUNT_MASK 0x000000C0L |
28324 | |
28325 | |
28326 | // addressBlock: gc_tcpdec |
28327 | //TCP_WATCH0_ADDR_H |
28328 | #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
28329 | #define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
28330 | //TCP_WATCH0_ADDR_L |
28331 | #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 |
28332 | #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
28333 | //TCP_WATCH0_CNTL |
28334 | #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 |
28335 | #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 |
28336 | #define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c |
28337 | #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d |
28338 | #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f |
28339 | #define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL |
28340 | #define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L |
28341 | #define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L |
28342 | #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L |
28343 | #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L |
28344 | //TCP_WATCH1_ADDR_H |
28345 | #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
28346 | #define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
28347 | //TCP_WATCH1_ADDR_L |
28348 | #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 |
28349 | #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
28350 | //TCP_WATCH1_CNTL |
28351 | #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 |
28352 | #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 |
28353 | #define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c |
28354 | #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d |
28355 | #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f |
28356 | #define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL |
28357 | #define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L |
28358 | #define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L |
28359 | #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L |
28360 | #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L |
28361 | //TCP_WATCH2_ADDR_H |
28362 | #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
28363 | #define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
28364 | //TCP_WATCH2_ADDR_L |
28365 | #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 |
28366 | #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
28367 | //TCP_WATCH2_CNTL |
28368 | #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 |
28369 | #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 |
28370 | #define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c |
28371 | #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d |
28372 | #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f |
28373 | #define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL |
28374 | #define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L |
28375 | #define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L |
28376 | #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L |
28377 | #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L |
28378 | //TCP_WATCH3_ADDR_H |
28379 | #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
28380 | #define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
28381 | //TCP_WATCH3_ADDR_L |
28382 | #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 |
28383 | #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
28384 | //TCP_WATCH3_CNTL |
28385 | #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 |
28386 | #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 |
28387 | #define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c |
28388 | #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d |
28389 | #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f |
28390 | #define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL |
28391 | #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L |
28392 | #define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L |
28393 | #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L |
28394 | #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L |
28395 | //TCP_GATCL1_CNTL |
28396 | #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 |
28397 | #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a |
28398 | #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b |
28399 | #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
28400 | #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
28401 | #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L |
28402 | #define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L |
28403 | #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L |
28404 | #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
28405 | #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
28406 | //TCP_ATC_EDC_GATCL1_CNT |
28407 | #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 |
28408 | #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL |
28409 | //TCP_GATCL1_DSM_CNTL |
28410 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 |
28411 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 |
28412 | #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 |
28413 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L |
28414 | #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L |
28415 | #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L |
28416 | //TCP_DSM_CNTL |
28417 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 |
28418 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 |
28419 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 |
28420 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 |
28421 | #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x6 |
28422 | #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 |
28423 | #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x9 |
28424 | #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0xb |
28425 | #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc |
28426 | #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe |
28427 | #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL__SHIFT 0xf |
28428 | #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 |
28429 | #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL__SHIFT 0x12 |
28430 | #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 |
28431 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x00000003L |
28432 | #define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L |
28433 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x00000018L |
28434 | #define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L |
28435 | #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_DATA_SEL_MASK 0x000000C0L |
28436 | #define TCP_DSM_CNTL__CMD_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L |
28437 | #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000600L |
28438 | #define TCP_DSM_CNTL__VM_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L |
28439 | #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L |
28440 | #define TCP_DSM_CNTL__DB_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L |
28441 | #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_DATA_SEL_MASK 0x00018000L |
28442 | #define TCP_DSM_CNTL__UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L |
28443 | #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_DATA_SEL_MASK 0x000C0000L |
28444 | #define TCP_DSM_CNTL__UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L |
28445 | //TCP_UTCL1_CNTL1 |
28446 | #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
28447 | #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 |
28448 | #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
28449 | #define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
28450 | #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
28451 | #define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
28452 | #define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE__SHIFT 0x10 |
28453 | #define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
28454 | #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
28455 | #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
28456 | #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
28457 | #define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
28458 | #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
28459 | #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
28460 | #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
28461 | #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L |
28462 | #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
28463 | #define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
28464 | #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
28465 | #define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
28466 | #define TCP_UTCL1_CNTL1__UTCL1_FGCG_REPEATER_DISABLE_MASK 0x00010000L |
28467 | #define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
28468 | #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
28469 | #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
28470 | #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
28471 | #define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
28472 | #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
28473 | #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
28474 | //TCP_UTCL1_CNTL2 |
28475 | #define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
28476 | #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
28477 | #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa |
28478 | #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
28479 | #define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
28480 | #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
28481 | #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
28482 | #define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
28483 | #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
28484 | #define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L |
28485 | #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
28486 | #define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
28487 | #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
28488 | #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
28489 | //TCP_UTCL1_STATUS |
28490 | #define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
28491 | #define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
28492 | #define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
28493 | #define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
28494 | #define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
28495 | #define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
28496 | //TCP_DSM_CNTL2 |
28497 | #define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28498 | #define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
28499 | #define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28500 | #define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 |
28501 | #define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
28502 | #define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
28503 | #define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 |
28504 | #define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY__SHIFT 0xb |
28505 | #define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
28506 | #define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
28507 | #define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT__SHIFT 0xf |
28508 | #define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY__SHIFT 0x11 |
28509 | #define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT__SHIFT 0x12 |
28510 | #define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY__SHIFT 0x14 |
28511 | #define TCP_DSM_CNTL2__TCP_INJECT_DELAY__SHIFT 0x1a |
28512 | #define TCP_DSM_CNTL2__CACHE_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28513 | #define TCP_DSM_CNTL2__CACHE_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
28514 | #define TCP_DSM_CNTL2__LFIFO_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28515 | #define TCP_DSM_CNTL2__LFIFO_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L |
28516 | #define TCP_DSM_CNTL2__CMD_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
28517 | #define TCP_DSM_CNTL2__CMD_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
28518 | #define TCP_DSM_CNTL2__VM_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L |
28519 | #define TCP_DSM_CNTL2__VM_FIFO_SELECT_INJECT_DELAY_MASK 0x00000800L |
28520 | #define TCP_DSM_CNTL2__DB_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28521 | #define TCP_DSM_CNTL2__DB_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
28522 | #define TCP_DSM_CNTL2__UTCL1_LFIFO0_ENABLE_ERROR_INJECT_MASK 0x00018000L |
28523 | #define TCP_DSM_CNTL2__UTCL1_LFIFO0_SELECT_INJECT_DELAY_MASK 0x00020000L |
28524 | #define TCP_DSM_CNTL2__UTCL1_LFIFO1_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
28525 | #define TCP_DSM_CNTL2__UTCL1_LFIFO1_SELECT_INJECT_DELAY_MASK 0x00100000L |
28526 | #define TCP_DSM_CNTL2__TCP_INJECT_DELAY_MASK 0xFC000000L |
28527 | //TCP_PERFCOUNTER_FILTER |
28528 | #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 |
28529 | #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 |
28530 | #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 |
28531 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 |
28532 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb |
28533 | #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf |
28534 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 |
28535 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 |
28536 | #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 |
28537 | #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a |
28538 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b |
28539 | #define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c |
28540 | #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L |
28541 | #define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L |
28542 | #define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL |
28543 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L |
28544 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L |
28545 | #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L |
28546 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L |
28547 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L |
28548 | #define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L |
28549 | #define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L |
28550 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L |
28551 | #define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L |
28552 | //TCP_PERFCOUNTER_FILTER_EN |
28553 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 |
28554 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 |
28555 | #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 |
28556 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 |
28557 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 |
28558 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 |
28559 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 |
28560 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 |
28561 | #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 |
28562 | #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 |
28563 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa |
28564 | #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb |
28565 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L |
28566 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L |
28567 | #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L |
28568 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L |
28569 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L |
28570 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L |
28571 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L |
28572 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L |
28573 | #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L |
28574 | #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L |
28575 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L |
28576 | #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L |
28577 | |
28578 | |
28579 | // addressBlock: gc_tpdec |
28580 | //TD_STATUS |
28581 | #define TD_STATUS__BUSY__SHIFT 0x1f |
28582 | #define TD_STATUS__BUSY_MASK 0x80000000L |
28583 | //TD_EDC_CNT |
28584 | #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0 |
28585 | #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2 |
28586 | #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4 |
28587 | #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6 |
28588 | #define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT 0x8 |
28589 | #define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT 0xa |
28590 | #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L |
28591 | #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL |
28592 | #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L |
28593 | #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L |
28594 | #define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK 0x00000300L |
28595 | #define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK 0x00000C00L |
28596 | //TD_DSM_CNTL |
28597 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
28598 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
28599 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 |
28600 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
28601 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
28602 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
28603 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
28604 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
28605 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L |
28606 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
28607 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
28608 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
28609 | //TD_DSM_CNTL2 |
28610 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28611 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 |
28612 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 |
28613 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 |
28614 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
28615 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
28616 | #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a |
28617 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28618 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L |
28619 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L |
28620 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L |
28621 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
28622 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
28623 | #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L |
28624 | //TD_SCRATCH |
28625 | #define TD_SCRATCH__SCRATCH__SHIFT 0x0 |
28626 | #define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
28627 | //TA_CNTL |
28628 | #define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 |
28629 | #define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 |
28630 | #define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd |
28631 | #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 |
28632 | #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 |
28633 | #define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL |
28634 | #define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L |
28635 | #define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L |
28636 | #define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L |
28637 | #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L |
28638 | //TA_CNTL_AUX |
28639 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 |
28640 | #define TA_CNTL_AUX__RESERVED__SHIFT 0x1 |
28641 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 |
28642 | #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 |
28643 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 |
28644 | #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 |
28645 | #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa |
28646 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc |
28647 | #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd |
28648 | #define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe |
28649 | #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf |
28650 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 |
28651 | #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 |
28652 | #define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 |
28653 | #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 |
28654 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 |
28655 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 |
28656 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 |
28657 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 |
28658 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 |
28659 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 |
28660 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a |
28661 | #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b |
28662 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c |
28663 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d |
28664 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e |
28665 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L |
28666 | #define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL |
28667 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L |
28668 | #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L |
28669 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L |
28670 | #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L |
28671 | #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L |
28672 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L |
28673 | #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L |
28674 | #define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L |
28675 | #define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L |
28676 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L |
28677 | #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L |
28678 | #define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L |
28679 | #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L |
28680 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L |
28681 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L |
28682 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L |
28683 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L |
28684 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L |
28685 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L |
28686 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L |
28687 | #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L |
28688 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L |
28689 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L |
28690 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L |
28691 | //TA_FEATURE_CNTL |
28692 | #define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN__SHIFT 0x4 |
28693 | #define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH__SHIFT 0xa |
28694 | #define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN__SHIFT 0xb |
28695 | #define TA_FEATURE_CNTL__TA_CAC_CHICKEN__SHIFT 0xc |
28696 | #define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN__SHIFT 0xd |
28697 | #define TA_FEATURE_CNTL__ATOMIC_COALESCING_EN_MASK 0x00000030L |
28698 | #define TA_FEATURE_CNTL__NONIMG_TA_FASTPATH_MASK 0x00000400L |
28699 | #define TA_FEATURE_CNTL__TA_ACFIFO_CHICKEN_MASK 0x00000800L |
28700 | #define TA_FEATURE_CNTL__TA_CAC_CHICKEN_MASK 0x00001000L |
28701 | #define TA_FEATURE_CNTL__AFIFO_SPLIT_CHICKEN_MASK 0x00002000L |
28702 | //TA_STATUS |
28703 | #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc |
28704 | #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd |
28705 | #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe |
28706 | #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 |
28707 | #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 |
28708 | #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 |
28709 | #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 |
28710 | #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 |
28711 | #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 |
28712 | #define TA_STATUS__IN_BUSY__SHIFT 0x18 |
28713 | #define TA_STATUS__FG_BUSY__SHIFT 0x19 |
28714 | #define TA_STATUS__LA_BUSY__SHIFT 0x1a |
28715 | #define TA_STATUS__FL_BUSY__SHIFT 0x1b |
28716 | #define TA_STATUS__TA_BUSY__SHIFT 0x1c |
28717 | #define TA_STATUS__FA_BUSY__SHIFT 0x1d |
28718 | #define TA_STATUS__AL_BUSY__SHIFT 0x1e |
28719 | #define TA_STATUS__BUSY__SHIFT 0x1f |
28720 | #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L |
28721 | #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L |
28722 | #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L |
28723 | #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L |
28724 | #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L |
28725 | #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L |
28726 | #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L |
28727 | #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L |
28728 | #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L |
28729 | #define TA_STATUS__IN_BUSY_MASK 0x01000000L |
28730 | #define TA_STATUS__FG_BUSY_MASK 0x02000000L |
28731 | #define TA_STATUS__LA_BUSY_MASK 0x04000000L |
28732 | #define TA_STATUS__FL_BUSY_MASK 0x08000000L |
28733 | #define TA_STATUS__TA_BUSY_MASK 0x10000000L |
28734 | #define TA_STATUS__FA_BUSY_MASK 0x20000000L |
28735 | #define TA_STATUS__AL_BUSY_MASK 0x40000000L |
28736 | #define TA_STATUS__BUSY_MASK 0x80000000L |
28737 | //TA_SCRATCH |
28738 | #define TA_SCRATCH__SCRATCH__SHIFT 0x0 |
28739 | #define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
28740 | //TA_DSM_CNTL |
28741 | #define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
28742 | #define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
28743 | #define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
28744 | #define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
28745 | #define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x9 |
28746 | #define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xb |
28747 | #define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc |
28748 | #define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe |
28749 | #define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0xf |
28750 | #define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
28751 | #define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x12 |
28752 | #define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
28753 | #define TA_DSM_CNTL__TA_FS_DFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
28754 | #define TA_DSM_CNTL__TA_FS_DFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
28755 | #define TA_DSM_CNTL__TA_FL_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
28756 | #define TA_DSM_CNTL__TA_FL_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
28757 | #define TA_DSM_CNTL__TA_FX_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000600L |
28758 | #define TA_DSM_CNTL__TA_FX_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
28759 | #define TA_DSM_CNTL__TA_FS_CFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L |
28760 | #define TA_DSM_CNTL__TA_FS_CFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
28761 | #define TA_DSM_CNTL__TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00018000L |
28762 | #define TA_DSM_CNTL__TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
28763 | #define TA_DSM_CNTL__TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
28764 | #define TA_DSM_CNTL__TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
28765 | //TA_DSM_CNTL2 |
28766 | #define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
28767 | #define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 |
28768 | #define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
28769 | #define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
28770 | #define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x9 |
28771 | #define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xb |
28772 | #define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc |
28773 | #define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY__SHIFT 0xe |
28774 | #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0xf |
28775 | #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x11 |
28776 | #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x12 |
28777 | #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x14 |
28778 | #define TA_DSM_CNTL2__TA_INJECT_DELAY__SHIFT 0x1a |
28779 | #define TA_DSM_CNTL2__TA_FS_DFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
28780 | #define TA_DSM_CNTL2__TA_FS_DFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L |
28781 | #define TA_DSM_CNTL2__TA_FL_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
28782 | #define TA_DSM_CNTL2__TA_FL_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
28783 | #define TA_DSM_CNTL2__TA_FX_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000600L |
28784 | #define TA_DSM_CNTL2__TA_FX_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000800L |
28785 | #define TA_DSM_CNTL2__TA_FS_CFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L |
28786 | #define TA_DSM_CNTL2__TA_FS_CFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L |
28787 | #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00018000L |
28788 | #define TA_DSM_CNTL2__TA_FS_AFIFO_LO_SELECT_INJECT_DELAY_MASK 0x00020000L |
28789 | #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
28790 | #define TA_DSM_CNTL2__TA_FS_AFIFO_HI_SELECT_INJECT_DELAY_MASK 0x00100000L |
28791 | #define TA_DSM_CNTL2__TA_INJECT_DELAY_MASK 0xFC000000L |
28792 | //TA_EDC_CNT |
28793 | #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 |
28794 | #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 |
28795 | #define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT__SHIFT 0x4 |
28796 | #define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT__SHIFT 0x6 |
28797 | #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 |
28798 | #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa |
28799 | #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc |
28800 | #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe |
28801 | #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 |
28802 | #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 |
28803 | #define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT__SHIFT 0x14 |
28804 | #define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT__SHIFT 0x16 |
28805 | #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L |
28806 | #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL |
28807 | #define TA_EDC_CNT__TA_FS_AFIFO_LO_SEC_COUNT_MASK 0x00000030L |
28808 | #define TA_EDC_CNT__TA_FS_AFIFO_LO_DED_COUNT_MASK 0x000000C0L |
28809 | #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L |
28810 | #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L |
28811 | #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L |
28812 | #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L |
28813 | #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L |
28814 | #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L |
28815 | #define TA_EDC_CNT__TA_FS_AFIFO_HI_SEC_COUNT_MASK 0x00300000L |
28816 | #define TA_EDC_CNT__TA_FS_AFIFO_HI_DED_COUNT_MASK 0x00C00000L |
28817 | |
28818 | |
28819 | // addressBlock: gc_utcl2_atcl2dec |
28820 | //ATC_L2_CNTL |
28821 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 |
28822 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 |
28823 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 |
28824 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 |
28825 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 |
28826 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb |
28827 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe |
28828 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf |
28829 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 |
28830 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 |
28831 | #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 |
28832 | #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 |
28833 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L |
28834 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L |
28835 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L |
28836 | #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L |
28837 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L |
28838 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L |
28839 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L |
28840 | #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L |
28841 | #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L |
28842 | #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L |
28843 | #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L |
28844 | #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L |
28845 | //ATC_L2_CNTL2 |
28846 | #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 |
28847 | #define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 |
28848 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 |
28849 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb |
28850 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc |
28851 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf |
28852 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 |
28853 | #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL |
28854 | #define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L |
28855 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L |
28856 | #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L |
28857 | #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L |
28858 | #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L |
28859 | #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L |
28860 | //ATC_L2_CACHE_DATA0 |
28861 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 |
28862 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 |
28863 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 |
28864 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 |
28865 | #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L |
28866 | #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L |
28867 | #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL |
28868 | #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L |
28869 | //ATC_L2_CACHE_DATA1 |
28870 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 |
28871 | #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL |
28872 | //ATC_L2_CACHE_DATA2 |
28873 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
28874 | #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
28875 | //ATC_L2_CACHE_DATA3 |
28876 | #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
28877 | #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
28878 | //ATC_L2_CNTL3 |
28879 | #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
28880 | #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 |
28881 | #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc |
28882 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 |
28883 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 |
28884 | #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b |
28885 | #define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e |
28886 | #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL |
28887 | #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L |
28888 | #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L |
28889 | #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L |
28890 | #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L |
28891 | #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L |
28892 | #define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L |
28893 | //ATC_L2_STATUS |
28894 | #define ATC_L2_STATUS__BUSY__SHIFT 0x0 |
28895 | #define ATC_L2_STATUS__BUSY_MASK 0x00000001L |
28896 | //ATC_L2_STATUS2 |
28897 | #define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 |
28898 | #define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc |
28899 | #define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12 |
28900 | #define ATC_L2_STATUS2__UCE__SHIFT 0x13 |
28901 | #define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL |
28902 | #define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L |
28903 | #define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L |
28904 | #define ATC_L2_STATUS2__UCE_MASK 0x00080000L |
28905 | //ATC_L2_MISC_CG |
28906 | #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 |
28907 | #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 |
28908 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 |
28909 | #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L |
28910 | #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L |
28911 | #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L |
28912 | //ATC_L2_MEM_POWER_LS |
28913 | #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
28914 | #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
28915 | #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
28916 | #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
28917 | //ATC_L2_CGTT_CLK_CTRL |
28918 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
28919 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
28920 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
28921 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
28922 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
28923 | #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
28924 | #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
28925 | #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
28926 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
28927 | #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
28928 | //ATC_L2_CACHE_4K_DSM_INDEX |
28929 | #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 |
28930 | #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL |
28931 | //ATC_L2_CACHE_32K_DSM_INDEX |
28932 | #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 |
28933 | #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL |
28934 | //ATC_L2_CACHE_2M_DSM_INDEX |
28935 | #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 |
28936 | #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL |
28937 | //ATC_L2_CACHE_4K_DSM_CNTL |
28938 | #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
28939 | #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
28940 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
28941 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
28942 | #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
28943 | #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
28944 | #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
28945 | #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf |
28946 | #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
28947 | #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
28948 | #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
28949 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
28950 | #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
28951 | #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
28952 | #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
28953 | #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
28954 | #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
28955 | #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
28956 | //ATC_L2_CACHE_32K_DSM_CNTL |
28957 | #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
28958 | #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
28959 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
28960 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
28961 | #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
28962 | #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
28963 | #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
28964 | #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf |
28965 | #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
28966 | #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
28967 | #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
28968 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
28969 | #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
28970 | #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
28971 | #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
28972 | #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
28973 | #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
28974 | #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
28975 | //ATC_L2_CACHE_2M_DSM_CNTL |
28976 | #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 |
28977 | #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
28978 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
28979 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
28980 | #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
28981 | #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc |
28982 | #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd |
28983 | #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf |
28984 | #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 |
28985 | #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL |
28986 | #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
28987 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
28988 | #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
28989 | #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
28990 | #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L |
28991 | #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L |
28992 | #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L |
28993 | #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L |
28994 | //ATC_L2_CNTL4 |
28995 | #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 |
28996 | #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa |
28997 | #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL |
28998 | #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L |
28999 | //ATC_L2_MM_GROUP_RT_CLASSES |
29000 | #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 |
29001 | #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL |
29002 | |
29003 | |
29004 | // addressBlock: gc_utcl2_atcl2pfcntldec |
29005 | //ATC_L2_PERFCOUNTER0_CFG |
29006 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
29007 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
29008 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
29009 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
29010 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
29011 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
29012 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29013 | #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
29014 | #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
29015 | #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
29016 | //ATC_L2_PERFCOUNTER1_CFG |
29017 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
29018 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
29019 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
29020 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
29021 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
29022 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
29023 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29024 | #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
29025 | #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
29026 | #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
29027 | //ATC_L2_PERFCOUNTER_RSLT_CNTL |
29028 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
29029 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
29030 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
29031 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
29032 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
29033 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
29034 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
29035 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
29036 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
29037 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
29038 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
29039 | #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
29040 | |
29041 | |
29042 | // addressBlock: gc_utcl2_atcl2pfcntrdec |
29043 | //ATC_L2_PERFCOUNTER_LO |
29044 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29045 | #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29046 | //ATC_L2_PERFCOUNTER_HI |
29047 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29048 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29049 | #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29050 | #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29051 | |
29052 | |
29053 | // addressBlock: gc_utcl2_l2tlbdec |
29054 | //L2TLB_TLB0_STATUS |
29055 | #define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 |
29056 | #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
29057 | #define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L |
29058 | #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
29059 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO |
29060 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 |
29061 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL |
29062 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI |
29063 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 |
29064 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 |
29065 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 |
29066 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd |
29067 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe |
29068 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 |
29069 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 |
29070 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 |
29071 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 |
29072 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f |
29073 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL |
29074 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L |
29075 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L |
29076 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L |
29077 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L |
29078 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L |
29079 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L |
29080 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L |
29081 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L |
29082 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L |
29083 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO |
29084 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 |
29085 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL |
29086 | //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI |
29087 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 |
29088 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 |
29089 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 |
29090 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd |
29091 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe |
29092 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf |
29093 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 |
29094 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 |
29095 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 |
29096 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 |
29097 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15 |
29098 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e |
29099 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL |
29100 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L |
29101 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L |
29102 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L |
29103 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L |
29104 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L |
29105 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L |
29106 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L |
29107 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L |
29108 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L |
29109 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L |
29110 | #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L |
29111 | |
29112 | |
29113 | // addressBlock: gc_utcl2_l2tlbpldec |
29114 | //L2TLB_PERFCOUNTER0_CFG |
29115 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
29116 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
29117 | #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
29118 | #define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
29119 | #define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
29120 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
29121 | #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29122 | #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
29123 | #define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
29124 | #define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
29125 | //L2TLB_PERFCOUNTER1_CFG |
29126 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
29127 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
29128 | #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
29129 | #define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
29130 | #define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
29131 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
29132 | #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29133 | #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
29134 | #define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
29135 | #define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
29136 | //L2TLB_PERFCOUNTER2_CFG |
29137 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
29138 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
29139 | #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
29140 | #define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
29141 | #define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
29142 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
29143 | #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29144 | #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
29145 | #define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
29146 | #define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
29147 | //L2TLB_PERFCOUNTER3_CFG |
29148 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
29149 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
29150 | #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
29151 | #define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
29152 | #define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
29153 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
29154 | #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29155 | #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
29156 | #define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
29157 | #define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
29158 | //L2TLB_PERFCOUNTER_RSLT_CNTL |
29159 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
29160 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
29161 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
29162 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
29163 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
29164 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
29165 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
29166 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
29167 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
29168 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
29169 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
29170 | #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
29171 | |
29172 | |
29173 | // addressBlock: gc_utcl2_l2tlbprdec |
29174 | //L2TLB_PERFCOUNTER_LO |
29175 | #define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29176 | #define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29177 | //L2TLB_PERFCOUNTER_HI |
29178 | #define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29179 | #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29180 | #define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29181 | #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29182 | |
29183 | |
29184 | // addressBlock: gc_utcl2_vml2pfdec |
29185 | //VM_L2_CNTL |
29186 | #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
29187 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
29188 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
29189 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
29190 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
29191 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
29192 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
29193 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
29194 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
29195 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
29196 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
29197 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
29198 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
29199 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
29200 | #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
29201 | #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
29202 | #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
29203 | #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
29204 | #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
29205 | #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
29206 | #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
29207 | #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
29208 | #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
29209 | #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
29210 | #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
29211 | #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
29212 | #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
29213 | #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
29214 | //VM_L2_CNTL2 |
29215 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
29216 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
29217 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
29218 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
29219 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
29220 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
29221 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
29222 | #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
29223 | #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
29224 | #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
29225 | #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
29226 | #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
29227 | #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
29228 | #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
29229 | //VM_L2_CNTL3 |
29230 | #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
29231 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
29232 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
29233 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
29234 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
29235 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
29236 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
29237 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
29238 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
29239 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
29240 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
29241 | #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
29242 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
29243 | #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
29244 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
29245 | #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
29246 | #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
29247 | #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
29248 | #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
29249 | #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
29250 | #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
29251 | #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
29252 | //VM_L2_STATUS |
29253 | #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
29254 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
29255 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
29256 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
29257 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
29258 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
29259 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
29260 | #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
29261 | #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
29262 | #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
29263 | #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
29264 | #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
29265 | #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
29266 | #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
29267 | //VM_DUMMY_PAGE_FAULT_CNTL |
29268 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
29269 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
29270 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
29271 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
29272 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
29273 | #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
29274 | //VM_DUMMY_PAGE_FAULT_ADDR_LO32 |
29275 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
29276 | #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
29277 | //VM_DUMMY_PAGE_FAULT_ADDR_HI32 |
29278 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
29279 | #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
29280 | //VM_L2_PROTECTION_FAULT_CNTL |
29281 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
29282 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
29283 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
29284 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
29285 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
29286 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
29287 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
29288 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
29289 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
29290 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
29291 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29292 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
29293 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29294 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
29295 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
29296 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
29297 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
29298 | #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
29299 | #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
29300 | #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
29301 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
29302 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
29303 | #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
29304 | #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
29305 | #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
29306 | #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
29307 | #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
29308 | #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29309 | #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
29310 | #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29311 | #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
29312 | #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
29313 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
29314 | #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
29315 | //VM_L2_PROTECTION_FAULT_CNTL2 |
29316 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
29317 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
29318 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
29319 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
29320 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
29321 | #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
29322 | #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
29323 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
29324 | #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
29325 | #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
29326 | //VM_L2_PROTECTION_FAULT_MM_CNTL3 |
29327 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
29328 | #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
29329 | //VM_L2_PROTECTION_FAULT_MM_CNTL4 |
29330 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
29331 | #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
29332 | //VM_L2_PROTECTION_FAULT_STATUS |
29333 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
29334 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
29335 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
29336 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
29337 | #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
29338 | #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
29339 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
29340 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
29341 | #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
29342 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
29343 | #define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d |
29344 | #define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e |
29345 | #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
29346 | #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
29347 | #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
29348 | #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
29349 | #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
29350 | #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
29351 | #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
29352 | #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
29353 | #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
29354 | #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L |
29355 | #define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L |
29356 | #define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L |
29357 | //VM_L2_PROTECTION_FAULT_ADDR_LO32 |
29358 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
29359 | #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
29360 | //VM_L2_PROTECTION_FAULT_ADDR_HI32 |
29361 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
29362 | #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
29363 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
29364 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
29365 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
29366 | //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
29367 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
29368 | #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
29369 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
29370 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
29371 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
29372 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
29373 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
29374 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
29375 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
29376 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
29377 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
29378 | //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
29379 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
29380 | #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
29381 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
29382 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
29383 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
29384 | //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
29385 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
29386 | #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
29387 | //VM_L2_CNTL4 |
29388 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
29389 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
29390 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
29391 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
29392 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
29393 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
29394 | #define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d |
29395 | #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e |
29396 | #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
29397 | #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
29398 | #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
29399 | #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
29400 | #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
29401 | #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
29402 | #define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L |
29403 | #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L |
29404 | //VM_L2_MM_GROUP_RT_CLASSES |
29405 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
29406 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
29407 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
29408 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
29409 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
29410 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
29411 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
29412 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
29413 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
29414 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
29415 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
29416 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
29417 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
29418 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
29419 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
29420 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
29421 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
29422 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
29423 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
29424 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
29425 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
29426 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
29427 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
29428 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
29429 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
29430 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
29431 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
29432 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
29433 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
29434 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
29435 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
29436 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
29437 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
29438 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
29439 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
29440 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
29441 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
29442 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
29443 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
29444 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
29445 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
29446 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
29447 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
29448 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
29449 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
29450 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
29451 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
29452 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
29453 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
29454 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
29455 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
29456 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
29457 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
29458 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
29459 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
29460 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
29461 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
29462 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
29463 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
29464 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
29465 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
29466 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
29467 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
29468 | #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
29469 | //VM_L2_BANK_SELECT_RESERVED_CID |
29470 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
29471 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
29472 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
29473 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
29474 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
29475 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
29476 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
29477 | #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
29478 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
29479 | #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
29480 | //VM_L2_BANK_SELECT_RESERVED_CID2 |
29481 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
29482 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
29483 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
29484 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
29485 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
29486 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
29487 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
29488 | #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
29489 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
29490 | #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
29491 | //VM_L2_CACHE_PARITY_CNTL |
29492 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
29493 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
29494 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
29495 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
29496 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
29497 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
29498 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
29499 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
29500 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
29501 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
29502 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
29503 | #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
29504 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
29505 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
29506 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
29507 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
29508 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
29509 | #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
29510 | //VM_L2_CGTT_CLK_CTRL |
29511 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
29512 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
29513 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
29514 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
29515 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
29516 | #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
29517 | #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
29518 | #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
29519 | #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
29520 | #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
29521 | //VM_L2_CGTT_BUSY_CTRL |
29522 | #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 |
29523 | #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 |
29524 | #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL |
29525 | #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L |
29526 | //VML2_MEM_ECC_INDEX |
29527 | #define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
29528 | #define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
29529 | //VML2_WALKER_MEM_ECC_INDEX |
29530 | #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
29531 | #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
29532 | //UTCL2_MEM_ECC_INDEX |
29533 | #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 |
29534 | #define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL |
29535 | //VML2_MEM_ECC_CNTL |
29536 | #define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
29537 | #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
29538 | #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
29539 | #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
29540 | #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
29541 | #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
29542 | #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
29543 | #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
29544 | #define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
29545 | #define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
29546 | #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
29547 | #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
29548 | #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
29549 | #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
29550 | #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
29551 | #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
29552 | #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
29553 | #define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
29554 | //VML2_WALKER_MEM_ECC_CNTL |
29555 | #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
29556 | #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
29557 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
29558 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
29559 | #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
29560 | #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
29561 | #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
29562 | #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
29563 | #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
29564 | #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
29565 | #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
29566 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
29567 | #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
29568 | #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
29569 | #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
29570 | #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
29571 | #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
29572 | #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
29573 | //UTCL2_MEM_ECC_CNTL |
29574 | #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 |
29575 | #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 |
29576 | #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 |
29577 | #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 |
29578 | #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb |
29579 | #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc |
29580 | #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe |
29581 | #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 |
29582 | #define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 |
29583 | #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL |
29584 | #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L |
29585 | #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L |
29586 | #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L |
29587 | #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L |
29588 | #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L |
29589 | #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L |
29590 | #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L |
29591 | #define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L |
29592 | //VML2_MEM_ECC_STATUS |
29593 | #define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
29594 | #define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 |
29595 | #define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
29596 | #define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L |
29597 | //VML2_WALKER_MEM_ECC_STATUS |
29598 | #define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
29599 | #define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 |
29600 | #define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
29601 | #define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L |
29602 | //UTCL2_MEM_ECC_STATUS |
29603 | #define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 |
29604 | #define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 |
29605 | #define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L |
29606 | #define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L |
29607 | //UTCL2_EDC_MODE |
29608 | #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
29609 | #define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
29610 | #define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 |
29611 | #define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 |
29612 | #define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d |
29613 | #define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f |
29614 | #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
29615 | #define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
29616 | #define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L |
29617 | #define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L |
29618 | #define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L |
29619 | #define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L |
29620 | //UTCL2_EDC_CONFIG |
29621 | #define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
29622 | #define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
29623 | |
29624 | |
29625 | // addressBlock: gc_utcl2_vml2pldec |
29626 | //MC_VM_L2_PERFCOUNTER0_CFG |
29627 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
29628 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
29629 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
29630 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
29631 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
29632 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
29633 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29634 | #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
29635 | #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
29636 | #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
29637 | //MC_VM_L2_PERFCOUNTER1_CFG |
29638 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
29639 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
29640 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
29641 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
29642 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
29643 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
29644 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29645 | #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
29646 | #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
29647 | #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
29648 | //MC_VM_L2_PERFCOUNTER2_CFG |
29649 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
29650 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
29651 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
29652 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
29653 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
29654 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
29655 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29656 | #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
29657 | #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
29658 | #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
29659 | //MC_VM_L2_PERFCOUNTER3_CFG |
29660 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
29661 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
29662 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
29663 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
29664 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
29665 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
29666 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29667 | #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
29668 | #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
29669 | #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
29670 | //MC_VM_L2_PERFCOUNTER4_CFG |
29671 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
29672 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
29673 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
29674 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
29675 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
29676 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
29677 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29678 | #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
29679 | #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
29680 | #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
29681 | //MC_VM_L2_PERFCOUNTER5_CFG |
29682 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
29683 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
29684 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
29685 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
29686 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
29687 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
29688 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29689 | #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
29690 | #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
29691 | #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
29692 | //MC_VM_L2_PERFCOUNTER6_CFG |
29693 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
29694 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
29695 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
29696 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
29697 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
29698 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
29699 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29700 | #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
29701 | #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
29702 | #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
29703 | //MC_VM_L2_PERFCOUNTER7_CFG |
29704 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
29705 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
29706 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
29707 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
29708 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
29709 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
29710 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29711 | #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
29712 | #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
29713 | #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
29714 | //MC_VM_L2_PERFCOUNTER_RSLT_CNTL |
29715 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
29716 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
29717 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
29718 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
29719 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
29720 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
29721 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
29722 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
29723 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
29724 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
29725 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
29726 | #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
29727 | |
29728 | |
29729 | // addressBlock: gc_utcl2_vml2prdec |
29730 | //MC_VM_L2_PERFCOUNTER_LO |
29731 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29732 | #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29733 | //MC_VM_L2_PERFCOUNTER_HI |
29734 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29735 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29736 | #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29737 | #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29738 | |
29739 | |
29740 | // addressBlock: gc_utcl2_vml2vcdec |
29741 | //VM_CONTEXT0_CNTL |
29742 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29743 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29744 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29745 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29746 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29747 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29748 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29749 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29750 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29751 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29752 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29753 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29754 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29755 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29756 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29757 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29758 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29759 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29760 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29761 | #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29762 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29763 | #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29764 | #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29765 | #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29766 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29767 | #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29768 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29769 | #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29770 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29771 | #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29772 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29773 | #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29774 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29775 | #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29776 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29777 | #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29778 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29779 | #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29780 | //VM_CONTEXT1_CNTL |
29781 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29782 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29783 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29784 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29785 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29786 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29787 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29788 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29789 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29790 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29791 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29792 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29793 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29794 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29795 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29796 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29797 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29798 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29799 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29800 | #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29801 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29802 | #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29803 | #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29804 | #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29805 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29806 | #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29807 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29808 | #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29809 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29810 | #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29811 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29812 | #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29813 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29814 | #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29815 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29816 | #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29817 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29818 | #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29819 | //VM_CONTEXT2_CNTL |
29820 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29821 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29822 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29823 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29824 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29825 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29826 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29827 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29828 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29829 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29830 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29831 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29832 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29833 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29834 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29835 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29836 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29837 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29838 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29839 | #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29840 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29841 | #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29842 | #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29843 | #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29844 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29845 | #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29846 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29847 | #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29848 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29849 | #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29850 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29851 | #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29852 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29853 | #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29854 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29855 | #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29856 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29857 | #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29858 | //VM_CONTEXT3_CNTL |
29859 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29860 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29861 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29862 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29863 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29864 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29865 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29866 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29867 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29868 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29869 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29870 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29871 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29872 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29873 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29874 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29875 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29876 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29877 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29878 | #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29879 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29880 | #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29881 | #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29882 | #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29883 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29884 | #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29885 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29886 | #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29887 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29888 | #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29889 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29890 | #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29891 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29892 | #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29893 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29894 | #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29895 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29896 | #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29897 | //VM_CONTEXT4_CNTL |
29898 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29899 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29900 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29901 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29902 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29903 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29904 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29905 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29906 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29907 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29908 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29909 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29910 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29911 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29912 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29913 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29914 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29915 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29916 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29917 | #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29918 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29919 | #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29920 | #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29921 | #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29922 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29923 | #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29924 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29925 | #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29926 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29927 | #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29928 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29929 | #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29930 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29931 | #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29932 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29933 | #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29934 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29935 | #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29936 | //VM_CONTEXT5_CNTL |
29937 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29938 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29939 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29940 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29941 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29942 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29943 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29944 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29945 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29946 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29947 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29948 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29949 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29950 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29951 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29952 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29953 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29954 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29955 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29956 | #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29957 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29958 | #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29959 | #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29960 | #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
29961 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
29962 | #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
29963 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
29964 | #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
29965 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
29966 | #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
29967 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
29968 | #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
29969 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
29970 | #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
29971 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
29972 | #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
29973 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
29974 | #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
29975 | //VM_CONTEXT6_CNTL |
29976 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
29977 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
29978 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
29979 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
29980 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
29981 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
29982 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
29983 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
29984 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
29985 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
29986 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
29987 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
29988 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
29989 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
29990 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
29991 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
29992 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
29993 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
29994 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
29995 | #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
29996 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
29997 | #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
29998 | #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
29999 | #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30000 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30001 | #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30002 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30003 | #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30004 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30005 | #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30006 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30007 | #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30008 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30009 | #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30010 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30011 | #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30012 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30013 | #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30014 | //VM_CONTEXT7_CNTL |
30015 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30016 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30017 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30018 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30019 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30020 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30021 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30022 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30023 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30024 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30025 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30026 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30027 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30028 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30029 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30030 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30031 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30032 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30033 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30034 | #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30035 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30036 | #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30037 | #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30038 | #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30039 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30040 | #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30041 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30042 | #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30043 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30044 | #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30045 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30046 | #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30047 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30048 | #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30049 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30050 | #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30051 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30052 | #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30053 | //VM_CONTEXT8_CNTL |
30054 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30055 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30056 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30057 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30058 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30059 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30060 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30061 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30062 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30063 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30064 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30065 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30066 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30067 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30068 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30069 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30070 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30071 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30072 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30073 | #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30074 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30075 | #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30076 | #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30077 | #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30078 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30079 | #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30080 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30081 | #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30082 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30083 | #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30084 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30085 | #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30086 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30087 | #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30088 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30089 | #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30090 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30091 | #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30092 | //VM_CONTEXT9_CNTL |
30093 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30094 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30095 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30096 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30097 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30098 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30099 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30100 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30101 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30102 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30103 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30104 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30105 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30106 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30107 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30108 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30109 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30110 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30111 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30112 | #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30113 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30114 | #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30115 | #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30116 | #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30117 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30118 | #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30119 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30120 | #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30121 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30122 | #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30123 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30124 | #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30125 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30126 | #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30127 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30128 | #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30129 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30130 | #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30131 | //VM_CONTEXT10_CNTL |
30132 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30133 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30134 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30135 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30136 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30137 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30138 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30139 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30140 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30141 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30142 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30143 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30144 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30145 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30146 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30147 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30148 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30149 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30150 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30151 | #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30152 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30153 | #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30154 | #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30155 | #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30156 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30157 | #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30158 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30159 | #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30160 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30161 | #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30162 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30163 | #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30164 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30165 | #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30166 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30167 | #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30168 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30169 | #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30170 | //VM_CONTEXT11_CNTL |
30171 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30172 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30173 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30174 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30175 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30176 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30177 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30178 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30179 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30180 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30181 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30182 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30183 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30184 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30185 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30186 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30187 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30188 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30189 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30190 | #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30191 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30192 | #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30193 | #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30194 | #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30195 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30196 | #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30197 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30198 | #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30199 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30200 | #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30201 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30202 | #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30203 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30204 | #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30205 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30206 | #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30207 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30208 | #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30209 | //VM_CONTEXT12_CNTL |
30210 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30211 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30212 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30213 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30214 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30215 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30216 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30217 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30218 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30219 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30220 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30221 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30222 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30223 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30224 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30225 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30226 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30227 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30228 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30229 | #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30230 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30231 | #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30232 | #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30233 | #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30234 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30235 | #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30236 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30237 | #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30238 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30239 | #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30240 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30241 | #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30242 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30243 | #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30244 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30245 | #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30246 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30247 | #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30248 | //VM_CONTEXT13_CNTL |
30249 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30250 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30251 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30252 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30253 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30254 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30255 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30256 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30257 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30258 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30259 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30260 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30261 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30262 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30263 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30264 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30265 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30266 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30267 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30268 | #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30269 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30270 | #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30271 | #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30272 | #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30273 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30274 | #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30275 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30276 | #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30277 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30278 | #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30279 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30280 | #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30281 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30282 | #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30283 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30284 | #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30285 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30286 | #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30287 | //VM_CONTEXT14_CNTL |
30288 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30289 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30290 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30291 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30292 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30293 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30294 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30295 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30296 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30297 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30298 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30299 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30300 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30301 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30302 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30303 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30304 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30305 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30306 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30307 | #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30308 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30309 | #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30310 | #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30311 | #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30312 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30313 | #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30314 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30315 | #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30316 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30317 | #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30318 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30319 | #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30320 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30321 | #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30322 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30323 | #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30324 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30325 | #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30326 | //VM_CONTEXT15_CNTL |
30327 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
30328 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
30329 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
30330 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
30331 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
30332 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
30333 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
30334 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
30335 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
30336 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
30337 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
30338 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
30339 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
30340 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
30341 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
30342 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
30343 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
30344 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
30345 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
30346 | #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
30347 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
30348 | #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
30349 | #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
30350 | #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
30351 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
30352 | #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
30353 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
30354 | #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
30355 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
30356 | #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
30357 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
30358 | #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
30359 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
30360 | #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
30361 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
30362 | #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
30363 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
30364 | #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
30365 | //VM_CONTEXTS_DISABLE |
30366 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
30367 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
30368 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
30369 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
30370 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
30371 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
30372 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
30373 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
30374 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
30375 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
30376 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
30377 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
30378 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
30379 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
30380 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
30381 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
30382 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
30383 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
30384 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
30385 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
30386 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
30387 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
30388 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
30389 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
30390 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
30391 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
30392 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
30393 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
30394 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
30395 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
30396 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
30397 | #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
30398 | //VM_INVALIDATE_ENG0_SEM |
30399 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
30400 | #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
30401 | //VM_INVALIDATE_ENG1_SEM |
30402 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
30403 | #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
30404 | //VM_INVALIDATE_ENG2_SEM |
30405 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
30406 | #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
30407 | //VM_INVALIDATE_ENG3_SEM |
30408 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
30409 | #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
30410 | //VM_INVALIDATE_ENG4_SEM |
30411 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
30412 | #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
30413 | //VM_INVALIDATE_ENG5_SEM |
30414 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
30415 | #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
30416 | //VM_INVALIDATE_ENG6_SEM |
30417 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
30418 | #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
30419 | //VM_INVALIDATE_ENG7_SEM |
30420 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
30421 | #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
30422 | //VM_INVALIDATE_ENG8_SEM |
30423 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
30424 | #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
30425 | //VM_INVALIDATE_ENG9_SEM |
30426 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
30427 | #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
30428 | //VM_INVALIDATE_ENG10_SEM |
30429 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
30430 | #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
30431 | //VM_INVALIDATE_ENG11_SEM |
30432 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
30433 | #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
30434 | //VM_INVALIDATE_ENG12_SEM |
30435 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
30436 | #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
30437 | //VM_INVALIDATE_ENG13_SEM |
30438 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
30439 | #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
30440 | //VM_INVALIDATE_ENG14_SEM |
30441 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
30442 | #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
30443 | //VM_INVALIDATE_ENG15_SEM |
30444 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
30445 | #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
30446 | //VM_INVALIDATE_ENG16_SEM |
30447 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
30448 | #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
30449 | //VM_INVALIDATE_ENG17_SEM |
30450 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
30451 | #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
30452 | //VM_INVALIDATE_ENG0_REQ |
30453 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30454 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
30455 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30456 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30457 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30458 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30459 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30460 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30461 | #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 |
30462 | #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30463 | #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L |
30464 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30465 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30466 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30467 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30468 | #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30469 | #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30470 | #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L |
30471 | //VM_INVALIDATE_ENG1_REQ |
30472 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30473 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
30474 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30475 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30476 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30477 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30478 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30479 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30480 | #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 |
30481 | #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30482 | #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L |
30483 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30484 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30485 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30486 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30487 | #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30488 | #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30489 | #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L |
30490 | //VM_INVALIDATE_ENG2_REQ |
30491 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30492 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
30493 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30494 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30495 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30496 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30497 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30498 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30499 | #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 |
30500 | #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30501 | #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L |
30502 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30503 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30504 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30505 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30506 | #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30507 | #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30508 | #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L |
30509 | //VM_INVALIDATE_ENG3_REQ |
30510 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30511 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
30512 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30513 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30514 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30515 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30516 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30517 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30518 | #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 |
30519 | #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30520 | #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L |
30521 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30522 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30523 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30524 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30525 | #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30526 | #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30527 | #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L |
30528 | //VM_INVALIDATE_ENG4_REQ |
30529 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30530 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
30531 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30532 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30533 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30534 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30535 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30536 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30537 | #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 |
30538 | #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30539 | #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L |
30540 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30541 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30542 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30543 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30544 | #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30545 | #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30546 | #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L |
30547 | //VM_INVALIDATE_ENG5_REQ |
30548 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30549 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
30550 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30551 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30552 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30553 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30554 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30555 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30556 | #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 |
30557 | #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30558 | #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L |
30559 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30560 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30561 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30562 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30563 | #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30564 | #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30565 | #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L |
30566 | //VM_INVALIDATE_ENG6_REQ |
30567 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30568 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
30569 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30570 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30571 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30572 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30573 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30574 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30575 | #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 |
30576 | #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30577 | #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L |
30578 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30579 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30580 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30581 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30582 | #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30583 | #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30584 | #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L |
30585 | //VM_INVALIDATE_ENG7_REQ |
30586 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30587 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
30588 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30589 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30590 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30591 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30592 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30593 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30594 | #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 |
30595 | #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30596 | #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L |
30597 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30598 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30599 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30600 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30601 | #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30602 | #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30603 | #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L |
30604 | //VM_INVALIDATE_ENG8_REQ |
30605 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30606 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
30607 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30608 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30609 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30610 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30611 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30612 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30613 | #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 |
30614 | #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30615 | #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L |
30616 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30617 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30618 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30619 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30620 | #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30621 | #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30622 | #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L |
30623 | //VM_INVALIDATE_ENG9_REQ |
30624 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30625 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
30626 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30627 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30628 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30629 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30630 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30631 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30632 | #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 |
30633 | #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30634 | #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L |
30635 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30636 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30637 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30638 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30639 | #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30640 | #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30641 | #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L |
30642 | //VM_INVALIDATE_ENG10_REQ |
30643 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30644 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
30645 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30646 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30647 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30648 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30649 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30650 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30651 | #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 |
30652 | #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30653 | #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L |
30654 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30655 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30656 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30657 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30658 | #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30659 | #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30660 | #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L |
30661 | //VM_INVALIDATE_ENG11_REQ |
30662 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30663 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
30664 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30665 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30666 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30667 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30668 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30669 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30670 | #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 |
30671 | #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30672 | #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L |
30673 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30674 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30675 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30676 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30677 | #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30678 | #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30679 | #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L |
30680 | //VM_INVALIDATE_ENG12_REQ |
30681 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30682 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
30683 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30684 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30685 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30686 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30687 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30688 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30689 | #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 |
30690 | #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30691 | #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L |
30692 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30693 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30694 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30695 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30696 | #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30697 | #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30698 | #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L |
30699 | //VM_INVALIDATE_ENG13_REQ |
30700 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30701 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
30702 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30703 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30704 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30705 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30706 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30707 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30708 | #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 |
30709 | #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30710 | #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L |
30711 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30712 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30713 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30714 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30715 | #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30716 | #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30717 | #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L |
30718 | //VM_INVALIDATE_ENG14_REQ |
30719 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30720 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
30721 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30722 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30723 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30724 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30725 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30726 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30727 | #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 |
30728 | #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30729 | #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L |
30730 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30731 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30732 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30733 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30734 | #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30735 | #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30736 | #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L |
30737 | //VM_INVALIDATE_ENG15_REQ |
30738 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30739 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
30740 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30741 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30742 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30743 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30744 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30745 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30746 | #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 |
30747 | #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30748 | #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L |
30749 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30750 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30751 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30752 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30753 | #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30754 | #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30755 | #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L |
30756 | //VM_INVALIDATE_ENG16_REQ |
30757 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30758 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
30759 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30760 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30761 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30762 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30763 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30764 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30765 | #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 |
30766 | #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30767 | #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L |
30768 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30769 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30770 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30771 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30772 | #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30773 | #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30774 | #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L |
30775 | //VM_INVALIDATE_ENG17_REQ |
30776 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
30777 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
30778 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 |
30779 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 |
30780 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 |
30781 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 |
30782 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 |
30783 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 |
30784 | #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 |
30785 | #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
30786 | #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L |
30787 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L |
30788 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L |
30789 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L |
30790 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L |
30791 | #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L |
30792 | #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L |
30793 | #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L |
30794 | //VM_INVALIDATE_ENG0_ACK |
30795 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30796 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
30797 | #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30798 | #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
30799 | //VM_INVALIDATE_ENG1_ACK |
30800 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30801 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
30802 | #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30803 | #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
30804 | //VM_INVALIDATE_ENG2_ACK |
30805 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30806 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
30807 | #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30808 | #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
30809 | //VM_INVALIDATE_ENG3_ACK |
30810 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30811 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
30812 | #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30813 | #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
30814 | //VM_INVALIDATE_ENG4_ACK |
30815 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30816 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
30817 | #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30818 | #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
30819 | //VM_INVALIDATE_ENG5_ACK |
30820 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30821 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
30822 | #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30823 | #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
30824 | //VM_INVALIDATE_ENG6_ACK |
30825 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30826 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
30827 | #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30828 | #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
30829 | //VM_INVALIDATE_ENG7_ACK |
30830 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30831 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
30832 | #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30833 | #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
30834 | //VM_INVALIDATE_ENG8_ACK |
30835 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30836 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
30837 | #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30838 | #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
30839 | //VM_INVALIDATE_ENG9_ACK |
30840 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30841 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
30842 | #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30843 | #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
30844 | //VM_INVALIDATE_ENG10_ACK |
30845 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30846 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
30847 | #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30848 | #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
30849 | //VM_INVALIDATE_ENG11_ACK |
30850 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30851 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
30852 | #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30853 | #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
30854 | //VM_INVALIDATE_ENG12_ACK |
30855 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30856 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
30857 | #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30858 | #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
30859 | //VM_INVALIDATE_ENG13_ACK |
30860 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30861 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
30862 | #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30863 | #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
30864 | //VM_INVALIDATE_ENG14_ACK |
30865 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30866 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
30867 | #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30868 | #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
30869 | //VM_INVALIDATE_ENG15_ACK |
30870 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30871 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
30872 | #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30873 | #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
30874 | //VM_INVALIDATE_ENG16_ACK |
30875 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30876 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
30877 | #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30878 | #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
30879 | //VM_INVALIDATE_ENG17_ACK |
30880 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
30881 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
30882 | #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
30883 | #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
30884 | //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
30885 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30886 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30887 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30888 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30889 | //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
30890 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30891 | #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30892 | //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
30893 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30894 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30895 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30896 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30897 | //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
30898 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30899 | #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30900 | //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
30901 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30902 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30903 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30904 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30905 | //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
30906 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30907 | #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30908 | //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
30909 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30910 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30911 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30912 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30913 | //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
30914 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30915 | #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30916 | //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
30917 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30918 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30919 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30920 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30921 | //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
30922 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30923 | #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30924 | //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
30925 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30926 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30927 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30928 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30929 | //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
30930 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30931 | #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30932 | //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
30933 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30934 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30935 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30936 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30937 | //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
30938 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30939 | #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30940 | //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
30941 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30942 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30943 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30944 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30945 | //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
30946 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30947 | #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30948 | //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
30949 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30950 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30951 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30952 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30953 | //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
30954 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30955 | #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30956 | //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
30957 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30958 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30959 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30960 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30961 | //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
30962 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30963 | #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30964 | //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
30965 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30966 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30967 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30968 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30969 | //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
30970 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30971 | #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30972 | //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
30973 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30974 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30975 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30976 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30977 | //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
30978 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30979 | #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30980 | //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
30981 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30982 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30983 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30984 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30985 | //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
30986 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30987 | #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30988 | //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
30989 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30990 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30991 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
30992 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
30993 | //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
30994 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
30995 | #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
30996 | //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
30997 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
30998 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
30999 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
31000 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
31001 | //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
31002 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
31003 | #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
31004 | //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
31005 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
31006 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
31007 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
31008 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
31009 | //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
31010 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
31011 | #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
31012 | //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
31013 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
31014 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
31015 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
31016 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
31017 | //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
31018 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
31019 | #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
31020 | //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
31021 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
31022 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
31023 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
31024 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
31025 | //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
31026 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
31027 | #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
31028 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
31029 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31030 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31031 | //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
31032 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31033 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31034 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
31035 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31036 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31037 | //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
31038 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31039 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31040 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
31041 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31042 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31043 | //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
31044 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31045 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31046 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
31047 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31048 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31049 | //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
31050 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31051 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31052 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
31053 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31054 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31055 | //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
31056 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31057 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31058 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
31059 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31060 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31061 | //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
31062 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31063 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31064 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
31065 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31066 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31067 | //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
31068 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31069 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31070 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
31071 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31072 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31073 | //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
31074 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31075 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31076 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
31077 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31078 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31079 | //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
31080 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31081 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31082 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
31083 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31084 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31085 | //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
31086 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31087 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31088 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
31089 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31090 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31091 | //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
31092 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31093 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31094 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
31095 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31096 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31097 | //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
31098 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31099 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31100 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
31101 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31102 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31103 | //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
31104 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31105 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31106 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
31107 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31108 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31109 | //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
31110 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31111 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31112 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
31113 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31114 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31115 | //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
31116 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31117 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31118 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
31119 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
31120 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
31121 | //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
31122 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
31123 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
31124 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
31125 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31126 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31127 | //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
31128 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31129 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31130 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
31131 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31132 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31133 | //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
31134 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31135 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31136 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
31137 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31138 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31139 | //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
31140 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31141 | #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31142 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
31143 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31144 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31145 | //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
31146 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31147 | #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31148 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
31149 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31150 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31151 | //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
31152 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31153 | #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31154 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
31155 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31156 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31157 | //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
31158 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31159 | #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31160 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
31161 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31162 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31163 | //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
31164 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31165 | #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31166 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
31167 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31168 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31169 | //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
31170 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31171 | #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31172 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
31173 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31174 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31175 | //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
31176 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31177 | #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31178 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
31179 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31180 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31181 | //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
31182 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31183 | #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31184 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
31185 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31186 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31187 | //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
31188 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31189 | #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31190 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
31191 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31192 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31193 | //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
31194 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31195 | #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31196 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
31197 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31198 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31199 | //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
31200 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31201 | #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31202 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
31203 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31204 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31205 | //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
31206 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31207 | #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31208 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
31209 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31210 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31211 | //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
31212 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31213 | #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31214 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
31215 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31216 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31217 | //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
31218 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31219 | #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31220 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
31221 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31222 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31223 | //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
31224 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31225 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31226 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
31227 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31228 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31229 | //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
31230 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31231 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31232 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
31233 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31234 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31235 | //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
31236 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31237 | #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31238 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
31239 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31240 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31241 | //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
31242 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31243 | #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31244 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
31245 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31246 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31247 | //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
31248 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31249 | #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31250 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
31251 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31252 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31253 | //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
31254 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31255 | #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31256 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
31257 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31258 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31259 | //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
31260 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31261 | #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31262 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
31263 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31264 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31265 | //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
31266 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31267 | #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31268 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
31269 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31270 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31271 | //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
31272 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31273 | #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31274 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
31275 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31276 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31277 | //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
31278 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31279 | #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31280 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
31281 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31282 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31283 | //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
31284 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31285 | #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31286 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
31287 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31288 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31289 | //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
31290 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31291 | #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31292 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
31293 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31294 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31295 | //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
31296 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31297 | #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31298 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
31299 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31300 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31301 | //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
31302 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31303 | #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31304 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
31305 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31306 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31307 | //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
31308 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31309 | #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31310 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
31311 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
31312 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
31313 | //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
31314 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
31315 | #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
31316 | |
31317 | |
31318 | // addressBlock: gc_utcl2_vmsharedhvdec |
31319 | //MC_VM_FB_SIZE_OFFSET_VF0 |
31320 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
31321 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
31322 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
31323 | #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
31324 | //MC_VM_FB_SIZE_OFFSET_VF1 |
31325 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
31326 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
31327 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
31328 | #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
31329 | //MC_VM_FB_SIZE_OFFSET_VF2 |
31330 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
31331 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
31332 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
31333 | #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
31334 | //MC_VM_FB_SIZE_OFFSET_VF3 |
31335 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
31336 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
31337 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
31338 | #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
31339 | //MC_VM_FB_SIZE_OFFSET_VF4 |
31340 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
31341 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
31342 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
31343 | #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
31344 | //MC_VM_FB_SIZE_OFFSET_VF5 |
31345 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
31346 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
31347 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
31348 | #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
31349 | //MC_VM_FB_SIZE_OFFSET_VF6 |
31350 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
31351 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
31352 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
31353 | #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
31354 | //MC_VM_FB_SIZE_OFFSET_VF7 |
31355 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
31356 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
31357 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
31358 | #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
31359 | //MC_VM_FB_SIZE_OFFSET_VF8 |
31360 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
31361 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
31362 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
31363 | #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
31364 | //MC_VM_FB_SIZE_OFFSET_VF9 |
31365 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
31366 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
31367 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
31368 | #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
31369 | //MC_VM_FB_SIZE_OFFSET_VF10 |
31370 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
31371 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
31372 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
31373 | #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
31374 | //MC_VM_FB_SIZE_OFFSET_VF11 |
31375 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
31376 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
31377 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
31378 | #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
31379 | //MC_VM_FB_SIZE_OFFSET_VF12 |
31380 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
31381 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
31382 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
31383 | #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
31384 | //MC_VM_FB_SIZE_OFFSET_VF13 |
31385 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
31386 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
31387 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
31388 | #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
31389 | //MC_VM_FB_SIZE_OFFSET_VF14 |
31390 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
31391 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
31392 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
31393 | #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
31394 | //MC_VM_FB_SIZE_OFFSET_VF15 |
31395 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
31396 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
31397 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
31398 | #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
31399 | //MC_VM_MARC_BASE_LO_0 |
31400 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
31401 | #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
31402 | //MC_VM_MARC_BASE_LO_1 |
31403 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
31404 | #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
31405 | //MC_VM_MARC_BASE_LO_2 |
31406 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
31407 | #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
31408 | //MC_VM_MARC_BASE_LO_3 |
31409 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
31410 | #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
31411 | //MC_VM_MARC_BASE_HI_0 |
31412 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
31413 | #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
31414 | //MC_VM_MARC_BASE_HI_1 |
31415 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
31416 | #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
31417 | //MC_VM_MARC_BASE_HI_2 |
31418 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
31419 | #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
31420 | //MC_VM_MARC_BASE_HI_3 |
31421 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
31422 | #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
31423 | //MC_VM_MARC_RELOC_LO_0 |
31424 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
31425 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
31426 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
31427 | #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
31428 | #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
31429 | #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
31430 | //MC_VM_MARC_RELOC_LO_1 |
31431 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
31432 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
31433 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
31434 | #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
31435 | #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
31436 | #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
31437 | //MC_VM_MARC_RELOC_LO_2 |
31438 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
31439 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
31440 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
31441 | #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
31442 | #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
31443 | #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
31444 | //MC_VM_MARC_RELOC_LO_3 |
31445 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
31446 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
31447 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
31448 | #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
31449 | #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
31450 | #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
31451 | //MC_VM_MARC_RELOC_HI_0 |
31452 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
31453 | #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
31454 | //MC_VM_MARC_RELOC_HI_1 |
31455 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
31456 | #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
31457 | //MC_VM_MARC_RELOC_HI_2 |
31458 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
31459 | #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
31460 | //MC_VM_MARC_RELOC_HI_3 |
31461 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
31462 | #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
31463 | //MC_VM_MARC_LEN_LO_0 |
31464 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
31465 | #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
31466 | //MC_VM_MARC_LEN_LO_1 |
31467 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
31468 | #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
31469 | //MC_VM_MARC_LEN_LO_2 |
31470 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
31471 | #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
31472 | //MC_VM_MARC_LEN_LO_3 |
31473 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
31474 | #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
31475 | //MC_VM_MARC_LEN_HI_0 |
31476 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
31477 | #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
31478 | //MC_VM_MARC_LEN_HI_1 |
31479 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
31480 | #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
31481 | //MC_VM_MARC_LEN_HI_2 |
31482 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
31483 | #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
31484 | //MC_VM_MARC_LEN_HI_3 |
31485 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
31486 | #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
31487 | //VM_PCIE_ATS_CNTL |
31488 | #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 |
31489 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f |
31490 | #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L |
31491 | #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L |
31492 | //VM_PCIE_ATS_CNTL_VF_0 |
31493 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f |
31494 | #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L |
31495 | //VM_PCIE_ATS_CNTL_VF_1 |
31496 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f |
31497 | #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L |
31498 | //VM_PCIE_ATS_CNTL_VF_2 |
31499 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f |
31500 | #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L |
31501 | //VM_PCIE_ATS_CNTL_VF_3 |
31502 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f |
31503 | #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L |
31504 | //VM_PCIE_ATS_CNTL_VF_4 |
31505 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f |
31506 | #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L |
31507 | //VM_PCIE_ATS_CNTL_VF_5 |
31508 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f |
31509 | #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L |
31510 | //VM_PCIE_ATS_CNTL_VF_6 |
31511 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f |
31512 | #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L |
31513 | //VM_PCIE_ATS_CNTL_VF_7 |
31514 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f |
31515 | #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L |
31516 | //VM_PCIE_ATS_CNTL_VF_8 |
31517 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f |
31518 | #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L |
31519 | //VM_PCIE_ATS_CNTL_VF_9 |
31520 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f |
31521 | #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L |
31522 | //VM_PCIE_ATS_CNTL_VF_10 |
31523 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f |
31524 | #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L |
31525 | //VM_PCIE_ATS_CNTL_VF_11 |
31526 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f |
31527 | #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L |
31528 | //VM_PCIE_ATS_CNTL_VF_12 |
31529 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f |
31530 | #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L |
31531 | //VM_PCIE_ATS_CNTL_VF_13 |
31532 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f |
31533 | #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L |
31534 | //VM_PCIE_ATS_CNTL_VF_14 |
31535 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f |
31536 | #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L |
31537 | //VM_PCIE_ATS_CNTL_VF_15 |
31538 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f |
31539 | #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L |
31540 | //MC_SHARED_ACTIVE_FCN_ID |
31541 | #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
31542 | #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
31543 | #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
31544 | #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
31545 | //MC_VM_XGMI_GPUIOV_ENABLE |
31546 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 |
31547 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 |
31548 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 |
31549 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 |
31550 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 |
31551 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 |
31552 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 |
31553 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 |
31554 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 |
31555 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 |
31556 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa |
31557 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb |
31558 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc |
31559 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd |
31560 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe |
31561 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf |
31562 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f |
31563 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L |
31564 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L |
31565 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L |
31566 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L |
31567 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L |
31568 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L |
31569 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L |
31570 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L |
31571 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L |
31572 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L |
31573 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L |
31574 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L |
31575 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L |
31576 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L |
31577 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L |
31578 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L |
31579 | #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L |
31580 | |
31581 | |
31582 | // addressBlock: gc_utcl2_vmsharedpfdec |
31583 | //MC_VM_FB_OFFSET |
31584 | #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
31585 | #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
31586 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
31587 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
31588 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
31589 | //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
31590 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
31591 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
31592 | //MC_VM_STEERING |
31593 | #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
31594 | #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
31595 | //MC_SHARED_VIRT_RESET_REQ |
31596 | #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
31597 | #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
31598 | #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
31599 | #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
31600 | //MC_MEM_POWER_LS |
31601 | #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
31602 | #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
31603 | #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
31604 | #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
31605 | //MC_VM_CACHEABLE_DRAM_ADDRESS_START |
31606 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
31607 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL |
31608 | //MC_VM_CACHEABLE_DRAM_ADDRESS_END |
31609 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
31610 | #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL |
31611 | //MC_VM_APT_CNTL |
31612 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
31613 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
31614 | #define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 |
31615 | #define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 |
31616 | #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
31617 | #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
31618 | #define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L |
31619 | #define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L |
31620 | //MC_VM_LOCAL_HBM_ADDRESS_START |
31621 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
31622 | #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL |
31623 | //MC_VM_LOCAL_HBM_ADDRESS_END |
31624 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
31625 | #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL |
31626 | //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL |
31627 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
31628 | #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
31629 | //UTCL2_CGTT_CLK_CTRL |
31630 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
31631 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
31632 | #define 0xc |
31633 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
31634 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
31635 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
31636 | #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
31637 | #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
31638 | #define 0x00007000L |
31639 | #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
31640 | #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
31641 | #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
31642 | //MC_VM_XGMI_LFB_CNTL |
31643 | #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 |
31644 | #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 |
31645 | #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL |
31646 | #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L |
31647 | //MC_VM_XGMI_LFB_SIZE |
31648 | #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 |
31649 | #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL |
31650 | //MC_VM_CACHEABLE_DRAM_CNTL |
31651 | #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 |
31652 | #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L |
31653 | //MC_VM_HOST_MAPPING |
31654 | #define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 |
31655 | #define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L |
31656 | |
31657 | |
31658 | // addressBlock: gc_utcl2_vmsharedvcdec |
31659 | //MC_VM_FB_LOCATION_BASE |
31660 | #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
31661 | #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
31662 | //MC_VM_FB_LOCATION_TOP |
31663 | #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
31664 | #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
31665 | //MC_VM_AGP_TOP |
31666 | #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
31667 | #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
31668 | //MC_VM_AGP_BOT |
31669 | #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
31670 | #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
31671 | //MC_VM_AGP_BASE |
31672 | #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
31673 | #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
31674 | //MC_VM_SYSTEM_APERTURE_LOW_ADDR |
31675 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
31676 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
31677 | //MC_VM_SYSTEM_APERTURE_HIGH_ADDR |
31678 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
31679 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
31680 | //MC_VM_MX_L1_TLB_CNTL |
31681 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
31682 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
31683 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
31684 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
31685 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
31686 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
31687 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd |
31688 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
31689 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
31690 | #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
31691 | #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
31692 | #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
31693 | #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L |
31694 | #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L |
31695 | |
31696 | |
31697 | // addressBlock: gccacind |
31698 | //GC_CAC_CNTL |
31699 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
31700 | #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
31701 | #define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 |
31702 | #define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 |
31703 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
31704 | #define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
31705 | #define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L |
31706 | #define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L |
31707 | //GC_CAC_OVR_SEL |
31708 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
31709 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
31710 | //GC_CAC_OVR_VAL |
31711 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
31712 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
31713 | //GC_CAC_WEIGHT_BCI_0 |
31714 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 |
31715 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 |
31716 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL |
31717 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L |
31718 | //GC_CAC_WEIGHT_CB_0 |
31719 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 |
31720 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 |
31721 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL |
31722 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L |
31723 | //GC_CAC_WEIGHT_CB_1 |
31724 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 |
31725 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 |
31726 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL |
31727 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L |
31728 | //GC_CAC_WEIGHT_CP_0 |
31729 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 |
31730 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 |
31731 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL |
31732 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L |
31733 | //GC_CAC_WEIGHT_CP_1 |
31734 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 |
31735 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL |
31736 | //GC_CAC_WEIGHT_DB_0 |
31737 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 |
31738 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 |
31739 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL |
31740 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L |
31741 | //GC_CAC_WEIGHT_DB_1 |
31742 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 |
31743 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 |
31744 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL |
31745 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L |
31746 | //GC_CAC_WEIGHT_GDS_0 |
31747 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 |
31748 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 |
31749 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL |
31750 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L |
31751 | //GC_CAC_WEIGHT_GDS_1 |
31752 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 |
31753 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 |
31754 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL |
31755 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L |
31756 | //GC_CAC_WEIGHT_IA_0 |
31757 | #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 |
31758 | #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL |
31759 | //GC_CAC_WEIGHT_LDS_0 |
31760 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 |
31761 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 |
31762 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL |
31763 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L |
31764 | //GC_CAC_WEIGHT_LDS_1 |
31765 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 |
31766 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 |
31767 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL |
31768 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L |
31769 | //GC_CAC_WEIGHT_PA_0 |
31770 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 |
31771 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 |
31772 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL |
31773 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L |
31774 | //GC_CAC_WEIGHT_PC_0 |
31775 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 |
31776 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL |
31777 | //GC_CAC_WEIGHT_SC_0 |
31778 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 |
31779 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL |
31780 | //GC_CAC_WEIGHT_SPI_0 |
31781 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 |
31782 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 |
31783 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL |
31784 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L |
31785 | //GC_CAC_WEIGHT_SPI_1 |
31786 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 |
31787 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 |
31788 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL |
31789 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L |
31790 | //GC_CAC_WEIGHT_SPI_2 |
31791 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 |
31792 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 |
31793 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL |
31794 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L |
31795 | //GC_CAC_WEIGHT_SQ_0 |
31796 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 |
31797 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 |
31798 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL |
31799 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L |
31800 | //GC_CAC_WEIGHT_SQ_1 |
31801 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 |
31802 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 |
31803 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL |
31804 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L |
31805 | //GC_CAC_WEIGHT_SQ_2 |
31806 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 |
31807 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 |
31808 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL |
31809 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L |
31810 | //GC_CAC_WEIGHT_SQ_3 |
31811 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 |
31812 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 |
31813 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL |
31814 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L |
31815 | //GC_CAC_WEIGHT_SQ_4 |
31816 | #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 |
31817 | #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL |
31818 | //GC_CAC_WEIGHT_SX_0 |
31819 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 |
31820 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL |
31821 | //GC_CAC_WEIGHT_SXRB_0 |
31822 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 |
31823 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL |
31824 | //GC_CAC_WEIGHT_TA_0 |
31825 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 |
31826 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL |
31827 | //GC_CAC_WEIGHT_TCC_0 |
31828 | #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 |
31829 | #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 |
31830 | #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL |
31831 | #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L |
31832 | //GC_CAC_WEIGHT_TCC_1 |
31833 | #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 |
31834 | #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 |
31835 | #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL |
31836 | #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L |
31837 | //GC_CAC_WEIGHT_TCC_2 |
31838 | #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 |
31839 | #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL |
31840 | //GC_CAC_WEIGHT_TCP_0 |
31841 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 |
31842 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 |
31843 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL |
31844 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L |
31845 | //GC_CAC_WEIGHT_TCP_1 |
31846 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 |
31847 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 |
31848 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL |
31849 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L |
31850 | //GC_CAC_WEIGHT_TCP_2 |
31851 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 |
31852 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL |
31853 | //GC_CAC_WEIGHT_TD_0 |
31854 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 |
31855 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 |
31856 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL |
31857 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L |
31858 | //GC_CAC_WEIGHT_TD_1 |
31859 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 |
31860 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 |
31861 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL |
31862 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L |
31863 | //GC_CAC_WEIGHT_TD_2 |
31864 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 |
31865 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 |
31866 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL |
31867 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L |
31868 | //GC_CAC_WEIGHT_VGT_0 |
31869 | #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 |
31870 | #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 |
31871 | #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL |
31872 | #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L |
31873 | //GC_CAC_WEIGHT_VGT_1 |
31874 | #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 |
31875 | #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL |
31876 | //GC_CAC_WEIGHT_WD_0 |
31877 | #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 |
31878 | #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL |
31879 | //GC_CAC_WEIGHT_CU_0 |
31880 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 |
31881 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL |
31882 | //GC_CAC_ACC_BCI0 |
31883 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 |
31884 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31885 | //GC_CAC_ACC_CB0 |
31886 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 |
31887 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31888 | //GC_CAC_ACC_CB1 |
31889 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 |
31890 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31891 | //GC_CAC_ACC_CB2 |
31892 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 |
31893 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31894 | //GC_CAC_ACC_CB3 |
31895 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 |
31896 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31897 | //GC_CAC_ACC_CP0 |
31898 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 |
31899 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31900 | //GC_CAC_ACC_CP1 |
31901 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 |
31902 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31903 | //GC_CAC_ACC_CP2 |
31904 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 |
31905 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31906 | //GC_CAC_ACC_DB0 |
31907 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 |
31908 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31909 | //GC_CAC_ACC_DB1 |
31910 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 |
31911 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31912 | //GC_CAC_ACC_DB2 |
31913 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 |
31914 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31915 | //GC_CAC_ACC_DB3 |
31916 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 |
31917 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31918 | //GC_CAC_ACC_GDS0 |
31919 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
31920 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31921 | //GC_CAC_ACC_GDS1 |
31922 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
31923 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31924 | //GC_CAC_ACC_GDS2 |
31925 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
31926 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31927 | //GC_CAC_ACC_GDS3 |
31928 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
31929 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31930 | //GC_CAC_ACC_IA0 |
31931 | #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 |
31932 | #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31933 | //GC_CAC_ACC_LDS0 |
31934 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
31935 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31936 | //GC_CAC_ACC_LDS1 |
31937 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
31938 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31939 | //GC_CAC_ACC_LDS2 |
31940 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
31941 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31942 | //GC_CAC_ACC_LDS3 |
31943 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
31944 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31945 | //GC_CAC_ACC_PA0 |
31946 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 |
31947 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31948 | //GC_CAC_ACC_PA1 |
31949 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 |
31950 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31951 | //GC_CAC_ACC_PC0 |
31952 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 |
31953 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31954 | //GC_CAC_ACC_SC0 |
31955 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 |
31956 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31957 | //GC_CAC_ACC_SPI0 |
31958 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 |
31959 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31960 | //GC_CAC_ACC_SPI1 |
31961 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 |
31962 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31963 | //GC_CAC_ACC_SPI2 |
31964 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 |
31965 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31966 | //GC_CAC_ACC_SPI3 |
31967 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 |
31968 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31969 | //GC_CAC_ACC_SPI4 |
31970 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 |
31971 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31972 | //GC_CAC_ACC_SPI5 |
31973 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 |
31974 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31975 | //GC_CAC_WEIGHT_UTCL2_ATCL2_0 |
31976 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 |
31977 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 |
31978 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL |
31979 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L |
31980 | //GC_CAC_ACC_EA0 |
31981 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 |
31982 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31983 | //GC_CAC_ACC_EA1 |
31984 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 |
31985 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31986 | //GC_CAC_ACC_EA2 |
31987 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 |
31988 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31989 | //GC_CAC_ACC_EA3 |
31990 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 |
31991 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31992 | //GC_CAC_ACC_UTCL2_ATCL20 |
31993 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 |
31994 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
31995 | //GC_CAC_OVRD_EA |
31996 | #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 |
31997 | #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 |
31998 | #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL |
31999 | #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L |
32000 | //GC_CAC_OVRD_UTCL2_ATCL2 |
32001 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 |
32002 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 |
32003 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL |
32004 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L |
32005 | //GC_CAC_WEIGHT_EA_0 |
32006 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 |
32007 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 |
32008 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL |
32009 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L |
32010 | //GC_CAC_WEIGHT_EA_1 |
32011 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 |
32012 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 |
32013 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL |
32014 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L |
32015 | //GC_CAC_WEIGHT_RMI_0 |
32016 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 |
32017 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL |
32018 | //GC_CAC_ACC_RMI0 |
32019 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 |
32020 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32021 | //GC_CAC_OVRD_RMI |
32022 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 |
32023 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 |
32024 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L |
32025 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L |
32026 | //GC_CAC_WEIGHT_UTCL2_ATCL2_1 |
32027 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 |
32028 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 |
32029 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL |
32030 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L |
32031 | //GC_CAC_ACC_UTCL2_ATCL21 |
32032 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 |
32033 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32034 | //GC_CAC_ACC_UTCL2_ATCL22 |
32035 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 |
32036 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32037 | //GC_CAC_ACC_UTCL2_ATCL23 |
32038 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 |
32039 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32040 | //GC_CAC_ACC_EA4 |
32041 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 |
32042 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32043 | //GC_CAC_ACC_EA5 |
32044 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 |
32045 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32046 | //GC_CAC_WEIGHT_EA_2 |
32047 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 |
32048 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 |
32049 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL |
32050 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L |
32051 | //GC_CAC_ACC_SQ0_LOWER |
32052 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32053 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32054 | //GC_CAC_ACC_SQ0_UPPER |
32055 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32056 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32057 | //GC_CAC_ACC_SQ1_LOWER |
32058 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32059 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32060 | //GC_CAC_ACC_SQ1_UPPER |
32061 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32062 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32063 | //GC_CAC_ACC_SQ2_LOWER |
32064 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32065 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32066 | //GC_CAC_ACC_SQ2_UPPER |
32067 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32068 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32069 | //GC_CAC_ACC_SQ3_LOWER |
32070 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32071 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32072 | //GC_CAC_ACC_SQ3_UPPER |
32073 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32074 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32075 | //GC_CAC_ACC_SQ4_LOWER |
32076 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32077 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32078 | //GC_CAC_ACC_SQ4_UPPER |
32079 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32080 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32081 | //GC_CAC_ACC_SQ5_LOWER |
32082 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32083 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32084 | //GC_CAC_ACC_SQ5_UPPER |
32085 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32086 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32087 | //GC_CAC_ACC_SQ6_LOWER |
32088 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32089 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32090 | //GC_CAC_ACC_SQ6_UPPER |
32091 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32092 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32093 | //GC_CAC_ACC_SQ7_LOWER |
32094 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32095 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32096 | //GC_CAC_ACC_SQ7_UPPER |
32097 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32098 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32099 | //GC_CAC_ACC_SQ8_LOWER |
32100 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
32101 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32102 | //GC_CAC_ACC_SQ8_UPPER |
32103 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
32104 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
32105 | //GC_CAC_ACC_SX0 |
32106 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 |
32107 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32108 | //GC_CAC_ACC_SXRB0 |
32109 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 |
32110 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32111 | //GC_CAC_ACC_SXRB1 |
32112 | #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 |
32113 | #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32114 | //GC_CAC_ACC_TA0 |
32115 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 |
32116 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32117 | //GC_CAC_ACC_TCC0 |
32118 | #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 |
32119 | #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32120 | //GC_CAC_ACC_TCC1 |
32121 | #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 |
32122 | #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32123 | //GC_CAC_ACC_TCC2 |
32124 | #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 |
32125 | #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32126 | //GC_CAC_ACC_TCC3 |
32127 | #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 |
32128 | #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32129 | //GC_CAC_ACC_TCC4 |
32130 | #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 |
32131 | #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32132 | //GC_CAC_ACC_TCP0 |
32133 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 |
32134 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32135 | //GC_CAC_ACC_TCP1 |
32136 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 |
32137 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32138 | //GC_CAC_ACC_TCP2 |
32139 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 |
32140 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32141 | //GC_CAC_ACC_TCP3 |
32142 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 |
32143 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32144 | //GC_CAC_ACC_TCP4 |
32145 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 |
32146 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32147 | //GC_CAC_ACC_TD0 |
32148 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 |
32149 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32150 | //GC_CAC_ACC_TD1 |
32151 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 |
32152 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32153 | //GC_CAC_ACC_TD2 |
32154 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 |
32155 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32156 | //GC_CAC_ACC_TD3 |
32157 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 |
32158 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32159 | //GC_CAC_ACC_TD4 |
32160 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 |
32161 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32162 | //GC_CAC_ACC_TD5 |
32163 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 |
32164 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32165 | //GC_CAC_ACC_VGT0 |
32166 | #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 |
32167 | #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32168 | //GC_CAC_ACC_VGT1 |
32169 | #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 |
32170 | #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32171 | //GC_CAC_ACC_VGT2 |
32172 | #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 |
32173 | #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32174 | //GC_CAC_ACC_WD0 |
32175 | #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 |
32176 | #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32177 | //GC_CAC_ACC_CU0 |
32178 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 |
32179 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32180 | //GC_CAC_ACC_CU1 |
32181 | #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 |
32182 | #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32183 | //GC_CAC_ACC_CU2 |
32184 | #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 |
32185 | #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32186 | //GC_CAC_ACC_CU3 |
32187 | #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 |
32188 | #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32189 | //GC_CAC_ACC_CU4 |
32190 | #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 |
32191 | #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32192 | //GC_CAC_ACC_CU5 |
32193 | #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 |
32194 | #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32195 | //GC_CAC_ACC_CU6 |
32196 | #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 |
32197 | #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32198 | //GC_CAC_ACC_CU7 |
32199 | #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 |
32200 | #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32201 | //GC_CAC_ACC_CU8 |
32202 | #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 |
32203 | #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32204 | //GC_CAC_ACC_CU9 |
32205 | #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 |
32206 | #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32207 | //GC_CAC_ACC_CU10 |
32208 | #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 |
32209 | #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32210 | //GC_CAC_ACC_CU11 |
32211 | #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0 |
32212 | #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32213 | //GC_CAC_ACC_CU12 |
32214 | #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0 |
32215 | #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32216 | //GC_CAC_ACC_CU13 |
32217 | #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0 |
32218 | #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32219 | //GC_CAC_OVRD_BCI |
32220 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 |
32221 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 |
32222 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L |
32223 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL |
32224 | //GC_CAC_OVRD_CB |
32225 | #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 |
32226 | #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 |
32227 | #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL |
32228 | #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L |
32229 | //GC_CAC_OVRD_CP |
32230 | #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 |
32231 | #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 |
32232 | #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L |
32233 | #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L |
32234 | //GC_CAC_OVRD_DB |
32235 | #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 |
32236 | #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 |
32237 | #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL |
32238 | #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L |
32239 | //GC_CAC_OVRD_GDS |
32240 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 |
32241 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 |
32242 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL |
32243 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L |
32244 | //GC_CAC_OVRD_IA |
32245 | #define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 |
32246 | #define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 |
32247 | #define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L |
32248 | #define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L |
32249 | //GC_CAC_OVRD_LDS |
32250 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 |
32251 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 |
32252 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL |
32253 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L |
32254 | //GC_CAC_OVRD_PA |
32255 | #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 |
32256 | #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 |
32257 | #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L |
32258 | #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL |
32259 | //GC_CAC_OVRD_PC |
32260 | #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 |
32261 | #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 |
32262 | #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L |
32263 | #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L |
32264 | //GC_CAC_OVRD_SC |
32265 | #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 |
32266 | #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 |
32267 | #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L |
32268 | #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L |
32269 | //GC_CAC_OVRD_SPI |
32270 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 |
32271 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 |
32272 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL |
32273 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L |
32274 | //GC_CAC_OVRD_CU |
32275 | #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 |
32276 | #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 |
32277 | #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L |
32278 | #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L |
32279 | //GC_CAC_OVRD_SQ |
32280 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 |
32281 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 |
32282 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL |
32283 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L |
32284 | //GC_CAC_OVRD_SX |
32285 | #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 |
32286 | #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 |
32287 | #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L |
32288 | #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L |
32289 | //GC_CAC_OVRD_SXRB |
32290 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 |
32291 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 |
32292 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L |
32293 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L |
32294 | //GC_CAC_OVRD_TA |
32295 | #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 |
32296 | #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 |
32297 | #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L |
32298 | #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L |
32299 | //GC_CAC_OVRD_TCC |
32300 | #define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 |
32301 | #define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 |
32302 | #define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL |
32303 | #define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L |
32304 | //GC_CAC_OVRD_TCP |
32305 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 |
32306 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 |
32307 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL |
32308 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L |
32309 | //GC_CAC_OVRD_TD |
32310 | #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 |
32311 | #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 |
32312 | #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL |
32313 | #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L |
32314 | //GC_CAC_OVRD_VGT |
32315 | #define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 |
32316 | #define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 |
32317 | #define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L |
32318 | #define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L |
32319 | //GC_CAC_OVRD_WD |
32320 | #define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 |
32321 | #define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 |
32322 | #define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L |
32323 | #define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L |
32324 | //GC_CAC_ACC_BCI1 |
32325 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 |
32326 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32327 | //GC_CAC_WEIGHT_UTCL2_ATCL2_2 |
32328 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 |
32329 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL |
32330 | //GC_CAC_WEIGHT_UTCL2_ROUTER_0 |
32331 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 |
32332 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 |
32333 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL |
32334 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L |
32335 | //GC_CAC_WEIGHT_UTCL2_ROUTER_1 |
32336 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 |
32337 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 |
32338 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL |
32339 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L |
32340 | //GC_CAC_WEIGHT_UTCL2_ROUTER_2 |
32341 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 |
32342 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 |
32343 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL |
32344 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L |
32345 | //GC_CAC_WEIGHT_UTCL2_ROUTER_3 |
32346 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 |
32347 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 |
32348 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL |
32349 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L |
32350 | //GC_CAC_WEIGHT_UTCL2_ROUTER_4 |
32351 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 |
32352 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 |
32353 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL |
32354 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L |
32355 | //GC_CAC_WEIGHT_UTCL2_VML2_0 |
32356 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 |
32357 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 |
32358 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL |
32359 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L |
32360 | //GC_CAC_WEIGHT_UTCL2_VML2_1 |
32361 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 |
32362 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 |
32363 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL |
32364 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L |
32365 | //GC_CAC_WEIGHT_UTCL2_VML2_2 |
32366 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 |
32367 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL |
32368 | //GC_CAC_ACC_UTCL2_ATCL24 |
32369 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 |
32370 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32371 | //GC_CAC_ACC_UTCL2_ROUTER0 |
32372 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 |
32373 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32374 | //GC_CAC_ACC_UTCL2_ROUTER1 |
32375 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 |
32376 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32377 | //GC_CAC_ACC_UTCL2_ROUTER2 |
32378 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 |
32379 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32380 | //GC_CAC_ACC_UTCL2_ROUTER3 |
32381 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 |
32382 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32383 | //GC_CAC_ACC_UTCL2_ROUTER4 |
32384 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 |
32385 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32386 | //GC_CAC_ACC_UTCL2_ROUTER5 |
32387 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 |
32388 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32389 | //GC_CAC_ACC_UTCL2_ROUTER6 |
32390 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 |
32391 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32392 | //GC_CAC_ACC_UTCL2_ROUTER7 |
32393 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 |
32394 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32395 | //GC_CAC_ACC_UTCL2_ROUTER8 |
32396 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 |
32397 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32398 | //GC_CAC_ACC_UTCL2_ROUTER9 |
32399 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 |
32400 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32401 | //GC_CAC_ACC_UTCL2_VML20 |
32402 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 |
32403 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32404 | //GC_CAC_ACC_UTCL2_VML21 |
32405 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 |
32406 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32407 | //GC_CAC_ACC_UTCL2_VML22 |
32408 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 |
32409 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32410 | //GC_CAC_ACC_UTCL2_VML23 |
32411 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 |
32412 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32413 | //GC_CAC_ACC_UTCL2_VML24 |
32414 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 |
32415 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32416 | //GC_CAC_OVRD_UTCL2_ROUTER |
32417 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 |
32418 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa |
32419 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL |
32420 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L |
32421 | //GC_CAC_OVRD_UTCL2_VML2 |
32422 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 |
32423 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 |
32424 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL |
32425 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L |
32426 | //GC_CAC_WEIGHT_UTCL2_WALKER_0 |
32427 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 |
32428 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 |
32429 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL |
32430 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L |
32431 | //GC_CAC_WEIGHT_UTCL2_WALKER_1 |
32432 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 |
32433 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 |
32434 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL |
32435 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L |
32436 | //GC_CAC_WEIGHT_UTCL2_WALKER_2 |
32437 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 |
32438 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL |
32439 | //GC_CAC_ACC_UTCL2_WALKER0 |
32440 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 |
32441 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32442 | //GC_CAC_ACC_UTCL2_WALKER1 |
32443 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 |
32444 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32445 | //GC_CAC_ACC_UTCL2_WALKER2 |
32446 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 |
32447 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32448 | //GC_CAC_ACC_UTCL2_WALKER3 |
32449 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 |
32450 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32451 | //GC_CAC_ACC_UTCL2_WALKER4 |
32452 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 |
32453 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
32454 | //GC_CAC_OVRD_UTCL2_WALKER |
32455 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 |
32456 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 |
32457 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL |
32458 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L |
32459 | //EDC_STALL_PATTERN_1_2 |
32460 | #define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
32461 | #define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
32462 | #define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
32463 | #define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
32464 | //EDC_STALL_PATTERN_3_4 |
32465 | #define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
32466 | #define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
32467 | #define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
32468 | #define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
32469 | //EDC_STALL_PATTERN_5_6 |
32470 | #define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
32471 | #define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
32472 | #define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
32473 | #define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
32474 | //EDC_STALL_PATTERN_7 |
32475 | #define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
32476 | #define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
32477 | //PCC_STALL_PATTERN_1_2 |
32478 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 |
32479 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 |
32480 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL |
32481 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L |
32482 | //PCC_STALL_PATTERN_3_4 |
32483 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 |
32484 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 |
32485 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL |
32486 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L |
32487 | //PCC_STALL_PATTERN_5_6 |
32488 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 |
32489 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 |
32490 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL |
32491 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L |
32492 | //PCC_STALL_PATTERN_7 |
32493 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 |
32494 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL |
32495 | //PCC_THROT_REINCR_FIRST_PATN_1_8 |
32496 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
32497 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
32498 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
32499 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT 0xc |
32500 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
32501 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
32502 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
32503 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
32504 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
32505 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
32506 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
32507 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
32508 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
32509 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
32510 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
32511 | #define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
32512 | //PCC_THROT_REINCR_FIRST_PATN_9_16 |
32513 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
32514 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
32515 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
32516 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT 0xc |
32517 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
32518 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
32519 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
32520 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
32521 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
32522 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
32523 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
32524 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
32525 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
32526 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
32527 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
32528 | #define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
32529 | //PCC_THROT_REINCR_FIRST_PATN_17_20 |
32530 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
32531 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
32532 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
32533 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT 0xc |
32534 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
32535 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
32536 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
32537 | #define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
32538 | //PCC_THROT_DECR_FIRST_PATN_1_4 |
32539 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
32540 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
32541 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
32542 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
32543 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
32544 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
32545 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
32546 | #define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
32547 | //PCC_THROT_DECR_FIRST_PATN_5_7 |
32548 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
32549 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
32550 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
32551 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
32552 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
32553 | #define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
32554 | //PWRBRK_STALL_PATTERN_CTRL |
32555 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 |
32556 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa |
32557 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf |
32558 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
32559 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL |
32560 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L |
32561 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L |
32562 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
32563 | //PWRBRK_STALL_PATTERN_1_2 |
32564 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 |
32565 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 |
32566 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL |
32567 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L |
32568 | //PWRBRK_STALL_PATTERN_3_4 |
32569 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 |
32570 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 |
32571 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL |
32572 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L |
32573 | //PWRBRK_STALL_PATTERN_5_6 |
32574 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 |
32575 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 |
32576 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL |
32577 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L |
32578 | //PWRBRK_STALL_PATTERN_7 |
32579 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 |
32580 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL |
32581 | //PCC_PWRBRK_HYSTERESIS_CTRL |
32582 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x0 |
32583 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x000000FFL |
32584 | //FIXED_PATTERN_PERF_COUNTER_CTRL |
32585 | #define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x0 |
32586 | #define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x1 |
32587 | #define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00000001L |
32588 | #define FIXED_PATTERN_PERF_COUNTER_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x0000003EL |
32589 | //FIXED_PATTERN_PERF_COUNTER_1 |
32590 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 |
32591 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL |
32592 | //FIXED_PATTERN_PERF_COUNTER_2 |
32593 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 |
32594 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL |
32595 | //FIXED_PATTERN_PERF_COUNTER_3 |
32596 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 |
32597 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL |
32598 | //FIXED_PATTERN_PERF_COUNTER_4 |
32599 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 |
32600 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL |
32601 | //FIXED_PATTERN_PERF_COUNTER_5 |
32602 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 |
32603 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL |
32604 | //FIXED_PATTERN_PERF_COUNTER_6 |
32605 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 |
32606 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL |
32607 | //FIXED_PATTERN_PERF_COUNTER_7 |
32608 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 |
32609 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL |
32610 | //FIXED_PATTERN_PERF_COUNTER_8 |
32611 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 |
32612 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL |
32613 | //FIXED_PATTERN_PERF_COUNTER_9 |
32614 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 |
32615 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL |
32616 | //FIXED_PATTERN_PERF_COUNTER_10 |
32617 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 |
32618 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL |
32619 | |
32620 | |
32621 | |
32622 | |
32623 | // addressBlock: secacind |
32624 | //SE_CAC_CNTL |
32625 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
32626 | #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
32627 | #define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 |
32628 | #define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 |
32629 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
32630 | #define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
32631 | #define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L |
32632 | #define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L |
32633 | //SE_CAC_OVR_SEL |
32634 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
32635 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
32636 | //SE_CAC_OVR_VAL |
32637 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
32638 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
32639 | |
32640 | |
32641 | // addressBlock: sqind |
32642 | //SQ_DEBUG_STS_LOCAL |
32643 | #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 |
32644 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 |
32645 | #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L |
32646 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L |
32647 | //SQ_DEBUG_CTRL_LOCAL |
32648 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 |
32649 | #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE__SHIFT 0x8 |
32650 | #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE__SHIFT 0x9 |
32651 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL |
32652 | #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_NON_WAVE_MASK 0x00000100L |
32653 | #define SQ_DEBUG_CTRL_LOCAL__PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE_MASK 0x00000200L |
32654 | //SQ_WAVE_VALID_AND_IDLE |
32655 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 |
32656 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0xFFFFFFFFL |
32657 | //SQ_WAVE_MODE |
32658 | #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 |
32659 | #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 |
32660 | #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 |
32661 | #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 |
32662 | #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa |
32663 | #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc |
32664 | #define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 |
32665 | #define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 |
32666 | #define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 |
32667 | #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a |
32668 | #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b |
32669 | #define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c |
32670 | #define SQ_WAVE_MODE__CSP__SHIFT 0x1d |
32671 | #define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL |
32672 | #define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L |
32673 | #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L |
32674 | #define SQ_WAVE_MODE__IEEE_MASK 0x00000200L |
32675 | #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L |
32676 | #define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L |
32677 | #define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L |
32678 | #define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L |
32679 | #define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L |
32680 | #define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L |
32681 | #define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L |
32682 | #define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L |
32683 | #define SQ_WAVE_MODE__CSP_MASK 0xE0000000L |
32684 | //SQ_WAVE_STATUS |
32685 | #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 |
32686 | #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 |
32687 | #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 |
32688 | #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 |
32689 | #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 |
32690 | #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 |
32691 | #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 |
32692 | #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 |
32693 | #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa |
32694 | #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb |
32695 | #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc |
32696 | #define SQ_WAVE_STATUS__HALT__SHIFT 0xd |
32697 | #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe |
32698 | #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf |
32699 | #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 |
32700 | #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 |
32701 | #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 |
32702 | #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 |
32703 | #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 |
32704 | #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 |
32705 | #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b |
32706 | #define SQ_WAVE_STATUS__SCC_MASK 0x00000001L |
32707 | #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L |
32708 | #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L |
32709 | #define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L |
32710 | #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L |
32711 | #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L |
32712 | #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L |
32713 | #define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L |
32714 | #define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L |
32715 | #define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L |
32716 | #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L |
32717 | #define SQ_WAVE_STATUS__HALT_MASK 0x00002000L |
32718 | #define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L |
32719 | #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L |
32720 | #define SQ_WAVE_STATUS__VALID_MASK 0x00010000L |
32721 | #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L |
32722 | #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L |
32723 | #define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L |
32724 | #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L |
32725 | #define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L |
32726 | #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L |
32727 | //SQ_WAVE_TRAPSTS |
32728 | #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 |
32729 | #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa |
32730 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb |
32731 | #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc |
32732 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 |
32733 | #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c |
32734 | #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d |
32735 | #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL |
32736 | #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L |
32737 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L |
32738 | #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L |
32739 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L |
32740 | #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L |
32741 | #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L |
32742 | //SQ_WAVE_HW_ID |
32743 | #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 |
32744 | #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 |
32745 | #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 |
32746 | #define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 |
32747 | #define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc |
32748 | #define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd |
32749 | #define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 |
32750 | #define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 |
32751 | #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 |
32752 | #define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b |
32753 | #define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e |
32754 | #define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL |
32755 | #define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L |
32756 | #define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L |
32757 | #define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L |
32758 | #define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L |
32759 | #define SQ_WAVE_HW_ID__SE_ID_MASK 0x0000E000L |
32760 | #define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L |
32761 | #define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L |
32762 | #define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L |
32763 | #define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L |
32764 | #define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L |
32765 | //SQ_WAVE_GPR_ALLOC |
32766 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 |
32767 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x6 |
32768 | #define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET__SHIFT 0xc |
32769 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x12 |
32770 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 |
32771 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL |
32772 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00000FC0L |
32773 | #define SQ_WAVE_GPR_ALLOC__ACCV_OFFSET_MASK 0x0003F000L |
32774 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FC0000L |
32775 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L |
32776 | //SQ_WAVE_LDS_ALLOC |
32777 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 |
32778 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc |
32779 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL |
32780 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L |
32781 | //SQ_WAVE_IB_STS |
32782 | #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 |
32783 | #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 |
32784 | #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 |
32785 | #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc |
32786 | #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf |
32787 | #define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 |
32788 | #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 |
32789 | #define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL |
32790 | #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L |
32791 | #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L |
32792 | #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L |
32793 | #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L |
32794 | #define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L |
32795 | #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L |
32796 | //SQ_WAVE_PC_LO |
32797 | #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 |
32798 | #define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL |
32799 | //SQ_WAVE_PC_HI |
32800 | #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 |
32801 | #define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL |
32802 | //SQ_WAVE_INST_DW0 |
32803 | #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 |
32804 | #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL |
32805 | //SQ_WAVE_INST_DW1 |
32806 | #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 |
32807 | #define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL |
32808 | //SQ_WAVE_IB_DBG0 |
32809 | #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 |
32810 | #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 |
32811 | #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 |
32812 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 |
32813 | #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 |
32814 | #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa |
32815 | #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 |
32816 | #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 |
32817 | #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a |
32818 | #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b |
32819 | #define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d |
32820 | #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e |
32821 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f |
32822 | #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L |
32823 | #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L |
32824 | #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L |
32825 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L |
32826 | #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L |
32827 | #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L |
32828 | #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L |
32829 | #define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L |
32830 | #define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L |
32831 | #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L |
32832 | #define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L |
32833 | #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L |
32834 | #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L |
32835 | //SQ_WAVE_IB_DBG1 |
32836 | #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 |
32837 | #define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 |
32838 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 |
32839 | #define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 |
32840 | #define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb |
32841 | #define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 |
32842 | #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 |
32843 | #define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L |
32844 | #define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L |
32845 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L |
32846 | #define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L |
32847 | #define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L |
32848 | #define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L |
32849 | #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L |
32850 | //SQ_WAVE_FLUSH_IB |
32851 | #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 |
32852 | #define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL |
32853 | //SQ_WAVE_TTMP0 |
32854 | #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 |
32855 | #define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL |
32856 | //SQ_WAVE_TTMP1 |
32857 | #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 |
32858 | #define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL |
32859 | //SQ_WAVE_TTMP3 |
32860 | #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 |
32861 | #define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL |
32862 | //SQ_WAVE_TTMP4 |
32863 | #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 |
32864 | #define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL |
32865 | //SQ_WAVE_TTMP5 |
32866 | #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 |
32867 | #define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL |
32868 | //SQ_WAVE_TTMP6 |
32869 | #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 |
32870 | #define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL |
32871 | //SQ_WAVE_TTMP7 |
32872 | #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 |
32873 | #define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL |
32874 | //SQ_WAVE_TTMP8 |
32875 | #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 |
32876 | #define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL |
32877 | //SQ_WAVE_TTMP9 |
32878 | #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 |
32879 | #define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL |
32880 | //SQ_WAVE_TTMP10 |
32881 | #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 |
32882 | #define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL |
32883 | //SQ_WAVE_TTMP11 |
32884 | #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 |
32885 | #define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL |
32886 | //SQ_WAVE_TTMP12 |
32887 | #define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 |
32888 | #define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL |
32889 | //SQ_WAVE_TTMP13 |
32890 | #define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 |
32891 | #define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL |
32892 | //SQ_WAVE_TTMP14 |
32893 | #define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 |
32894 | #define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL |
32895 | //SQ_WAVE_TTMP15 |
32896 | #define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 |
32897 | #define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL |
32898 | //SQ_WAVE_M0 |
32899 | #define SQ_WAVE_M0__M0__SHIFT 0x0 |
32900 | #define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL |
32901 | //SQ_WAVE_EXEC_LO |
32902 | #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 |
32903 | #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL |
32904 | //SQ_WAVE_EXEC_HI |
32905 | #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 |
32906 | #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL |
32907 | //SQ_INTERRUPT_WORD_AUTO_CTXID |
32908 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 |
32909 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 |
32910 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 |
32911 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 |
32912 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 |
32913 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 |
32914 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 |
32915 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 |
32916 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 |
32917 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 |
32918 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a |
32919 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L |
32920 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L |
32921 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L |
32922 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L |
32923 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L |
32924 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L |
32925 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L |
32926 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L |
32927 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L |
32928 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L |
32929 | #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L |
32930 | //SQ_INTERRUPT_WORD_AUTO_HI |
32931 | #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 |
32932 | #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa |
32933 | #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L |
32934 | #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L |
32935 | //SQ_INTERRUPT_WORD_AUTO_LO |
32936 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 |
32937 | #define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 |
32938 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 |
32939 | #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 |
32940 | #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 |
32941 | #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 |
32942 | #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 |
32943 | #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 |
32944 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 |
32945 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L |
32946 | #define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L |
32947 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L |
32948 | #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L |
32949 | #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L |
32950 | #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L |
32951 | #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L |
32952 | #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L |
32953 | #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L |
32954 | //SQ_INTERRUPT_WORD_CMN_CTXID |
32955 | #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 |
32956 | #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a |
32957 | #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L |
32958 | #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L |
32959 | //SQ_INTERRUPT_WORD_CMN_HI |
32960 | #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 |
32961 | #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa |
32962 | #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L |
32963 | #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L |
32964 | //SQ_INTERRUPT_WORD_WAVE_CTXID |
32965 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 |
32966 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc |
32967 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd |
32968 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe |
32969 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 |
32970 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 |
32971 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 |
32972 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a |
32973 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL |
32974 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L |
32975 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L |
32976 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L |
32977 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L |
32978 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L |
32979 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L |
32980 | #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L |
32981 | //SQ_INTERRUPT_WORD_WAVE_HI |
32982 | #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 |
32983 | #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 |
32984 | #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 |
32985 | #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa |
32986 | #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL |
32987 | #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L |
32988 | #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L |
32989 | #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L |
32990 | //SQ_INTERRUPT_WORD_WAVE_LO |
32991 | #define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 |
32992 | #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 |
32993 | #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 |
32994 | #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a |
32995 | #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e |
32996 | #define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL |
32997 | #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L |
32998 | #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L |
32999 | #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L |
33000 | #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L |
33001 | |
33002 | |
33003 | #endif |
33004 | |