1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GMC_6_0_SH_MASK_H
24#define GMC_6_0_SH_MASK_H
25
26#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
36#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x00000004L
37#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x00000002
38#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x00004000L
39#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0x0000000e
40#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x00000080L
41#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x00000007
42#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x00000002L
43#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x00000001
44#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x00008000L
45#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0x0000000f
46#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x00000001L
47#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x00000000
48#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x00010000L
49#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x00000010
50#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x00003c00L
51#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0x0000000a
52#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x00000100L
53#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x00000008
54#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x00000020L
55#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x00000005
56#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x00000040L
57#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x00000006
58#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x00000200L
59#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x00000009
60#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x0000003cL
61#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x00000002
62#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x00000001L
63#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x00000000
64#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffffL
65#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x00000000
66#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x03f00000L
67#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x00000014
68#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0000fc00L
69#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0x0000000a
70#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x0000003fL
71#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x00000000
72#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000100L
73#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x00000008
74#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x00010000L
75#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x00000010
76#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x0000001fL
77#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x00000000
78#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffffL
79#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x00000000
80#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L
81#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x00000010
82#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L
83#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0x0000000f
84#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x0000003fL
85#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x00000000
86#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L
87#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x00000011
88#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0f000000L
89#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x00000018
90#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L
91#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x00000012
92#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00f80000L
93#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x00000013
94#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007c00L
95#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0x0000000a
96#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L
97#define ATC_ATS_STATUS__BUSY__SHIFT 0x00000000
98#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L
99#define ATC_ATS_STATUS__CRASHED__SHIFT 0x00000001
100#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L
101#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000002
102#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffffL
103#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x00000000
104#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x00000003L
105#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x00000000
106#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x00000004L
107#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x00000002
108#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x00000010L
109#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x00000004
110#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
111#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
112#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
113#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
114#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
115#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
116#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
117#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
118#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
119#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
120#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
121#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
122#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
123#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
124#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x00000100L
125#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
126#define ATC_L1RD_STATUS__BUSY_MASK 0x00000001L
127#define ATC_L1RD_STATUS__BUSY__SHIFT 0x00000000
128#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
129#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
130#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x0003f000L
131#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0x0000000c
132#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0x0ff00000L
133#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x00000014
134#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000L
135#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x0000001c
136#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x00000001L
137#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x00000000
138#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0x000000f0L
139#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x00000004
140#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
141#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x00000008
142#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000L
143#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x0000001e
144#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x00000100L
145#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x00000008
146#define ATC_L1WR_STATUS__BUSY_MASK 0x00000001L
147#define ATC_L1WR_STATUS__BUSY__SHIFT 0x00000000
148#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x00000002L
149#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x00000001
150#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
151#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x00000000
152#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L
153#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000a
154#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000030L
155#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x00000004
156#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L
157#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x0000000b
158#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x0000003fL
159#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x00000000
160#define ATC_MISC_CG__ENABLE_MASK 0x00040000L
161#define ATC_MISC_CG__ENABLE__SHIFT 0x00000012
162#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
163#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x00000013
164#define ATC_MISC_CG__OFFDLY_MASK 0x00000fc0L
165#define ATC_MISC_CG__OFFDLY__SHIFT 0x00000006
166#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
167#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
168#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
169#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
170#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
171#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
172#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
173#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
174#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0x0000ffffL
175#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x00000000
176#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x00000003L
177#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x00000000
178#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
179#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
180#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0x0fffffffL
181#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x00000000
182#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000ffffL
183#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x00000000
184#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L
185#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x0000001f
186#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000ffffL
187#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x00000000
188#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L
189#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x0000001f
190#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000ffffL
191#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x00000000
192#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L
193#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x0000001f
194#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000ffffL
195#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x00000000
196#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L
197#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x0000001f
198#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000ffffL
199#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x00000000
200#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L
201#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x0000001f
202#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000ffffL
203#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x00000000
204#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L
205#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x0000001f
206#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000ffffL
207#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x00000000
208#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L
209#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x0000001f
210#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000ffffL
211#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x00000000
212#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L
213#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x0000001f
214#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000ffffL
215#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x00000000
216#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L
217#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x0000001f
218#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000ffffL
219#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x00000000
220#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L
221#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x0000001f
222#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000ffffL
223#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x00000000
224#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L
225#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x0000001f
226#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000ffffL
227#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x00000000
228#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L
229#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x0000001f
230#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000ffffL
231#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x00000000
232#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L
233#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x0000001f
234#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000ffffL
235#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x00000000
236#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L
237#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x0000001f
238#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000ffffL
239#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x00000000
240#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L
241#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x0000001f
242#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000ffffL
243#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x00000000
244#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L
245#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x0000001f
246#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L
247#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x00000000
248#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L
249#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0x0000000a
250#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L
251#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0x0000000b
252#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L
253#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0x0000000c
254#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L
255#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0x0000000d
256#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L
257#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0x0000000e
258#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L
259#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0x0000000f
260#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L
261#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x00000001
262#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L
263#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x00000002
264#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L
265#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x00000003
266#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L
267#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x00000004
268#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L
269#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x00000005
270#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L
271#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x00000006
272#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L
273#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x00000007
274#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L
275#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x00000008
276#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L
277#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x00000009
278#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x0000001eL
279#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x00000001
280#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x003ff000L
281#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0x0000000c
282#define DLL_CNTL__DLL_RESET_TIME_MASK 0x000003ffL
283#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x00000000
284#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x01000000L
285#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x00000018
286#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x02000000L
287#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x00000019
288#define DLL_CNTL__PWR2_MODE_MASK 0x04000000L
289#define DLL_CNTL__PWR2_MODE__SHIFT 0x0000001a
290#define GMCON_DEBUG__GFX_CLEAR_MASK 0x00000002L
291#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x00000001
292#define GMCON_DEBUG__GFX_STALL_MASK 0x00000001L
293#define GMCON_DEBUG__GFX_STALL__SHIFT 0x00000000
294#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffcL
295#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x00000002
296#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x00000007L
297#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x00000000
298#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x00000038L
299#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x00000003
300#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x0000fc00L
301#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0x0000000a
302#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x20000000L
303#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x0000001d
304#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x10000000L
305#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x0000001c
306#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x0fff0000L
307#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x00000010
308#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x0000003fL
309#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x00000000
310#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0x00000fc0L
311#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x00000006
312#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00fff000L
313#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x0000000c
314#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000L
315#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0000001c
316#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x08000000L
317#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x0000001b
318#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x00000400L
319#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0x0000000a
320#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00000800L
321#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x0000000b
322#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0x0000f000L
323#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0x0000000c
324#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x02000000L
325#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x00000019
326#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x04000000L
327#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x0000001a
328#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x40000000L
329#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x0000001e
330#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x00060000L
331#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x00000011
332#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x00400000L
333#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x00000016
334#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x00200000L
335#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x00000015
336#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x01000000L
337#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x00000018
338#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x00800000L
339#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x00000017
340#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x00180000L
341#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x00000013
342#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x00010000L
343#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x00000010
344#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000L
345#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x0000001c
346#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x03000000L
347#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x00000018
348#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0x00000fffL
349#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x00000000
350#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0x0c000000L
351#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x0000001a
352#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0x00fff000L
353#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0x0000000c
354#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x00fc0000L
355#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x00000012
356#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000L
357#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x00000018
358#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0x00000fc0L
359#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x00000006
360#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x0003f000L
361#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x0000000c
362#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x0000003fL
363#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x00000000
364#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffffL
365#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x00000000
366#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffffL
367#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x00000000
368#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000ffL
369#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x00000000
370#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
371#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0x0000000a
372#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
373#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0x0000000b
374#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
375#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x00000008
376#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
377#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x00000009
378#define GMCON_PGFSM_CONFIG__READ_MASK 0x00002000L
379#define GMCON_PGFSM_CONFIG__READ__SHIFT 0x0000000d
380#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000L
381#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x0000001c
382#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x07ffc000L
383#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0x0000000e
384#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
385#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x0000001b
386#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x00001000L
387#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0x0000000c
388#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0x0f000000L
389#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x00000018
390#define GMCON_PGFSM_READ__READ_VALUE_MASK 0x00ffffffL
391#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x00000000
392#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000L
393#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x0000001c
394#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffffL
395#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x00000000
396#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x003ff000L
397#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0x0000000c
398#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000L
399#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x00000016
400#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L
401#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x00000001
402#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000ffcL
403#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x00000002
404#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L
405#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x00000000
406#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffffL
407#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x00000000
408#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003ffL
409#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x00000000
410#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000ffffL
411#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x00000000
412#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000L
413#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x00000010
414#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000ffffL
415#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x00000000
416#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000L
417#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x00000010
418#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0x0000ffffL
419#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x00000000
420#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000L
421#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x00000010
422#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0x0000ffffL
423#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x00000000
424#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000L
425#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x00000010
426#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0x0000ffffL
427#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x00000000
428#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000L
429#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x00000010
430#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0x0000000fL
431#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x00000000
432#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0x00000ff0L
433#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x00000004
434#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0x0ffff000L
435#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0x0000000c
436#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x01000000L
437#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x00000018
438#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x02000000L
439#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x00000019
440#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x04000000L
441#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x0000001a
442#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x08000000L
443#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x0000001b
444#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000L
445#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x0000001c
446#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000L
447#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x0000001d
448#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000L
449#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x0000001e
450#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000L
451#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x0000001f
452#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x00010000L
453#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x00000010
454#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x00020000L
455#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x00000011
456#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x00040000L
457#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x00000012
458#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x00080000L
459#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x00000013
460#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x00100000L
461#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x00000014
462#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x00200000L
463#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x00000015
464#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x00400000L
465#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x00000016
466#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x00800000L
467#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x00000017
468#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x00000003L
469#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x00000000
470#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0x0000000cL
471#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x00000002
472#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x00000030L
473#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x00000004
474#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0x000000c0L
475#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x00000006
476#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x00000300L
477#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x00000008
478#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0x00000c00L
479#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0x0000000a
480#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x00003000L
481#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0x0000000c
482#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0x0000c000L
483#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0x0000000e
484#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x01000000L
485#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x00000018
486#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x02000000L
487#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x00000019
488#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x04000000L
489#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x0000001a
490#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x08000000L
491#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x0000001b
492#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000L
493#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x0000001c
494#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000L
495#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x0000001d
496#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000L
497#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x0000001e
498#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000L
499#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x0000001f
500#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x00010000L
501#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x00000010
502#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x00020000L
503#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x00000011
504#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x00040000L
505#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x00000012
506#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x00080000L
507#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x00000013
508#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x00100000L
509#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x00000014
510#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x00200000L
511#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x00000015
512#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x00400000L
513#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x00000016
514#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x00800000L
515#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x00000017
516#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x00000003L
517#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x00000000
518#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0x0000000cL
519#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x00000002
520#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x00000030L
521#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x00000004
522#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0x000000c0L
523#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x00000006
524#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x00000300L
525#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x00000008
526#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0x00000c00L
527#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0x0000000a
528#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x00003000L
529#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0x0000000c
530#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0x0000c000L
531#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0x0000000e
532#define MC_ARB_BANKMAP__BANK0_MASK 0x0000000fL
533#define MC_ARB_BANKMAP__BANK0__SHIFT 0x00000000
534#define MC_ARB_BANKMAP__BANK1_MASK 0x000000f0L
535#define MC_ARB_BANKMAP__BANK1__SHIFT 0x00000004
536#define MC_ARB_BANKMAP__BANK2_MASK 0x00000f00L
537#define MC_ARB_BANKMAP__BANK2__SHIFT 0x00000008
538#define MC_ARB_BANKMAP__BANK3_MASK 0x0000f000L
539#define MC_ARB_BANKMAP__BANK3__SHIFT 0x0000000c
540#define MC_ARB_BANKMAP__RANK_MASK 0x000f0000L
541#define MC_ARB_BANKMAP__RANK__SHIFT 0x00000010
542#define MC_ARB_BURST_TIME__STATE0_MASK 0x0000001fL
543#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x00000000
544#define MC_ARB_BURST_TIME__STATE1_MASK 0x000003e0L
545#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x00000005
546#define MC_ARB_BURST_TIME__STATE2_MASK 0x00007c00L
547#define MC_ARB_BURST_TIME__STATE2__SHIFT 0x0000000a
548#define MC_ARB_BURST_TIME__STATE3_MASK 0x000f8000L
549#define MC_ARB_BURST_TIME__STATE3__SHIFT 0x0000000f
550#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x00002000L
551#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0x0000000d
552#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x00000001L
553#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x00000000
554#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x0000007eL
555#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x00000001
556#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x00001f80L
557#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x00000007
558#define MC_ARB_CG__CG_ARB_REQ_MASK 0x000000ffL
559#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x00000000
560#define MC_ARB_CG__CG_ARB_RESP_MASK 0x0000ff00L
561#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x00000008
562#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0x000000ffL
563#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x00000000
564#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0x0000ff00L
565#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x00000008
566#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0x00ff0000L
567#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x00000010
568#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000L
569#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x00000018
570#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000L
571#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x00000018
572#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0x000000ffL
573#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x00000000
574#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0x0000ff00L
575#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x00000008
576#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0x00ff0000L
577#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x00000010
578#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000L
579#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x00000018
580#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0x000000ffL
581#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x00000000
582#define MC_ARB_DRAM_TIMING2__RP_MASK 0x0000ff00L
583#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x00000008
584#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0x00ff0000L
585#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x00000010
586#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0x000000ffL
587#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x00000000
588#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0x0000ff00L
589#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x00000008
590#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0x00ff0000L
591#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x00000010
592#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000L
593#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x00000018
594#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x00000010L
595#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x00000004
596#define MC_ARB_FED_CNTL__MODE_MASK 0x00000003L
597#define MC_ARB_FED_CNTL__MODE__SHIFT 0x00000000
598#define MC_ARB_FED_CNTL__WR_ERR_MASK 0x0000000cL
599#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x00000002
600#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0x0000000fL
601#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x00000000
602#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0x000000f0L
603#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x00000004
604#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
605#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
606#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x00000100L
607#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x00000008
608#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x00000200L
609#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x00000009
610#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0x0000000fL
611#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x00000000
612#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0x000000f0L
613#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x00000004
614#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x00003c00L
615#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0x0000000a
616#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x00000100L
617#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x00000008
618#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x00000200L
619#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x00000009
620#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0x000000ffL
621#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x00000000
622#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0x0000ff00L
623#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x00000008
624#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0x00ff0000L
625#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x00000010
626#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000L
627#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x00000018
628#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x00004000L
629#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0x0000000e
630#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x001f8000L
631#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0x0000000f
632#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0x0000ff00L
633#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x00000008
634#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0x00ff0000L
635#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x00000010
636#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000L
637#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x00000018
638#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0x000000ffL
639#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x00000000
640#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x00000018L
641#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x00000003
642#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x00000004L
643#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x00000002
644#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x00000003L
645#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x00000000
646#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x00000020L
647#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x00000005
648#define MC_ARB_GECC2__ECC_MODE_MASK 0x00000006L
649#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x00000001
650#define MC_ARB_GECC2__ENABLE_MASK 0x00000001L
651#define MC_ARB_GECC2__ENABLE__SHIFT 0x00000000
652#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x00000060L
653#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x00000005
654#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0x0000000fL
655#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x00000000
656#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x00000780L
657#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x00000007
658#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x00000018L
659#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x00000003
660#define MC_ARB_GECC2__READ_ERR_MASK 0x00003800L
661#define MC_ARB_GECC2__READ_ERR__SHIFT 0x0000000b
662#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x00000100L
663#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x00000008
664#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x00001000L
665#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0x0000000c
666#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x00000001L
667#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x00000000
668#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x00000010L
669#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x00000004
670#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x00000400L
671#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0x0000000a
672#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x00004000L
673#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0x0000000e
674#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x00000004L
675#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x00000002
676#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x00000040L
677#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x00000006
678#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x00000008L
679#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x00000003
680#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x00000080L
681#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x00000007
682#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x00000800L
683#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0x0000000b
684#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x00000200L
685#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x00000009
686#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x00002000L
687#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0x0000000d
688#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x00000002L
689#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x00000001
690#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x00000020L
691#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x00000005
692#define MC_ARB_LAZY0_RD__GROUP0_MASK 0x000000ffL
693#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x00000000
694#define MC_ARB_LAZY0_RD__GROUP1_MASK 0x0000ff00L
695#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x00000008
696#define MC_ARB_LAZY0_RD__GROUP2_MASK 0x00ff0000L
697#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x00000010
698#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000L
699#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x00000018
700#define MC_ARB_LAZY0_WR__GROUP0_MASK 0x000000ffL
701#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x00000000
702#define MC_ARB_LAZY0_WR__GROUP1_MASK 0x0000ff00L
703#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x00000008
704#define MC_ARB_LAZY0_WR__GROUP2_MASK 0x00ff0000L
705#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x00000010
706#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000L
707#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x00000018
708#define MC_ARB_LAZY1_RD__GROUP4_MASK 0x000000ffL
709#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x00000000
710#define MC_ARB_LAZY1_RD__GROUP5_MASK 0x0000ff00L
711#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x00000008
712#define MC_ARB_LAZY1_RD__GROUP6_MASK 0x00ff0000L
713#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x00000010
714#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000L
715#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x00000018
716#define MC_ARB_LAZY1_WR__GROUP4_MASK 0x000000ffL
717#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x00000000
718#define MC_ARB_LAZY1_WR__GROUP5_MASK 0x0000ff00L
719#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x00000008
720#define MC_ARB_LAZY1_WR__GROUP6_MASK 0x00ff0000L
721#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x00000010
722#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000L
723#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x00000018
724#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0x00e00000L
725#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x00000015
726#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x00040000L
727#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x00000012
728#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x00080000L
729#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
730#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x00100000L
731#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x00000014
732#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x00010000L
733#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x00000010
734#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0x000000ffL
735#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x00000000
736#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0x0000ff00L
737#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x00000008
738#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x00020000L
739#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x00000011
740#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0x00e00000L
741#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x00000015
742#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x00040000L
743#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x00000012
744#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x00080000L
745#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x00000013
746#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x00100000L
747#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x00000014
748#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x00010000L
749#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x00000010
750#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0x000000ffL
751#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x00000000
752#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0x0000ff00L
753#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x00000008
754#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x00020000L
755#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x00000011
756#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x00010000L
757#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x00000010
758#define MC_ARB_MINCLKS__READ_CLKS_MASK 0x000000ffL
759#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x00000000
760#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0x0000ff00L
761#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x00000008
762#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000L
763#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x0000001d
764#define MC_ARB_MISC2__GECC_MASK 0x00040000L
765#define MC_ARB_MISC2__GECC_RST_MASK 0x00080000L
766#define MC_ARB_MISC2__GECC_RST__SHIFT 0x00000013
767#define MC_ARB_MISC2__GECC__SHIFT 0x00000012
768#define MC_ARB_MISC2__GECC_STATUS_MASK 0x00100000L
769#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x00000014
770#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x00000800L
771#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0x0000000b
772#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x00002000L
773#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0x0000000d
774#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x00001000L
775#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0x0000000c
776#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x0003c000L
777#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0x0000000e
778#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000L
779#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x0000001c
780#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000L
781#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x0000001e
782#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x01e00000L
783#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x00000015
784#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x00000040L
785#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x00000006
786#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x00000080L
787#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x00000007
788#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x00000100L
789#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x00000008
790#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x00000200L
791#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x00000009
792#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x00000400L
793#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0x0000000a
794#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x00000020L
795#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x00000005
796#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000L
797#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x0000001f
798#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0x0e000000L
799#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x00000019
800#define MC_ARB_MISC__CALI_ENABLE_MASK 0x00100000L
801#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x00000014
802#define MC_ARB_MISC__CALI_RATES_MASK 0x00600000L
803#define MC_ARB_MISC__CALI_RATES__SHIFT 0x00000015
804#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x000007f8L
805#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x00000003
806#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x01000000L
807#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x00000018
808#define MC_ARB_MISC__DISPURG_STALL_MASK 0x02000000L
809#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x00000019
810#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000L
811#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x0000001a
812#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x00800000L
813#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x00000017
814#define MC_ARB_MISC__HARSHNESS_MASK 0x0007f800L
815#define MC_ARB_MISC__HARSHNESS__SHIFT 0x0000000b
816#define MC_ARB_MISC__IDLE_RFSH_MASK 0x00000002L
817#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x00000001
818#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x00080000L
819#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x00000013
820#define MC_ARB_MISC__STICKY_RFSH_MASK 0x00000001L
821#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x00000000
822#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x00000004L
823#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x00000002
824#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x00000020L
825#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x00000005
826#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0x00f00000L
827#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x00000014
828#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x00000040L
829#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x00000006
830#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x00040000L
831#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x00000012
832#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x00080000L
833#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x00000013
834#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x00000003L
835#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x00000000
836#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x00000004L
837#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x00000002
838#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x00000008L
839#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x00000003
840#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x00000080L
841#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x00000007
842#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x00000300L
843#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x00000008
844#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x00000400L
845#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0x0000000a
846#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x00000800L
847#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b
848#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x00004000L
849#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0x0000000e
850#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L
851#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0x0000000f
852#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x00001000L
853#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0x0000000c
854#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x00002000L
855#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0x0000000d
856#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x00000010L
857#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x00000004
858#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x00080000L
859#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x00000013
860#define MC_ARB_POP__ENABLE_ARB_MASK 0x00000001L
861#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x00000000
862#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x00040000L
863#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x00000012
864#define MC_ARB_POP__POP_DEPTH_MASK 0x0000003cL
865#define MC_ARB_POP__POP_DEPTH__SHIFT 0x00000002
866#define MC_ARB_POP__QUICK_STOP_MASK 0x00020000L
867#define MC_ARB_POP__QUICK_STOP__SHIFT 0x00000011
868#define MC_ARB_POP__SKID_DEPTH_MASK 0x00007000L
869#define MC_ARB_POP__SKID_DEPTH__SHIFT 0x0000000c
870#define MC_ARB_POP__SPEC_OPEN_MASK 0x00000002L
871#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x00000001
872#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x00018000L
873#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0x0000000f
874#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0x00000fc0L
875#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x00000006
876#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x00000100L
877#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x00000008
878#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x00000003L
879#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x00000000
880#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0x000000c0L
881#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x00000006
882#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x00001000L
883#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0x0000000c
884#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x00000004L
885#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x00000002
886#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x00000038L
887#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x00000003
888#define MC_ARB_REMREQ__RD_WATER_MASK 0x000000ffL
889#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x00000000
890#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0x00f00000L
891#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x00000014
892#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0x000f0000L
893#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x00000010
894#define MC_ARB_REMREQ__WR_WATER_MASK 0x0000ff00L
895#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x00000008
896#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x00000080L
897#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x00000007
898#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x00007f00L
899#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x00000008
900#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x00000040L
901#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x00000006
902#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x00000001L
903#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x00000000
904#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x00000002L
905#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x00000001
906#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x00000020L
907#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x00000005
908#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x00000010L
909#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x00000004
910#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x00000008L
911#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x00000003
912#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x00000004L
913#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x00000002
914#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0x00ff0000L
915#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x00000010
916#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0x0000ff00L
917#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x00000008
918#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0x000000ffL
919#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x00000000
920#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000L
921#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x00000018
922#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0x0000ff00L
923#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x00000008
924#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0x000000ffL
925#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x00000000
926#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0x00ff0000L
927#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x00000010
928#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0x0f000000L
929#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x00000018
930#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x00000800L
931#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0x0000000b
932#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x00000001L
933#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x00000000
934#define MC_ARB_RFSH_CNTL__URG0_MASK 0x0000003eL
935#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x00000001
936#define MC_ARB_RFSH_CNTL__URG1_MASK 0x000007c0L
937#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x00000006
938#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0x000000ffL
939#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x00000000
940#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x00000100L
941#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x00000008
942#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x00000200L
943#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x00000009
944#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x00000400L
945#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0x0000000a
946#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x01000000L
947#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x00000018
948#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x00008000L
949#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0x0000000f
950#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x00010000L
951#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x00000010
952#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x00020000L
953#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x00000011
954#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x00040000L
955#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x00000012
956#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x00080000L
957#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x00000013
958#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x00100000L
959#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x00000014
960#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x00200000L
961#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x00000015
962#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x00400000L
963#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x00000016
964#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x00800000L
965#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x00000017
966#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x00000001L
967#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x00000000
968#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x00000010L
969#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x00000004
970#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x00000020L
971#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x00000005
972#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x02000000L
973#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x00000019
974#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x00000002L
975#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x00000001
976#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0x0000000cL
977#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x00004000L
978#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0x0000000e
979#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x00000002
980#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x00000040L
981#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x00000006
982#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x00003800L
983#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0x0000000b
984#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x00000080L
985#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x00000007
986#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0x000fe000L
987#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0x0000000d
988#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x00001fc0L
989#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x00000006
990#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x0000001fL
991#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x01f00000L
992#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x00000014
993#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000L
994#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x00000019
995#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x00000000
996#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000L
997#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x0000001e
998#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x00000020L
999#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x00000005
1000#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x00002000L
1001#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0x0000000d
1002#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x00001000L
1003#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0x0000000c
1004#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0x00000fc0L
1005#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x00000006
1006#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x0000003fL
1007#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x00000000
1008#define MC_ARB_RTT_DATA__PATTERN_MASK 0x000000ffL
1009#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x00000000
1010#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x00000003L
1011#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x00000000
1012#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0x0000000cL
1013#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x00000002
1014#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0x00000ff0L
1015#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x00000004
1016#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x01fe0000L
1017#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x00000011
1018#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x0001f000L
1019#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0x0000000c
1020#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000L
1021#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x00000019
1022#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x00000100L
1023#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x00000008
1024#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0x000000ffL
1025#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x00000000
1026#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000L
1027#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x00000018
1028#define MC_ARB_SQM_CNTL__RATIO_MASK 0x00ff0000L
1029#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x00000010
1030#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0x0000fe00L
1031#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0x00000009
1032#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x00000006L
1033#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x00000001
1034#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x00000001L
1035#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x00000000
1036#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x00000010L
1037#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x00000004
1038#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x00000008L
1039#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x00000003
1040#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x00000006L
1041#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x00000001
1042#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x00000001L
1043#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x00000000
1044#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x00000010L
1045#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x00000004
1046#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x00000008L
1047#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x00000003
1048#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x00000200L
1049#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x00000009
1050#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x00000400L
1051#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0x0000000a
1052#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x00000800L
1053#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0x0000000b
1054#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x00001000L
1055#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0x0000000c
1056#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x00002000L
1057#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0x0000000d
1058#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x00004000L
1059#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0x0000000e
1060#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0x0000000fL
1061#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x00000000
1062#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x000001f0L
1063#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x00000004
1064#define MC_ARB_WCDR__IDLE_BURST_MASK 0x00001f80L
1065#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x00002000L
1066#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0x0000000d
1067#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x00000007
1068#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x00010000L
1069#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x00000010
1070#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x00000001L
1071#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x00000000
1072#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x0000007cL
1073#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x00000002
1074#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0x0000c000L
1075#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0x0000000e
1076#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x00000002L
1077#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x00000001
1078#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x00020000L
1079#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x00000011
1080#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x02000000L
1081#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x00000019
1082#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x08000000L
1083#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x0000001b
1084#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x04000000L
1085#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x0000001a
1086#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x01c00000L
1087#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x00000016
1088#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x003c0000L
1089#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x00000012
1090#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000L
1091#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x0000001c
1092#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x00000008L
1093#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
1094#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x00000010L
1095#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
1096#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x00000020L
1097#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
1098#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x00000040L
1099#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
1100#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x00000080L
1101#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
1102#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x00000100L
1103#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
1104#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x00000200L
1105#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
1106#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x00000400L
1107#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
1108#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x00000004L
1109#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x00000002
1110#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x00000003L
1111#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x00000000
1112#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x00000008L
1113#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x00000003
1114#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x00000010L
1115#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x00000004
1116#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x00000020L
1117#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x00000005
1118#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x00000040L
1119#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x00000006
1120#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x00000080L
1121#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x00000007
1122#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x00000100L
1123#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x00000008
1124#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x00000200L
1125#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x00000009
1126#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x00000400L
1127#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0x0000000a
1128#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x00000004L
1129#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x00000002
1130#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x00000003L
1131#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x00000000
1132#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x00000003L
1133#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x00000000
1134#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0x0000000cL
1135#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x00000002
1136#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x00000030L
1137#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x00000004
1138#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0x000000c0L
1139#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x00000006
1140#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x00000300L
1141#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x00000008
1142#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0x00000c00L
1143#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0x0000000a
1144#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x00003000L
1145#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0x0000000c
1146#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0x0000c000L
1147#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0x0000000e
1148#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0x00ff0000L
1149#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x00000010
1150#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x00000003L
1151#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x00000000
1152#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0x0000000cL
1153#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x00000002
1154#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x00000030L
1155#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x00000004
1156#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0x000000c0L
1157#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x00000006
1158#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x00000300L
1159#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x00000008
1160#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0x00000c00L
1161#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0x0000000a
1162#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x00003000L
1163#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0x0000000c
1164#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0x0000c000L
1165#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0x0000000e
1166#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0x00ff0000L
1167#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x00000010
1168#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0x000000f0L
1169#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x00000004
1170#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x02000000L
1171#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x00000019
1172#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0x00ffff00L
1173#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x00000008
1174#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x01000000L
1175#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x00000018
1176#define MC_BIST_AUTO_CNTL__MOP_MASK 0x00000003L
1177#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x00000000
1178#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x00000004L
1179#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x00000002
1180#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x00000002L
1181#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x00000001
1182#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x00010000L
1183#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x00000010
1184#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x00020000L
1185#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x00000011
1186#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000L
1187#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x0000001f
1188#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000L
1189#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x0000001c
1190#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000L
1191#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x0000001d
1192#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0x0000fff0L
1193#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x00000004
1194#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0x0ffc0000L
1195#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x00000012
1196#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x00000008L
1197#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x00000003
1198#define MC_BIST_CMD_CNTL__RESET_MASK 0x00000001L
1199#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x00000000
1200#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000L
1201#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x0000001e
1202#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x0000001fL
1203#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x00000100L
1204#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x00000008
1205#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x00000000
1206#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x0001f000L
1207#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x00100000L
1208#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x00000014
1209#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0x0000000c
1210#define MC_BIST_CMP_CNTL__CMP_MASK 0x00030000L
1211#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0x00000ff0L
1212#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x00000004
1213#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0x0000000fL
1214#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x00000000
1215#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x00000010
1216#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x00300000L
1217#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x00000014
1218#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x00002000L
1219#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0x0000000d
1220#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x00040000L
1221#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x00000012
1222#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x00080000L
1223#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x00000013
1224#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x00004000L
1225#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0x0000000e
1226#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x00008000L
1227#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0x0000000f
1228#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x00001000L
1229#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0x0000000c
1230#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000L
1231#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x00000016
1232#define MC_BIST_CNTL__ADR_MODE_MASK 0x00000020L
1233#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x00000005
1234#define MC_BIST_CNTL__DAT_MODE_MASK 0x00000040L
1235#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x00000006
1236#define MC_BIST_CNTL__DONE_MASK 0x40000000L
1237#define MC_BIST_CNTL__DONE__SHIFT 0x0000001e
1238#define MC_BIST_CNTL__ENABLE_D0_MASK 0x00001000L
1239#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0x0000000c
1240#define MC_BIST_CNTL__ENABLE_D1_MASK 0x00002000L
1241#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0x0000000d
1242#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x00004000L
1243#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0x0000000e
1244#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000L
1245#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x0000001f
1246#define MC_BIST_CNTL__LOOP_CNT_MASK 0x0fff0000L
1247#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x00000010
1248#define MC_BIST_CNTL__LOOP_MASK 0x00000c00L
1249#define MC_BIST_CNTL__LOOP__SHIFT 0x0000000a
1250#define MC_BIST_CNTL__MOP_MODE_MASK 0x00000010L
1251#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x00000004
1252#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x00000004L
1253#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x00000002
1254#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x00000008L
1255#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x00000003
1256#define MC_BIST_CNTL__RESET_MASK 0x00000001L
1257#define MC_BIST_CNTL__RESET__SHIFT 0x00000000
1258#define MC_BIST_CNTL__RUN_MASK 0x00000002L
1259#define MC_BIST_CNTL__RUN__SHIFT 0x00000001
1260#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffffL
1261#define MC_BIST_DATA_MASK__MASK__SHIFT 0x00000000
1262#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffffL
1263#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x00000000
1264#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffffL
1265#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x00000000
1266#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffffL
1267#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x00000000
1268#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffffL
1269#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x00000000
1270#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffffL
1271#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x00000000
1272#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffffL
1273#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x00000000
1274#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffffL
1275#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x00000000
1276#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffffL
1277#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x00000000
1278#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x00000040L
1279#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x00000006
1280#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x00000100L
1281#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x00000008
1282#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x00000020L
1283#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x00000005
1284#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x00000080L
1285#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x00000007
1286#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x00000200L
1287#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x00000009
1288#define MC_BIST_DIR_CNTL__EOB_MASK 0x00000008L
1289#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x00000003
1290#define MC_BIST_DIR_CNTL__MOP3_MASK 0x00000400L
1291#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0x0000000a
1292#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x00000010L
1293#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x00000004
1294#define MC_BIST_DIR_CNTL__MOP_MASK 0x00000007L
1295#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x00000000
1296#define MC_BIST_EADDR__BANK_MASK 0x0f000000L
1297#define MC_BIST_EADDR__BANK__SHIFT 0x00000018
1298#define MC_BIST_EADDR__COLH_MASK 0x20000000L
1299#define MC_BIST_EADDR__COLH__SHIFT 0x0000001d
1300#define MC_BIST_EADDR__COL_MASK 0x000003ffL
1301#define MC_BIST_EADDR__COL__SHIFT 0x00000000
1302#define MC_BIST_EADDR__RANK_MASK 0x10000000L
1303#define MC_BIST_EADDR__RANK__SHIFT 0x0000001c
1304#define MC_BIST_EADDR__ROWH_MASK 0xc0000000L
1305#define MC_BIST_EADDR__ROWH__SHIFT 0x0000001e
1306#define MC_BIST_EADDR__ROW_MASK 0x00fffc00L
1307#define MC_BIST_EADDR__ROW__SHIFT 0x0000000a
1308#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0x0f000000L
1309#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x00000018
1310#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000L
1311#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x0000001d
1312#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x000003ffL
1313#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x00000000
1314#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000L
1315#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x0000001c
1316#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000L
1317#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x0000001e
1318#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0x00fffc00L
1319#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0x0000000a
1320#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffffL
1321#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x00000000
1322#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffffL
1323#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x00000000
1324#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffffL
1325#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x00000000
1326#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffffL
1327#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x00000000
1328#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffffL
1329#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x00000000
1330#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffffL
1331#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x00000000
1332#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffffL
1333#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x00000000
1334#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffffL
1335#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x00000000
1336#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffffL
1337#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x00000000
1338#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffffL
1339#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x00000000
1340#define MC_BIST_SADDR__BANK_MASK 0x0f000000L
1341#define MC_BIST_SADDR__BANK__SHIFT 0x00000018
1342#define MC_BIST_SADDR__COLH_MASK 0x20000000L
1343#define MC_BIST_SADDR__COLH__SHIFT 0x0000001d
1344#define MC_BIST_SADDR__COL_MASK 0x000003ffL
1345#define MC_BIST_SADDR__COL__SHIFT 0x00000000
1346#define MC_BIST_SADDR__RANK_MASK 0x10000000L
1347#define MC_BIST_SADDR__RANK__SHIFT 0x0000001c
1348#define MC_BIST_SADDR__ROWH_MASK 0xc0000000L
1349#define MC_BIST_SADDR__ROWH__SHIFT 0x0000001e
1350#define MC_BIST_SADDR__ROW_MASK 0x00fffc00L
1351#define MC_BIST_SADDR__ROW__SHIFT 0x0000000a
1352#define MC_CG_CONFIG__INDEX_MASK 0x003fffc0L
1353#define MC_CG_CONFIG__INDEX__SHIFT 0x00000006
1354#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000L
1355#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0x0000000d
1356#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
1357#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
1358#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
1359#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
1360#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
1361#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
1362#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
1363#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
1364#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
1365#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
1366#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
1367#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
1368#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
1369#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
1370#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
1371#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
1372#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
1373#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
1374#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
1375#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
1376#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
1377#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
1378#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
1379#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
1380#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffffL
1381#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x00000000
1382#define MC_CITF_CNTL__EXEMPTPM_MASK 0x00000008L
1383#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x00000003
1384#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x00000030L
1385#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x00000004
1386#define MC_CITF_CNTL__IGNOREPM_MASK 0x00000004L
1387#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x00000002
1388#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x00000040L
1389#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x00000006
1390#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x02000000L
1391#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x00000019
1392#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x01000000L
1393#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x00000018
1394#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0x0000ff00L
1395#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x00000008
1396#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0x000000ffL
1397#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x00000000
1398#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0x00ff0000L
1399#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x00000010
1400#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x00010000L
1401#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x00000010
1402#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x00020000L
1403#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x00000011
1404#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0x0000ff00L
1405#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x00000008
1406#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0x000000ffL
1407#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x00000000
1408#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x0000003fL
1409#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x00000000
1410#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0x00000fc0L
1411#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x00000006
1412#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0x000000ffL
1413#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x00000000
1414#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0x0000ff00L
1415#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x00000008
1416#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x0000001eL
1417#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x00000001
1418#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x000003c0L
1419#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x00000006
1420#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x00000020L
1421#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x00000005
1422#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x00000001L
1423#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x00000000
1424#define MC_CITF_DAGB_DLY__CLI_MASK 0x001f0000L
1425#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x00000010
1426#define MC_CITF_DAGB_DLY__DLY_MASK 0x0000001fL
1427#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x00000000
1428#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000L
1429#define MC_CITF_DAGB_DLY__POS__SHIFT 0x00000018
1430#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0x00fc0000L
1431#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x00000012
1432#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x0003f000L
1433#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0x0000000c
1434#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000L
1435#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x00000018
1436#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x0000003fL
1437#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x00000000
1438#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x0000003fL
1439#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x00000000
1440#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0x00000fc0L
1441#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x00000006
1442#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x00040000L
1443#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x00000012
1444#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x00080000L
1445#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1446#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0x00000fc0L
1447#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x00000006
1448#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x0000003fL
1449#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x00000000
1450#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x0003f000L
1451#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0x0000000c
1452#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x00040000L
1453#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x00000012
1454#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
1455#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1456#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
1457#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
1458#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x0000003fL
1459#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x00000000
1460#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
1461#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
1462#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x00040000L
1463#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x00000012
1464#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x00080000L
1465#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1466#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0x00000fc0L
1467#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x00000006
1468#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x0000003fL
1469#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x00000000
1470#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x0003f000L
1471#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0x0000000c
1472#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0x000001ffL
1473#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x00000000
1474#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x00000040L
1475#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x00000006
1476#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x00001000L
1477#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x0000000c
1478#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x00000080L
1479#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x00000007
1480#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x00002000L
1481#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x0000000d
1482#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x00004000L
1483#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x0000000e
1484#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x00000100L
1485#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x00000008
1486#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x00010000L
1487#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x00000010
1488#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x00000400L
1489#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x0000000a
1490#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x00020000L
1491#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x00000011
1492#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x00008000L
1493#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0x0000000f
1494#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x00040000L
1495#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x00000012
1496#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x00000200L
1497#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x00000009
1498#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x00000800L
1499#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x0000000b
1500#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x00004000L
1501#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0x0000000e
1502#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x0000007fL
1503#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x00000000
1504#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x00003f80L
1505#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x00000007
1506#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x00000001L
1507#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x00000000
1508#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x00000002L
1509#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x00000001
1510#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x00000010L
1511#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x00000004
1512#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x00000020L
1513#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x00000005
1514#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x00000004L
1515#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x00000002
1516#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x00000008L
1517#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x00000003
1518#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x01000000L
1519#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
1520#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
1521#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
1522#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
1523#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
1524#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
1525#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
1526#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
1527#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
1528#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
1529#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
1530#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
1531#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
1532#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
1533#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
1534#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
1535#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
1536#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x01000000L
1537#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x00000018
1538#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
1539#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
1540#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
1541#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
1542#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
1543#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
1544#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
1545#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
1546#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
1547#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
1548#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
1549#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
1550#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
1551#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
1552#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
1553#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
1554#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0x00000f00L
1555#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x00000008
1556#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x00000001L
1557#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x00000000
1558#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x00000002L
1559#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x00000001
1560#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x00000004L
1561#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x00000002
1562#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x00000008L
1563#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x00000003
1564#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x00000010L
1565#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x00000004
1566#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x00001000L
1567#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0x0000000c
1568#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000L
1569#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x0000001f
1570#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x00000001L
1571#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x00000000
1572#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x00000002L
1573#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x00000001
1574#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x00000004L
1575#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x00000002
1576#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x00000008L
1577#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x00000003
1578#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x00000010L
1579#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x00000004
1580#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L
1581#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x00000005
1582#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000L
1583#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x0000001f
1584#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x00000700L
1585#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x00000008
1586#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x00000001L
1587#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x00000000
1588#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x00000002L
1589#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x00000001
1590#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x00000004L
1591#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x00000002
1592#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x00000008L
1593#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x00000003
1594#define MC_CONFIG__MC_RD_ENABLE_MASK 0x00000030L
1595#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x00000004
1596#define MC_HUB_MISC_DBG__SELECT0_MASK 0x0000000fL
1597#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x00000000
1598#define MC_HUB_MISC_DBG__SELECT1_MASK 0x000000f0L
1599#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x00000004
1600#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffffL
1601#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x00000000
1602#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x00040000L
1603#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x00000012
1604#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x00080000L
1605#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1606#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0x00000fc0L
1607#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x00000006
1608#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x0000003fL
1609#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x00000000
1610#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x0003f000L
1611#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0x0000000c
1612#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x00000001L
1613#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x00000000
1614#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x00000002L
1615#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x00000001
1616#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x00000400L
1617#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x0000000a
1618#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x00000800L
1619#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x0000000b
1620#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x00000004L
1621#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x00000002
1622#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x00000008L
1623#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x00000003
1624#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x00010000L
1625#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0x00000010
1626#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x00020000L
1627#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0x00000011
1628#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x00040000L
1629#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x00000012
1630#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x00080000L
1631#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x00000013
1632#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x00000040L
1633#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x00000006
1634#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x00000080L
1635#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x00000007
1636#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x00004000L
1637#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0x0000000e
1638#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x00008000L
1639#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0x0000000f
1640#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x00001000L
1641#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0x0000000c
1642#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x00002000L
1643#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0x0000000d
1644#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x01000000L
1645#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x00000018
1646#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x02000000L
1647#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x00000019
1648#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x00100000L
1649#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x00000014
1650#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x00200000L
1651#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x00000015
1652#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x00000003L
1653#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x00000000
1654#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x00000018L
1655#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x00000003
1656#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x00000004L
1657#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x00000002
1658#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x00040000L
1659#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x00000012
1660#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x00080000L
1661#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1662#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0x00000fc0L
1663#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x00000006
1664#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x0000003fL
1665#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x00000000
1666#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x0003f000L
1667#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0x0000000c
1668#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x00002000L
1669#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x0000000d
1670#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x00000004L
1671#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x00000002
1672#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x00000008L
1673#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x00000003
1674#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x00000010L
1675#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x00000004
1676#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x00000020L
1677#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x00000005
1678#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x00000100L
1679#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x00000008
1680#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x00000200L
1681#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x00000009
1682#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x00000001L
1683#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x00000000
1684#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x00000040L
1685#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x00000006
1686#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x00000080L
1687#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x00000007
1688#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x00000002L
1689#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x00000001
1690#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x00001000L
1691#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x0000000c
1692#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x00000400L
1693#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0x0000000a
1694#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x00000800L
1695#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x0000000b
1696#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x00040000L
1697#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x00000012
1698#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x00080000L
1699#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x00000013
1700#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0x00000fc0L
1701#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x00000006
1702#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x0000003fL
1703#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x00000000
1704#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x0003f000L
1705#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0x0000000c
1706#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x00000200L
1707#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x00000009
1708#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x0001fc00L
1709#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0x0000000a
1710#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00020000L
1711#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x00000011
1712#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00040000L
1713#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x00000012
1714#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x00000004L
1715#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000002
1716#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x00000008L
1717#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000003
1718#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x00000020L
1719#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x00000005
1720#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x00000040L
1721#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x00000006
1722#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x00000080L
1723#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x00000007
1724#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x00000100L
1725#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x00000008
1726#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
1727#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
1728#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x00080000L
1729#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x00000013
1730#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x00000001L
1731#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x00000000
1732#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0x000000ffL
1733#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x00000000
1734#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0x00ff0000L
1735#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x00000010
1736#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000L
1737#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x00000018
1738#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0x000000ffL
1739#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x00000000
1740#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0x0000ff00L
1741#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x00000008
1742#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x00000008L
1743#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
1744#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x00000001L
1745#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x00000000
1746#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x00007800L
1747#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0x0000000b
1748#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x00000003L
1749#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x00000000
1750#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x0000007cL
1751#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x00000002
1752#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x00000780L
1753#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x00000007
1754#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x00000006L
1755#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x00000001
1756#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x00000030L
1757#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x00000004
1758#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x00000040L
1759#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x00000006
1760#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
1761#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1762#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0x000000ffL
1763#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x00000000
1764#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0x000000ffL
1765#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x00000000
1766#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
1767#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
1768#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x00000001L
1769#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x00000000
1770#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x00007800L
1771#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0x0000000b
1772#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x00000780L
1773#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x00000007
1774#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x00000006L
1775#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x00000001
1776#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x00000030L
1777#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x00000004
1778#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x00000040L
1779#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x00000006
1780#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
1781#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1782#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x0003f800L
1783#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0x0000000b
1784#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
1785#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
1786#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x00000004L
1787#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x00000002
1788#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x01fc0000L
1789#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x00000012
1790#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x00000001L
1791#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x00000000
1792#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x00000780L
1793#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x00000007
1794#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x00000078L
1795#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x00000003
1796#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000L
1797#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x00000019
1798#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x0003f800L
1799#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0x0000000b
1800#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
1801#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
1802#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x00000004L
1803#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x00000002
1804#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x01fc0000L
1805#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x00000012
1806#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x00000001L
1807#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x00000000
1808#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x00000780L
1809#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x00000007
1810#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x00000078L
1811#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x00000003
1812#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000L
1813#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x00000019
1814#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x0003f800L
1815#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0x0000000b
1816#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
1817#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
1818#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x00000004L
1819#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x00000002
1820#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x01fc0000L
1821#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x00000012
1822#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x00000001L
1823#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x00000000
1824#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x00000780L
1825#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x00000007
1826#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x00000078L
1827#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x00000003
1828#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000L
1829#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x00000019
1830#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x0003f800L
1831#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0x0000000b
1832#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
1833#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
1834#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x00000004L
1835#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x00000002
1836#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x01fc0000L
1837#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x00000012
1838#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x00000001L
1839#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x00000000
1840#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x00000780L
1841#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x00000007
1842#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x00000078L
1843#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x00000003
1844#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000L
1845#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x00000019
1846#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
1847#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
1848#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x00000001L
1849#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x00000000
1850#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x00007800L
1851#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0x0000000b
1852#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x00000780L
1853#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x00000007
1854#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x00000006L
1855#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x00000001
1856#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x00000030L
1857#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x00000004
1858#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x00000040L
1859#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
1860#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
1861#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1862#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
1863#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
1864#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x00000001L
1865#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x00000000
1866#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x00007800L
1867#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0x0000000b
1868#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x00000780L
1869#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x00000007
1870#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x00000006L
1871#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x00000001
1872#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x00000030L
1873#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x00000004
1874#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x00000040L
1875#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x00000006
1876#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
1877#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1878#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
1879#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
1880#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x00000001L
1881#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x00000000
1882#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x00007800L
1883#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0x0000000b
1884#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x00000780L
1885#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x00000007
1886#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x00000006L
1887#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x00000001
1888#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x00000030L
1889#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x00000004
1890#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x00000040L
1891#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x00000006
1892#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
1893#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1894#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x0000007fL
1895#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x00000000
1896#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x00007f00L
1897#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x00000008
1898#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x00000080L
1899#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x00000007
1900#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
1901#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
1902#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x00000001L
1903#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x00000000
1904#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x00007800L
1905#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0x0000000b
1906#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x00000780L
1907#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x00000007
1908#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x00000006L
1909#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x00000001
1910#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x00000030L
1911#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x00000004
1912#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x00000040L
1913#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x00000006
1914#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
1915#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1916#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
1917#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
1918#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
1919#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
1920#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x00000020L
1921#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
1922#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
1923#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
1924#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
1925#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
1926#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x00000100L
1927#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
1928#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
1929#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
1930#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
1931#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
1932#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
1933#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
1934#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
1935#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
1936#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x00000800L
1937#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0x0000000b
1938#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x00000001L
1939#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x00000000
1940#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
1941#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
1942#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x00000001L
1943#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x00000000
1944#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x00007800L
1945#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0x0000000b
1946#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x00000780L
1947#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x00000007
1948#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x00000006L
1949#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x00000001
1950#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x00000030L
1951#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x00000004
1952#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x00000040L
1953#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x00000006
1954#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
1955#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1956#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
1957#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
1958#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x00000001L
1959#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x00000000
1960#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x00007800L
1961#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0x0000000b
1962#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x00000780L
1963#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x00000007
1964#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x00000006L
1965#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x00000001
1966#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x00000030L
1967#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x00000004
1968#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x00000040L
1969#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x00000006
1970#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
1971#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1972#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x00010000L
1973#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x00000010
1974#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
1975#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
1976#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x00000001L
1977#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x00000000
1978#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x00007800L
1979#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0x0000000b
1980#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x00000780L
1981#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x00000007
1982#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x00000006L
1983#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x00000001
1984#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x00000030L
1985#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x00000004
1986#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x00000040L
1987#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x00000006
1988#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
1989#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
1990#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
1991#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
1992#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x00000001L
1993#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x00000000
1994#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x00007800L
1995#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0x0000000b
1996#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x00000780L
1997#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x00000007
1998#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x00000006L
1999#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x00000001
2000#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x00000030L
2001#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x00000004
2002#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x00000040L
2003#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
2004#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2005#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2006#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x00000008L
2007#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2008#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x00000001L
2009#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x00000000
2010#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x00007800L
2011#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0x0000000b
2012#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x00000780L
2013#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x00000007
2014#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x00000006L
2015#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x00000001
2016#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x00000030L
2017#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x00000004
2018#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x00000040L
2019#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x00000006
2020#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2021#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2022#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
2023#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
2024#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
2025#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
2026#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
2027#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
2028#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
2029#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
2030#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
2031#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
2032#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
2033#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
2034#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
2035#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
2036#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
2037#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
2038#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
2039#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2040#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x00000001L
2041#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x00000000
2042#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x00007800L
2043#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
2044#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x00000780L
2045#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x00000007
2046#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x00000006L
2047#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x00000001
2048#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x00000030L
2049#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x00000004
2050#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
2051#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
2052#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2053#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2054#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x001f0000L
2055#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x00000010
2056#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x0000003fL
2057#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x00000000
2058#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000L
2059#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x00000018
2060#define MC_HUB_WDP_BP__ENABLE_MASK 0x00000001L
2061#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x00000000
2062#define MC_HUB_WDP_BP__RDRET_MASK 0x0003fffeL
2063#define MC_HUB_WDP_BP__RDRET__SHIFT 0x00000001
2064#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000L
2065#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x00000012
2066#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x00001fe0L
2067#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x00000005
2068#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x00002000L
2069#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x0000000d
2070#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x00004000L
2071#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x0000000e
2072#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x00008000L
2073#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0x0000000f
2074#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x00040000L
2075#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x00000012
2076#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x00010000L
2077#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x00000010
2078#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x00000002L
2079#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x00000001
2080#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x00000004L
2081#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x00000002
2082#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x00000008L
2083#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x00000003
2084#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x00020000L
2085#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x00000011
2086#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x00080000L
2087#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x00000013
2088#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x00000010L
2089#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x00000004
2090#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x00100000L
2091#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x00000014
2092#define MC_HUB_WDP_CREDITS__STOR0_MASK 0x00ff0000L
2093#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x00000010
2094#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000L
2095#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x00000018
2096#define MC_HUB_WDP_CREDITS__VM0_MASK 0x000000ffL
2097#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x00000000
2098#define MC_HUB_WDP_CREDITS__VM1_MASK 0x0000ff00L
2099#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x00000008
2100#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x00000001L
2101#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x00000000
2102#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x00000002L
2103#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x00000001
2104#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0x000000f0L
2105#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x00000004
2106#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0x0000000fL
2107#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x00000000
2108#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x00010000L
2109#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x00000010
2110#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0x0000ff00L
2111#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x00000008
2112#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0x000000f0L
2113#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x00000004
2114#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0x0000000fL
2115#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x00000000
2116#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x00010000L
2117#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x00000010
2118#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0x0000ff00L
2119#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x00000008
2120#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x00000008L
2121#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
2122#define MC_HUB_WDP_HDP__ENABLE_MASK 0x00000001L
2123#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x00000000
2124#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x00007800L
2125#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0x0000000b
2126#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x00000780L
2127#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x00000007
2128#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x00000006L
2129#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x00000001
2130#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x00000030L
2131#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x00000004
2132#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x00000040L
2133#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x00000006
2134#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
2135#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2136#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x00000008L
2137#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x00000003
2138#define MC_HUB_WDP_IH__ENABLE_MASK 0x00000001L
2139#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x00000000
2140#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x00007800L
2141#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0x0000000b
2142#define MC_HUB_WDP_IH__MAXBURST_MASK 0x00000780L
2143#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x00000007
2144#define MC_HUB_WDP_IH__PRESCALE_MASK 0x00000006L
2145#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x00000001
2146#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x00000030L
2147#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x00000004
2148#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x00000040L
2149#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x00000006
2150#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x00008000L
2151#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2152#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x00001f80L
2153#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x00000007
2154#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000L
2155#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x00000018
2156#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x00000002L
2157#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x00000001
2158#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x00000001L
2159#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x00000000
2160#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x0001e000L
2161#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0x0000000d
2162#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x00000078L
2163#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x00000003
2164#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x00000004L
2165#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x00000002
2166#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0x00fe0000L
2167#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x00000011
2168#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x00001f80L
2169#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x00000007
2170#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000L
2171#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x00000018
2172#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x00000002L
2173#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x00000001
2174#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x00000001L
2175#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x00000000
2176#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x0001e000L
2177#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0x0000000d
2178#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x00000078L
2179#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x00000003
2180#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x00000004L
2181#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x00000002
2182#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0x00fe0000L
2183#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x00000011
2184#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x00001f80L
2185#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x00000007
2186#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000L
2187#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x00000018
2188#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x00000002L
2189#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x00000001
2190#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x00000001L
2191#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x00000000
2192#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x0001e000L
2193#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0x0000000d
2194#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x00000078L
2195#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x00000003
2196#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x00000004L
2197#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x00000002
2198#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0x00fe0000L
2199#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x00000011
2200#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x00001f80L
2201#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x00000007
2202#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000L
2203#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x00000018
2204#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x00000002L
2205#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x00000001
2206#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x00000001L
2207#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x00000000
2208#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x0001e000L
2209#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0x0000000d
2210#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x00000078L
2211#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x00000003
2212#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x00000004L
2213#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x00000002
2214#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0x00fe0000L
2215#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x00000011
2216#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x00000008L
2217#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x00000003
2218#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x00000001L
2219#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x00000000
2220#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x00007800L
2221#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0x0000000b
2222#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x00000780L
2223#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x00000007
2224#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x00000006L
2225#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x00000001
2226#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x00000030L
2227#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x00000004
2228#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x00000040L
2229#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x00000006
2230#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x00008000L
2231#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2232#define MC_HUB_WDP_MGPU2__CID2_MASK 0x000000ffL
2233#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x00000000
2234#define MC_HUB_WDP_MGPU__CID_MASK 0x0000ff00L
2235#define MC_HUB_WDP_MGPU__CID__SHIFT 0x00000008
2236#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x00800000L
2237#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x00000017
2238#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x007f0000L
2239#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x00000010
2240#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000L
2241#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x00000018
2242#define MC_HUB_WDP_MGPU__STOR_MASK 0x000000ffL
2243#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x00000000
2244#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x00000008L
2245#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2246#define MC_HUB_WDP_RLC__ENABLE_MASK 0x00000001L
2247#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x00000000
2248#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x00007800L
2249#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0x0000000b
2250#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x00000780L
2251#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x00000007
2252#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x00000006L
2253#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x00000001
2254#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x00000030L
2255#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x00000004
2256#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x00000040L
2257#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x00000006
2258#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2259#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2260#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x00000008L
2261#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2262#define MC_HUB_WDP_SEM__ENABLE_MASK 0x00000001L
2263#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x00000000
2264#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x00007800L
2265#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0x0000000b
2266#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x00000780L
2267#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x00000007
2268#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x00000006L
2269#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x00000001
2270#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x00000030L
2271#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x00000004
2272#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x00000040L
2273#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x00000006
2274#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2275#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2276#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x00000008L
2277#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x00000003
2278#define MC_HUB_WDP_SH0__ENABLE_MASK 0x00000001L
2279#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x00000000
2280#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x00007800L
2281#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0x0000000b
2282#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x00000780L
2283#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x00000007
2284#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x00000006L
2285#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x00000001
2286#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x00000030L
2287#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x00000004
2288#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x00000040L
2289#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x00000006
2290#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x00008000L
2291#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2292#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x00000008L
2293#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x00000003
2294#define MC_HUB_WDP_SH1__ENABLE_MASK 0x00000001L
2295#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x00000000
2296#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x00007800L
2297#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0x0000000b
2298#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x00000780L
2299#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x00000007
2300#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x00000006L
2301#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x00000001
2302#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x00000030L
2303#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x00000004
2304#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x00000040L
2305#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x00000006
2306#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x00008000L
2307#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2308#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x000001fcL
2309#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x00000002
2310#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x00000003L
2311#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x00000000
2312#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x00000008L
2313#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x00000003
2314#define MC_HUB_WDP_SMU__ENABLE_MASK 0x00000001L
2315#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x00000000
2316#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x00007800L
2317#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0x0000000b
2318#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x00000780L
2319#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x00000007
2320#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x00000006L
2321#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x00000001
2322#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x00000030L
2323#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x00000004
2324#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x00000040L
2325#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x00000006
2326#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2327#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2328#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x00000080L
2329#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x00000007
2330#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x00000040L
2331#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x00000006
2332#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x00000020L
2333#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x00000005
2334#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x00000400L
2335#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x0000000a
2336#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x00000200L
2337#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x00000009
2338#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x00000100L
2339#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x00000008
2340#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x00000002L
2341#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x00000001
2342#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x00000800L
2343#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x0000000b
2344#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x00000004L
2345#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x00000002
2346#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x00001000L
2347#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0x0000000c
2348#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x00000008L
2349#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x00000003
2350#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x00002000L
2351#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0x0000000d
2352#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x00000010L
2353#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x00000004
2354#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x00004000L
2355#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0x0000000e
2356#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x00000001L
2357#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x00000000
2358#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x00000008L
2359#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x00000003
2360#define MC_HUB_WDP_UMC__ENABLE_MASK 0x00000001L
2361#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x00000000
2362#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x00007800L
2363#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0x0000000b
2364#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x00000780L
2365#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x00000007
2366#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x00000006L
2367#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x00000001
2368#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x00000030L
2369#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x00000004
2370#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x00000040L
2371#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x00000006
2372#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x00008000L
2373#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2374#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x00000008L
2375#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x00000003
2376#define MC_HUB_WDP_UVD__ENABLE_MASK 0x00000001L
2377#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x00000000
2378#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x00007800L
2379#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0x0000000b
2380#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x00000780L
2381#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x00000007
2382#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x00000006L
2383#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x00000001
2384#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x00000030L
2385#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x00000004
2386#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x00000040L
2387#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x00000006
2388#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x00008000L
2389#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2390#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x00010000L
2391#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x00000010
2392#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x00000008L
2393#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x00000003
2394#define MC_HUB_WDP_VCE__ENABLE_MASK 0x00000001L
2395#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x00000000
2396#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x00007800L
2397#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0x0000000b
2398#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x00000780L
2399#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x00000007
2400#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x00000006L
2401#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x00000001
2402#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x00000030L
2403#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x00000004
2404#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x00000040L
2405#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x00000006
2406#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x00008000L
2407#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2408#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x00000008L
2409#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x00000003
2410#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x00000001L
2411#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x00000000
2412#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x00007800L
2413#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0x0000000b
2414#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x00000780L
2415#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x00000007
2416#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x00000006L
2417#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x00000001
2418#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x00000030L
2419#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x00000004
2420#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x00000040L
2421#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x00000006
2422#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x00008000L
2423#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2424#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x00000007L
2425#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x00000000
2426#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x00000038L
2427#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x00000003
2428#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x000001c0L
2429#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x00000006
2430#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0x00000e00L
2431#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x00000009
2432#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x00007000L
2433#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0x0000000c
2434#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x00038000L
2435#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0x0000000f
2436#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x001c0000L
2437#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x00000012
2438#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0x00e00000L
2439#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x00000015
2440#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x00000008L
2441#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x00000003
2442#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
2443#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
2444#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x00000001L
2445#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x00000000
2446#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x00007800L
2447#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0x0000000b
2448#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x00000780L
2449#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x00000007
2450#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x00000008L
2451#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x00000003
2452#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x00010000L
2453#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x00000010
2454#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x00000001L
2455#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x00000000
2456#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x00007800L
2457#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0x0000000b
2458#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x00000780L
2459#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x00000007
2460#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x00000006L
2461#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x00000001
2462#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x00000030L
2463#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x00000004
2464#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x00000040L
2465#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x00000006
2466#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x00008000L
2467#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2468#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x00000006L
2469#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x00000001
2470#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x00000030L
2471#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x00000004
2472#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x00000040L
2473#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x00000006
2474#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x00008000L
2475#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2476#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x00000008L
2477#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x00000003
2478#define MC_HUB_WDP_XDP__ENABLE_MASK 0x00000001L
2479#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x00000000
2480#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x00007800L
2481#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0x0000000b
2482#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x00000780L
2483#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x00000007
2484#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x00000006L
2485#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x00000001
2486#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x00000030L
2487#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x00000004
2488#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x00000040L
2489#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x00000006
2490#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x00008000L
2491#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0x0000000f
2492#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x00200000L
2493#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x00000015
2494#define MC_HUB_WRRET_CNTL__BP_MASK 0x001ffffeL
2495#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x00000001
2496#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000L
2497#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x00000016
2498#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000L
2499#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x0000001e
2500#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000L
2501#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x0000001f
2502#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x00000001L
2503#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x00000000
2504#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0x000000feL
2505#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x00000001
2506#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x00000001L
2507#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x00000000
2508#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0x000000feL
2509#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x00000001
2510#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x00000001L
2511#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x00000000
2512#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0x000000feL
2513#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x00000001
2514#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x00000001L
2515#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x00000000
2516#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0x000000feL
2517#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x00000001
2518#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x00000001L
2519#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x00000000
2520#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x00000001L
2521#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x00000000
2522#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x00000002L
2523#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x00000001
2524#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x00000004L
2525#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x00000002
2526#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x00000008L
2527#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x00000003
2528#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000L
2529#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x0000001f
2530#define MC_IMP_CNTL__CAL_VREF_MASK 0x007f0000L
2531#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x00000040L
2532#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x00000006
2533#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x00000020L
2534#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x00000005
2535#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x00000010
2536#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000L
2537#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x0000001d
2538#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000L
2539#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x0000001e
2540#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x00000200L
2541#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x00000009
2542#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0x0000e000L
2543#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0x0000000d
2544#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x0000001fL
2545#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x00000000
2546#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x00000100L
2547#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x00000008
2548#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000L
2549#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x0000001f
2550#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000L
2551#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x0000001c
2552#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000L
2553#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x0000001e
2554#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000L
2555#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x0000001d
2556#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0x0fff0000L
2557#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x00000010
2558#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0x0000ff00L
2559#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x00000008
2560#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0x000000ffL
2561#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x00000000
2562#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0x0000ff00L
2563#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x00000008
2564#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0x000000ffL
2565#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x00000000
2566#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000L
2567#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x00000018
2568#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0x00ff0000L
2569#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x00000010
2570#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000L
2571#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x00000018
2572#define MC_IMP_STATUS__NSTR_CAL_MASK 0x00ff0000L
2573#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x00000010
2574#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0x0000ff00L
2575#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x00000008
2576#define MC_IMP_STATUS__PSTR_CAL_MASK 0x000000ffL
2577#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x00000000
2578#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0x0c000000L
2579#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x0000001a
2580#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000L
2581#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x0000001c
2582#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000L
2583#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x0000001d
2584#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0x00000fc0L
2585#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x00000006
2586#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x0000003fL
2587#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x00000000
2588#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x0003f000L
2589#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0x0000000c
2590#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x01000000L
2591#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x00000018
2592#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x02000000L
2593#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x00000019
2594#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0x0c000000L
2595#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x0000001a
2596#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000L
2597#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x0000001c
2598#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000L
2599#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x0000001d
2600#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0x00000fc0L
2601#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x00000006
2602#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x0000003fL
2603#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x00000000
2604#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x0003f000L
2605#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0x0000000c
2606#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x01000000L
2607#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x00000018
2608#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x02000000L
2609#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x00000019
2610#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0x000000ffL
2611#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x00000000
2612#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0x0000ff00L
2613#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x00000008
2614#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0x00ff0000L
2615#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x00000010
2616#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000L
2617#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x00000018
2618#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0x000000ffL
2619#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x00000000
2620#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0x0000ff00L
2621#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x00000008
2622#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0x00ff0000L
2623#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x00000010
2624#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000L
2625#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x00000018
2626#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x00000001L
2627#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x00000000
2628#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x00000002L
2629#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x00000001
2630#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x00000004L
2631#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x00000002
2632#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x00000008L
2633#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x00000003
2634#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x00000010L
2635#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x00000004
2636#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x00000020L
2637#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x00000005
2638#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x00000040L
2639#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x00000006
2640#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x00000080L
2641#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x00000007
2642#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x00000001L
2643#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x00000000
2644#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x00000002L
2645#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x00000001
2646#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x00000004L
2647#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x00000002
2648#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x00000008L
2649#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x00000003
2650#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x00000010L
2651#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x00000004
2652#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x00000020L
2653#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x00000005
2654#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x00000040L
2655#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x00000006
2656#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x00000080L
2657#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x00000007
2658#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x00400000L
2659#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x00000016
2660#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x00800000L
2661#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x00000017
2662#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000L
2663#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x0000001c
2664#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000L
2665#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x0000001d
2666#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x00100000L
2667#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x00000014
2668#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x00200000L
2669#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x00000015
2670#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000L
2671#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x0000001e
2672#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000L
2673#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x0000001f
2674#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x00000400L
2675#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0x0000000a
2676#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x00000800L
2677#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0x0000000b
2678#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x00000100L
2679#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x00000008
2680#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x00000200L
2681#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x00000009
2682#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0x0000f000L
2683#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0x0000000c
2684#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0x000f0000L
2685#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x00000010
2686#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0x0000000fL
2687#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x00000000
2688#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0x000000f0L
2689#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x00000004
2690#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x04000000L
2691#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x0000001a
2692#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x08000000L
2693#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x0000001b
2694#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x01000000L
2695#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x00000018
2696#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x02000000L
2697#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x00000019
2698#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x00400000L
2699#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x00000016
2700#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x00800000L
2701#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x00000017
2702#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000L
2703#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x0000001c
2704#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000L
2705#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x0000001d
2706#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x00100000L
2707#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x00000014
2708#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x00200000L
2709#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x00000015
2710#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000L
2711#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x0000001e
2712#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000L
2713#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x0000001f
2714#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x00000400L
2715#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0x0000000a
2716#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x00000800L
2717#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0x0000000b
2718#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x00000100L
2719#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x00000008
2720#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x00000200L
2721#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x00000009
2722#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0x0000f000L
2723#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0x0000000c
2724#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0x000f0000L
2725#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x00000010
2726#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0x0000000fL
2727#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x00000000
2728#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0x000000f0L
2729#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x00000004
2730#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x04000000L
2731#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x0000001a
2732#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x08000000L
2733#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x0000001b
2734#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x01000000L
2735#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x00000018
2736#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x02000000L
2737#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x00000019
2738#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2739#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2740#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2741#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2742#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2743#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2744#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000L
2745#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2746#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2747#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2748#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2749#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2750#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2751#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2752#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000L
2753#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2754#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0x000000ffL
2755#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x00000000
2756#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0x0000ff00L
2757#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x00000008
2758#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0x00ff0000L
2759#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x00000010
2760#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000L
2761#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x00000018
2762#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0x000000ffL
2763#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x00000000
2764#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0x0000ff00L
2765#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x00000008
2766#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0x00ff0000L
2767#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x00000010
2768#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000L
2769#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x00000018
2770#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL
2771#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000
2772#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
2773#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008
2774#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
2775#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010
2776#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000L
2777#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018
2778#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL
2779#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000
2780#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
2781#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008
2782#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
2783#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010
2784#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000L
2785#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018
2786#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL
2787#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000
2788#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
2789#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008
2790#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
2791#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010
2792#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000L
2793#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018
2794#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL
2795#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000
2796#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
2797#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008
2798#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
2799#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010
2800#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000L
2801#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018
2802#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
2803#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
2804#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
2805#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
2806#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
2807#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
2808#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L
2809#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
2810#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
2811#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
2812#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
2813#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
2814#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
2815#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
2816#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L
2817#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
2818#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
2819#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
2820#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
2821#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
2822#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
2823#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
2824#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L
2825#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
2826#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
2827#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
2828#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
2829#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
2830#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
2831#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
2832#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L
2833#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
2834#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL
2835#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000
2836#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
2837#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008
2838#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
2839#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010
2840#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000L
2841#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018
2842#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL
2843#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000
2844#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
2845#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008
2846#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
2847#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010
2848#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000L
2849#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018
2850#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0x000000ffL
2851#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x00000000
2852#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L
2853#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x00000008
2854#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L
2855#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x00000010
2856#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000L
2857#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x00000018
2858#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0x000000ffL
2859#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x00000000
2860#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L
2861#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x00000008
2862#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L
2863#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x00000010
2864#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000L
2865#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x00000018
2866#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2867#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2868#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2869#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2870#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2871#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2872#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000L
2873#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2874#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2875#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2876#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2877#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2878#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2879#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2880#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000L
2881#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2882#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0x000000ffL
2883#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x00000000
2884#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0x0000ff00L
2885#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x00000008
2886#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0x00ff0000L
2887#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x00000010
2888#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000L
2889#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x00000018
2890#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0x000000ffL
2891#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x00000000
2892#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0x0000ff00L
2893#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x00000008
2894#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0x00ff0000L
2895#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x00000010
2896#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000L
2897#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x00000018
2898#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0x000000ffL
2899#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x00000000
2900#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
2901#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x00000008
2902#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
2903#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x00000010
2904#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000L
2905#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x00000018
2906#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0x000000ffL
2907#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x00000000
2908#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
2909#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x00000008
2910#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
2911#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x00000010
2912#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000L
2913#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x00000018
2914#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
2915#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
2916#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
2917#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
2918#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
2919#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
2920#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000L
2921#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
2922#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
2923#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
2924#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
2925#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
2926#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
2927#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
2928#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000L
2929#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
2930#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
2931#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
2932#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
2933#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
2934#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
2935#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
2936#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000L
2937#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
2938#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
2939#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
2940#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
2941#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
2942#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
2943#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
2944#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000L
2945#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
2946#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0x000000ffL
2947#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x00000000
2948#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
2949#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x00000008
2950#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
2951#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x00000010
2952#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000L
2953#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x00000018
2954#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0x000000ffL
2955#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x00000000
2956#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
2957#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x00000008
2958#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
2959#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x00000010
2960#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000L
2961#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x00000018
2962#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0x000000ffL
2963#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x00000000
2964#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0x0000ff00L
2965#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x00000008
2966#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0x00ff0000L
2967#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x00000010
2968#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000L
2969#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x00000018
2970#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0x000000ffL
2971#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x00000000
2972#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0x0000ff00L
2973#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x00000008
2974#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0x00ff0000L
2975#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x00000010
2976#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000L
2977#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x00000018
2978#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0x000000ffL
2979#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x00000000
2980#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
2981#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x00000008
2982#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
2983#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x00000010
2984#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000L
2985#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x00000018
2986#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0x000000ffL
2987#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x00000000
2988#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
2989#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x00000008
2990#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
2991#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x00000010
2992#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000L
2993#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x00000018
2994#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0x000000ffL
2995#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x00000000
2996#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0x0000ff00L
2997#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x00000008
2998#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0x00ff0000L
2999#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x00000010
3000#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000L
3001#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x00000018
3002#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0x000000ffL
3003#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x00000000
3004#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0x0000ff00L
3005#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x00000008
3006#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0x00ff0000L
3007#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x00000010
3008#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000L
3009#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x00000018
3010#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3011#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3012#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3013#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3014#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3015#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3016#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000L
3017#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3018#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3019#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3020#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3021#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3022#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3023#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3024#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000L
3025#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3026#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3027#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3028#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3029#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3030#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3031#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3032#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3033#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3034#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3035#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3036#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3037#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3038#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3039#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3040#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3041#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3042#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3043#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3044#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3045#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3046#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3047#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3048#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3049#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3050#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3051#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3052#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3053#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3054#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3055#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3056#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3057#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3058#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3059#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3060#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3061#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3062#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3063#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3064#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000L
3065#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3066#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3067#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3068#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3069#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3070#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3071#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3072#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000L
3073#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3074#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0x000000ffL
3075#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x00000000
3076#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3077#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x00000008
3078#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3079#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x00000010
3080#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000L
3081#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x00000018
3082#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0x000000ffL
3083#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x00000000
3084#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3085#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x00000008
3086#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3087#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x00000010
3088#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000L
3089#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x00000018
3090#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3091#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3092#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3093#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3094#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3095#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3096#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000L
3097#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3098#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3099#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3100#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3101#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3102#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3103#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3104#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000L
3105#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3106#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0x000000ffL
3107#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x00000000
3108#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0x0000ff00L
3109#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x00000008
3110#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0x00ff0000L
3111#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x00000010
3112#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000L
3113#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x00000018
3114#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0x000000ffL
3115#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x00000000
3116#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0x0000ff00L
3117#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x00000008
3118#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0x00ff0000L
3119#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x00000010
3120#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000L
3121#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x00000018
3122#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3123#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3124#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3125#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3126#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3127#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3128#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000L
3129#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3130#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3131#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3132#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3133#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3134#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3135#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3136#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000L
3137#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3138#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3139#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3140#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3141#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3142#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3143#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3144#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3145#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3146#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3147#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3148#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3149#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3150#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3151#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3152#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3153#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3154#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3155#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3156#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3157#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3158#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3159#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3160#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3161#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3162#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3163#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3164#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3165#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3166#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3167#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3168#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3169#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3170#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3171#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3172#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3173#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3174#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3175#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3176#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000L
3177#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3178#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3179#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3180#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3181#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3182#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3183#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3184#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000L
3185#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3186#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0x000000ffL
3187#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x00000000
3188#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3189#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x00000008
3190#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3191#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x00000010
3192#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000L
3193#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x00000018
3194#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0x000000ffL
3195#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x00000000
3196#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3197#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x00000008
3198#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3199#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x00000010
3200#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000L
3201#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x00000018
3202#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3203#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3204#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3205#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3206#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3207#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3208#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000L
3209#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3210#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3211#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3212#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3213#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3214#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3215#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3216#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000L
3217#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3218#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0x000000ffL
3219#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x00000000
3220#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0x0000ff00L
3221#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x00000008
3222#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0x00ff0000L
3223#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x00000010
3224#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000L
3225#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x00000018
3226#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0x000000ffL
3227#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x00000000
3228#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0x0000ff00L
3229#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x00000008
3230#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0x00ff0000L
3231#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x00000010
3232#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000L
3233#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x00000018
3234#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3235#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3236#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3237#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3238#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3239#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3240#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000L
3241#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3242#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3243#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3244#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3245#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3246#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3247#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3248#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000L
3249#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3250#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3251#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3252#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3253#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3254#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3255#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3256#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000L
3257#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3258#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3259#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3260#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3261#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3262#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3263#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3264#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000L
3265#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3266#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3267#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3268#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3269#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3270#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3271#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3272#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000L
3273#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3274#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3275#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3276#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3277#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3278#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3279#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3280#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000L
3281#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3282#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3283#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3284#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3285#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3286#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3287#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3288#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3289#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3290#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3291#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3292#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3293#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3294#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3295#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3296#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3297#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3298#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3299#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3300#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3301#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3302#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3303#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3304#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3305#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3306#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3307#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3308#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3309#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3310#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3311#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3312#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3313#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3314#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3315#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3316#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3317#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3318#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3319#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3320#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000L
3321#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3322#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3323#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3324#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3325#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3326#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3327#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3328#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000L
3329#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3330#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0x000000ffL
3331#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x00000000
3332#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3333#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x00000008
3334#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3335#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x00000010
3336#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000L
3337#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x00000018
3338#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0x000000ffL
3339#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x00000000
3340#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3341#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x00000008
3342#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3343#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x00000010
3344#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000L
3345#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x00000018
3346#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3347#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3348#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3349#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3350#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3351#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3352#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3353#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3354#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3355#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3356#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3357#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3358#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3359#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3360#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3361#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3362#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3363#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3364#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3365#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3366#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3367#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3368#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000L
3369#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3370#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3371#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3372#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3373#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3374#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3375#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3376#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000L
3377#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3378#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0x000000ffL
3379#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x00000000
3380#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0x0000ff00L
3381#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x00000008
3382#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0x00ff0000L
3383#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x00000010
3384#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000L
3385#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x00000018
3386#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0x000000ffL
3387#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x00000000
3388#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0x0000ff00L
3389#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x00000008
3390#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0x00ff0000L
3391#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x00000010
3392#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000L
3393#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x00000018
3394#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3395#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3396#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3397#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3398#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3399#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3400#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000L
3401#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3402#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3403#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3404#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3405#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3406#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3407#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3408#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000L
3409#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3410#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3411#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3412#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3413#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3414#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3415#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3416#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000L
3417#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3418#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3419#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3420#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3421#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3422#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3423#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3424#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000L
3425#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3426#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3427#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3428#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3429#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3430#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3431#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3432#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000L
3433#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3434#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3435#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3436#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3437#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3438#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3439#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3440#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000L
3441#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3442#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3443#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3444#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3445#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3446#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3447#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3448#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3449#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3450#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3451#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3452#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3453#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3454#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3455#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3456#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3457#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3458#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3459#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3460#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3461#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3462#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3463#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3464#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3465#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3466#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3467#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3468#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3469#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3470#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3471#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3472#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3473#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3474#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3475#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3476#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3477#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3478#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3479#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3480#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3481#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3482#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3483#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3484#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3485#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3486#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3487#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3488#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3489#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3490#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3491#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3492#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3493#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3494#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3495#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3496#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000L
3497#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3498#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3499#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3500#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3501#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3502#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3503#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3504#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000L
3505#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3506#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0x000000ffL
3507#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x00000000
3508#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3509#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x00000008
3510#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3511#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x00000010
3512#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000L
3513#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x00000018
3514#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0x000000ffL
3515#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x00000000
3516#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3517#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x00000008
3518#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3519#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x00000010
3520#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000L
3521#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x00000018
3522#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
3523#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
3524#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
3525#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
3526#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
3527#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
3528#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
3529#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
3530#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
3531#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
3532#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
3533#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
3534#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
3535#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
3536#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
3537#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
3538#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
3539#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
3540#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
3541#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
3542#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
3543#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
3544#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
3545#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
3546#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
3547#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
3548#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
3549#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
3550#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
3551#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
3552#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
3553#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
3554#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0x000000ffL
3555#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x00000000
3556#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0x0000ff00L
3557#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x00000008
3558#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0x00ff0000L
3559#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x00000010
3560#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000L
3561#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x00000018
3562#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0x000000ffL
3563#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x00000000
3564#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0x0000ff00L
3565#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x00000008
3566#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0x00ff0000L
3567#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x00000010
3568#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000L
3569#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x00000018
3570#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0x000000ffL
3571#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x00000000
3572#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0x0000ff00L
3573#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x00000008
3574#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0x00ff0000L
3575#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x00000010
3576#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000L
3577#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x00000018
3578#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0x000000ffL
3579#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x00000000
3580#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0x0000ff00L
3581#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x00000008
3582#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0x00ff0000L
3583#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x00000010
3584#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000L
3585#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x00000018
3586#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3587#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3588#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3589#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3590#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3591#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3592#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3593#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3594#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3595#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3596#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3597#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3598#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3599#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3600#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3601#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3602#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3603#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3604#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3605#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3606#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3607#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3608#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000L
3609#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3610#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3611#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3612#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3613#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3614#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3615#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3616#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000L
3617#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3618#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0x000000ffL
3619#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x00000000
3620#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0x0000ff00L
3621#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x00000008
3622#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0x00ff0000L
3623#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x00000010
3624#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000L
3625#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x00000018
3626#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0x000000ffL
3627#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x00000000
3628#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0x0000ff00L
3629#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x00000008
3630#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0x00ff0000L
3631#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x00000010
3632#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000L
3633#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x00000018
3634#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3635#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3636#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3637#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3638#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3639#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3640#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000L
3641#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3642#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3643#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3644#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3645#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3646#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3647#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3648#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000L
3649#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3650#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3651#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3652#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3653#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3654#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3655#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3656#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000L
3657#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3658#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3659#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3660#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3661#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3662#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3663#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3664#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000L
3665#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3666#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3667#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3668#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3669#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3670#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3671#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3672#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000L
3673#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3674#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3675#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3676#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3677#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3678#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3679#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3680#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000L
3681#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3682#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3683#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3684#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3685#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3686#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3687#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3688#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3689#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3690#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3691#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3692#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3693#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3694#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3695#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3696#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3697#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3698#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3699#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3700#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3701#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3702#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3703#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3704#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3705#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3706#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3707#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3708#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3709#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3710#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3711#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3712#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3713#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3714#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3715#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3716#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3717#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3718#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3719#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3720#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3721#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3722#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3723#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3724#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3725#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3726#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3727#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3728#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3729#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3730#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3731#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3732#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3733#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3734#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3735#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3736#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000L
3737#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3738#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3739#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3740#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3741#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3742#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3743#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3744#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000L
3745#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3746#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0x000000ffL
3747#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x00000000
3748#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3749#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x00000008
3750#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3751#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x00000010
3752#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000L
3753#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x00000018
3754#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0x000000ffL
3755#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x00000000
3756#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3757#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x00000008
3758#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3759#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x00000010
3760#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000L
3761#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x00000018
3762#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3763#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3764#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3765#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3766#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3767#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3768#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000L
3769#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3770#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3771#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3772#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3773#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3774#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3775#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3776#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000L
3777#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3778#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0x000000ffL
3779#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x00000000
3780#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0x0000ff00L
3781#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x00000008
3782#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0x00ff0000L
3783#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x00000010
3784#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000L
3785#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x00000018
3786#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0x000000ffL
3787#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x00000000
3788#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0x0000ff00L
3789#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x00000008
3790#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0x00ff0000L
3791#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x00000010
3792#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000L
3793#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x00000018
3794#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3795#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3796#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3797#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3798#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3799#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3800#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000L
3801#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3802#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3803#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3804#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3805#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3806#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3807#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3808#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000L
3809#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3810#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3811#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3812#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3813#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3814#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3815#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3816#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000L
3817#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3818#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3819#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3820#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3821#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3822#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3823#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
3824#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000L
3825#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
3826#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
3827#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
3828#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
3829#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
3830#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
3831#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
3832#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000L
3833#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
3834#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
3835#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
3836#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
3837#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
3838#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
3839#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
3840#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000L
3841#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
3842#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
3843#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
3844#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
3845#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
3846#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
3847#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
3848#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
3849#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
3850#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
3851#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
3852#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
3853#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
3854#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
3855#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
3856#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
3857#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
3858#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
3859#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
3860#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
3861#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
3862#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
3863#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
3864#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
3865#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
3866#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
3867#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
3868#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
3869#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
3870#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
3871#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
3872#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
3873#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
3874#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
3875#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
3876#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
3877#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
3878#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
3879#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
3880#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
3881#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
3882#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
3883#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
3884#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
3885#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
3886#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
3887#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
3888#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
3889#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
3890#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
3891#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
3892#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
3893#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
3894#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
3895#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
3896#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000L
3897#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
3898#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
3899#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
3900#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
3901#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
3902#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
3903#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
3904#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000L
3905#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
3906#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0x000000ffL
3907#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x00000000
3908#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
3909#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x00000008
3910#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
3911#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x00000010
3912#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000L
3913#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x00000018
3914#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0x000000ffL
3915#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x00000000
3916#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
3917#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x00000008
3918#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
3919#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x00000010
3920#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000L
3921#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x00000018
3922#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
3923#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
3924#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
3925#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
3926#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
3927#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
3928#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
3929#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
3930#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
3931#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
3932#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
3933#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
3934#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
3935#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
3936#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
3937#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
3938#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
3939#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
3940#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
3941#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
3942#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
3943#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
3944#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000L
3945#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
3946#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
3947#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
3948#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
3949#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
3950#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
3951#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
3952#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000L
3953#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
3954#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0x000000ffL
3955#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x00000000
3956#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0x0000ff00L
3957#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x00000008
3958#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0x00ff0000L
3959#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x00000010
3960#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000L
3961#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x00000018
3962#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0x000000ffL
3963#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x00000000
3964#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0x0000ff00L
3965#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x00000008
3966#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0x00ff0000L
3967#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x00000010
3968#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000L
3969#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x00000018
3970#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
3971#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
3972#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
3973#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
3974#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
3975#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
3976#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000L
3977#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
3978#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
3979#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
3980#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
3981#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
3982#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
3983#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
3984#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000L
3985#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
3986#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
3987#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
3988#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
3989#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
3990#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
3991#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
3992#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000L
3993#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
3994#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
3995#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
3996#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
3997#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
3998#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
3999#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4000#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000L
4001#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4002#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4003#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4004#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4005#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4006#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4007#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4008#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000L
4009#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4010#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4011#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4012#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4013#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4014#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4015#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4016#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000L
4017#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4018#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4019#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4020#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4021#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4022#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4023#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4024#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4025#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4026#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4027#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4028#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4029#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4030#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4031#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4032#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4033#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4034#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4035#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4036#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4037#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4038#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4039#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4040#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4041#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4042#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4043#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4044#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4045#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4046#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4047#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4048#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4049#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4050#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4051#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4052#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4053#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4054#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4055#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4056#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4057#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4058#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4059#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4060#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4061#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4062#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4063#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4064#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4065#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4066#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4067#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4068#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4069#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4070#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4071#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4072#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000L
4073#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4074#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4075#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4076#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4077#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4078#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4079#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4080#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000L
4081#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4082#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0x000000ffL
4083#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x00000000
4084#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4085#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x00000008
4086#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4087#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x00000010
4088#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000L
4089#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x00000018
4090#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0x000000ffL
4091#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x00000000
4092#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4093#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x00000008
4094#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4095#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x00000010
4096#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000L
4097#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x00000018
4098#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4099#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4100#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4101#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4102#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4103#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4104#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000L
4105#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4106#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4107#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4108#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4109#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4110#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4111#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4112#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000L
4113#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4114#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0x000000ffL
4115#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x00000000
4116#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0x0000ff00L
4117#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x00000008
4118#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0x00ff0000L
4119#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x00000010
4120#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000L
4121#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x00000018
4122#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0x000000ffL
4123#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x00000000
4124#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0x0000ff00L
4125#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x00000008
4126#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0x00ff0000L
4127#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x00000010
4128#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000L
4129#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x00000018
4130#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4131#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4132#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4133#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4134#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4135#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4136#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000L
4137#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4138#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4139#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4140#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4141#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4142#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4143#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4144#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000L
4145#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4146#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4147#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4148#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4149#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4150#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4151#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4152#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000L
4153#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4154#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4155#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4156#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4157#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4158#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4159#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4160#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000L
4161#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4162#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4163#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4164#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4165#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4166#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4167#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4168#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000L
4169#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4170#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4171#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4172#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4173#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4174#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4175#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4176#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000L
4177#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4178#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4179#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4180#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4181#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4182#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4183#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4184#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4185#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4186#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4187#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4188#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4189#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4190#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4191#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4192#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4193#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4194#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4195#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4196#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4197#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4198#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4199#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4200#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4201#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4202#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4203#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4204#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4205#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4206#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4207#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4208#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4209#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4210#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4211#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4212#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4213#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4214#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4215#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4216#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4217#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4218#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4219#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4220#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4221#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4222#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4223#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4224#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4225#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4226#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4227#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4228#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4229#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4230#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4231#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4232#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000L
4233#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4234#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4235#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4236#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4237#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4238#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4239#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4240#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000L
4241#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4242#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0x000000ffL
4243#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x00000000
4244#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4245#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x00000008
4246#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4247#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x00000010
4248#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000L
4249#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x00000018
4250#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0x000000ffL
4251#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x00000000
4252#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4253#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x00000008
4254#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4255#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x00000010
4256#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000L
4257#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x00000018
4258#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0x000000ffL
4259#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x00000000
4260#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0x0000ff00L
4261#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x00000008
4262#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0x00ff0000L
4263#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x00000010
4264#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000L
4265#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x00000018
4266#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0x000000ffL
4267#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x00000000
4268#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0x0000ff00L
4269#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x00000008
4270#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0x00ff0000L
4271#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x00000010
4272#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000L
4273#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x00000018
4274#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4275#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4276#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4277#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4278#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4279#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4280#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000L
4281#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4282#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4283#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4284#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4285#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4286#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4287#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4288#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000L
4289#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4290#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0x000000ffL
4291#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x00000000
4292#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0x0000ff00L
4293#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x00000008
4294#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0x00ff0000L
4295#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x00000010
4296#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000L
4297#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x00000018
4298#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0x000000ffL
4299#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x00000000
4300#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0x0000ff00L
4301#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x00000008
4302#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0x00ff0000L
4303#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x00000010
4304#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000L
4305#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x00000018
4306#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4307#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4308#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4309#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4310#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4311#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4312#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000L
4313#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4314#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4315#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4316#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4317#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4318#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4319#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4320#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000L
4321#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4322#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4323#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4324#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4325#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4326#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4327#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4328#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000L
4329#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4330#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4331#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4332#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4333#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4334#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4335#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4336#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000L
4337#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4338#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4339#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4340#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4341#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4342#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4343#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4344#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000L
4345#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4346#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4347#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4348#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4349#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4350#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4351#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4352#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000L
4353#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4354#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4355#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4356#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4357#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4358#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4359#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4360#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4361#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4362#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4363#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4364#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4365#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4366#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4367#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4368#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4369#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4370#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4371#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x00000000
4372#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0x0000ff00L
4373#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x00000008
4374#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0x00ff0000L
4375#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x00000010
4376#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000L
4377#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x00000018
4378#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0x000000ffL
4379#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x00000000
4380#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0x0000ff00L
4381#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x00000008
4382#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0x00ff0000L
4383#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x00000010
4384#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000L
4385#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x00000018
4386#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0x000000ffL
4387#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x00000000
4388#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0x0000ff00L
4389#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x00000008
4390#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0x00ff0000L
4391#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x00000010
4392#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000L
4393#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x00000018
4394#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0x000000ffL
4395#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x00000000
4396#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0x0000ff00L
4397#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x00000008
4398#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0x00ff0000L
4399#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x00000010
4400#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000L
4401#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x00000018
4402#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0x000000ffL
4403#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x00000000
4404#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0x0000ff00L
4405#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x00000008
4406#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0x00ff0000L
4407#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x00000010
4408#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000L
4409#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x00000018
4410#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0x000000ffL
4411#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x00000000
4412#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0x0000ff00L
4413#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x00000008
4414#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0x00ff0000L
4415#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x00000010
4416#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000L
4417#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x00000018
4418#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0x000000ffL
4419#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x00000000
4420#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0x0000ff00L
4421#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x00000008
4422#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0x00ff0000L
4423#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x00000010
4424#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000L
4425#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x00000018
4426#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0x000000ffL
4427#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x00000000
4428#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0x0000ff00L
4429#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x00000008
4430#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0x00ff0000L
4431#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x00000010
4432#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000L
4433#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x00000018
4434#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0x000000ffL
4435#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x00000000
4436#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0x0000ff00L
4437#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x00000008
4438#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0x00ff0000L
4439#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x00000010
4440#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000L
4441#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x00000018
4442#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0x000000ffL
4443#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x00000000
4444#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0x0000ff00L
4445#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x00000008
4446#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0x00ff0000L
4447#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x00000010
4448#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000L
4449#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x00000018
4450#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0x000000ffL
4451#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x00000000
4452#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0x0000ff00L
4453#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x00000008
4454#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0x00ff0000L
4455#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x00000010
4456#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000L
4457#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x00000018
4458#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0x000000ffL
4459#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x00000000
4460#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0x0000ff00L
4461#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x00000008
4462#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0x00ff0000L
4463#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x00000010
4464#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000L
4465#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x00000018
4466#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0x000000ffL
4467#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x00000000
4468#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0x0000ff00L
4469#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x00000008
4470#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0x00ff0000L
4471#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x00000010
4472#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000L
4473#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x00000018
4474#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0x000000ffL
4475#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x00000000
4476#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0x0000ff00L
4477#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x00000008
4478#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0x00ff0000L
4479#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x00000010
4480#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000L
4481#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x00000018
4482#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0x000000ffL
4483#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x00000000
4484#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0x0000ff00L
4485#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x00000008
4486#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0x00ff0000L
4487#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x00000010
4488#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000L
4489#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x00000018
4490#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0x000000ffL
4491#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x00000000
4492#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0x0000ff00L
4493#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x00000008
4494#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0x00ff0000L
4495#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x00000010
4496#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000L
4497#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x00000018
4498#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0x000000ffL
4499#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x00000000
4500#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0x0000ff00L
4501#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x00000008
4502#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0x00ff0000L
4503#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x00000010
4504#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000L
4505#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x00000018
4506#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0x000000ffL
4507#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x00000000
4508#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0x0000ff00L
4509#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x00000008
4510#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0x00ff0000L
4511#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x00000010
4512#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000L
4513#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x00000018
4514#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0x000000ffL
4515#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x00000000
4516#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0x0000ff00L
4517#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x00000008
4518#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0x00ff0000L
4519#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x00000010
4520#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000L
4521#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x00000018
4522#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0x000000ffL
4523#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x00000000
4524#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0x0000ff00L
4525#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x00000008
4526#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0x00ff0000L
4527#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x00000010
4528#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000L
4529#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x00000018
4530#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0x000000ffL
4531#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT