| 1 | /* |
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| 2 | * Copyright 2021 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef _hdp_6_0_0_OFFSET_HEADER |
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| 24 | #define |
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| 25 | |
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| 26 | |
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| 27 | |
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| 28 | // addressBlock: hdp_hdpdec |
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| 29 | // base address: 0x3c80 |
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| 30 | #define regHDP_NONSURFACE_BASE 0x0040 |
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| 31 | #define regHDP_NONSURFACE_BASE_BASE_IDX 0 |
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| 32 | #define regHDP_NONSURFACE_INFO 0x0041 |
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| 33 | #define regHDP_NONSURFACE_INFO_BASE_IDX 0 |
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| 34 | #define regHDP_NONSURFACE_BASE_HI 0x0042 |
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| 35 | #define regHDP_NONSURFACE_BASE_HI_BASE_IDX 0 |
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| 36 | #define regHDP_SURFACE_WRITE_FLAGS 0x00c4 |
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| 37 | #define regHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0 |
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| 38 | #define regHDP_SURFACE_READ_FLAGS 0x00c5 |
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| 39 | #define regHDP_SURFACE_READ_FLAGS_BASE_IDX 0 |
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| 40 | #define regHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6 |
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| 41 | #define regHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0 |
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| 42 | #define regHDP_SURFACE_READ_FLAGS_CLR 0x00c7 |
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| 43 | #define regHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0 |
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| 44 | #define regHDP_NONSURF_FLAGS 0x00c8 |
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| 45 | #define regHDP_NONSURF_FLAGS_BASE_IDX 0 |
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| 46 | #define regHDP_NONSURF_FLAGS_CLR 0x00c9 |
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| 47 | #define regHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 |
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| 48 | #define regHDP_HOST_PATH_CNTL 0x00cc |
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| 49 | #define regHDP_HOST_PATH_CNTL_BASE_IDX 0 |
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| 50 | #define regHDP_SW_SEMAPHORE 0x00cd |
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| 51 | #define regHDP_SW_SEMAPHORE_BASE_IDX 0 |
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| 52 | #define regHDP_DEBUG0 0x00ce |
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| 53 | #define regHDP_DEBUG0_BASE_IDX 0 |
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| 54 | #define regHDP_LAST_SURFACE_HIT 0x00d0 |
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| 55 | #define regHDP_LAST_SURFACE_HIT_BASE_IDX 0 |
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| 56 | #define regHDP_OUTSTANDING_REQ 0x00d2 |
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| 57 | #define regHDP_OUTSTANDING_REQ_BASE_IDX 0 |
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| 58 | #define regHDP_MISC_CNTL 0x00d3 |
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| 59 | #define regHDP_MISC_CNTL_BASE_IDX 0 |
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| 60 | #define regHDP_MEM_POWER_CTRL 0x00d4 |
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| 61 | #define regHDP_MEM_POWER_CTRL_BASE_IDX 0 |
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| 62 | #define regHDP_MMHUB_CNTL 0x00d5 |
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| 63 | #define regHDP_MMHUB_CNTL_BASE_IDX 0 |
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| 64 | #define regHDP_VERSION 0x00d7 |
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| 65 | #define regHDP_VERSION_BASE_IDX 0 |
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| 66 | #define regHDP_CLK_CNTL 0x00d8 |
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| 67 | #define regHDP_CLK_CNTL_BASE_IDX 0 |
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| 68 | #define regHDP_MEMIO_CNTL 0x00f6 |
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| 69 | #define regHDP_MEMIO_CNTL_BASE_IDX 0 |
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| 70 | #define regHDP_MEMIO_ADDR 0x00f7 |
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| 71 | #define regHDP_MEMIO_ADDR_BASE_IDX 0 |
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| 72 | #define regHDP_MEMIO_STATUS 0x00f8 |
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| 73 | #define regHDP_MEMIO_STATUS_BASE_IDX 0 |
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| 74 | #define regHDP_MEMIO_WR_DATA 0x00f9 |
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| 75 | #define regHDP_MEMIO_WR_DATA_BASE_IDX 0 |
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| 76 | #define regHDP_MEMIO_RD_DATA 0x00fa |
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| 77 | #define regHDP_MEMIO_RD_DATA_BASE_IDX 0 |
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| 78 | #define regHDP_XDP_DIRECT2HDP_FIRST 0x0100 |
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| 79 | #define regHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 |
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| 80 | #define regHDP_XDP_D2H_FLUSH 0x0101 |
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| 81 | #define regHDP_XDP_D2H_FLUSH_BASE_IDX 0 |
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| 82 | #define regHDP_XDP_D2H_BAR_UPDATE 0x0102 |
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| 83 | #define regHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 |
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| 84 | #define regHDP_XDP_D2H_RSVD_3 0x0103 |
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| 85 | #define regHDP_XDP_D2H_RSVD_3_BASE_IDX 0 |
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| 86 | #define regHDP_XDP_D2H_RSVD_4 0x0104 |
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| 87 | #define regHDP_XDP_D2H_RSVD_4_BASE_IDX 0 |
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| 88 | #define regHDP_XDP_D2H_RSVD_5 0x0105 |
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| 89 | #define regHDP_XDP_D2H_RSVD_5_BASE_IDX 0 |
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| 90 | #define regHDP_XDP_D2H_RSVD_6 0x0106 |
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| 91 | #define regHDP_XDP_D2H_RSVD_6_BASE_IDX 0 |
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| 92 | #define regHDP_XDP_D2H_RSVD_7 0x0107 |
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| 93 | #define regHDP_XDP_D2H_RSVD_7_BASE_IDX 0 |
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| 94 | #define regHDP_XDP_D2H_RSVD_8 0x0108 |
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| 95 | #define regHDP_XDP_D2H_RSVD_8_BASE_IDX 0 |
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| 96 | #define regHDP_XDP_D2H_RSVD_9 0x0109 |
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| 97 | #define regHDP_XDP_D2H_RSVD_9_BASE_IDX 0 |
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| 98 | #define regHDP_XDP_D2H_RSVD_10 0x010a |
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| 99 | #define regHDP_XDP_D2H_RSVD_10_BASE_IDX 0 |
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| 100 | #define regHDP_XDP_D2H_RSVD_11 0x010b |
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| 101 | #define regHDP_XDP_D2H_RSVD_11_BASE_IDX 0 |
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| 102 | #define regHDP_XDP_D2H_RSVD_12 0x010c |
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| 103 | #define regHDP_XDP_D2H_RSVD_12_BASE_IDX 0 |
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| 104 | #define regHDP_XDP_D2H_RSVD_13 0x010d |
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| 105 | #define regHDP_XDP_D2H_RSVD_13_BASE_IDX 0 |
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| 106 | #define regHDP_XDP_D2H_RSVD_14 0x010e |
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| 107 | #define regHDP_XDP_D2H_RSVD_14_BASE_IDX 0 |
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| 108 | #define regHDP_XDP_D2H_RSVD_15 0x010f |
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| 109 | #define regHDP_XDP_D2H_RSVD_15_BASE_IDX 0 |
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| 110 | #define regHDP_XDP_D2H_RSVD_16 0x0110 |
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| 111 | #define regHDP_XDP_D2H_RSVD_16_BASE_IDX 0 |
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| 112 | #define regHDP_XDP_D2H_RSVD_17 0x0111 |
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| 113 | #define regHDP_XDP_D2H_RSVD_17_BASE_IDX 0 |
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| 114 | #define regHDP_XDP_D2H_RSVD_18 0x0112 |
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| 115 | #define regHDP_XDP_D2H_RSVD_18_BASE_IDX 0 |
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| 116 | #define regHDP_XDP_D2H_RSVD_19 0x0113 |
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| 117 | #define regHDP_XDP_D2H_RSVD_19_BASE_IDX 0 |
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| 118 | #define regHDP_XDP_D2H_RSVD_20 0x0114 |
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| 119 | #define regHDP_XDP_D2H_RSVD_20_BASE_IDX 0 |
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| 120 | #define regHDP_XDP_D2H_RSVD_21 0x0115 |
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| 121 | #define regHDP_XDP_D2H_RSVD_21_BASE_IDX 0 |
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| 122 | #define regHDP_XDP_D2H_RSVD_22 0x0116 |
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| 123 | #define regHDP_XDP_D2H_RSVD_22_BASE_IDX 0 |
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| 124 | #define regHDP_XDP_D2H_RSVD_23 0x0117 |
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| 125 | #define regHDP_XDP_D2H_RSVD_23_BASE_IDX 0 |
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| 126 | #define regHDP_XDP_D2H_RSVD_24 0x0118 |
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| 127 | #define regHDP_XDP_D2H_RSVD_24_BASE_IDX 0 |
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| 128 | #define regHDP_XDP_D2H_RSVD_25 0x0119 |
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| 129 | #define regHDP_XDP_D2H_RSVD_25_BASE_IDX 0 |
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| 130 | #define regHDP_XDP_D2H_RSVD_26 0x011a |
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| 131 | #define regHDP_XDP_D2H_RSVD_26_BASE_IDX 0 |
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| 132 | #define regHDP_XDP_D2H_RSVD_27 0x011b |
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| 133 | #define regHDP_XDP_D2H_RSVD_27_BASE_IDX 0 |
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| 134 | #define regHDP_XDP_D2H_RSVD_28 0x011c |
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| 135 | #define regHDP_XDP_D2H_RSVD_28_BASE_IDX 0 |
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| 136 | #define regHDP_XDP_D2H_RSVD_29 0x011d |
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| 137 | #define regHDP_XDP_D2H_RSVD_29_BASE_IDX 0 |
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| 138 | #define regHDP_XDP_D2H_RSVD_30 0x011e |
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| 139 | #define regHDP_XDP_D2H_RSVD_30_BASE_IDX 0 |
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| 140 | #define regHDP_XDP_D2H_RSVD_31 0x011f |
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| 141 | #define regHDP_XDP_D2H_RSVD_31_BASE_IDX 0 |
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| 142 | #define regHDP_XDP_D2H_RSVD_32 0x0120 |
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| 143 | #define regHDP_XDP_D2H_RSVD_32_BASE_IDX 0 |
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| 144 | #define regHDP_XDP_D2H_RSVD_33 0x0121 |
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| 145 | #define regHDP_XDP_D2H_RSVD_33_BASE_IDX 0 |
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| 146 | #define regHDP_XDP_D2H_RSVD_34 0x0122 |
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| 147 | #define regHDP_XDP_D2H_RSVD_34_BASE_IDX 0 |
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| 148 | #define regHDP_XDP_DIRECT2HDP_LAST 0x0123 |
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| 149 | #define regHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 |
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| 150 | #define regHDP_XDP_P2P_BAR_CFG 0x0124 |
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| 151 | #define regHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 |
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| 152 | #define regHDP_XDP_P2P_MBX_OFFSET 0x0125 |
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| 153 | #define regHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 |
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| 154 | #define regHDP_XDP_P2P_MBX_ADDR0 0x0126 |
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| 155 | #define regHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 |
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| 156 | #define regHDP_XDP_P2P_MBX_ADDR1 0x0127 |
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| 157 | #define regHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 |
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| 158 | #define regHDP_XDP_P2P_MBX_ADDR2 0x0128 |
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| 159 | #define regHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 |
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| 160 | #define regHDP_XDP_P2P_MBX_ADDR3 0x0129 |
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| 161 | #define regHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 |
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| 162 | #define regHDP_XDP_P2P_MBX_ADDR4 0x012a |
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| 163 | #define regHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 |
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| 164 | #define regHDP_XDP_P2P_MBX_ADDR5 0x012b |
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| 165 | #define regHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 |
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| 166 | #define regHDP_XDP_P2P_MBX_ADDR6 0x012c |
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| 167 | #define regHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 |
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| 168 | #define regHDP_XDP_HDP_MBX_MC_CFG 0x012d |
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| 169 | #define regHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 |
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| 170 | #define regHDP_XDP_HDP_MC_CFG 0x012e |
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| 171 | #define regHDP_XDP_HDP_MC_CFG_BASE_IDX 0 |
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| 172 | #define regHDP_XDP_HST_CFG 0x012f |
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| 173 | #define regHDP_XDP_HST_CFG_BASE_IDX 0 |
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| 174 | #define regHDP_XDP_HDP_IPH_CFG 0x0131 |
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| 175 | #define regHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 |
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| 176 | #define regHDP_XDP_P2P_BAR0 0x0134 |
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| 177 | #define regHDP_XDP_P2P_BAR0_BASE_IDX 0 |
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| 178 | #define regHDP_XDP_P2P_BAR1 0x0135 |
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| 179 | #define regHDP_XDP_P2P_BAR1_BASE_IDX 0 |
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| 180 | #define regHDP_XDP_P2P_BAR2 0x0136 |
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| 181 | #define regHDP_XDP_P2P_BAR2_BASE_IDX 0 |
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| 182 | #define regHDP_XDP_P2P_BAR3 0x0137 |
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| 183 | #define regHDP_XDP_P2P_BAR3_BASE_IDX 0 |
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| 184 | #define regHDP_XDP_P2P_BAR4 0x0138 |
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| 185 | #define regHDP_XDP_P2P_BAR4_BASE_IDX 0 |
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| 186 | #define regHDP_XDP_P2P_BAR5 0x0139 |
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| 187 | #define regHDP_XDP_P2P_BAR5_BASE_IDX 0 |
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| 188 | #define regHDP_XDP_P2P_BAR6 0x013a |
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| 189 | #define regHDP_XDP_P2P_BAR6_BASE_IDX 0 |
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| 190 | #define regHDP_XDP_P2P_BAR7 0x013b |
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| 191 | #define regHDP_XDP_P2P_BAR7_BASE_IDX 0 |
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| 192 | #define regHDP_XDP_FLUSH_ARMED_STS 0x013c |
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| 193 | #define regHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 |
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| 194 | #define regHDP_XDP_FLUSH_CNTR0_STS 0x013d |
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| 195 | #define regHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 |
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| 196 | #define regHDP_XDP_BUSY_STS 0x013e |
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| 197 | #define regHDP_XDP_BUSY_STS_BASE_IDX 0 |
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| 198 | #define regHDP_XDP_STICKY 0x013f |
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| 199 | #define regHDP_XDP_STICKY_BASE_IDX 0 |
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| 200 | #define regHDP_XDP_CHKN 0x0140 |
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| 201 | #define regHDP_XDP_CHKN_BASE_IDX 0 |
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| 202 | #define regHDP_XDP_BARS_ADDR_39_36 0x0144 |
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| 203 | #define regHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 |
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| 204 | #define regHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 |
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| 205 | #define regHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 |
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| 206 | #define regHDP_XDP_MMHUB_ERROR 0x014a |
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| 207 | #define regHDP_XDP_MMHUB_ERROR_BASE_IDX 0 |
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| 208 | |
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| 209 | #endif |
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| 210 | |
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