1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _lsdma_6_0_0_OFFSET_HEADER |
24 | #define |
25 | |
26 | |
27 | |
28 | // addressBlock: lsdma0_lsdma0dec |
29 | // base address: 0x45000 |
30 | #define regLSDMA_UCODE_ADDR 0x0000 |
31 | #define regLSDMA_UCODE_ADDR_BASE_IDX 0 |
32 | #define regLSDMA_UCODE_DATA 0x0001 |
33 | #define regLSDMA_UCODE_DATA_BASE_IDX 0 |
34 | #define regLSDMA_ERROR_INJECT_CNTL 0x0004 |
35 | #define regLSDMA_ERROR_INJECT_CNTL_BASE_IDX 0 |
36 | #define regLSDMA_ERROR_INJECT_SELECT 0x0005 |
37 | #define regLSDMA_ERROR_INJECT_SELECT_BASE_IDX 0 |
38 | #define regLSDMA_CONTEXT_GROUP_BOUNDARY 0x001f |
39 | #define regLSDMA_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 |
40 | #define regLSDMA_RB_RPTR_FETCH_HI 0x0020 |
41 | #define regLSDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 |
42 | #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 |
43 | #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 |
44 | #define regLSDMA_RB_RPTR_FETCH 0x0022 |
45 | #define regLSDMA_RB_RPTR_FETCH_BASE_IDX 0 |
46 | #define regLSDMA_IB_OFFSET_FETCH 0x0023 |
47 | #define regLSDMA_IB_OFFSET_FETCH_BASE_IDX 0 |
48 | #define regLSDMA_PROGRAM 0x0024 |
49 | #define regLSDMA_PROGRAM_BASE_IDX 0 |
50 | #define regLSDMA_STATUS_REG 0x0025 |
51 | #define regLSDMA_STATUS_REG_BASE_IDX 0 |
52 | #define regLSDMA_STATUS1_REG 0x0026 |
53 | #define regLSDMA_STATUS1_REG_BASE_IDX 0 |
54 | #define regLSDMA_RD_BURST_CNTL 0x0027 |
55 | #define regLSDMA_RD_BURST_CNTL_BASE_IDX 0 |
56 | #define regLSDMA_HBM_PAGE_CONFIG 0x0028 |
57 | #define regLSDMA_HBM_PAGE_CONFIG_BASE_IDX 0 |
58 | #define regLSDMA_UCODE_CHECKSUM 0x0029 |
59 | #define regLSDMA_UCODE_CHECKSUM_BASE_IDX 0 |
60 | #define regLSDMA_FREEZE 0x002b |
61 | #define regLSDMA_FREEZE_BASE_IDX 0 |
62 | #define regLSDMA_PF_PIO_STATUS 0x002c |
63 | #define regLSDMA_PF_PIO_STATUS_BASE_IDX 0 |
64 | #define regLSDMA_VF_PIO_STATUS 0x002d |
65 | #define regLSDMA_VF_PIO_STATUS_BASE_IDX 0 |
66 | #define regLSDMA_POWER_GATING 0x002e |
67 | #define regLSDMA_POWER_GATING_BASE_IDX 0 |
68 | #define regLSDMA_PGFSM_CONFIG 0x002f |
69 | #define regLSDMA_PGFSM_CONFIG_BASE_IDX 0 |
70 | #define regLSDMA_PGFSM_WRITE 0x0030 |
71 | #define regLSDMA_PGFSM_WRITE_BASE_IDX 0 |
72 | #define regLSDMA_PGFSM_READ 0x0031 |
73 | #define regLSDMA_PGFSM_READ_BASE_IDX 0 |
74 | #define regLSDMA_PIO_STATUS 0x0032 |
75 | #define regLSDMA_PIO_STATUS_BASE_IDX 0 |
76 | #define regLSDMA_BA_THRESHOLD 0x0033 |
77 | #define regLSDMA_BA_THRESHOLD_BASE_IDX 0 |
78 | #define regLSDMA_ID 0x0034 |
79 | #define regLSDMA_ID_BASE_IDX 0 |
80 | #define regLSDMA_VERSION 0x0035 |
81 | #define regLSDMA_VERSION_BASE_IDX 0 |
82 | #define regLSDMA_EDC_COUNTER 0x0036 |
83 | #define regLSDMA_EDC_COUNTER_BASE_IDX 0 |
84 | #define regLSDMA_EDC_COUNTER2 0x0037 |
85 | #define regLSDMA_EDC_COUNTER2_BASE_IDX 0 |
86 | #define regLSDMA_STATUS2_REG 0x0038 |
87 | #define regLSDMA_STATUS2_REG_BASE_IDX 0 |
88 | #define regLSDMA_ATOMIC_CNTL 0x0039 |
89 | #define regLSDMA_ATOMIC_CNTL_BASE_IDX 0 |
90 | #define regLSDMA_ATOMIC_PREOP_LO 0x003a |
91 | #define regLSDMA_ATOMIC_PREOP_LO_BASE_IDX 0 |
92 | #define regLSDMA_ATOMIC_PREOP_HI 0x003b |
93 | #define regLSDMA_ATOMIC_PREOP_HI_BASE_IDX 0 |
94 | #define regLSDMA_UTCL1_CNTL 0x003c |
95 | #define regLSDMA_UTCL1_CNTL_BASE_IDX 0 |
96 | #define regLSDMA_UTCL1_WATERMK 0x003d |
97 | #define regLSDMA_UTCL1_WATERMK_BASE_IDX 0 |
98 | #define regLSDMA_UTCL1_RD_STATUS 0x003e |
99 | #define regLSDMA_UTCL1_RD_STATUS_BASE_IDX 0 |
100 | #define regLSDMA_UTCL1_WR_STATUS 0x003f |
101 | #define regLSDMA_UTCL1_WR_STATUS_BASE_IDX 0 |
102 | #define regLSDMA_UTCL1_INV0 0x0040 |
103 | #define regLSDMA_UTCL1_INV0_BASE_IDX 0 |
104 | #define regLSDMA_UTCL1_INV1 0x0041 |
105 | #define regLSDMA_UTCL1_INV1_BASE_IDX 0 |
106 | #define regLSDMA_UTCL1_INV2 0x0042 |
107 | #define regLSDMA_UTCL1_INV2_BASE_IDX 0 |
108 | #define regLSDMA_UTCL1_RD_XNACK0 0x0043 |
109 | #define regLSDMA_UTCL1_RD_XNACK0_BASE_IDX 0 |
110 | #define regLSDMA_UTCL1_RD_XNACK1 0x0044 |
111 | #define regLSDMA_UTCL1_RD_XNACK1_BASE_IDX 0 |
112 | #define regLSDMA_UTCL1_WR_XNACK0 0x0045 |
113 | #define regLSDMA_UTCL1_WR_XNACK0_BASE_IDX 0 |
114 | #define regLSDMA_UTCL1_WR_XNACK1 0x0046 |
115 | #define regLSDMA_UTCL1_WR_XNACK1_BASE_IDX 0 |
116 | #define regLSDMA_UTCL1_TIMEOUT 0x0047 |
117 | #define regLSDMA_UTCL1_TIMEOUT_BASE_IDX 0 |
118 | #define regLSDMA_UTCL1_PAGE 0x0048 |
119 | #define regLSDMA_UTCL1_PAGE_BASE_IDX 0 |
120 | #define regLSDMA_RELAX_ORDERING_LUT 0x004a |
121 | #define regLSDMA_RELAX_ORDERING_LUT_BASE_IDX 0 |
122 | #define regLSDMA_CHICKEN_BITS_2 0x004b |
123 | #define regLSDMA_CHICKEN_BITS_2_BASE_IDX 0 |
124 | #define regLSDMA_STATUS3_REG 0x004c |
125 | #define regLSDMA_STATUS3_REG_BASE_IDX 0 |
126 | #define regLSDMA_PHYSICAL_ADDR_LO 0x004d |
127 | #define regLSDMA_PHYSICAL_ADDR_LO_BASE_IDX 0 |
128 | #define regLSDMA_PHYSICAL_ADDR_HI 0x004e |
129 | #define regLSDMA_PHYSICAL_ADDR_HI_BASE_IDX 0 |
130 | #define regLSDMA_ECC_CNTL 0x004f |
131 | #define regLSDMA_ECC_CNTL_BASE_IDX 0 |
132 | #define regLSDMA_ERROR_LOG 0x0050 |
133 | #define regLSDMA_ERROR_LOG_BASE_IDX 0 |
134 | #define regLSDMA_PUB_DUMMY0 0x0051 |
135 | #define regLSDMA_PUB_DUMMY0_BASE_IDX 0 |
136 | #define regLSDMA_PUB_DUMMY1 0x0052 |
137 | #define regLSDMA_PUB_DUMMY1_BASE_IDX 0 |
138 | #define regLSDMA_PUB_DUMMY2 0x0053 |
139 | #define regLSDMA_PUB_DUMMY2_BASE_IDX 0 |
140 | #define regLSDMA_PUB_DUMMY3 0x0054 |
141 | #define regLSDMA_PUB_DUMMY3_BASE_IDX 0 |
142 | #define regLSDMA_F32_COUNTER 0x0055 |
143 | #define regLSDMA_F32_COUNTER_BASE_IDX 0 |
144 | #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG 0x0057 |
145 | #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 |
146 | #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG 0x0058 |
147 | #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 |
148 | #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059 |
149 | #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
150 | #define regLSDMA_PERFCNT_MISC_CNTL 0x005a |
151 | #define regLSDMA_PERFCNT_MISC_CNTL_BASE_IDX 0 |
152 | #define regLSDMA_PERFCNT_PERFCOUNTER_LO 0x005b |
153 | #define regLSDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 |
154 | #define regLSDMA_PERFCNT_PERFCOUNTER_HI 0x005c |
155 | #define regLSDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 |
156 | #define regLSDMA_CRD_CNTL 0x005d |
157 | #define regLSDMA_CRD_CNTL_BASE_IDX 0 |
158 | #define regLSDMA_ULV_CNTL 0x005f |
159 | #define regLSDMA_ULV_CNTL_BASE_IDX 0 |
160 | #define regLSDMA_EA_DBIT_ADDR_DATA 0x0060 |
161 | #define regLSDMA_EA_DBIT_ADDR_DATA_BASE_IDX 0 |
162 | #define regLSDMA_EA_DBIT_ADDR_INDEX 0x0061 |
163 | #define regLSDMA_EA_DBIT_ADDR_INDEX_BASE_IDX 0 |
164 | #define regLSDMA_STATUS4_REG 0x0063 |
165 | #define regLSDMA_STATUS4_REG_BASE_IDX 0 |
166 | #define regLSDMA_CE_CTRL 0x0066 |
167 | #define regLSDMA_CE_CTRL_BASE_IDX 0 |
168 | #define regLSDMA_EXCEPTION_STATUS 0x0067 |
169 | #define regLSDMA_EXCEPTION_STATUS_BASE_IDX 0 |
170 | #define regLSDMA_PIO_SRC_ADDR_LO 0x0069 |
171 | #define regLSDMA_PIO_SRC_ADDR_LO_BASE_IDX 0 |
172 | #define regLSDMA_PIO_SRC_ADDR_HI 0x006a |
173 | #define regLSDMA_PIO_SRC_ADDR_HI_BASE_IDX 0 |
174 | #define regLSDMA_PIO_DST_ADDR_LO 0x006b |
175 | #define regLSDMA_PIO_DST_ADDR_LO_BASE_IDX 0 |
176 | #define regLSDMA_PIO_DST_ADDR_HI 0x006c |
177 | #define regLSDMA_PIO_DST_ADDR_HI_BASE_IDX 0 |
178 | #define regLSDMA_PIO_COMMAND 0x006d |
179 | #define regLSDMA_PIO_COMMAND_BASE_IDX 0 |
180 | #define regLSDMA_PIO_CONSTFILL_DATA 0x006e |
181 | #define regLSDMA_PIO_CONSTFILL_DATA_BASE_IDX 0 |
182 | #define regLSDMA_PIO_CONTROL 0x006f |
183 | #define regLSDMA_PIO_CONTROL_BASE_IDX 0 |
184 | #define regLSDMA_INT_CNTL 0x0070 |
185 | #define regLSDMA_INT_CNTL_BASE_IDX 0 |
186 | #define regLSDMA_MEM_POWER_CTRL 0x0071 |
187 | #define regLSDMA_MEM_POWER_CTRL_BASE_IDX 0 |
188 | #define regLSDMA_CLK_CTRL 0x0072 |
189 | #define regLSDMA_CLK_CTRL_BASE_IDX 0 |
190 | #define regLSDMA_CNTL 0x0073 |
191 | #define regLSDMA_CNTL_BASE_IDX 0 |
192 | #define regLSDMA_CHICKEN_BITS 0x0074 |
193 | #define regLSDMA_CHICKEN_BITS_BASE_IDX 0 |
194 | #define regLSDMA_GB_ADDR_CONFIG 0x0075 |
195 | #define regLSDMA_GB_ADDR_CONFIG_BASE_IDX 0 |
196 | #define regLSDMA_GB_ADDR_CONFIG_READ 0x0076 |
197 | #define regLSDMA_GB_ADDR_CONFIG_READ_BASE_IDX 0 |
198 | #define regLSDMA_QUEUE0_RB_CNTL 0x0080 |
199 | #define regLSDMA_QUEUE0_RB_CNTL_BASE_IDX 0 |
200 | #define regLSDMA_QUEUE0_RB_BASE 0x0081 |
201 | #define regLSDMA_QUEUE0_RB_BASE_BASE_IDX 0 |
202 | #define regLSDMA_QUEUE0_RB_BASE_HI 0x0082 |
203 | #define regLSDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 |
204 | #define regLSDMA_QUEUE0_RB_RPTR 0x0083 |
205 | #define regLSDMA_QUEUE0_RB_RPTR_BASE_IDX 0 |
206 | #define regLSDMA_QUEUE0_RB_RPTR_HI 0x0084 |
207 | #define regLSDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 |
208 | #define regLSDMA_QUEUE0_RB_WPTR 0x0085 |
209 | #define regLSDMA_QUEUE0_RB_WPTR_BASE_IDX 0 |
210 | #define regLSDMA_QUEUE0_RB_WPTR_HI 0x0086 |
211 | #define regLSDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 |
212 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL 0x0087 |
213 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
214 | #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0088 |
215 | #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 |
216 | #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0089 |
217 | #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 |
218 | #define regLSDMA_QUEUE0_IB_CNTL 0x008a |
219 | #define regLSDMA_QUEUE0_IB_CNTL_BASE_IDX 0 |
220 | #define regLSDMA_QUEUE0_IB_RPTR 0x008b |
221 | #define regLSDMA_QUEUE0_IB_RPTR_BASE_IDX 0 |
222 | #define regLSDMA_QUEUE0_IB_OFFSET 0x008c |
223 | #define regLSDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 |
224 | #define regLSDMA_QUEUE0_IB_BASE_LO 0x008d |
225 | #define regLSDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 |
226 | #define regLSDMA_QUEUE0_IB_BASE_HI 0x008e |
227 | #define regLSDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 |
228 | #define regLSDMA_QUEUE0_IB_SIZE 0x008f |
229 | #define regLSDMA_QUEUE0_IB_SIZE_BASE_IDX 0 |
230 | #define regLSDMA_QUEUE0_SKIP_CNTL 0x0090 |
231 | #define regLSDMA_QUEUE0_SKIP_CNTL_BASE_IDX 0 |
232 | #define regLSDMA_QUEUE0_CONTEXT_STATUS 0x0091 |
233 | #define regLSDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 |
234 | #define regLSDMA_QUEUE0_DOORBELL 0x0092 |
235 | #define regLSDMA_QUEUE0_DOORBELL_BASE_IDX 0 |
236 | #define regLSDMA_QUEUE0_STATUS 0x00a8 |
237 | #define regLSDMA_QUEUE0_STATUS_BASE_IDX 0 |
238 | #define regLSDMA_QUEUE0_DOORBELL_LOG 0x00a9 |
239 | #define regLSDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 |
240 | #define regLSDMA_QUEUE0_WATERMARK 0x00aa |
241 | #define regLSDMA_QUEUE0_WATERMARK_BASE_IDX 0 |
242 | #define regLSDMA_QUEUE0_DOORBELL_OFFSET 0x00ab |
243 | #define regLSDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 |
244 | #define regLSDMA_QUEUE0_CSA_ADDR_LO 0x00ac |
245 | #define regLSDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 |
246 | #define regLSDMA_QUEUE0_CSA_ADDR_HI 0x00ad |
247 | #define regLSDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 |
248 | #define regLSDMA_QUEUE0_RB_PREEMPT 0x00ae |
249 | #define regLSDMA_QUEUE0_RB_PREEMPT_BASE_IDX 0 |
250 | #define regLSDMA_QUEUE0_IB_SUB_REMAIN 0x00af |
251 | #define regLSDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 |
252 | #define regLSDMA_QUEUE0_PREEMPT 0x00b0 |
253 | #define regLSDMA_QUEUE0_PREEMPT_BASE_IDX 0 |
254 | #define regLSDMA_QUEUE0_DUMMY0 0x00b1 |
255 | #define regLSDMA_QUEUE0_DUMMY0_BASE_IDX 0 |
256 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x00b2 |
257 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
258 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x00b3 |
259 | #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
260 | #define regLSDMA_QUEUE0_RB_AQL_CNTL 0x00b4 |
261 | #define regLSDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 |
262 | #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE 0x00b5 |
263 | #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 |
264 | #define regLSDMA_QUEUE0_CNTL 0x00b6 |
265 | #define regLSDMA_QUEUE0_CNTL_BASE_IDX 0 |
266 | #define regLSDMA_QUEUE0_DUMMY1 0x00b8 |
267 | #define regLSDMA_QUEUE0_DUMMY1_BASE_IDX 0 |
268 | #define regLSDMA_QUEUE0_DUMMY2 0x00b9 |
269 | #define regLSDMA_QUEUE0_DUMMY2_BASE_IDX 0 |
270 | #define regLSDMA_QUEUE0_MIDCMD_DATA0 0x00c0 |
271 | #define regLSDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 |
272 | #define regLSDMA_QUEUE0_MIDCMD_DATA1 0x00c1 |
273 | #define regLSDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 |
274 | #define regLSDMA_QUEUE0_MIDCMD_DATA2 0x00c2 |
275 | #define regLSDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 |
276 | #define regLSDMA_QUEUE0_MIDCMD_DATA3 0x00c3 |
277 | #define regLSDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 |
278 | #define regLSDMA_QUEUE0_MIDCMD_DATA4 0x00c4 |
279 | #define regLSDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 |
280 | #define regLSDMA_QUEUE0_MIDCMD_DATA5 0x00c5 |
281 | #define regLSDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 |
282 | #define regLSDMA_QUEUE0_MIDCMD_DATA6 0x00c6 |
283 | #define regLSDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 |
284 | #define regLSDMA_QUEUE0_MIDCMD_DATA7 0x00c7 |
285 | #define regLSDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 |
286 | #define regLSDMA_QUEUE0_MIDCMD_DATA8 0x00c8 |
287 | #define regLSDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 |
288 | #define regLSDMA_QUEUE0_MIDCMD_DATA9 0x00c9 |
289 | #define regLSDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 |
290 | #define regLSDMA_QUEUE0_MIDCMD_DATA10 0x00ca |
291 | #define regLSDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 |
292 | #define regLSDMA_QUEUE0_MIDCMD_CNTL 0x00cb |
293 | #define regLSDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 |
294 | #define regLSDMA_QUEUE1_RB_CNTL 0x00d8 |
295 | #define regLSDMA_QUEUE1_RB_CNTL_BASE_IDX 0 |
296 | #define regLSDMA_QUEUE1_RB_BASE 0x00d9 |
297 | #define regLSDMA_QUEUE1_RB_BASE_BASE_IDX 0 |
298 | #define regLSDMA_QUEUE1_RB_BASE_HI 0x00da |
299 | #define regLSDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 |
300 | #define regLSDMA_QUEUE1_RB_RPTR 0x00db |
301 | #define regLSDMA_QUEUE1_RB_RPTR_BASE_IDX 0 |
302 | #define regLSDMA_QUEUE1_RB_RPTR_HI 0x00dc |
303 | #define regLSDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 |
304 | #define regLSDMA_QUEUE1_RB_WPTR 0x00dd |
305 | #define regLSDMA_QUEUE1_RB_WPTR_BASE_IDX 0 |
306 | #define regLSDMA_QUEUE1_RB_WPTR_HI 0x00de |
307 | #define regLSDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 |
308 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL 0x00df |
309 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL_BASE_IDX 0 |
310 | #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI 0x00e0 |
311 | #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 |
312 | #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO 0x00e1 |
313 | #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 |
314 | #define regLSDMA_QUEUE1_IB_CNTL 0x00e2 |
315 | #define regLSDMA_QUEUE1_IB_CNTL_BASE_IDX 0 |
316 | #define regLSDMA_QUEUE1_IB_RPTR 0x00e3 |
317 | #define regLSDMA_QUEUE1_IB_RPTR_BASE_IDX 0 |
318 | #define regLSDMA_QUEUE1_IB_OFFSET 0x00e4 |
319 | #define regLSDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 |
320 | #define regLSDMA_QUEUE1_IB_BASE_LO 0x00e5 |
321 | #define regLSDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 |
322 | #define regLSDMA_QUEUE1_IB_BASE_HI 0x00e6 |
323 | #define regLSDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 |
324 | #define regLSDMA_QUEUE1_IB_SIZE 0x00e7 |
325 | #define regLSDMA_QUEUE1_IB_SIZE_BASE_IDX 0 |
326 | #define regLSDMA_QUEUE1_SKIP_CNTL 0x00e8 |
327 | #define regLSDMA_QUEUE1_SKIP_CNTL_BASE_IDX 0 |
328 | #define regLSDMA_QUEUE1_CONTEXT_STATUS 0x00e9 |
329 | #define regLSDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 |
330 | #define regLSDMA_QUEUE1_DOORBELL 0x00ea |
331 | #define regLSDMA_QUEUE1_DOORBELL_BASE_IDX 0 |
332 | #define regLSDMA_QUEUE1_STATUS 0x0100 |
333 | #define regLSDMA_QUEUE1_STATUS_BASE_IDX 0 |
334 | #define regLSDMA_QUEUE1_DOORBELL_LOG 0x0101 |
335 | #define regLSDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 |
336 | #define regLSDMA_QUEUE1_WATERMARK 0x0102 |
337 | #define regLSDMA_QUEUE1_WATERMARK_BASE_IDX 0 |
338 | #define regLSDMA_QUEUE1_DOORBELL_OFFSET 0x0103 |
339 | #define regLSDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 |
340 | #define regLSDMA_QUEUE1_CSA_ADDR_LO 0x0104 |
341 | #define regLSDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 |
342 | #define regLSDMA_QUEUE1_CSA_ADDR_HI 0x0105 |
343 | #define regLSDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 |
344 | #define regLSDMA_QUEUE1_RB_PREEMPT 0x0106 |
345 | #define regLSDMA_QUEUE1_RB_PREEMPT_BASE_IDX 0 |
346 | #define regLSDMA_QUEUE1_IB_SUB_REMAIN 0x0107 |
347 | #define regLSDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 |
348 | #define regLSDMA_QUEUE1_PREEMPT 0x0108 |
349 | #define regLSDMA_QUEUE1_PREEMPT_BASE_IDX 0 |
350 | #define regLSDMA_QUEUE1_DUMMY0 0x0109 |
351 | #define regLSDMA_QUEUE1_DUMMY0_BASE_IDX 0 |
352 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x010a |
353 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 |
354 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x010b |
355 | #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 |
356 | #define regLSDMA_QUEUE1_RB_AQL_CNTL 0x010c |
357 | #define regLSDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 |
358 | #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE 0x010d |
359 | #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 |
360 | #define regLSDMA_QUEUE1_CNTL 0x010e |
361 | #define regLSDMA_QUEUE1_CNTL_BASE_IDX 0 |
362 | #define regLSDMA_QUEUE1_DUMMY1 0x0110 |
363 | #define regLSDMA_QUEUE1_DUMMY1_BASE_IDX 0 |
364 | #define regLSDMA_QUEUE1_DUMMY2 0x0111 |
365 | #define regLSDMA_QUEUE1_DUMMY2_BASE_IDX 0 |
366 | #define regLSDMA_QUEUE1_MIDCMD_DATA0 0x0118 |
367 | #define regLSDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 |
368 | #define regLSDMA_QUEUE1_MIDCMD_DATA1 0x0119 |
369 | #define regLSDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 |
370 | #define regLSDMA_QUEUE1_MIDCMD_DATA2 0x011a |
371 | #define regLSDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 |
372 | #define regLSDMA_QUEUE1_MIDCMD_DATA3 0x011b |
373 | #define regLSDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 |
374 | #define regLSDMA_QUEUE1_MIDCMD_DATA4 0x011c |
375 | #define regLSDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 |
376 | #define regLSDMA_QUEUE1_MIDCMD_DATA5 0x011d |
377 | #define regLSDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 |
378 | #define regLSDMA_QUEUE1_MIDCMD_DATA6 0x011e |
379 | #define regLSDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 |
380 | #define regLSDMA_QUEUE1_MIDCMD_DATA7 0x011f |
381 | #define regLSDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 |
382 | #define regLSDMA_QUEUE1_MIDCMD_DATA8 0x0120 |
383 | #define regLSDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 |
384 | #define regLSDMA_QUEUE1_MIDCMD_DATA9 0x0121 |
385 | #define regLSDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 |
386 | #define regLSDMA_QUEUE1_MIDCMD_DATA10 0x0122 |
387 | #define regLSDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 |
388 | #define regLSDMA_QUEUE1_MIDCMD_CNTL 0x0123 |
389 | #define regLSDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 |
390 | |
391 | #endif |
392 | |