1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _lsdma_6_0_0_SH_MASK_HEADER
24#define _lsdma_6_0_0_SH_MASK_HEADER
25
26
27// addressBlock: lsdma0_lsdma0dec
28//LSDMA_UCODE_ADDR
29#define LSDMA_UCODE_ADDR__VALUE__SHIFT 0x0
30#define LSDMA_UCODE_ADDR__VALUE_MASK 0x00001FFFL
31//LSDMA_UCODE_DATA
32#define LSDMA_UCODE_DATA__VALUE__SHIFT 0x0
33#define LSDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL
34//LSDMA_ERROR_INJECT_CNTL
35#define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION__SHIFT 0x0
36#define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x1
37#define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x2
38#define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION_MASK 0x00000001L
39#define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000002L
40#define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT_MASK 0x0000000CL
41//LSDMA_ERROR_INJECT_SELECT
42#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0__SHIFT 0x0
43#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1__SHIFT 0x1
44#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2__SHIFT 0x2
45#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3__SHIFT 0x3
46#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4__SHIFT 0x4
47#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5__SHIFT 0x5
48#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6__SHIFT 0x6
49#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7__SHIFT 0x7
50#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8__SHIFT 0x8
51#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9__SHIFT 0x9
52#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10__SHIFT 0xa
53#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11__SHIFT 0xb
54#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12__SHIFT 0xc
55#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13__SHIFT 0xd
56#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14__SHIFT 0xe
57#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15__SHIFT 0xf
58#define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF__SHIFT 0x10
59#define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF__SHIFT 0x11
60#define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF__SHIFT 0x12
61#define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO__SHIFT 0x13
62#define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO__SHIFT 0x14
63#define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO__SHIFT 0x15
64#define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO__SHIFT 0x16
65#define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO__SHIFT 0x17
66#define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO__SHIFT 0x18
67#define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF__SHIFT 0x19
68#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0_MASK 0x00000001L
69#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1_MASK 0x00000002L
70#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2_MASK 0x00000004L
71#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3_MASK 0x00000008L
72#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4_MASK 0x00000010L
73#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5_MASK 0x00000020L
74#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6_MASK 0x00000040L
75#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7_MASK 0x00000080L
76#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8_MASK 0x00000100L
77#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9_MASK 0x00000200L
78#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10_MASK 0x00000400L
79#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11_MASK 0x00000800L
80#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12_MASK 0x00001000L
81#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13_MASK 0x00002000L
82#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14_MASK 0x00004000L
83#define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15_MASK 0x00008000L
84#define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF_MASK 0x00010000L
85#define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF_MASK 0x00020000L
86#define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF_MASK 0x00040000L
87#define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO_MASK 0x00080000L
88#define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO_MASK 0x00100000L
89#define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO_MASK 0x00200000L
90#define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO_MASK 0x00400000L
91#define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO_MASK 0x00800000L
92#define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO_MASK 0x01000000L
93#define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF_MASK 0x02000000L
94#define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR__SHIFT 0x0
95#define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA__SHIFT 0x1
96#define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR_MASK 0x00000001L
97#define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA_MASK 0x00000002L
98#define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL__SHIFT 0x12
99#define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL_MASK 0x00040000L
100//LSDMA_CONTEXT_GROUP_BOUNDARY
101#define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0
102#define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL
103//LSDMA_RB_RPTR_FETCH_HI
104#define LSDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0
105#define LSDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL
106//LSDMA_SEM_WAIT_FAIL_TIMER_CNTL
107#define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
108#define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL
109//LSDMA_RB_RPTR_FETCH
110#define LSDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
111#define LSDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL
112//LSDMA_IB_OFFSET_FETCH
113#define LSDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
114#define LSDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL
115//LSDMA_PROGRAM
116#define LSDMA_PROGRAM__STREAM__SHIFT 0x0
117#define LSDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL
118//LSDMA_STATUS_REG
119#define LSDMA_STATUS_REG__IDLE__SHIFT 0x0
120#define LSDMA_STATUS_REG__REG_IDLE__SHIFT 0x1
121#define LSDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2
122#define LSDMA_STATUS_REG__RB_FULL__SHIFT 0x3
123#define LSDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
124#define LSDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
125#define LSDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
126#define LSDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
127#define LSDMA_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
128#define LSDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9
129#define LSDMA_STATUS_REG__EX_IDLE__SHIFT 0xa
130#define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
131#define LSDMA_STATUS_REG__PACKET_READY__SHIFT 0xc
132#define LSDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
133#define LSDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe
134#define LSDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
135#define LSDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
136#define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
137#define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
138#define LSDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
139#define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
140#define LSDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
141#define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
142#define LSDMA_STATUS_REG__Reserved__SHIFT 0x18
143#define LSDMA_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
144#define LSDMA_STATUS_REG__SEM_IDLE__SHIFT 0x1a
145#define LSDMA_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
146#define LSDMA_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
147#define LSDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e
148#define LSDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
149#define LSDMA_STATUS_REG__IDLE_MASK 0x00000001L
150#define LSDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L
151#define LSDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L
152#define LSDMA_STATUS_REG__RB_FULL_MASK 0x00000008L
153#define LSDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L
154#define LSDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L
155#define LSDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L
156#define LSDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L
157#define LSDMA_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L
158#define LSDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L
159#define LSDMA_STATUS_REG__EX_IDLE_MASK 0x00000400L
160#define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L
161#define LSDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L
162#define LSDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L
163#define LSDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L
164#define LSDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L
165#define LSDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L
166#define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L
167#define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L
168#define LSDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L
169#define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L
170#define LSDMA_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L
171#define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L
172#define LSDMA_STATUS_REG__Reserved_MASK 0x01000000L
173#define LSDMA_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L
174#define LSDMA_STATUS_REG__SEM_IDLE_MASK 0x04000000L
175#define LSDMA_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L
176#define LSDMA_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L
177#define LSDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L
178#define LSDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L
179//LSDMA_STATUS1_REG
180#define LSDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
181#define LSDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
182#define LSDMA_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
183#define LSDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
184#define LSDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
185#define LSDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
186#define LSDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
187#define LSDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
188#define LSDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
189#define LSDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb
190#define LSDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc
191#define LSDMA_STATUS1_REG__EX_START__SHIFT 0xd
192#define LSDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf
193#define LSDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10
194#define LSDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L
195#define LSDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L
196#define LSDMA_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L
197#define LSDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L
198#define LSDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L
199#define LSDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L
200#define LSDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L
201#define LSDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L
202#define LSDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L
203#define LSDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L
204#define LSDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L
205#define LSDMA_STATUS1_REG__EX_START_MASK 0x00002000L
206#define LSDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L
207#define LSDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L
208//LSDMA_RD_BURST_CNTL
209#define LSDMA_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
210#define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2
211#define LSDMA_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L
212#define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL
213//LSDMA_HBM_PAGE_CONFIG
214#define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0
215#define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L
216//LSDMA_UCODE_CHECKSUM
217#define LSDMA_UCODE_CHECKSUM__DATA__SHIFT 0x0
218#define LSDMA_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL
219//LSDMA_FREEZE
220#define LSDMA_FREEZE__PREEMPT__SHIFT 0x0
221#define LSDMA_FREEZE__FREEZE__SHIFT 0x4
222#define LSDMA_FREEZE__FROZEN__SHIFT 0x5
223#define LSDMA_FREEZE__F32_FREEZE__SHIFT 0x6
224#define LSDMA_FREEZE__PREEMPT_MASK 0x00000001L
225#define LSDMA_FREEZE__FREEZE_MASK 0x00000010L
226#define LSDMA_FREEZE__FROZEN_MASK 0x00000020L
227#define LSDMA_FREEZE__F32_FREEZE_MASK 0x00000040L
228//LSDMA_PF_PIO_STATUS
229#define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0
230#define LSDMA_PF_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3
231#define LSDMA_PF_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8
232#define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9
233#define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa
234#define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb
235#define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf
236#define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10
237#define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11
238#define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12
239#define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c
240#define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d
241#define LSDMA_PF_PIO_STATUS__PIO_IDLE__SHIFT 0x1f
242#define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L
243#define LSDMA_PF_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L
244#define LSDMA_PF_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L
245#define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L
246#define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L
247#define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L
248#define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L
249#define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L
250#define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L
251#define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L
252#define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L
253#define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L
254#define LSDMA_PF_PIO_STATUS__PIO_IDLE_MASK 0x80000000L
255//LSDMA_VF_PIO_STATUS
256#define LSDMA_VF_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0
257#define LSDMA_VF_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3
258#define LSDMA_VF_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8
259#define LSDMA_VF_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9
260#define LSDMA_VF_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa
261#define LSDMA_VF_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb
262#define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf
263#define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10
264#define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11
265#define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12
266#define LSDMA_VF_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c
267#define LSDMA_VF_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d
268#define LSDMA_VF_PIO_STATUS__PIO_IDLE__SHIFT 0x1f
269#define LSDMA_VF_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L
270#define LSDMA_VF_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L
271#define LSDMA_VF_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L
272#define LSDMA_VF_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L
273#define LSDMA_VF_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L
274#define LSDMA_VF_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L
275#define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L
276#define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L
277#define LSDMA_VF_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L
278#define LSDMA_VF_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L
279#define LSDMA_VF_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L
280#define LSDMA_VF_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L
281#define LSDMA_VF_PIO_STATUS__PIO_IDLE_MASK 0x80000000L
282//LSDMA_POWER_GATING
283#define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION__SHIFT 0x0
284#define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION__SHIFT 0x1
285#define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ__SHIFT 0x2
286#define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ__SHIFT 0x3
287#define LSDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
288#define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION_MASK 0x00000001L
289#define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION_MASK 0x00000002L
290#define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ_MASK 0x00000004L
291#define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ_MASK 0x00000008L
292#define LSDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L
293//LSDMA_PGFSM_CONFIG
294#define LSDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
295#define LSDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
296#define LSDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
297#define LSDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
298#define LSDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
299#define LSDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
300#define LSDMA_PGFSM_CONFIG__READ__SHIFT 0xd
301#define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
302#define LSDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
303#define LSDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL
304#define LSDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L
305#define LSDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L
306#define LSDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L
307#define LSDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L
308#define LSDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L
309#define LSDMA_PGFSM_CONFIG__READ_MASK 0x00002000L
310#define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L
311#define LSDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L
312//LSDMA_PGFSM_WRITE
313#define LSDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
314#define LSDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL
315//LSDMA_PGFSM_READ
316#define LSDMA_PGFSM_READ__VALUE__SHIFT 0x0
317#define LSDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL
318//LSDMA_PIO_STATUS
319#define LSDMA_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0
320#define LSDMA_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3
321#define LSDMA_PIO_STATUS__ERROR_VM_HOLE__SHIFT 0x8
322#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9
323#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa
324#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb
325#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf
326#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10
327#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11
328#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12
329#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c
330#define LSDMA_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d
331#define LSDMA_PIO_STATUS__PIO_IDLE__SHIFT 0x1f
332#define LSDMA_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L
333#define LSDMA_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L
334#define LSDMA_PIO_STATUS__ERROR_VM_HOLE_MASK 0x00000100L
335#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L
336#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L
337#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L
338#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L
339#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L
340#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L
341#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L
342#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L
343#define LSDMA_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L
344#define LSDMA_PIO_STATUS__PIO_IDLE_MASK 0x80000000L
345//LSDMA_BA_THRESHOLD
346#define LSDMA_BA_THRESHOLD__READ_THRES__SHIFT 0x0
347#define LSDMA_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
348#define LSDMA_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL
349#define LSDMA_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L
350//LSDMA_ID
351#define LSDMA_ID__DEVICE_ID__SHIFT 0x0
352#define LSDMA_ID__DEVICE_ID_MASK 0x000000FFL
353//LSDMA_VERSION
354#define LSDMA_VERSION__MINVER__SHIFT 0x0
355#define LSDMA_VERSION__MAJVER__SHIFT 0x8
356#define LSDMA_VERSION__REV__SHIFT 0x10
357#define LSDMA_VERSION__MINVER_MASK 0x0000007FL
358#define LSDMA_VERSION__MAJVER_MASK 0x00007F00L
359#define LSDMA_VERSION__REV_MASK 0x003F0000L
360//LSDMA_EDC_COUNTER
361#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0
362#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2
363#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4
364#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6
365#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8
366#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
367#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc
368#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe
369#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10
370#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12
371#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14
372#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16
373#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18
374#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a
375#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c
376#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e
377#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L
378#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL
379#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L
380#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L
381#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L
382#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L
383#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L
384#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L
385#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L
386#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L
387#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L
388#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L
389#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L
390#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L
391#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L
392#define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L
393//LSDMA_EDC_COUNTER2
394#define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED__SHIFT 0x0
395#define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED__SHIFT 0x2
396#define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED__SHIFT 0x4
397#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6
398#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8
399#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa
400#define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED__SHIFT 0xc
401#define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe
402#define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
403#define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED__SHIFT 0x12
404#define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED_MASK 0x00000003L
405#define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED_MASK 0x0000000CL
406#define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED_MASK 0x00000030L
407#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L
408#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L
409#define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L
410#define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L
411#define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L
412#define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L
413#define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L
414//LSDMA_STATUS2_REG
415#define LSDMA_STATUS2_REG__ID__SHIFT 0x0
416#define LSDMA_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3
417#define LSDMA_STATUS2_REG__CMD_OP__SHIFT 0x10
418#define LSDMA_STATUS2_REG__ID_MASK 0x00000007L
419#define LSDMA_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L
420#define LSDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L
421//LSDMA_ATOMIC_CNTL
422#define LSDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
423#define LSDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL
424//LSDMA_ATOMIC_PREOP_LO
425#define LSDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
426#define LSDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL
427//LSDMA_ATOMIC_PREOP_HI
428#define LSDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
429#define LSDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL
430//LSDMA_UTCL1_CNTL
431#define LSDMA_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0
432#define LSDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1
433#define LSDMA_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb
434#define LSDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe
435#define LSDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
436#define LSDMA_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
437#define LSDMA_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L
438#define LSDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL
439#define LSDMA_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L
440#define LSDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L
441#define LSDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L
442#define LSDMA_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L
443//LSDMA_UTCL1_WATERMK
444#define LSDMA_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0
445#define LSDMA_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3
446#define LSDMA_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5
447#define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8
448#define LSDMA_UTCL1_WATERMK__RESERVED__SHIFT 0x10
449#define LSDMA_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L
450#define LSDMA_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L
451#define LSDMA_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L
452#define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L
453#define LSDMA_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L
454//LSDMA_UTCL1_RD_STATUS
455#define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
456#define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
457#define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
458#define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
459#define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
460#define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
461#define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
462#define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
463#define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
464#define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
465#define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
466#define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
467#define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
468#define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
469#define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
470#define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
471#define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
472#define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
473#define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12
474#define LSDMA_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13
475#define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14
476#define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
477#define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
478#define LSDMA_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
479#define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
480#define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e
481#define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f
482#define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
483#define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
484#define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
485#define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
486#define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
487#define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
488#define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
489#define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
490#define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
491#define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
492#define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
493#define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
494#define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
495#define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
496#define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
497#define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
498#define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
499#define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
500#define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L
501#define LSDMA_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L
502#define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L
503#define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L
504#define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L
505#define LSDMA_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L
506#define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L
507#define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L
508#define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L
509//LSDMA_UTCL1_WR_STATUS
510#define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
511#define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
512#define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
513#define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
514#define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
515#define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
516#define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
517#define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
518#define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
519#define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
520#define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
521#define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
522#define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
523#define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
524#define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
525#define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
526#define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
527#define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
528#define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12
529#define LSDMA_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13
530#define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14
531#define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
532#define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
533#define LSDMA_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19
534#define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c
535#define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
536#define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e
537#define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f
538#define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L
539#define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L
540#define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L
541#define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L
542#define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L
543#define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L
544#define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L
545#define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L
546#define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L
547#define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L
548#define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L
549#define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L
550#define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L
551#define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L
552#define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L
553#define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L
554#define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L
555#define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L
556#define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L
557#define LSDMA_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L
558#define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L
559#define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L
560#define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L
561#define LSDMA_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L
562#define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L
563#define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L
564#define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L
565#define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L
566//LSDMA_UTCL1_INV0
567#define LSDMA_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0
568#define LSDMA_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1
569#define LSDMA_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2
570#define LSDMA_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3
571#define LSDMA_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4
572#define LSDMA_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5
573#define LSDMA_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6
574#define LSDMA_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7
575#define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8
576#define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9
577#define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa
578#define LSDMA_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
579#define LSDMA_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc
580#define LSDMA_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
581#define LSDMA_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L
582#define LSDMA_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L
583#define LSDMA_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L
584#define LSDMA_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L
585#define LSDMA_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L
586#define LSDMA_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L
587#define LSDMA_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L
588#define LSDMA_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L
589#define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L
590#define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L
591#define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L
592#define LSDMA_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L
593#define LSDMA_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L
594#define LSDMA_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L
595//LSDMA_UTCL1_INV1
596#define LSDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0
597#define LSDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL
598//LSDMA_UTCL1_INV2
599#define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
600#define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL
601//LSDMA_UTCL1_RD_XNACK0
602#define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
603#define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
604//LSDMA_UTCL1_RD_XNACK1
605#define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
606#define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
607#define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8
608#define LSDMA_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a
609#define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
610#define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L
611#define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
612#define LSDMA_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L
613//LSDMA_UTCL1_WR_XNACK0
614#define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
615#define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL
616//LSDMA_UTCL1_WR_XNACK1
617#define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
618#define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
619#define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8
620#define LSDMA_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a
621#define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL
622#define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L
623#define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L
624#define LSDMA_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L
625//LSDMA_UTCL1_TIMEOUT
626#define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
627#define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
628#define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL
629#define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L
630//LSDMA_UTCL1_PAGE
631#define LSDMA_UTCL1_PAGE__VM_HOLE__SHIFT 0x0
632#define LSDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1
633#define LSDMA_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5
634#define LSDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6
635#define LSDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9
636#define LSDMA_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L
637#define LSDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL
638#define LSDMA_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L
639#define LSDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L
640#define LSDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L
641//LSDMA_RELAX_ORDERING_LUT
642#define LSDMA_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0
643#define LSDMA_RELAX_ORDERING_LUT__COPY__SHIFT 0x1
644#define LSDMA_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2
645#define LSDMA_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3
646#define LSDMA_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4
647#define LSDMA_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5
648#define LSDMA_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6
649#define LSDMA_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8
650#define LSDMA_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9
651#define LSDMA_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa
652#define LSDMA_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb
653#define LSDMA_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc
654#define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd
655#define LSDMA_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe
656#define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b
657#define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c
658#define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
659#define LSDMA_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e
660#define LSDMA_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f
661#define LSDMA_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L
662#define LSDMA_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L
663#define LSDMA_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L
664#define LSDMA_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L
665#define LSDMA_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L
666#define LSDMA_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L
667#define LSDMA_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L
668#define LSDMA_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L
669#define LSDMA_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L
670#define LSDMA_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L
671#define LSDMA_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L
672#define LSDMA_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L
673#define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L
674#define LSDMA_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L
675#define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L
676#define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L
677#define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L
678#define LSDMA_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L
679#define LSDMA_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L
680//LSDMA_CHICKEN_BITS_2
681#define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0
682#define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4
683#define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL
684#define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L
685//LSDMA_STATUS3_REG
686#define LSDMA_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0
687#define LSDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10
688#define LSDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14
689#define LSDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15
690#define LSDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16
691#define LSDMA_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL
692#define LSDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L
693#define LSDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L
694#define LSDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L
695#define LSDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L
696//LSDMA_PHYSICAL_ADDR_LO
697#define LSDMA_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0
698#define LSDMA_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1
699#define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2
700#define LSDMA_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc
701#define LSDMA_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L
702#define LSDMA_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L
703#define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L
704#define LSDMA_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L
705//LSDMA_PHYSICAL_ADDR_HI
706#define LSDMA_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0
707#define LSDMA_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL
708//LSDMA_ECC_CNTL
709#define LSDMA_ECC_CNTL__ECC_DISABLE__SHIFT 0x0
710#define LSDMA_ECC_CNTL__ECC_DISABLE_MASK 0x00000001L
711//LSDMA_ERROR_LOG
712#define LSDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0
713#define LSDMA_ERROR_LOG__STATUS__SHIFT 0x10
714#define LSDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL
715#define LSDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L
716//LSDMA_PUB_DUMMY0
717#define LSDMA_PUB_DUMMY0__DUMMY__SHIFT 0x0
718#define LSDMA_PUB_DUMMY0__DUMMY_MASK 0xFFFFFFFFL
719//LSDMA_PUB_DUMMY1
720#define LSDMA_PUB_DUMMY1__DUMMY__SHIFT 0x0
721#define LSDMA_PUB_DUMMY1__DUMMY_MASK 0xFFFFFFFFL
722//LSDMA_PUB_DUMMY2
723#define LSDMA_PUB_DUMMY2__DUMMY__SHIFT 0x0
724#define LSDMA_PUB_DUMMY2__DUMMY_MASK 0xFFFFFFFFL
725//LSDMA_PUB_DUMMY3
726#define LSDMA_PUB_DUMMY3__DUMMY__SHIFT 0x0
727#define LSDMA_PUB_DUMMY3__DUMMY_MASK 0xFFFFFFFFL
728//LSDMA_F32_COUNTER
729#define LSDMA_F32_COUNTER__VALUE__SHIFT 0x0
730#define LSDMA_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL
731//LSDMA_PERFCNT_PERFCOUNTER0_CFG
732#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
733#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
734#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
735#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
736#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
737#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
738#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
739#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
740#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
741#define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
742//LSDMA_PERFCNT_PERFCOUNTER1_CFG
743#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
744#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
745#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
746#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
747#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
748#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
749#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
750#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
751#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
752#define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
753//LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL
754#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
755#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
756#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
757#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
758#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
759#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
760#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
761#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
762#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
763#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
764#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
765#define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
766//LSDMA_PERFCNT_MISC_CNTL
767#define LSDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0
768#define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10
769#define LSDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL
770#define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L
771//LSDMA_PERFCNT_PERFCOUNTER_LO
772#define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
773#define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
774//LSDMA_PERFCNT_PERFCOUNTER_HI
775#define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
776#define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
777#define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
778#define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
779//LSDMA_CRD_CNTL
780#define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7
781#define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
782#define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L
783#define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L
784//LSDMA_ULV_CNTL
785#define LSDMA_ULV_CNTL__HYSTERESIS__SHIFT 0x0
786#define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b
787#define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c
788#define LSDMA_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
789#define LSDMA_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e
790#define LSDMA_ULV_CNTL__ULV_STATUS__SHIFT 0x1f
791#define LSDMA_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL
792#define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L
793#define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L
794#define LSDMA_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L
795#define LSDMA_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L
796#define LSDMA_ULV_CNTL__ULV_STATUS_MASK 0x80000000L
797//LSDMA_EA_DBIT_ADDR_DATA
798#define LSDMA_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0
799#define LSDMA_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL
800//LSDMA_EA_DBIT_ADDR_INDEX
801#define LSDMA_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0
802#define LSDMA_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L
803//LSDMA_STATUS4_REG
804#define LSDMA_STATUS4_REG__IDLE__SHIFT 0x0
805#define LSDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2
806#define LSDMA_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3
807#define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4
808#define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5
809#define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6
810#define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7
811#define LSDMA_STATUS4_REG__REG_POLLING__SHIFT 0x8
812#define LSDMA_STATUS4_REG__MEM_POLLING__SHIFT 0x9
813#define LSDMA_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa
814#define LSDMA_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc
815#define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe
816#define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12
817#define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD__SHIFT 0x13
818#define LSDMA_STATUS4_REG__IDLE_MASK 0x00000001L
819#define LSDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L
820#define LSDMA_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L
821#define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L
822#define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L
823#define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L
824#define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L
825#define LSDMA_STATUS4_REG__REG_POLLING_MASK 0x00000100L
826#define LSDMA_STATUS4_REG__MEM_POLLING_MASK 0x00000200L
827#define LSDMA_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L
828#define LSDMA_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L
829#define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L
830#define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L
831#define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD_MASK 0x00080000L
832//LSDMA_CE_CTRL
833#define LSDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0
834#define LSDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3
835#define LSDMA_CE_CTRL__RESERVED_7_5__SHIFT 0x5
836#define LSDMA_CE_CTRL__RESERVED__SHIFT 0x8
837#define LSDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L
838#define LSDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L
839#define LSDMA_CE_CTRL__RESERVED_7_5_MASK 0x000000E0L
840#define LSDMA_CE_CTRL__RESERVED_MASK 0xFFFFFF00L
841//LSDMA_EXCEPTION_STATUS
842#define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC__SHIFT 0x0
843#define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC__SHIFT 0x1
844#define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC__SHIFT 0x2
845#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC__SHIFT 0x3
846#define LSDMA_EXCEPTION_STATUS__SRAM_ECC__SHIFT 0x6
847#define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8
848#define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9
849#define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR__SHIFT 0xa
850#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR__SHIFT 0xb
851#define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR__SHIFT 0xd
852#define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT__SHIFT 0x10
853#define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT__SHIFT 0x11
854#define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT__SHIFT 0x12
855#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT__SHIFT 0x13
856#define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT__SHIFT 0x15
857#define LSDMA_EXCEPTION_STATUS__VM_HOLE__SHIFT 0x18
858#define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC_MASK 0x00000001L
859#define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC_MASK 0x00000002L
860#define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC_MASK 0x00000004L
861#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC_MASK 0x00000008L
862#define LSDMA_EXCEPTION_STATUS__SRAM_ECC_MASK 0x00000040L
863#define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L
864#define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L
865#define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR_MASK 0x00000400L
866#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR_MASK 0x00000800L
867#define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR_MASK 0x00002000L
868#define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT_MASK 0x00010000L
869#define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT_MASK 0x00020000L
870#define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT_MASK 0x00040000L
871#define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT_MASK 0x00080000L
872#define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT_MASK 0x00200000L
873#define LSDMA_EXCEPTION_STATUS__VM_HOLE_MASK 0x01000000L
874//LSDMA_PIO_SRC_ADDR_LO
875#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO__SHIFT 0x0
876#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO_MASK 0xFFFFFFFFL
877//LSDMA_PIO_SRC_ADDR_HI
878#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
879#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xFFFFFFFFL
880//LSDMA_PIO_DST_ADDR_LO
881#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO__SHIFT 0x0
882#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO_MASK 0xFFFFFFFFL
883//LSDMA_PIO_DST_ADDR_HI
884#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
885#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0xFFFFFFFFL
886//LSDMA_PIO_COMMAND
887#define LSDMA_PIO_COMMAND__BYTE_COUNT__SHIFT 0x0
888#define LSDMA_PIO_COMMAND__SRC_LOCATION__SHIFT 0x1a
889#define LSDMA_PIO_COMMAND__DST_LOCATION__SHIFT 0x1b
890#define LSDMA_PIO_COMMAND__SRC_ADDR_INC__SHIFT 0x1c
891#define LSDMA_PIO_COMMAND__DST_ADDR_INC__SHIFT 0x1d
892#define LSDMA_PIO_COMMAND__OVERLAP_DISABLE__SHIFT 0x1e
893#define LSDMA_PIO_COMMAND__CONSTANT_FILL__SHIFT 0x1f
894#define LSDMA_PIO_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
895#define LSDMA_PIO_COMMAND__SRC_LOCATION_MASK 0x04000000L
896#define LSDMA_PIO_COMMAND__DST_LOCATION_MASK 0x08000000L
897#define LSDMA_PIO_COMMAND__SRC_ADDR_INC_MASK 0x10000000L
898#define LSDMA_PIO_COMMAND__DST_ADDR_INC_MASK 0x20000000L
899#define LSDMA_PIO_COMMAND__OVERLAP_DISABLE_MASK 0x40000000L
900#define LSDMA_PIO_COMMAND__CONSTANT_FILL_MASK 0x80000000L
901//LSDMA_PIO_CONSTFILL_DATA
902#define LSDMA_PIO_CONSTFILL_DATA__DATA__SHIFT 0x0
903#define LSDMA_PIO_CONSTFILL_DATA__DATA_MASK 0xFFFFFFFFL
904//LSDMA_PIO_CONTROL
905#define LSDMA_PIO_CONTROL__VMID__SHIFT 0x0
906#define LSDMA_PIO_CONTROL__GPA__SHIFT 0x4
907#define LSDMA_PIO_CONTROL__SYS__SHIFT 0x5
908#define LSDMA_PIO_CONTROL__GCC__SHIFT 0x6
909#define LSDMA_PIO_CONTROL__SNOOP__SHIFT 0x7
910#define LSDMA_PIO_CONTROL__VMID_MASK 0x0000000FL
911#define LSDMA_PIO_CONTROL__GPA_MASK 0x00000010L
912#define LSDMA_PIO_CONTROL__SYS_MASK 0x00000020L
913#define LSDMA_PIO_CONTROL__GCC_MASK 0x00000040L
914#define LSDMA_PIO_CONTROL__SNOOP_MASK 0x00000080L
915//LSDMA_INT_CNTL
916#define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE__SHIFT 0x0
917#define LSDMA_INT_CNTL__TRAP_INT_ENABLE__SHIFT 0x1
918#define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE__SHIFT 0x2
919#define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE__SHIFT 0x3
920#define LSDMA_INT_CNTL__FROZEN_INT_ENABLE__SHIFT 0x4
921#define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE__SHIFT 0x5
922#define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x6
923#define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE__SHIFT 0x7
924#define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE__SHIFT 0x8
925#define LSDMA_INT_CNTL__VM_HOLE_INT_ENABLE__SHIFT 0x9
926#define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xa
927#define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xb
928#define LSDMA_INT_CNTL__ECC_INT_ENABLE__SHIFT 0xc
929#define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE_MASK 0x00000001L
930#define LSDMA_INT_CNTL__TRAP_INT_ENABLE_MASK 0x00000002L
931#define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE_MASK 0x00000004L
932#define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE_MASK 0x00000008L
933#define LSDMA_INT_CNTL__FROZEN_INT_ENABLE_MASK 0x00000010L
934#define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE_MASK 0x00000020L
935#define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x00000040L
936#define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE_MASK 0x00000080L
937#define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE_MASK 0x00000100L
938#define LSDMA_INT_CNTL__VM_HOLE_INT_ENABLE_MASK 0x00000200L
939#define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00000400L
940#define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00000800L
941#define LSDMA_INT_CNTL__ECC_INT_ENABLE_MASK 0x00001000L
942//LSDMA_MEM_POWER_CTRL
943#define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0
944#define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L
945//LSDMA_CLK_CTRL
946#define LSDMA_CLK_CTRL__SOFT_OVERRIDE_SRAM_FGCG__SHIFT 0x0
947#define LSDMA_CLK_CTRL__RESERVED__SHIFT 0x1
948#define LSDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
949#define LSDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
950#define LSDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
951#define LSDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
952#define LSDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
953#define LSDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
954#define LSDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
955#define LSDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
956#define LSDMA_CLK_CTRL__SOFT_OVERRIDE_SRAM_FGCG_MASK 0x00000001L
957#define LSDMA_CLK_CTRL__RESERVED_MASK 0x00FFFFFEL
958#define LSDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
959#define LSDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
960#define LSDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
961#define LSDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
962#define LSDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
963#define LSDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
964#define LSDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
965#define LSDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
966//LSDMA_CNTL
967#define LSDMA_CNTL__UTC_L1_ENABLE__SHIFT 0x1
968#define LSDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
969#define LSDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
970#define LSDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
971#define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
972#define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6
973#define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
974#define LSDMA_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
975#define LSDMA_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
976#define LSDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
977#define LSDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
978#define LSDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
979#define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
980#define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L
981#define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
982#define LSDMA_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L
983//LSDMA_CHICKEN_BITS
984#define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
985#define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
986#define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE__SHIFT 0x3
987#define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8
988#define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
989#define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
990#define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
991#define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
992#define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
993#define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
994#define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
995#define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
996#define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE_MASK 0x00000008L
997#define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L
998#define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L
999#define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
1000#define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
1001#define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
1002#define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L
1003#define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L
1004//LSDMA_GB_ADDR_CONFIG
1005#define LSDMA_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
1006#define LSDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
1007#define LSDMA_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
1008#define LSDMA_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
1009#define LSDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
1010#define LSDMA_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
1011#define LSDMA_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
1012#define LSDMA_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
1013#define LSDMA_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
1014#define LSDMA_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
1015#define LSDMA_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
1016#define LSDMA_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
1017//LSDMA_GB_ADDR_CONFIG_READ
1018#define LSDMA_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
1019#define LSDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
1020#define LSDMA_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
1021#define LSDMA_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8
1022#define LSDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
1023#define LSDMA_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
1024#define LSDMA_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
1025#define LSDMA_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
1026#define LSDMA_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
1027#define LSDMA_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L
1028#define LSDMA_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
1029#define LSDMA_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
1030//LSDMA_QUEUE0_RB_CNTL
1031#define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1032#define LSDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1
1033#define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1034#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1035#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1036#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1037#define LSDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18
1038#define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1039#define LSDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1040#define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1041#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1042#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1043#define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1044#define LSDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L
1045//LSDMA_QUEUE0_RB_BASE
1046#define LSDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0
1047#define LSDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1048//LSDMA_QUEUE0_RB_BASE_HI
1049#define LSDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0
1050#define LSDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1051//LSDMA_QUEUE0_RB_RPTR
1052#define LSDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0
1053#define LSDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1054//LSDMA_QUEUE0_RB_RPTR_HI
1055#define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0
1056#define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1057//LSDMA_QUEUE0_RB_WPTR
1058#define LSDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0
1059#define LSDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1060//LSDMA_QUEUE0_RB_WPTR_HI
1061#define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0
1062#define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1063//LSDMA_QUEUE0_RB_WPTR_POLL_CNTL
1064#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1065#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1066#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1067#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1068#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1069#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1070#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1071#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1072#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1073#define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1074//LSDMA_QUEUE0_RB_RPTR_ADDR_HI
1075#define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1076#define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1077//LSDMA_QUEUE0_RB_RPTR_ADDR_LO
1078#define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1079#define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1080#define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1081#define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1082//LSDMA_QUEUE0_IB_CNTL
1083#define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1084#define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1085#define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1086#define LSDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10
1087#define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1088#define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1089#define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1090#define LSDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1091//LSDMA_QUEUE0_IB_RPTR
1092#define LSDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2
1093#define LSDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1094//LSDMA_QUEUE0_IB_OFFSET
1095#define LSDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2
1096#define LSDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1097//LSDMA_QUEUE0_IB_BASE_LO
1098#define LSDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5
1099#define LSDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
1100//LSDMA_QUEUE0_IB_BASE_HI
1101#define LSDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0
1102#define LSDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
1103//LSDMA_QUEUE0_IB_SIZE
1104#define LSDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0
1105#define LSDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL
1106//LSDMA_QUEUE0_SKIP_CNTL
1107#define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1108#define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
1109//LSDMA_QUEUE0_CONTEXT_STATUS
1110#define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1111#define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1112#define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1113#define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1114#define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1115#define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1116#define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1117#define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1118#define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
1119#define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L
1120#define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
1121#define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
1122#define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
1123#define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
1124#define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
1125#define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
1126//LSDMA_QUEUE0_DOORBELL
1127#define LSDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c
1128#define LSDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e
1129#define LSDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L
1130#define LSDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L
1131//LSDMA_QUEUE0_STATUS
1132#define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
1133#define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
1134#define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
1135#define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
1136//LSDMA_QUEUE0_DOORBELL_LOG
1137#define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1138#define LSDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2
1139#define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
1140#define LSDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
1141//LSDMA_QUEUE0_WATERMARK
1142#define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1143#define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1144#define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
1145#define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
1146//LSDMA_QUEUE0_DOORBELL_OFFSET
1147#define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
1148#define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
1149//LSDMA_QUEUE0_CSA_ADDR_LO
1150#define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1151#define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1152//LSDMA_QUEUE0_CSA_ADDR_HI
1153#define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0
1154#define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1155//LSDMA_QUEUE0_RB_PREEMPT
1156#define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0
1157#define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L
1158//LSDMA_QUEUE0_IB_SUB_REMAIN
1159#define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1160#define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
1161//LSDMA_QUEUE0_PREEMPT
1162#define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0
1163#define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L
1164//LSDMA_QUEUE0_DUMMY0
1165#define LSDMA_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0
1166#define LSDMA_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL
1167//LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI
1168#define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1169#define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1170//LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO
1171#define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1172#define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1173//LSDMA_QUEUE0_RB_AQL_CNTL
1174#define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
1175#define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
1176#define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
1177#define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
1178#define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
1179#define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
1180//LSDMA_QUEUE0_MINOR_PTR_UPDATE
1181#define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
1182#define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
1183//LSDMA_QUEUE0_CNTL
1184#define LSDMA_QUEUE0_CNTL__QUANTUM__SHIFT 0x0
1185#define LSDMA_QUEUE0_CNTL__QUANTUM_MASK 0x000000FFL
1186//LSDMA_QUEUE0_DUMMY1
1187#define LSDMA_QUEUE0_DUMMY1__DUMMY__SHIFT 0x0
1188#define LSDMA_QUEUE0_DUMMY1__DUMMY_MASK 0xFFFFFFFFL
1189//LSDMA_QUEUE0_DUMMY2
1190#define LSDMA_QUEUE0_DUMMY2__DUMMY__SHIFT 0x0
1191#define LSDMA_QUEUE0_DUMMY2__DUMMY_MASK 0xFFFFFFFFL
1192//LSDMA_QUEUE0_MIDCMD_DATA0
1193#define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0
1194#define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
1195//LSDMA_QUEUE0_MIDCMD_DATA1
1196#define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0
1197#define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
1198//LSDMA_QUEUE0_MIDCMD_DATA2
1199#define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0
1200#define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
1201//LSDMA_QUEUE0_MIDCMD_DATA3
1202#define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0
1203#define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
1204//LSDMA_QUEUE0_MIDCMD_DATA4
1205#define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0
1206#define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
1207//LSDMA_QUEUE0_MIDCMD_DATA5
1208#define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0
1209#define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
1210//LSDMA_QUEUE0_MIDCMD_DATA6
1211#define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0
1212#define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
1213//LSDMA_QUEUE0_MIDCMD_DATA7
1214#define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0
1215#define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
1216//LSDMA_QUEUE0_MIDCMD_DATA8
1217#define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0
1218#define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
1219//LSDMA_QUEUE0_MIDCMD_DATA9
1220#define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0
1221#define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
1222//LSDMA_QUEUE0_MIDCMD_DATA10
1223#define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0
1224#define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
1225//LSDMA_QUEUE0_MIDCMD_CNTL
1226#define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
1227#define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1228#define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
1229#define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
1230#define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
1231#define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
1232#define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
1233#define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
1234//LSDMA_QUEUE1_RB_CNTL
1235#define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1236#define LSDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1
1237#define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1238#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1239#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1240#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1241#define LSDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18
1242#define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L
1243#define LSDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL
1244#define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L
1245#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L
1246#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L
1247#define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L
1248#define LSDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L
1249//LSDMA_QUEUE1_RB_BASE
1250#define LSDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0
1251#define LSDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL
1252//LSDMA_QUEUE1_RB_BASE_HI
1253#define LSDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0
1254#define LSDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL
1255//LSDMA_QUEUE1_RB_RPTR
1256#define LSDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0
1257#define LSDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL
1258//LSDMA_QUEUE1_RB_RPTR_HI
1259#define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0
1260#define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1261//LSDMA_QUEUE1_RB_WPTR
1262#define LSDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0
1263#define LSDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL
1264//LSDMA_QUEUE1_RB_WPTR_HI
1265#define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0
1266#define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL
1267//LSDMA_QUEUE1_RB_WPTR_POLL_CNTL
1268#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1269#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1270#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
1271#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1272#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1273#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L
1274#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L
1275#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L
1276#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L
1277#define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1278//LSDMA_QUEUE1_RB_RPTR_ADDR_HI
1279#define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1280#define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1281//LSDMA_QUEUE1_RB_RPTR_ADDR_LO
1282#define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0
1283#define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1284#define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L
1285#define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1286//LSDMA_QUEUE1_IB_CNTL
1287#define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1288#define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1289#define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1290#define LSDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10
1291#define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L
1292#define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L
1293#define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L
1294#define LSDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L
1295//LSDMA_QUEUE1_IB_RPTR
1296#define LSDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2
1297#define LSDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL
1298//LSDMA_QUEUE1_IB_OFFSET
1299#define LSDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2
1300#define LSDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL
1301//LSDMA_QUEUE1_IB_BASE_LO
1302#define LSDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5
1303#define LSDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L
1304//LSDMA_QUEUE1_IB_BASE_HI
1305#define LSDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0
1306#define LSDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL
1307//LSDMA_QUEUE1_IB_SIZE
1308#define LSDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0
1309#define LSDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL
1310//LSDMA_QUEUE1_SKIP_CNTL
1311#define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1312#define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL
1313//LSDMA_QUEUE1_CONTEXT_STATUS
1314#define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1315#define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1316#define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1317#define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1318#define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1319#define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1320#define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1321#define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1322#define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L
1323#define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L
1324#define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L
1325#define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L
1326#define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L
1327#define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L
1328#define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L
1329#define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L
1330//LSDMA_QUEUE1_DOORBELL
1331#define LSDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c
1332#define LSDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e
1333#define LSDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L
1334#define LSDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L
1335//LSDMA_QUEUE1_STATUS
1336#define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0
1337#define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8
1338#define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL
1339#define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L
1340//LSDMA_QUEUE1_DOORBELL_LOG
1341#define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1342#define LSDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2
1343#define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L
1344#define LSDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL
1345//LSDMA_QUEUE1_WATERMARK
1346#define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1347#define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1348#define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL
1349#define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L
1350//LSDMA_QUEUE1_DOORBELL_OFFSET
1351#define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2
1352#define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL
1353//LSDMA_QUEUE1_CSA_ADDR_LO
1354#define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2
1355#define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1356//LSDMA_QUEUE1_CSA_ADDR_HI
1357#define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0
1358#define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1359//LSDMA_QUEUE1_RB_PREEMPT
1360#define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0
1361#define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L
1362//LSDMA_QUEUE1_IB_SUB_REMAIN
1363#define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1364#define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL
1365//LSDMA_QUEUE1_PREEMPT
1366#define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0
1367#define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L
1368//LSDMA_QUEUE1_DUMMY0
1369#define LSDMA_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0
1370#define LSDMA_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL
1371//LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI
1372#define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1373#define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL
1374//LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO
1375#define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1376#define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
1377//LSDMA_QUEUE1_RB_AQL_CNTL
1378#define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0
1379#define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1
1380#define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8
1381#define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L
1382#define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL
1383#define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L
1384//LSDMA_QUEUE1_MINOR_PTR_UPDATE
1385#define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0
1386#define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L
1387//LSDMA_QUEUE1_CNTL
1388#define LSDMA_QUEUE1_CNTL__QUANTUM__SHIFT 0x0
1389#define LSDMA_QUEUE1_CNTL__QUANTUM_MASK 0x000000FFL
1390//LSDMA_QUEUE1_DUMMY1
1391#define LSDMA_QUEUE1_DUMMY1__DUMMY__SHIFT 0x0
1392#define LSDMA_QUEUE1_DUMMY1__DUMMY_MASK 0xFFFFFFFFL
1393//LSDMA_QUEUE1_DUMMY2
1394#define LSDMA_QUEUE1_DUMMY2__DUMMY__SHIFT 0x0
1395#define LSDMA_QUEUE1_DUMMY2__DUMMY_MASK 0xFFFFFFFFL
1396//LSDMA_QUEUE1_MIDCMD_DATA0
1397#define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0
1398#define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL
1399//LSDMA_QUEUE1_MIDCMD_DATA1
1400#define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0
1401#define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL
1402//LSDMA_QUEUE1_MIDCMD_DATA2
1403#define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0
1404#define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL
1405//LSDMA_QUEUE1_MIDCMD_DATA3
1406#define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0
1407#define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL
1408//LSDMA_QUEUE1_MIDCMD_DATA4
1409#define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0
1410#define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL
1411//LSDMA_QUEUE1_MIDCMD_DATA5
1412#define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0
1413#define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL
1414//LSDMA_QUEUE1_MIDCMD_DATA6
1415#define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0
1416#define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL
1417//LSDMA_QUEUE1_MIDCMD_DATA7
1418#define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0
1419#define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL
1420//LSDMA_QUEUE1_MIDCMD_DATA8
1421#define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0
1422#define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL
1423//LSDMA_QUEUE1_MIDCMD_DATA9
1424#define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0
1425#define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL
1426//LSDMA_QUEUE1_MIDCMD_DATA10
1427#define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0
1428#define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL
1429//LSDMA_QUEUE1_MIDCMD_CNTL
1430#define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
1431#define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1432#define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
1433#define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
1434#define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L
1435#define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L
1436#define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L
1437#define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L
1438
1439#endif
1440

source code of linux/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_6_0_0_sh_mask.h