| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _mmhub_1_0_DEFAULT_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | // addressBlock: mmhub_dagbdec |
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| 26 | #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 |
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| 27 | #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 |
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| 28 | #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 |
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| 29 | #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 |
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| 30 | #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 |
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| 31 | #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 |
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| 32 | #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 |
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| 33 | #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 |
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| 34 | #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 |
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| 35 | #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 |
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| 36 | #define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 |
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| 37 | #define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 |
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| 38 | #define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 |
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| 39 | #define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 |
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| 40 | #define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 |
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| 41 | #define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 |
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| 42 | #define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 |
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| 43 | #define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f |
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| 44 | #define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 |
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| 45 | #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
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| 46 | #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
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| 47 | #define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 48 | #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 49 | #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 50 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
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| 51 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
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| 52 | #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
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| 53 | #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
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| 54 | #define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
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| 55 | #define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
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| 56 | #define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
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| 57 | #define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
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| 58 | #define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
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| 59 | #define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
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| 60 | #define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
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| 61 | #define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
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| 62 | #define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 |
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| 63 | #define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
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| 64 | #define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
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| 65 | #define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
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| 66 | #define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
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| 67 | #define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
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| 68 | #define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
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| 69 | #define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
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| 70 | #define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 |
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| 71 | #define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 |
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| 72 | #define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 |
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| 73 | #define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 |
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| 74 | #define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 |
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| 75 | #define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 |
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| 76 | #define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 |
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| 77 | #define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 |
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| 78 | #define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 |
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| 79 | #define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 |
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| 80 | #define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 |
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| 81 | #define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 |
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| 82 | #define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 |
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| 83 | #define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 |
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| 84 | #define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 |
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| 85 | #define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 |
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| 86 | #define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 |
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| 87 | #define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f |
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| 88 | #define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 |
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| 89 | #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
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| 90 | #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
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| 91 | #define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 92 | #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 93 | #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 94 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
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| 95 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
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| 96 | #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
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| 97 | #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
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| 98 | #define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 |
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| 99 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
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| 100 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
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| 101 | #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
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| 102 | #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
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| 103 | #define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
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| 104 | #define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
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| 105 | #define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
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| 106 | #define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
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| 107 | #define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
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| 108 | #define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
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| 109 | #define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
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| 110 | #define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
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| 111 | #define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 |
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| 112 | #define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
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| 113 | #define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 |
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| 114 | #define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
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| 115 | #define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
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| 116 | #define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
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| 117 | #define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
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| 118 | #define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
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| 119 | #define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
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| 120 | #define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
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| 121 | #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
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| 122 | #define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
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| 123 | #define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 |
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| 124 | #define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa |
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| 125 | #define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 |
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| 126 | #define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff |
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| 127 | #define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 |
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| 128 | #define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff |
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| 129 | #define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
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| 130 | #define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
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| 131 | #define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
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| 132 | #define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
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| 133 | #define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
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| 134 | #define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
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| 135 | #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
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| 136 | #define mmDAGB0_RESERVE0_DEFAULT 0x00000000 |
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| 137 | #define mmDAGB0_RESERVE1_DEFAULT 0x00000000 |
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| 138 | #define mmDAGB0_RESERVE2_DEFAULT 0x00000000 |
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| 139 | #define mmDAGB0_RESERVE3_DEFAULT 0x00000000 |
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| 140 | #define mmDAGB0_RESERVE4_DEFAULT 0x00000000 |
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| 141 | #define mmDAGB0_RESERVE5_DEFAULT 0x00000000 |
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| 142 | #define mmDAGB0_RESERVE6_DEFAULT 0x00000000 |
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| 143 | #define mmDAGB0_RESERVE7_DEFAULT 0x00000000 |
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| 144 | #define mmDAGB0_RESERVE8_DEFAULT 0x00000000 |
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| 145 | #define mmDAGB0_RESERVE9_DEFAULT 0x00000000 |
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| 146 | #define mmDAGB0_RESERVE10_DEFAULT 0x00000000 |
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| 147 | #define mmDAGB0_RESERVE11_DEFAULT 0x00000000 |
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| 148 | #define mmDAGB0_RESERVE12_DEFAULT 0x00000000 |
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| 149 | #define mmDAGB0_RESERVE13_DEFAULT 0x00000000 |
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| 150 | #define mmDAGB0_RESERVE14_DEFAULT 0x00000000 |
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| 151 | #define mmDAGB0_RESERVE15_DEFAULT 0x00000000 |
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| 152 | #define mmDAGB0_RESERVE16_DEFAULT 0x00000000 |
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| 153 | #define mmDAGB0_RESERVE17_DEFAULT 0x00000000 |
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| 154 | #define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 |
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| 155 | #define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 |
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| 156 | #define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 |
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| 157 | #define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 |
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| 158 | #define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 |
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| 159 | #define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 |
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| 160 | #define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 |
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| 161 | #define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 |
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| 162 | #define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 |
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| 163 | #define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 |
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| 164 | #define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 |
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| 165 | #define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 |
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| 166 | #define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 |
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| 167 | #define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 |
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| 168 | #define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 |
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| 169 | #define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 |
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| 170 | #define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 |
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| 171 | #define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x0000304f |
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| 172 | #define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 |
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| 173 | #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
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| 174 | #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
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| 175 | #define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 176 | #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 177 | #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 178 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
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| 179 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
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| 180 | #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
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| 181 | #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
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| 182 | #define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
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| 183 | #define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
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| 184 | #define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
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| 185 | #define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
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| 186 | #define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
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| 187 | #define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
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| 188 | #define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
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| 189 | #define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
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| 190 | #define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x01a10408 |
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| 191 | #define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
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| 192 | #define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
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| 193 | #define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
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| 194 | #define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
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| 195 | #define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
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| 196 | #define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
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| 197 | #define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
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| 198 | #define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 |
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| 199 | #define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 |
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| 200 | #define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 |
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| 201 | #define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 |
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| 202 | #define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 |
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| 203 | #define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 |
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| 204 | #define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 |
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| 205 | #define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 |
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| 206 | #define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 |
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| 207 | #define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 |
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| 208 | #define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 |
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| 209 | #define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 |
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| 210 | #define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 |
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| 211 | #define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 |
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| 212 | #define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 |
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| 213 | #define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 |
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| 214 | #define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 |
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| 215 | #define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x0000304f |
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| 216 | #define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 |
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| 217 | #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
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| 218 | #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
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| 219 | #define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 220 | #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 221 | #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
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| 222 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
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| 223 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
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| 224 | #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
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| 225 | #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
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| 226 | #define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 |
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| 227 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
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| 228 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
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| 229 | #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
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| 230 | #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
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| 231 | #define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
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| 232 | #define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
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| 233 | #define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
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| 234 | #define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
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| 235 | #define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
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| 236 | #define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
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| 237 | #define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
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| 238 | #define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
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| 239 | #define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x01a10408 |
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| 240 | #define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
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| 241 | #define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x5c626870 |
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| 242 | #define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
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| 243 | #define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
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| 244 | #define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
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| 245 | #define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
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| 246 | #define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
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| 247 | #define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
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| 248 | #define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
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| 249 | #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
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| 250 | #define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
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| 251 | #define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 |
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| 252 | #define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa |
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| 253 | #define mmDAGB1_CNTL_MISC2_DEFAULT 0x00000000 |
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| 254 | #define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff |
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| 255 | #define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 |
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| 256 | #define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x0007ffff |
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| 257 | #define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
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| 258 | #define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
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| 259 | #define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
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| 260 | #define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
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| 261 | #define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
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| 262 | #define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
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| 263 | #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
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| 264 | #define mmDAGB1_RESERVE0_DEFAULT 0x00000000 |
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| 265 | #define mmDAGB1_RESERVE1_DEFAULT 0x00000000 |
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| 266 | #define mmDAGB1_RESERVE2_DEFAULT 0x00000000 |
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| 267 | #define mmDAGB1_RESERVE3_DEFAULT 0x00000000 |
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| 268 | #define mmDAGB1_RESERVE4_DEFAULT 0x00000000 |
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| 269 | #define mmDAGB1_RESERVE5_DEFAULT 0x00000000 |
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| 270 | #define mmDAGB1_RESERVE6_DEFAULT 0x00000000 |
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| 271 | #define mmDAGB1_RESERVE7_DEFAULT 0x00000000 |
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| 272 | #define mmDAGB1_RESERVE8_DEFAULT 0x00000000 |
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| 273 | #define mmDAGB1_RESERVE9_DEFAULT 0x00000000 |
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| 274 | #define mmDAGB1_RESERVE10_DEFAULT 0x00000000 |
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| 275 | #define mmDAGB1_RESERVE11_DEFAULT 0x00000000 |
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| 276 | #define mmDAGB1_RESERVE12_DEFAULT 0x00000000 |
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| 277 | #define mmDAGB1_RESERVE13_DEFAULT 0x00000000 |
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| 278 | #define mmDAGB1_RESERVE14_DEFAULT 0x00000000 |
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| 279 | #define mmDAGB1_RESERVE15_DEFAULT 0x00000000 |
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| 280 | #define mmDAGB1_RESERVE16_DEFAULT 0x00000000 |
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| 281 | #define mmDAGB1_RESERVE17_DEFAULT 0x00000000 |
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| 282 | |
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| 283 | |
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| 284 | // addressBlock: mmhub_ea_mmeadec |
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| 285 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
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| 286 | #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
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| 287 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
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| 288 | #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
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| 289 | #define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
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| 290 | #define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
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| 291 | #define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 |
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| 292 | #define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 |
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| 293 | #define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 |
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| 294 | #define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 |
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| 295 | #define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
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| 296 | #define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
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| 297 | #define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
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| 298 | #define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
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| 299 | #define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
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| 300 | #define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
|---|
| 301 | #define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
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| 302 | #define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
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| 303 | #define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
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| 304 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
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| 305 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
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| 306 | #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
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| 307 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
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| 308 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
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| 309 | #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
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| 310 | #define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
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| 311 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
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| 312 | #define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
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| 313 | #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
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| 314 | #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
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| 315 | #define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 |
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| 316 | #define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef |
|---|
| 317 | #define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 |
|---|
| 318 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
|---|
| 319 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
|---|
| 320 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
|---|
| 321 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
|---|
| 322 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
|---|
| 323 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
|---|
| 324 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
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| 325 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
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| 326 | #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
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| 327 | #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
|---|
| 328 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
|---|
| 329 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
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| 330 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
|---|
| 331 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
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| 332 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
|---|
| 333 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
|---|
| 334 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
|---|
| 335 | #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
|---|
| 336 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
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| 337 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
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| 338 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
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| 339 | #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
|---|
| 340 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
|---|
| 341 | #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
|---|
| 342 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
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| 343 | #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
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| 344 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
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| 345 | #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
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| 346 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
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| 347 | #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
|---|
| 348 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
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| 349 | #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
|---|
| 350 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
|---|
| 351 | #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
|---|
| 352 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
|---|
| 353 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
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| 354 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
|---|
| 355 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
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| 356 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
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| 357 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
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| 358 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
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| 359 | #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
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| 360 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
|---|
| 361 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
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| 362 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
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| 363 | #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
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| 364 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
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| 365 | #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
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| 366 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
|---|
| 367 | #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
|---|
| 368 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
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| 369 | #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
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| 370 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
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| 371 | #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
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| 372 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
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| 373 | #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
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| 374 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
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| 375 | #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
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| 376 | #define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
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| 377 | #define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
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| 378 | #define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
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| 379 | #define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
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| 380 | #define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
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| 381 | #define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
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| 382 | #define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
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| 383 | #define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
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| 384 | #define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
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| 385 | #define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
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| 386 | #define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
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| 387 | #define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
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| 388 | #define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
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| 389 | #define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
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| 390 | #define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
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| 391 | #define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
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| 392 | #define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
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| 393 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
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| 394 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
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| 395 | #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
|---|
| 396 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
|---|
| 397 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
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| 398 | #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
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| 399 | #define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 |
|---|
| 400 | #define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff |
|---|
| 401 | #define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
|---|
| 402 | #define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
|---|
| 403 | #define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf |
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| 404 | #define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
|---|
| 405 | #define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
|---|
| 406 | #define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
|---|
| 407 | #define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
|---|
| 408 | #define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
|---|
| 409 | #define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
|---|
| 410 | #define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f |
|---|
| 411 | #define mmMMEA0_MISC_DEFAULT 0x00180130 |
|---|
| 412 | #define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 |
|---|
| 413 | #define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
|---|
| 414 | #define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
|---|
| 415 | #define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
|---|
| 416 | #define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
|---|
| 417 | #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
|---|
| 418 | #define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 |
|---|
| 419 | #define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 |
|---|
| 420 | #define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 |
|---|
| 421 | #define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 |
|---|
| 422 | #define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 |
|---|
| 423 | #define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 |
|---|
| 424 | #define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 |
|---|
| 425 | #define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 |
|---|
| 426 | #define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
|---|
| 427 | #define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 |
|---|
| 428 | #define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 |
|---|
| 429 | #define mmMMEA0_MISC2_DEFAULT 0x00000000 |
|---|
| 430 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
|---|
| 431 | #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
|---|
| 432 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
|---|
| 433 | #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
|---|
| 434 | #define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
|---|
| 435 | #define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
|---|
| 436 | #define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 |
|---|
| 437 | #define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 |
|---|
| 438 | #define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 |
|---|
| 439 | #define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 |
|---|
| 440 | #define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
|---|
| 441 | #define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
|---|
| 442 | #define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
|---|
| 443 | #define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
|---|
| 444 | #define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
|---|
| 445 | #define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
|---|
| 446 | #define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
|---|
| 447 | #define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
|---|
| 448 | #define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
|---|
| 449 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
|---|
| 450 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
|---|
| 451 | #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
|---|
| 452 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
|---|
| 453 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
|---|
| 454 | #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
|---|
| 455 | #define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
|---|
| 456 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
|---|
| 457 | #define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
|---|
| 458 | #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
|---|
| 459 | #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
|---|
| 460 | #define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 |
|---|
| 461 | #define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef |
|---|
| 462 | #define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 |
|---|
| 463 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
|---|
| 464 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
|---|
| 465 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
|---|
| 466 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
|---|
| 467 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
|---|
| 468 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
|---|
| 469 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
|---|
| 470 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
|---|
| 471 | #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
|---|
| 472 | #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
|---|
| 473 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
|---|
| 474 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
|---|
| 475 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
|---|
| 476 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
|---|
| 477 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
|---|
| 478 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
|---|
| 479 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
|---|
| 480 | #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
|---|
| 481 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
|---|
| 482 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
|---|
| 483 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
|---|
| 484 | #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
|---|
| 485 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
|---|
| 486 | #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
|---|
| 487 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
|---|
| 488 | #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
|---|
| 489 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
|---|
| 490 | #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
|---|
| 491 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
|---|
| 492 | #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
|---|
| 493 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
|---|
| 494 | #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
|---|
| 495 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
|---|
| 496 | #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
|---|
| 497 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
|---|
| 498 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
|---|
| 499 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
|---|
| 500 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
|---|
| 501 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
|---|
| 502 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
|---|
| 503 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
|---|
| 504 | #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
|---|
| 505 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
|---|
| 506 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
|---|
| 507 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
|---|
| 508 | #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
|---|
| 509 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
|---|
| 510 | #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
|---|
| 511 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
|---|
| 512 | #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
|---|
| 513 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
|---|
| 514 | #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
|---|
| 515 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
|---|
| 516 | #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
|---|
| 517 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
|---|
| 518 | #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
|---|
| 519 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
|---|
| 520 | #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
|---|
| 521 | #define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
|---|
| 522 | #define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
|---|
| 523 | #define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
|---|
| 524 | #define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
|---|
| 525 | #define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
|---|
| 526 | #define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
|---|
| 527 | #define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
|---|
| 528 | #define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
|---|
| 529 | #define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
|---|
| 530 | #define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
|---|
| 531 | #define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
|---|
| 532 | #define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
|---|
| 533 | #define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
|---|
| 534 | #define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
|---|
| 535 | #define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
|---|
| 536 | #define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
|---|
| 537 | #define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
|---|
| 538 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
|---|
| 539 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
|---|
| 540 | #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
|---|
| 541 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
|---|
| 542 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
|---|
| 543 | #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
|---|
| 544 | #define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 |
|---|
| 545 | #define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff |
|---|
| 546 | #define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
|---|
| 547 | #define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
|---|
| 548 | #define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf |
|---|
| 549 | #define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
|---|
| 550 | #define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
|---|
| 551 | #define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
|---|
| 552 | #define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
|---|
| 553 | #define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
|---|
| 554 | #define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
|---|
| 555 | #define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f |
|---|
| 556 | #define mmMMEA1_MISC_DEFAULT 0x00180130 |
|---|
| 557 | #define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 |
|---|
| 558 | #define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
|---|
| 559 | #define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
|---|
| 560 | #define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
|---|
| 561 | #define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
|---|
| 562 | #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
|---|
| 563 | #define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 |
|---|
| 564 | #define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 |
|---|
| 565 | #define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 |
|---|
| 566 | #define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 |
|---|
| 567 | #define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 |
|---|
| 568 | #define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 |
|---|
| 569 | #define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 |
|---|
| 570 | #define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 |
|---|
| 571 | #define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
|---|
| 572 | #define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 |
|---|
| 573 | #define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 |
|---|
| 574 | #define mmMMEA1_MISC2_DEFAULT 0x00000000 |
|---|
| 575 | |
|---|
| 576 | |
|---|
| 577 | // addressBlock: mmhub_pctldec |
|---|
| 578 | #define mmPCTL_MISC_DEFAULT 0x00000889 |
|---|
| 579 | #define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 |
|---|
| 580 | #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 |
|---|
| 581 | #define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 |
|---|
| 582 | #define mmPCTL_PG_DAGB_DEFAULT 0x00000000 |
|---|
| 583 | #define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 |
|---|
| 584 | #define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 |
|---|
| 585 | #define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 |
|---|
| 586 | #define mmPCTL0_MISC_DEFAULT 0x00001000 |
|---|
| 587 | #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
|---|
| 588 | #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
|---|
| 589 | #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
|---|
| 590 | #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
|---|
| 591 | #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
|---|
| 592 | #define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 |
|---|
| 593 | #define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 |
|---|
| 594 | #define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 |
|---|
| 595 | #define mmPCTL1_MISC_DEFAULT 0x00000800 |
|---|
| 596 | #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 |
|---|
| 597 | #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 |
|---|
| 598 | #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
|---|
| 599 | #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
|---|
| 600 | #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
|---|
| 601 | #define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
|---|
| 602 | #define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 |
|---|
| 603 | #define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 |
|---|
| 604 | #define mmPCTL2_MISC_DEFAULT 0x00000800 |
|---|
| 605 | #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 |
|---|
| 606 | #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a |
|---|
| 607 | #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
|---|
| 608 | #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
|---|
| 609 | #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
|---|
| 610 | |
|---|
| 611 | |
|---|
| 612 | // addressBlock: mmhub_l1tlb_vml1dec |
|---|
| 613 | #define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 |
|---|
| 614 | #define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 |
|---|
| 615 | #define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 |
|---|
| 616 | #define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 |
|---|
| 617 | #define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 |
|---|
| 618 | #define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 |
|---|
| 619 | #define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 |
|---|
| 620 | #define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 |
|---|
| 621 | |
|---|
| 622 | |
|---|
| 623 | // addressBlock: mmhub_l1tlb_vml1pldec |
|---|
| 624 | #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
|---|
| 625 | #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
|---|
| 626 | #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
|---|
| 627 | #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
|---|
| 628 | #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
|---|
| 629 | |
|---|
| 630 | |
|---|
| 631 | // addressBlock: mmhub_l1tlb_vml1prdec |
|---|
| 632 | #define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
|---|
| 633 | #define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
|---|
| 634 | |
|---|
| 635 | |
|---|
| 636 | // addressBlock: mmhub_utcl2_atcl2dec |
|---|
| 637 | #define mmATC_L2_CNTL_DEFAULT 0x000001c9 |
|---|
| 638 | #define mmATC_L2_CNTL2_DEFAULT 0x00000100 |
|---|
| 639 | #define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 |
|---|
| 640 | #define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 |
|---|
| 641 | #define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 |
|---|
| 642 | #define mmATC_L2_CNTL3_DEFAULT 0x000001f8 |
|---|
| 643 | #define mmATC_L2_STATUS_DEFAULT 0x00000000 |
|---|
| 644 | #define mmATC_L2_STATUS2_DEFAULT 0x00000000 |
|---|
| 645 | #define mmATC_L2_MISC_CG_DEFAULT 0x00000200 |
|---|
| 646 | #define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 |
|---|
| 647 | #define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
|---|
| 648 | |
|---|
| 649 | |
|---|
| 650 | // addressBlock: mmhub_utcl2_vml2pfdec |
|---|
| 651 | #define mmVM_L2_CNTL_DEFAULT 0x00080602 |
|---|
| 652 | #define mmVM_L2_CNTL2_DEFAULT 0x00000000 |
|---|
| 653 | #define mmVM_L2_CNTL3_DEFAULT 0x80100007 |
|---|
| 654 | #define mmVM_L2_STATUS_DEFAULT 0x00000000 |
|---|
| 655 | #define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 |
|---|
| 656 | #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 657 | #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 658 | #define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc |
|---|
| 659 | #define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 |
|---|
| 660 | #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff |
|---|
| 661 | #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff |
|---|
| 662 | #define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 |
|---|
| 663 | #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 664 | #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 665 | #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 666 | #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 667 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 668 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 669 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 670 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 671 | #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 |
|---|
| 672 | #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 |
|---|
| 673 | #define mmVM_L2_CNTL4_DEFAULT 0x000000c1 |
|---|
| 674 | #define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 |
|---|
| 675 | #define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 |
|---|
| 676 | #define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 |
|---|
| 677 | #define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 |
|---|
| 678 | #define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
|---|
| 679 | |
|---|
| 680 | |
|---|
| 681 | // addressBlock: mmhub_utcl2_vml2vcdec |
|---|
| 682 | #define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 |
|---|
| 683 | #define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 |
|---|
| 684 | #define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 |
|---|
| 685 | #define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 |
|---|
| 686 | #define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 |
|---|
| 687 | #define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 |
|---|
| 688 | #define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 |
|---|
| 689 | #define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 |
|---|
| 690 | #define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 |
|---|
| 691 | #define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 |
|---|
| 692 | #define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 |
|---|
| 693 | #define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 |
|---|
| 694 | #define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 |
|---|
| 695 | #define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 |
|---|
| 696 | #define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 |
|---|
| 697 | #define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 |
|---|
| 698 | #define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 |
|---|
| 699 | #define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 |
|---|
| 700 | #define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 |
|---|
| 701 | #define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 |
|---|
| 702 | #define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 |
|---|
| 703 | #define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 |
|---|
| 704 | #define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 |
|---|
| 705 | #define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 |
|---|
| 706 | #define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 |
|---|
| 707 | #define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 |
|---|
| 708 | #define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 |
|---|
| 709 | #define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 |
|---|
| 710 | #define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 |
|---|
| 711 | #define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 |
|---|
| 712 | #define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 |
|---|
| 713 | #define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 |
|---|
| 714 | #define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 |
|---|
| 715 | #define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 |
|---|
| 716 | #define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 |
|---|
| 717 | #define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 |
|---|
| 718 | #define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 |
|---|
| 719 | #define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 |
|---|
| 720 | #define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 |
|---|
| 721 | #define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 |
|---|
| 722 | #define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 |
|---|
| 723 | #define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 |
|---|
| 724 | #define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 |
|---|
| 725 | #define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 |
|---|
| 726 | #define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 |
|---|
| 727 | #define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 |
|---|
| 728 | #define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 |
|---|
| 729 | #define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 |
|---|
| 730 | #define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 |
|---|
| 731 | #define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 |
|---|
| 732 | #define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 |
|---|
| 733 | #define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 |
|---|
| 734 | #define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 |
|---|
| 735 | #define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 |
|---|
| 736 | #define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 |
|---|
| 737 | #define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 |
|---|
| 738 | #define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 |
|---|
| 739 | #define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 |
|---|
| 740 | #define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 |
|---|
| 741 | #define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 |
|---|
| 742 | #define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 |
|---|
| 743 | #define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 |
|---|
| 744 | #define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 |
|---|
| 745 | #define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 |
|---|
| 746 | #define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 |
|---|
| 747 | #define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 |
|---|
| 748 | #define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 |
|---|
| 749 | #define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 |
|---|
| 750 | #define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 |
|---|
| 751 | #define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 |
|---|
| 752 | #define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 |
|---|
| 753 | #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 754 | #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 755 | #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 756 | #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 757 | #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 758 | #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 759 | #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 760 | #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 761 | #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 762 | #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 763 | #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 764 | #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 765 | #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 766 | #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 767 | #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 768 | #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 769 | #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 770 | #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 771 | #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 772 | #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 773 | #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 774 | #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 775 | #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 776 | #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 777 | #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 778 | #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 779 | #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 780 | #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 781 | #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 782 | #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 783 | #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 784 | #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 785 | #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 786 | #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 787 | #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
|---|
| 788 | #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
|---|
| 789 | #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 790 | #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 791 | #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 792 | #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 793 | #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 794 | #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 795 | #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 796 | #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 797 | #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 798 | #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 799 | #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 800 | #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 801 | #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 802 | #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 803 | #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 804 | #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 805 | #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 806 | #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 807 | #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 808 | #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 809 | #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 810 | #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 811 | #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 812 | #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 813 | #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 814 | #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 815 | #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 816 | #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 817 | #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 818 | #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 819 | #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 820 | #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 821 | #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 822 | #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 823 | #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 824 | #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 825 | #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 826 | #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 827 | #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 828 | #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 829 | #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 830 | #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 831 | #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 832 | #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 833 | #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 834 | #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 835 | #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 836 | #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 837 | #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 838 | #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 839 | #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 840 | #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 841 | #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 842 | #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 843 | #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 844 | #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 845 | #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 846 | #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 847 | #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 848 | #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 849 | #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 850 | #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 851 | #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 852 | #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 853 | #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 854 | #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 855 | #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 856 | #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 857 | #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 858 | #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 859 | #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 860 | #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 861 | #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 862 | #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 863 | #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 864 | #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 865 | #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 866 | #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 867 | #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 868 | #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 869 | #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 870 | #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 871 | #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 872 | #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 873 | #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 874 | #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 875 | #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 876 | #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 877 | #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 878 | #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 879 | #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 880 | #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 881 | #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 882 | #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 883 | #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
|---|
| 884 | #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
|---|
| 885 | |
|---|
| 886 | |
|---|
| 887 | // addressBlock: mmhub_utcl2_vml2pldec |
|---|
| 888 | #define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
|---|
| 889 | #define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
|---|
| 890 | #define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
|---|
| 891 | #define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
|---|
| 892 | #define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 |
|---|
| 893 | #define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 |
|---|
| 894 | #define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 |
|---|
| 895 | #define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 |
|---|
| 896 | #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
|---|
| 897 | |
|---|
| 898 | |
|---|
| 899 | // addressBlock: mmhub_utcl2_vml2prdec |
|---|
| 900 | #define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
|---|
| 901 | #define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
|---|
| 902 | |
|---|
| 903 | |
|---|
| 904 | // addressBlock: mmhub_utcl2_vmsharedhvdec |
|---|
| 905 | #define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 |
|---|
| 906 | #define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 |
|---|
| 907 | #define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 |
|---|
| 908 | #define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 |
|---|
| 909 | #define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 |
|---|
| 910 | #define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 |
|---|
| 911 | #define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 |
|---|
| 912 | #define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 |
|---|
| 913 | #define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 |
|---|
| 914 | #define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 |
|---|
| 915 | #define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 |
|---|
| 916 | #define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 |
|---|
| 917 | #define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 |
|---|
| 918 | #define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 |
|---|
| 919 | #define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 |
|---|
| 920 | #define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 |
|---|
| 921 | #define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 |
|---|
| 922 | #define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 |
|---|
| 923 | #define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 |
|---|
| 924 | #define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 |
|---|
| 925 | #define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 |
|---|
| 926 | #define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 |
|---|
| 927 | #define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 |
|---|
| 928 | #define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 |
|---|
| 929 | #define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 |
|---|
| 930 | #define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
|---|
| 931 | #define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
|---|
| 932 | #define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
|---|
| 933 | #define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
|---|
| 934 | #define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
|---|
| 935 | #define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
|---|
| 936 | #define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
|---|
| 937 | #define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
|---|
| 938 | #define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 |
|---|
| 939 | #define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 |
|---|
| 940 | #define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 |
|---|
| 941 | #define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 |
|---|
| 942 | #define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 |
|---|
| 943 | #define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 |
|---|
| 944 | #define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 |
|---|
| 945 | #define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 |
|---|
| 946 | #define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 |
|---|
| 947 | #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 |
|---|
| 948 | #define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
|---|
| 949 | #define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 |
|---|
| 950 | #define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 |
|---|
| 951 | #define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 |
|---|
| 952 | #define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 |
|---|
| 953 | #define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 |
|---|
| 954 | #define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 |
|---|
| 955 | #define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 |
|---|
| 956 | #define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 |
|---|
| 957 | #define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 |
|---|
| 958 | #define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 |
|---|
| 959 | #define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 |
|---|
| 960 | #define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 |
|---|
| 961 | #define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 |
|---|
| 962 | #define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 |
|---|
| 963 | #define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 |
|---|
| 964 | #define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 |
|---|
| 965 | #define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
|---|
| 966 | |
|---|
| 967 | |
|---|
| 968 | // addressBlock: mmhub_utcl2_vmsharedpfdec |
|---|
| 969 | #define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 |
|---|
| 970 | #define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 |
|---|
| 971 | #define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 |
|---|
| 972 | #define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 |
|---|
| 973 | #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
|---|
| 974 | #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
|---|
| 975 | #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
|---|
| 976 | #define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 |
|---|
| 977 | #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 |
|---|
| 978 | #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 |
|---|
| 979 | #define mmMC_VM_STEERING_DEFAULT 0x00000001 |
|---|
| 980 | #define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 |
|---|
| 981 | #define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 |
|---|
| 982 | #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 |
|---|
| 983 | #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 |
|---|
| 984 | #define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 |
|---|
| 985 | #define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 |
|---|
| 986 | #define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff |
|---|
| 987 | #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 |
|---|
| 988 | |
|---|
| 989 | |
|---|
| 990 | // addressBlock: mmhub_utcl2_vmsharedvcdec |
|---|
| 991 | #define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 |
|---|
| 992 | #define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 |
|---|
| 993 | #define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 |
|---|
| 994 | #define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 |
|---|
| 995 | #define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 |
|---|
| 996 | #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 |
|---|
| 997 | #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 |
|---|
| 998 | #define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 |
|---|
| 999 | |
|---|
| 1000 | |
|---|
| 1001 | // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
|---|
| 1002 | #define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
|---|
| 1003 | #define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
|---|
| 1004 | |
|---|
| 1005 | |
|---|
| 1006 | // addressBlock: mmhub_utcl2_atcl2pfcntldec |
|---|
| 1007 | #define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
|---|
| 1008 | #define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
|---|
| 1009 | #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
|---|
| 1010 | |
|---|
| 1011 | #endif |
|---|
| 1012 | |
|---|
