1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _mmhub_1_7_OFFSET_HEADER |
24 | #define |
25 | |
26 | |
27 | |
28 | // addressBlock: mmhub_dagb_dagbdec0 |
29 | // base address: 0x68000 |
30 | #define regDAGB0_RDCLI0 0x0000 |
31 | #define regDAGB0_RDCLI0_BASE_IDX 0 |
32 | #define regDAGB0_RDCLI1 0x0001 |
33 | #define regDAGB0_RDCLI1_BASE_IDX 0 |
34 | #define regDAGB0_RDCLI2 0x0002 |
35 | #define regDAGB0_RDCLI2_BASE_IDX 0 |
36 | #define regDAGB0_RDCLI3 0x0003 |
37 | #define regDAGB0_RDCLI3_BASE_IDX 0 |
38 | #define regDAGB0_RDCLI4 0x0004 |
39 | #define regDAGB0_RDCLI4_BASE_IDX 0 |
40 | #define regDAGB0_RDCLI5 0x0005 |
41 | #define regDAGB0_RDCLI5_BASE_IDX 0 |
42 | #define regDAGB0_RDCLI6 0x0006 |
43 | #define regDAGB0_RDCLI6_BASE_IDX 0 |
44 | #define regDAGB0_RDCLI7 0x0007 |
45 | #define regDAGB0_RDCLI7_BASE_IDX 0 |
46 | #define regDAGB0_RDCLI8 0x0008 |
47 | #define regDAGB0_RDCLI8_BASE_IDX 0 |
48 | #define regDAGB0_RDCLI9 0x0009 |
49 | #define regDAGB0_RDCLI9_BASE_IDX 0 |
50 | #define regDAGB0_RDCLI10 0x000a |
51 | #define regDAGB0_RDCLI10_BASE_IDX 0 |
52 | #define regDAGB0_RDCLI11 0x000b |
53 | #define regDAGB0_RDCLI11_BASE_IDX 0 |
54 | #define regDAGB0_RDCLI12 0x000c |
55 | #define regDAGB0_RDCLI12_BASE_IDX 0 |
56 | #define regDAGB0_RDCLI13 0x000d |
57 | #define regDAGB0_RDCLI13_BASE_IDX 0 |
58 | #define regDAGB0_RDCLI14 0x000e |
59 | #define regDAGB0_RDCLI14_BASE_IDX 0 |
60 | #define regDAGB0_RDCLI15 0x000f |
61 | #define regDAGB0_RDCLI15_BASE_IDX 0 |
62 | #define regDAGB0_RD_CNTL 0x0010 |
63 | #define regDAGB0_RD_CNTL_BASE_IDX 0 |
64 | #define regDAGB0_RD_GMI_CNTL 0x0011 |
65 | #define regDAGB0_RD_GMI_CNTL_BASE_IDX 0 |
66 | #define regDAGB0_RD_ADDR_DAGB 0x0012 |
67 | #define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0 |
68 | #define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 |
69 | #define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
70 | #define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 |
71 | #define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
72 | #define regDAGB0_RD_CGTT_CLK_CTRL 0x0015 |
73 | #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
74 | #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 |
75 | #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
76 | #define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 |
77 | #define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
78 | #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 |
79 | #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
80 | #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 |
81 | #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
82 | #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a |
83 | #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
84 | #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b |
85 | #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
86 | #define regDAGB0_RD_VC0_CNTL 0x001c |
87 | #define regDAGB0_RD_VC0_CNTL_BASE_IDX 0 |
88 | #define regDAGB0_RD_VC1_CNTL 0x001d |
89 | #define regDAGB0_RD_VC1_CNTL_BASE_IDX 0 |
90 | #define regDAGB0_RD_VC2_CNTL 0x001e |
91 | #define regDAGB0_RD_VC2_CNTL_BASE_IDX 0 |
92 | #define regDAGB0_RD_VC3_CNTL 0x001f |
93 | #define regDAGB0_RD_VC3_CNTL_BASE_IDX 0 |
94 | #define regDAGB0_RD_VC4_CNTL 0x0020 |
95 | #define regDAGB0_RD_VC4_CNTL_BASE_IDX 0 |
96 | #define regDAGB0_RD_VC5_CNTL 0x0021 |
97 | #define regDAGB0_RD_VC5_CNTL_BASE_IDX 0 |
98 | #define regDAGB0_RD_VC6_CNTL 0x0022 |
99 | #define regDAGB0_RD_VC6_CNTL_BASE_IDX 0 |
100 | #define regDAGB0_RD_VC7_CNTL 0x0023 |
101 | #define regDAGB0_RD_VC7_CNTL_BASE_IDX 0 |
102 | #define regDAGB0_RD_CNTL_MISC 0x0024 |
103 | #define regDAGB0_RD_CNTL_MISC_BASE_IDX 0 |
104 | #define regDAGB0_RD_TLB_CREDIT 0x0025 |
105 | #define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0 |
106 | #define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026 |
107 | #define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
108 | #define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027 |
109 | #define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
110 | #define regDAGB0_RDCLI_ASK_PENDING 0x0028 |
111 | #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 |
112 | #define regDAGB0_RDCLI_GO_PENDING 0x0029 |
113 | #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 |
114 | #define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a |
115 | #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
116 | #define regDAGB0_RDCLI_TLB_PENDING 0x002b |
117 | #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 |
118 | #define regDAGB0_RDCLI_OARB_PENDING 0x002c |
119 | #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 |
120 | #define regDAGB0_RDCLI_OSD_PENDING 0x002d |
121 | #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 |
122 | #define regDAGB0_WRCLI0 0x002e |
123 | #define regDAGB0_WRCLI0_BASE_IDX 0 |
124 | #define regDAGB0_WRCLI1 0x002f |
125 | #define regDAGB0_WRCLI1_BASE_IDX 0 |
126 | #define regDAGB0_WRCLI2 0x0030 |
127 | #define regDAGB0_WRCLI2_BASE_IDX 0 |
128 | #define regDAGB0_WRCLI3 0x0031 |
129 | #define regDAGB0_WRCLI3_BASE_IDX 0 |
130 | #define regDAGB0_WRCLI4 0x0032 |
131 | #define regDAGB0_WRCLI4_BASE_IDX 0 |
132 | #define regDAGB0_WRCLI5 0x0033 |
133 | #define regDAGB0_WRCLI5_BASE_IDX 0 |
134 | #define regDAGB0_WRCLI6 0x0034 |
135 | #define regDAGB0_WRCLI6_BASE_IDX 0 |
136 | #define regDAGB0_WRCLI7 0x0035 |
137 | #define regDAGB0_WRCLI7_BASE_IDX 0 |
138 | #define regDAGB0_WRCLI8 0x0036 |
139 | #define regDAGB0_WRCLI8_BASE_IDX 0 |
140 | #define regDAGB0_WRCLI9 0x0037 |
141 | #define regDAGB0_WRCLI9_BASE_IDX 0 |
142 | #define regDAGB0_WRCLI10 0x0038 |
143 | #define regDAGB0_WRCLI10_BASE_IDX 0 |
144 | #define regDAGB0_WRCLI11 0x0039 |
145 | #define regDAGB0_WRCLI11_BASE_IDX 0 |
146 | #define regDAGB0_WRCLI12 0x003a |
147 | #define regDAGB0_WRCLI12_BASE_IDX 0 |
148 | #define regDAGB0_WRCLI13 0x003b |
149 | #define regDAGB0_WRCLI13_BASE_IDX 0 |
150 | #define regDAGB0_WRCLI14 0x003c |
151 | #define regDAGB0_WRCLI14_BASE_IDX 0 |
152 | #define regDAGB0_WRCLI15 0x003d |
153 | #define regDAGB0_WRCLI15_BASE_IDX 0 |
154 | #define regDAGB0_WR_CNTL 0x003e |
155 | #define regDAGB0_WR_CNTL_BASE_IDX 0 |
156 | #define regDAGB0_WR_GMI_CNTL 0x003f |
157 | #define regDAGB0_WR_GMI_CNTL_BASE_IDX 0 |
158 | #define regDAGB0_WR_ADDR_DAGB 0x0040 |
159 | #define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0 |
160 | #define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041 |
161 | #define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
162 | #define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042 |
163 | #define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
164 | #define regDAGB0_WR_CGTT_CLK_CTRL 0x0043 |
165 | #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
166 | #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044 |
167 | #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
168 | #define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045 |
169 | #define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
170 | #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046 |
171 | #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
172 | #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047 |
173 | #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
174 | #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048 |
175 | #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
176 | #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049 |
177 | #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
178 | #define regDAGB0_WR_DATA_DAGB 0x004a |
179 | #define regDAGB0_WR_DATA_DAGB_BASE_IDX 0 |
180 | #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b |
181 | #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
182 | #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c |
183 | #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
184 | #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d |
185 | #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
186 | #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e |
187 | #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
188 | #define regDAGB0_WR_VC0_CNTL 0x004f |
189 | #define regDAGB0_WR_VC0_CNTL_BASE_IDX 0 |
190 | #define regDAGB0_WR_VC1_CNTL 0x0050 |
191 | #define regDAGB0_WR_VC1_CNTL_BASE_IDX 0 |
192 | #define regDAGB0_WR_VC2_CNTL 0x0051 |
193 | #define regDAGB0_WR_VC2_CNTL_BASE_IDX 0 |
194 | #define regDAGB0_WR_VC3_CNTL 0x0052 |
195 | #define regDAGB0_WR_VC3_CNTL_BASE_IDX 0 |
196 | #define regDAGB0_WR_VC4_CNTL 0x0053 |
197 | #define regDAGB0_WR_VC4_CNTL_BASE_IDX 0 |
198 | #define regDAGB0_WR_VC5_CNTL 0x0054 |
199 | #define regDAGB0_WR_VC5_CNTL_BASE_IDX 0 |
200 | #define regDAGB0_WR_VC6_CNTL 0x0055 |
201 | #define regDAGB0_WR_VC6_CNTL_BASE_IDX 0 |
202 | #define regDAGB0_WR_VC7_CNTL 0x0056 |
203 | #define regDAGB0_WR_VC7_CNTL_BASE_IDX 0 |
204 | #define regDAGB0_WR_CNTL_MISC 0x0057 |
205 | #define regDAGB0_WR_CNTL_MISC_BASE_IDX 0 |
206 | #define regDAGB0_WR_TLB_CREDIT 0x0058 |
207 | #define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0 |
208 | #define regDAGB0_WR_DATA_CREDIT 0x0059 |
209 | #define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0 |
210 | #define regDAGB0_WR_MISC_CREDIT 0x005a |
211 | #define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0 |
212 | #define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b |
213 | #define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
214 | #define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c |
215 | #define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
216 | #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d |
217 | #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
218 | #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e |
219 | #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
220 | #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f |
221 | #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
222 | #define regDAGB0_WRCLI_ASK_PENDING 0x0060 |
223 | #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 |
224 | #define regDAGB0_WRCLI_GO_PENDING 0x0061 |
225 | #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 |
226 | #define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062 |
227 | #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
228 | #define regDAGB0_WRCLI_TLB_PENDING 0x0063 |
229 | #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 |
230 | #define regDAGB0_WRCLI_OARB_PENDING 0x0064 |
231 | #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 |
232 | #define regDAGB0_WRCLI_OSD_PENDING 0x0065 |
233 | #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 |
234 | #define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066 |
235 | #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
236 | #define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067 |
237 | #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
238 | #define regDAGB0_DAGB_DLY 0x0068 |
239 | #define regDAGB0_DAGB_DLY_BASE_IDX 0 |
240 | #define regDAGB0_CNTL_MISC 0x0069 |
241 | #define regDAGB0_CNTL_MISC_BASE_IDX 0 |
242 | #define regDAGB0_CNTL_MISC2 0x006a |
243 | #define regDAGB0_CNTL_MISC2_BASE_IDX 0 |
244 | #define regDAGB0_FATAL_ERROR_CNTL 0x006b |
245 | #define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0 |
246 | #define regDAGB0_FATAL_ERROR_CLEAR 0x006c |
247 | #define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0 |
248 | #define regDAGB0_FATAL_ERROR_STATUS0 0x006d |
249 | #define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0 |
250 | #define regDAGB0_FATAL_ERROR_STATUS1 0x006e |
251 | #define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0 |
252 | #define regDAGB0_FATAL_ERROR_STATUS2 0x006f |
253 | #define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0 |
254 | #define regDAGB0_FATAL_ERROR_STATUS3 0x0070 |
255 | #define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0 |
256 | #define regDAGB0_FIFO_EMPTY 0x0071 |
257 | #define regDAGB0_FIFO_EMPTY_BASE_IDX 0 |
258 | #define regDAGB0_FIFO_FULL 0x0072 |
259 | #define regDAGB0_FIFO_FULL_BASE_IDX 0 |
260 | #define regDAGB0_WR_CREDITS_FULL 0x0073 |
261 | #define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0 |
262 | #define regDAGB0_RD_CREDITS_FULL 0x0074 |
263 | #define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0 |
264 | #define regDAGB0_PERFCOUNTER_LO 0x0075 |
265 | #define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0 |
266 | #define regDAGB0_PERFCOUNTER_HI 0x0076 |
267 | #define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0 |
268 | #define regDAGB0_PERFCOUNTER0_CFG 0x0077 |
269 | #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 |
270 | #define regDAGB0_PERFCOUNTER1_CFG 0x0078 |
271 | #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 |
272 | #define regDAGB0_PERFCOUNTER2_CFG 0x0079 |
273 | #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 |
274 | #define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a |
275 | #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
276 | #define regDAGB0_L1TLB_REG_RW 0x007b |
277 | #define regDAGB0_L1TLB_REG_RW_BASE_IDX 0 |
278 | #define regDAGB0_RESERVE1 0x007c |
279 | #define regDAGB0_RESERVE1_BASE_IDX 0 |
280 | #define regDAGB0_RESERVE2 0x007d |
281 | #define regDAGB0_RESERVE2_BASE_IDX 0 |
282 | #define regDAGB0_RESERVE3 0x007e |
283 | #define regDAGB0_RESERVE3_BASE_IDX 0 |
284 | #define regDAGB0_RESERVE4 0x007f |
285 | #define regDAGB0_RESERVE4_BASE_IDX 0 |
286 | |
287 | |
288 | // addressBlock: mmhub_dagb_dagbdec1 |
289 | // base address: 0x68200 |
290 | #define regDAGB1_RDCLI0 0x0080 |
291 | #define regDAGB1_RDCLI0_BASE_IDX 0 |
292 | #define regDAGB1_RDCLI1 0x0081 |
293 | #define regDAGB1_RDCLI1_BASE_IDX 0 |
294 | #define regDAGB1_RDCLI2 0x0082 |
295 | #define regDAGB1_RDCLI2_BASE_IDX 0 |
296 | #define regDAGB1_RDCLI3 0x0083 |
297 | #define regDAGB1_RDCLI3_BASE_IDX 0 |
298 | #define regDAGB1_RDCLI4 0x0084 |
299 | #define regDAGB1_RDCLI4_BASE_IDX 0 |
300 | #define regDAGB1_RDCLI5 0x0085 |
301 | #define regDAGB1_RDCLI5_BASE_IDX 0 |
302 | #define regDAGB1_RDCLI6 0x0086 |
303 | #define regDAGB1_RDCLI6_BASE_IDX 0 |
304 | #define regDAGB1_RDCLI7 0x0087 |
305 | #define regDAGB1_RDCLI7_BASE_IDX 0 |
306 | #define regDAGB1_RDCLI8 0x0088 |
307 | #define regDAGB1_RDCLI8_BASE_IDX 0 |
308 | #define regDAGB1_RDCLI9 0x0089 |
309 | #define regDAGB1_RDCLI9_BASE_IDX 0 |
310 | #define regDAGB1_RDCLI10 0x008a |
311 | #define regDAGB1_RDCLI10_BASE_IDX 0 |
312 | #define regDAGB1_RDCLI11 0x008b |
313 | #define regDAGB1_RDCLI11_BASE_IDX 0 |
314 | #define regDAGB1_RDCLI12 0x008c |
315 | #define regDAGB1_RDCLI12_BASE_IDX 0 |
316 | #define regDAGB1_RDCLI13 0x008d |
317 | #define regDAGB1_RDCLI13_BASE_IDX 0 |
318 | #define regDAGB1_RDCLI14 0x008e |
319 | #define regDAGB1_RDCLI14_BASE_IDX 0 |
320 | #define regDAGB1_RDCLI15 0x008f |
321 | #define regDAGB1_RDCLI15_BASE_IDX 0 |
322 | #define regDAGB1_RD_CNTL 0x0090 |
323 | #define regDAGB1_RD_CNTL_BASE_IDX 0 |
324 | #define regDAGB1_RD_GMI_CNTL 0x0091 |
325 | #define regDAGB1_RD_GMI_CNTL_BASE_IDX 0 |
326 | #define regDAGB1_RD_ADDR_DAGB 0x0092 |
327 | #define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0 |
328 | #define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 |
329 | #define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
330 | #define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 |
331 | #define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
332 | #define regDAGB1_RD_CGTT_CLK_CTRL 0x0095 |
333 | #define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
334 | #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 |
335 | #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
336 | #define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 |
337 | #define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
338 | #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 |
339 | #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
340 | #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 |
341 | #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
342 | #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a |
343 | #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
344 | #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b |
345 | #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
346 | #define regDAGB1_RD_VC0_CNTL 0x009c |
347 | #define regDAGB1_RD_VC0_CNTL_BASE_IDX 0 |
348 | #define regDAGB1_RD_VC1_CNTL 0x009d |
349 | #define regDAGB1_RD_VC1_CNTL_BASE_IDX 0 |
350 | #define regDAGB1_RD_VC2_CNTL 0x009e |
351 | #define regDAGB1_RD_VC2_CNTL_BASE_IDX 0 |
352 | #define regDAGB1_RD_VC3_CNTL 0x009f |
353 | #define regDAGB1_RD_VC3_CNTL_BASE_IDX 0 |
354 | #define regDAGB1_RD_VC4_CNTL 0x00a0 |
355 | #define regDAGB1_RD_VC4_CNTL_BASE_IDX 0 |
356 | #define regDAGB1_RD_VC5_CNTL 0x00a1 |
357 | #define regDAGB1_RD_VC5_CNTL_BASE_IDX 0 |
358 | #define regDAGB1_RD_VC6_CNTL 0x00a2 |
359 | #define regDAGB1_RD_VC6_CNTL_BASE_IDX 0 |
360 | #define regDAGB1_RD_VC7_CNTL 0x00a3 |
361 | #define regDAGB1_RD_VC7_CNTL_BASE_IDX 0 |
362 | #define regDAGB1_RD_CNTL_MISC 0x00a4 |
363 | #define regDAGB1_RD_CNTL_MISC_BASE_IDX 0 |
364 | #define regDAGB1_RD_TLB_CREDIT 0x00a5 |
365 | #define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0 |
366 | #define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6 |
367 | #define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
368 | #define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7 |
369 | #define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
370 | #define regDAGB1_RDCLI_ASK_PENDING 0x00a8 |
371 | #define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0 |
372 | #define regDAGB1_RDCLI_GO_PENDING 0x00a9 |
373 | #define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0 |
374 | #define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa |
375 | #define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
376 | #define regDAGB1_RDCLI_TLB_PENDING 0x00ab |
377 | #define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0 |
378 | #define regDAGB1_RDCLI_OARB_PENDING 0x00ac |
379 | #define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0 |
380 | #define regDAGB1_RDCLI_OSD_PENDING 0x00ad |
381 | #define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0 |
382 | #define regDAGB1_WRCLI0 0x00ae |
383 | #define regDAGB1_WRCLI0_BASE_IDX 0 |
384 | #define regDAGB1_WRCLI1 0x00af |
385 | #define regDAGB1_WRCLI1_BASE_IDX 0 |
386 | #define regDAGB1_WRCLI2 0x00b0 |
387 | #define regDAGB1_WRCLI2_BASE_IDX 0 |
388 | #define regDAGB1_WRCLI3 0x00b1 |
389 | #define regDAGB1_WRCLI3_BASE_IDX 0 |
390 | #define regDAGB1_WRCLI4 0x00b2 |
391 | #define regDAGB1_WRCLI4_BASE_IDX 0 |
392 | #define regDAGB1_WRCLI5 0x00b3 |
393 | #define regDAGB1_WRCLI5_BASE_IDX 0 |
394 | #define regDAGB1_WRCLI6 0x00b4 |
395 | #define regDAGB1_WRCLI6_BASE_IDX 0 |
396 | #define regDAGB1_WRCLI7 0x00b5 |
397 | #define regDAGB1_WRCLI7_BASE_IDX 0 |
398 | #define regDAGB1_WRCLI8 0x00b6 |
399 | #define regDAGB1_WRCLI8_BASE_IDX 0 |
400 | #define regDAGB1_WRCLI9 0x00b7 |
401 | #define regDAGB1_WRCLI9_BASE_IDX 0 |
402 | #define regDAGB1_WRCLI10 0x00b8 |
403 | #define regDAGB1_WRCLI10_BASE_IDX 0 |
404 | #define regDAGB1_WRCLI11 0x00b9 |
405 | #define regDAGB1_WRCLI11_BASE_IDX 0 |
406 | #define regDAGB1_WRCLI12 0x00ba |
407 | #define regDAGB1_WRCLI12_BASE_IDX 0 |
408 | #define regDAGB1_WRCLI13 0x00bb |
409 | #define regDAGB1_WRCLI13_BASE_IDX 0 |
410 | #define regDAGB1_WRCLI14 0x00bc |
411 | #define regDAGB1_WRCLI14_BASE_IDX 0 |
412 | #define regDAGB1_WRCLI15 0x00bd |
413 | #define regDAGB1_WRCLI15_BASE_IDX 0 |
414 | #define regDAGB1_WR_CNTL 0x00be |
415 | #define regDAGB1_WR_CNTL_BASE_IDX 0 |
416 | #define regDAGB1_WR_GMI_CNTL 0x00bf |
417 | #define regDAGB1_WR_GMI_CNTL_BASE_IDX 0 |
418 | #define regDAGB1_WR_ADDR_DAGB 0x00c0 |
419 | #define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0 |
420 | #define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1 |
421 | #define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
422 | #define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2 |
423 | #define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
424 | #define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3 |
425 | #define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
426 | #define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4 |
427 | #define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
428 | #define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5 |
429 | #define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
430 | #define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6 |
431 | #define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
432 | #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7 |
433 | #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
434 | #define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8 |
435 | #define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
436 | #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c9 |
437 | #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
438 | #define regDAGB1_WR_DATA_DAGB 0x00ca |
439 | #define regDAGB1_WR_DATA_DAGB_BASE_IDX 0 |
440 | #define regDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00cb |
441 | #define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
442 | #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00cc |
443 | #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
444 | #define regDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cd |
445 | #define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
446 | #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00ce |
447 | #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
448 | #define regDAGB1_WR_VC0_CNTL 0x00cf |
449 | #define regDAGB1_WR_VC0_CNTL_BASE_IDX 0 |
450 | #define regDAGB1_WR_VC1_CNTL 0x00d0 |
451 | #define regDAGB1_WR_VC1_CNTL_BASE_IDX 0 |
452 | #define regDAGB1_WR_VC2_CNTL 0x00d1 |
453 | #define regDAGB1_WR_VC2_CNTL_BASE_IDX 0 |
454 | #define regDAGB1_WR_VC3_CNTL 0x00d2 |
455 | #define regDAGB1_WR_VC3_CNTL_BASE_IDX 0 |
456 | #define regDAGB1_WR_VC4_CNTL 0x00d3 |
457 | #define regDAGB1_WR_VC4_CNTL_BASE_IDX 0 |
458 | #define regDAGB1_WR_VC5_CNTL 0x00d4 |
459 | #define regDAGB1_WR_VC5_CNTL_BASE_IDX 0 |
460 | #define regDAGB1_WR_VC6_CNTL 0x00d5 |
461 | #define regDAGB1_WR_VC6_CNTL_BASE_IDX 0 |
462 | #define regDAGB1_WR_VC7_CNTL 0x00d6 |
463 | #define regDAGB1_WR_VC7_CNTL_BASE_IDX 0 |
464 | #define regDAGB1_WR_CNTL_MISC 0x00d7 |
465 | #define regDAGB1_WR_CNTL_MISC_BASE_IDX 0 |
466 | #define regDAGB1_WR_TLB_CREDIT 0x00d8 |
467 | #define regDAGB1_WR_TLB_CREDIT_BASE_IDX 0 |
468 | #define regDAGB1_WR_DATA_CREDIT 0x00d9 |
469 | #define regDAGB1_WR_DATA_CREDIT_BASE_IDX 0 |
470 | #define regDAGB1_WR_MISC_CREDIT 0x00da |
471 | #define regDAGB1_WR_MISC_CREDIT_BASE_IDX 0 |
472 | #define regDAGB1_WR_OSD_CREDIT_CNTL1 0x00db |
473 | #define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
474 | #define regDAGB1_WR_OSD_CREDIT_CNTL2 0x00dc |
475 | #define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
476 | #define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x00dd |
477 | #define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
478 | #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00de |
479 | #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
480 | #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00df |
481 | #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
482 | #define regDAGB1_WRCLI_ASK_PENDING 0x00e0 |
483 | #define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX 0 |
484 | #define regDAGB1_WRCLI_GO_PENDING 0x00e1 |
485 | #define regDAGB1_WRCLI_GO_PENDING_BASE_IDX 0 |
486 | #define regDAGB1_WRCLI_GBLSEND_PENDING 0x00e2 |
487 | #define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
488 | #define regDAGB1_WRCLI_TLB_PENDING 0x00e3 |
489 | #define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX 0 |
490 | #define regDAGB1_WRCLI_OARB_PENDING 0x00e4 |
491 | #define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX 0 |
492 | #define regDAGB1_WRCLI_OSD_PENDING 0x00e5 |
493 | #define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX 0 |
494 | #define regDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e6 |
495 | #define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
496 | #define regDAGB1_WRCLI_DBUS_GO_PENDING 0x00e7 |
497 | #define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
498 | #define regDAGB1_DAGB_DLY 0x00e8 |
499 | #define regDAGB1_DAGB_DLY_BASE_IDX 0 |
500 | #define regDAGB1_CNTL_MISC 0x00e9 |
501 | #define regDAGB1_CNTL_MISC_BASE_IDX 0 |
502 | #define regDAGB1_CNTL_MISC2 0x00ea |
503 | #define regDAGB1_CNTL_MISC2_BASE_IDX 0 |
504 | #define regDAGB1_FATAL_ERROR_CNTL 0x00eb |
505 | #define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX 0 |
506 | #define regDAGB1_FATAL_ERROR_CLEAR 0x00ec |
507 | #define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX 0 |
508 | #define regDAGB1_FATAL_ERROR_STATUS0 0x00ed |
509 | #define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX 0 |
510 | #define regDAGB1_FATAL_ERROR_STATUS1 0x00ee |
511 | #define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX 0 |
512 | #define regDAGB1_FATAL_ERROR_STATUS2 0x00ef |
513 | #define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX 0 |
514 | #define regDAGB1_FATAL_ERROR_STATUS3 0x00f0 |
515 | #define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX 0 |
516 | #define regDAGB1_FIFO_EMPTY 0x00f1 |
517 | #define regDAGB1_FIFO_EMPTY_BASE_IDX 0 |
518 | #define regDAGB1_FIFO_FULL 0x00f2 |
519 | #define regDAGB1_FIFO_FULL_BASE_IDX 0 |
520 | #define regDAGB1_WR_CREDITS_FULL 0x00f3 |
521 | #define regDAGB1_WR_CREDITS_FULL_BASE_IDX 0 |
522 | #define regDAGB1_RD_CREDITS_FULL 0x00f4 |
523 | #define regDAGB1_RD_CREDITS_FULL_BASE_IDX 0 |
524 | #define regDAGB1_PERFCOUNTER_LO 0x00f5 |
525 | #define regDAGB1_PERFCOUNTER_LO_BASE_IDX 0 |
526 | #define regDAGB1_PERFCOUNTER_HI 0x00f6 |
527 | #define regDAGB1_PERFCOUNTER_HI_BASE_IDX 0 |
528 | #define regDAGB1_PERFCOUNTER0_CFG 0x00f7 |
529 | #define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX 0 |
530 | #define regDAGB1_PERFCOUNTER1_CFG 0x00f8 |
531 | #define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX 0 |
532 | #define regDAGB1_PERFCOUNTER2_CFG 0x00f9 |
533 | #define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX 0 |
534 | #define regDAGB1_PERFCOUNTER_RSLT_CNTL 0x00fa |
535 | #define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
536 | #define regDAGB1_L1TLB_REG_RW 0x00fb |
537 | #define regDAGB1_L1TLB_REG_RW_BASE_IDX 0 |
538 | #define regDAGB1_RESERVE1 0x00fc |
539 | #define regDAGB1_RESERVE1_BASE_IDX 0 |
540 | #define regDAGB1_RESERVE2 0x00fd |
541 | #define regDAGB1_RESERVE2_BASE_IDX 0 |
542 | #define regDAGB1_RESERVE3 0x00fe |
543 | #define regDAGB1_RESERVE3_BASE_IDX 0 |
544 | #define regDAGB1_RESERVE4 0x00ff |
545 | #define regDAGB1_RESERVE4_BASE_IDX 0 |
546 | |
547 | |
548 | // addressBlock: mmhub_dagb_dagbdec2 |
549 | // base address: 0x68400 |
550 | #define regDAGB2_RDCLI0 0x0100 |
551 | #define regDAGB2_RDCLI0_BASE_IDX 0 |
552 | #define regDAGB2_RDCLI1 0x0101 |
553 | #define regDAGB2_RDCLI1_BASE_IDX 0 |
554 | #define regDAGB2_RDCLI2 0x0102 |
555 | #define regDAGB2_RDCLI2_BASE_IDX 0 |
556 | #define regDAGB2_RDCLI3 0x0103 |
557 | #define regDAGB2_RDCLI3_BASE_IDX 0 |
558 | #define regDAGB2_RDCLI4 0x0104 |
559 | #define regDAGB2_RDCLI4_BASE_IDX 0 |
560 | #define regDAGB2_RDCLI5 0x0105 |
561 | #define regDAGB2_RDCLI5_BASE_IDX 0 |
562 | #define regDAGB2_RDCLI6 0x0106 |
563 | #define regDAGB2_RDCLI6_BASE_IDX 0 |
564 | #define regDAGB2_RDCLI7 0x0107 |
565 | #define regDAGB2_RDCLI7_BASE_IDX 0 |
566 | #define regDAGB2_RDCLI8 0x0108 |
567 | #define regDAGB2_RDCLI8_BASE_IDX 0 |
568 | #define regDAGB2_RDCLI9 0x0109 |
569 | #define regDAGB2_RDCLI9_BASE_IDX 0 |
570 | #define regDAGB2_RDCLI10 0x010a |
571 | #define regDAGB2_RDCLI10_BASE_IDX 0 |
572 | #define regDAGB2_RDCLI11 0x010b |
573 | #define regDAGB2_RDCLI11_BASE_IDX 0 |
574 | #define regDAGB2_RDCLI12 0x010c |
575 | #define regDAGB2_RDCLI12_BASE_IDX 0 |
576 | #define regDAGB2_RDCLI13 0x010d |
577 | #define regDAGB2_RDCLI13_BASE_IDX 0 |
578 | #define regDAGB2_RDCLI14 0x010e |
579 | #define regDAGB2_RDCLI14_BASE_IDX 0 |
580 | #define regDAGB2_RDCLI15 0x010f |
581 | #define regDAGB2_RDCLI15_BASE_IDX 0 |
582 | #define regDAGB2_RD_CNTL 0x0110 |
583 | #define regDAGB2_RD_CNTL_BASE_IDX 0 |
584 | #define regDAGB2_RD_GMI_CNTL 0x0111 |
585 | #define regDAGB2_RD_GMI_CNTL_BASE_IDX 0 |
586 | #define regDAGB2_RD_ADDR_DAGB 0x0112 |
587 | #define regDAGB2_RD_ADDR_DAGB_BASE_IDX 0 |
588 | #define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 |
589 | #define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
590 | #define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 |
591 | #define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
592 | #define regDAGB2_RD_CGTT_CLK_CTRL 0x0115 |
593 | #define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
594 | #define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 |
595 | #define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
596 | #define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 |
597 | #define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
598 | #define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 |
599 | #define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
600 | #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 |
601 | #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
602 | #define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a |
603 | #define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
604 | #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b |
605 | #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
606 | #define regDAGB2_RD_VC0_CNTL 0x011c |
607 | #define regDAGB2_RD_VC0_CNTL_BASE_IDX 0 |
608 | #define regDAGB2_RD_VC1_CNTL 0x011d |
609 | #define regDAGB2_RD_VC1_CNTL_BASE_IDX 0 |
610 | #define regDAGB2_RD_VC2_CNTL 0x011e |
611 | #define regDAGB2_RD_VC2_CNTL_BASE_IDX 0 |
612 | #define regDAGB2_RD_VC3_CNTL 0x011f |
613 | #define regDAGB2_RD_VC3_CNTL_BASE_IDX 0 |
614 | #define regDAGB2_RD_VC4_CNTL 0x0120 |
615 | #define regDAGB2_RD_VC4_CNTL_BASE_IDX 0 |
616 | #define regDAGB2_RD_VC5_CNTL 0x0121 |
617 | #define regDAGB2_RD_VC5_CNTL_BASE_IDX 0 |
618 | #define regDAGB2_RD_VC6_CNTL 0x0122 |
619 | #define regDAGB2_RD_VC6_CNTL_BASE_IDX 0 |
620 | #define regDAGB2_RD_VC7_CNTL 0x0123 |
621 | #define regDAGB2_RD_VC7_CNTL_BASE_IDX 0 |
622 | #define regDAGB2_RD_CNTL_MISC 0x0124 |
623 | #define regDAGB2_RD_CNTL_MISC_BASE_IDX 0 |
624 | #define regDAGB2_RD_TLB_CREDIT 0x0125 |
625 | #define regDAGB2_RD_TLB_CREDIT_BASE_IDX 0 |
626 | #define regDAGB2_RD_RDRET_CREDIT_CNTL 0x0126 |
627 | #define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
628 | #define regDAGB2_RD_RDRET_CREDIT_CNTL2 0x0127 |
629 | #define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
630 | #define regDAGB2_RDCLI_ASK_PENDING 0x0128 |
631 | #define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX 0 |
632 | #define regDAGB2_RDCLI_GO_PENDING 0x0129 |
633 | #define regDAGB2_RDCLI_GO_PENDING_BASE_IDX 0 |
634 | #define regDAGB2_RDCLI_GBLSEND_PENDING 0x012a |
635 | #define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
636 | #define regDAGB2_RDCLI_TLB_PENDING 0x012b |
637 | #define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX 0 |
638 | #define regDAGB2_RDCLI_OARB_PENDING 0x012c |
639 | #define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX 0 |
640 | #define regDAGB2_RDCLI_OSD_PENDING 0x012d |
641 | #define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX 0 |
642 | #define regDAGB2_WRCLI0 0x012e |
643 | #define regDAGB2_WRCLI0_BASE_IDX 0 |
644 | #define regDAGB2_WRCLI1 0x012f |
645 | #define regDAGB2_WRCLI1_BASE_IDX 0 |
646 | #define regDAGB2_WRCLI2 0x0130 |
647 | #define regDAGB2_WRCLI2_BASE_IDX 0 |
648 | #define regDAGB2_WRCLI3 0x0131 |
649 | #define regDAGB2_WRCLI3_BASE_IDX 0 |
650 | #define regDAGB2_WRCLI4 0x0132 |
651 | #define regDAGB2_WRCLI4_BASE_IDX 0 |
652 | #define regDAGB2_WRCLI5 0x0133 |
653 | #define regDAGB2_WRCLI5_BASE_IDX 0 |
654 | #define regDAGB2_WRCLI6 0x0134 |
655 | #define regDAGB2_WRCLI6_BASE_IDX 0 |
656 | #define regDAGB2_WRCLI7 0x0135 |
657 | #define regDAGB2_WRCLI7_BASE_IDX 0 |
658 | #define regDAGB2_WRCLI8 0x0136 |
659 | #define regDAGB2_WRCLI8_BASE_IDX 0 |
660 | #define regDAGB2_WRCLI9 0x0137 |
661 | #define regDAGB2_WRCLI9_BASE_IDX 0 |
662 | #define regDAGB2_WRCLI10 0x0138 |
663 | #define regDAGB2_WRCLI10_BASE_IDX 0 |
664 | #define regDAGB2_WRCLI11 0x0139 |
665 | #define regDAGB2_WRCLI11_BASE_IDX 0 |
666 | #define regDAGB2_WRCLI12 0x013a |
667 | #define regDAGB2_WRCLI12_BASE_IDX 0 |
668 | #define regDAGB2_WRCLI13 0x013b |
669 | #define regDAGB2_WRCLI13_BASE_IDX 0 |
670 | #define regDAGB2_WRCLI14 0x013c |
671 | #define regDAGB2_WRCLI14_BASE_IDX 0 |
672 | #define regDAGB2_WRCLI15 0x013d |
673 | #define regDAGB2_WRCLI15_BASE_IDX 0 |
674 | #define regDAGB2_WR_CNTL 0x013e |
675 | #define regDAGB2_WR_CNTL_BASE_IDX 0 |
676 | #define regDAGB2_WR_GMI_CNTL 0x013f |
677 | #define regDAGB2_WR_GMI_CNTL_BASE_IDX 0 |
678 | #define regDAGB2_WR_ADDR_DAGB 0x0140 |
679 | #define regDAGB2_WR_ADDR_DAGB_BASE_IDX 0 |
680 | #define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x0141 |
681 | #define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
682 | #define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0142 |
683 | #define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
684 | #define regDAGB2_WR_CGTT_CLK_CTRL 0x0143 |
685 | #define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
686 | #define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0144 |
687 | #define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
688 | #define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0145 |
689 | #define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
690 | #define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0146 |
691 | #define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
692 | #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0147 |
693 | #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
694 | #define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0148 |
695 | #define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
696 | #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0149 |
697 | #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
698 | #define regDAGB2_WR_DATA_DAGB 0x014a |
699 | #define regDAGB2_WR_DATA_DAGB_BASE_IDX 0 |
700 | #define regDAGB2_WR_DATA_DAGB_MAX_BURST0 0x014b |
701 | #define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
702 | #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014c |
703 | #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
704 | #define regDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014d |
705 | #define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
706 | #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014e |
707 | #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
708 | #define regDAGB2_WR_VC0_CNTL 0x014f |
709 | #define regDAGB2_WR_VC0_CNTL_BASE_IDX 0 |
710 | #define regDAGB2_WR_VC1_CNTL 0x0150 |
711 | #define regDAGB2_WR_VC1_CNTL_BASE_IDX 0 |
712 | #define regDAGB2_WR_VC2_CNTL 0x0151 |
713 | #define regDAGB2_WR_VC2_CNTL_BASE_IDX 0 |
714 | #define regDAGB2_WR_VC3_CNTL 0x0152 |
715 | #define regDAGB2_WR_VC3_CNTL_BASE_IDX 0 |
716 | #define regDAGB2_WR_VC4_CNTL 0x0153 |
717 | #define regDAGB2_WR_VC4_CNTL_BASE_IDX 0 |
718 | #define regDAGB2_WR_VC5_CNTL 0x0154 |
719 | #define regDAGB2_WR_VC5_CNTL_BASE_IDX 0 |
720 | #define regDAGB2_WR_VC6_CNTL 0x0155 |
721 | #define regDAGB2_WR_VC6_CNTL_BASE_IDX 0 |
722 | #define regDAGB2_WR_VC7_CNTL 0x0156 |
723 | #define regDAGB2_WR_VC7_CNTL_BASE_IDX 0 |
724 | #define regDAGB2_WR_CNTL_MISC 0x0157 |
725 | #define regDAGB2_WR_CNTL_MISC_BASE_IDX 0 |
726 | #define regDAGB2_WR_TLB_CREDIT 0x0158 |
727 | #define regDAGB2_WR_TLB_CREDIT_BASE_IDX 0 |
728 | #define regDAGB2_WR_DATA_CREDIT 0x0159 |
729 | #define regDAGB2_WR_DATA_CREDIT_BASE_IDX 0 |
730 | #define regDAGB2_WR_MISC_CREDIT 0x015a |
731 | #define regDAGB2_WR_MISC_CREDIT_BASE_IDX 0 |
732 | #define regDAGB2_WR_OSD_CREDIT_CNTL1 0x015b |
733 | #define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
734 | #define regDAGB2_WR_OSD_CREDIT_CNTL2 0x015c |
735 | #define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
736 | #define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x015d |
737 | #define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
738 | #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015e |
739 | #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
740 | #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015f |
741 | #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
742 | #define regDAGB2_WRCLI_ASK_PENDING 0x0160 |
743 | #define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX 0 |
744 | #define regDAGB2_WRCLI_GO_PENDING 0x0161 |
745 | #define regDAGB2_WRCLI_GO_PENDING_BASE_IDX 0 |
746 | #define regDAGB2_WRCLI_GBLSEND_PENDING 0x0162 |
747 | #define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
748 | #define regDAGB2_WRCLI_TLB_PENDING 0x0163 |
749 | #define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX 0 |
750 | #define regDAGB2_WRCLI_OARB_PENDING 0x0164 |
751 | #define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX 0 |
752 | #define regDAGB2_WRCLI_OSD_PENDING 0x0165 |
753 | #define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX 0 |
754 | #define regDAGB2_WRCLI_DBUS_ASK_PENDING 0x0166 |
755 | #define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
756 | #define regDAGB2_WRCLI_DBUS_GO_PENDING 0x0167 |
757 | #define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
758 | #define regDAGB2_DAGB_DLY 0x0168 |
759 | #define regDAGB2_DAGB_DLY_BASE_IDX 0 |
760 | #define regDAGB2_CNTL_MISC 0x0169 |
761 | #define regDAGB2_CNTL_MISC_BASE_IDX 0 |
762 | #define regDAGB2_CNTL_MISC2 0x016a |
763 | #define regDAGB2_CNTL_MISC2_BASE_IDX 0 |
764 | #define regDAGB2_FATAL_ERROR_CNTL 0x016b |
765 | #define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX 0 |
766 | #define regDAGB2_FATAL_ERROR_CLEAR 0x016c |
767 | #define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX 0 |
768 | #define regDAGB2_FATAL_ERROR_STATUS0 0x016d |
769 | #define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX 0 |
770 | #define regDAGB2_FATAL_ERROR_STATUS1 0x016e |
771 | #define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX 0 |
772 | #define regDAGB2_FATAL_ERROR_STATUS2 0x016f |
773 | #define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX 0 |
774 | #define regDAGB2_FATAL_ERROR_STATUS3 0x0170 |
775 | #define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX 0 |
776 | #define regDAGB2_FIFO_EMPTY 0x0171 |
777 | #define regDAGB2_FIFO_EMPTY_BASE_IDX 0 |
778 | #define regDAGB2_FIFO_FULL 0x0172 |
779 | #define regDAGB2_FIFO_FULL_BASE_IDX 0 |
780 | #define regDAGB2_WR_CREDITS_FULL 0x0173 |
781 | #define regDAGB2_WR_CREDITS_FULL_BASE_IDX 0 |
782 | #define regDAGB2_RD_CREDITS_FULL 0x0174 |
783 | #define regDAGB2_RD_CREDITS_FULL_BASE_IDX 0 |
784 | #define regDAGB2_PERFCOUNTER_LO 0x0175 |
785 | #define regDAGB2_PERFCOUNTER_LO_BASE_IDX 0 |
786 | #define regDAGB2_PERFCOUNTER_HI 0x0176 |
787 | #define regDAGB2_PERFCOUNTER_HI_BASE_IDX 0 |
788 | #define regDAGB2_PERFCOUNTER0_CFG 0x0177 |
789 | #define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX 0 |
790 | #define regDAGB2_PERFCOUNTER1_CFG 0x0178 |
791 | #define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX 0 |
792 | #define regDAGB2_PERFCOUNTER2_CFG 0x0179 |
793 | #define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX 0 |
794 | #define regDAGB2_PERFCOUNTER_RSLT_CNTL 0x017a |
795 | #define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
796 | #define regDAGB2_L1TLB_REG_RW 0x017b |
797 | #define regDAGB2_L1TLB_REG_RW_BASE_IDX 0 |
798 | #define regDAGB2_RESERVE1 0x017c |
799 | #define regDAGB2_RESERVE1_BASE_IDX 0 |
800 | #define regDAGB2_RESERVE2 0x017d |
801 | #define regDAGB2_RESERVE2_BASE_IDX 0 |
802 | #define regDAGB2_RESERVE3 0x017e |
803 | #define regDAGB2_RESERVE3_BASE_IDX 0 |
804 | #define regDAGB2_RESERVE4 0x017f |
805 | #define regDAGB2_RESERVE4_BASE_IDX 0 |
806 | |
807 | |
808 | // addressBlock: mmhub_dagb_dagbdec3 |
809 | // base address: 0x68600 |
810 | #define regDAGB3_RDCLI0 0x0180 |
811 | #define regDAGB3_RDCLI0_BASE_IDX 0 |
812 | #define regDAGB3_RDCLI1 0x0181 |
813 | #define regDAGB3_RDCLI1_BASE_IDX 0 |
814 | #define regDAGB3_RDCLI2 0x0182 |
815 | #define regDAGB3_RDCLI2_BASE_IDX 0 |
816 | #define regDAGB3_RDCLI3 0x0183 |
817 | #define regDAGB3_RDCLI3_BASE_IDX 0 |
818 | #define regDAGB3_RDCLI4 0x0184 |
819 | #define regDAGB3_RDCLI4_BASE_IDX 0 |
820 | #define regDAGB3_RDCLI5 0x0185 |
821 | #define regDAGB3_RDCLI5_BASE_IDX 0 |
822 | #define regDAGB3_RDCLI6 0x0186 |
823 | #define regDAGB3_RDCLI6_BASE_IDX 0 |
824 | #define regDAGB3_RDCLI7 0x0187 |
825 | #define regDAGB3_RDCLI7_BASE_IDX 0 |
826 | #define regDAGB3_RDCLI8 0x0188 |
827 | #define regDAGB3_RDCLI8_BASE_IDX 0 |
828 | #define regDAGB3_RDCLI9 0x0189 |
829 | #define regDAGB3_RDCLI9_BASE_IDX 0 |
830 | #define regDAGB3_RDCLI10 0x018a |
831 | #define regDAGB3_RDCLI10_BASE_IDX 0 |
832 | #define regDAGB3_RDCLI11 0x018b |
833 | #define regDAGB3_RDCLI11_BASE_IDX 0 |
834 | #define regDAGB3_RDCLI12 0x018c |
835 | #define regDAGB3_RDCLI12_BASE_IDX 0 |
836 | #define regDAGB3_RDCLI13 0x018d |
837 | #define regDAGB3_RDCLI13_BASE_IDX 0 |
838 | #define regDAGB3_RDCLI14 0x018e |
839 | #define regDAGB3_RDCLI14_BASE_IDX 0 |
840 | #define regDAGB3_RDCLI15 0x018f |
841 | #define regDAGB3_RDCLI15_BASE_IDX 0 |
842 | #define regDAGB3_RD_CNTL 0x0190 |
843 | #define regDAGB3_RD_CNTL_BASE_IDX 0 |
844 | #define regDAGB3_RD_GMI_CNTL 0x0191 |
845 | #define regDAGB3_RD_GMI_CNTL_BASE_IDX 0 |
846 | #define regDAGB3_RD_ADDR_DAGB 0x0192 |
847 | #define regDAGB3_RD_ADDR_DAGB_BASE_IDX 0 |
848 | #define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 |
849 | #define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
850 | #define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 |
851 | #define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
852 | #define regDAGB3_RD_CGTT_CLK_CTRL 0x0195 |
853 | #define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
854 | #define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 |
855 | #define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
856 | #define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 |
857 | #define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
858 | #define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 |
859 | #define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
860 | #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 |
861 | #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
862 | #define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a |
863 | #define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
864 | #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b |
865 | #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
866 | #define regDAGB3_RD_VC0_CNTL 0x019c |
867 | #define regDAGB3_RD_VC0_CNTL_BASE_IDX 0 |
868 | #define regDAGB3_RD_VC1_CNTL 0x019d |
869 | #define regDAGB3_RD_VC1_CNTL_BASE_IDX 0 |
870 | #define regDAGB3_RD_VC2_CNTL 0x019e |
871 | #define regDAGB3_RD_VC2_CNTL_BASE_IDX 0 |
872 | #define regDAGB3_RD_VC3_CNTL 0x019f |
873 | #define regDAGB3_RD_VC3_CNTL_BASE_IDX 0 |
874 | #define regDAGB3_RD_VC4_CNTL 0x01a0 |
875 | #define regDAGB3_RD_VC4_CNTL_BASE_IDX 0 |
876 | #define regDAGB3_RD_VC5_CNTL 0x01a1 |
877 | #define regDAGB3_RD_VC5_CNTL_BASE_IDX 0 |
878 | #define regDAGB3_RD_VC6_CNTL 0x01a2 |
879 | #define regDAGB3_RD_VC6_CNTL_BASE_IDX 0 |
880 | #define regDAGB3_RD_VC7_CNTL 0x01a3 |
881 | #define regDAGB3_RD_VC7_CNTL_BASE_IDX 0 |
882 | #define regDAGB3_RD_CNTL_MISC 0x01a4 |
883 | #define regDAGB3_RD_CNTL_MISC_BASE_IDX 0 |
884 | #define regDAGB3_RD_TLB_CREDIT 0x01a5 |
885 | #define regDAGB3_RD_TLB_CREDIT_BASE_IDX 0 |
886 | #define regDAGB3_RD_RDRET_CREDIT_CNTL 0x01a6 |
887 | #define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
888 | #define regDAGB3_RD_RDRET_CREDIT_CNTL2 0x01a7 |
889 | #define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
890 | #define regDAGB3_RDCLI_ASK_PENDING 0x01a8 |
891 | #define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX 0 |
892 | #define regDAGB3_RDCLI_GO_PENDING 0x01a9 |
893 | #define regDAGB3_RDCLI_GO_PENDING_BASE_IDX 0 |
894 | #define regDAGB3_RDCLI_GBLSEND_PENDING 0x01aa |
895 | #define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
896 | #define regDAGB3_RDCLI_TLB_PENDING 0x01ab |
897 | #define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX 0 |
898 | #define regDAGB3_RDCLI_OARB_PENDING 0x01ac |
899 | #define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX 0 |
900 | #define regDAGB3_RDCLI_OSD_PENDING 0x01ad |
901 | #define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX 0 |
902 | #define regDAGB3_WRCLI0 0x01ae |
903 | #define regDAGB3_WRCLI0_BASE_IDX 0 |
904 | #define regDAGB3_WRCLI1 0x01af |
905 | #define regDAGB3_WRCLI1_BASE_IDX 0 |
906 | #define regDAGB3_WRCLI2 0x01b0 |
907 | #define regDAGB3_WRCLI2_BASE_IDX 0 |
908 | #define regDAGB3_WRCLI3 0x01b1 |
909 | #define regDAGB3_WRCLI3_BASE_IDX 0 |
910 | #define regDAGB3_WRCLI4 0x01b2 |
911 | #define regDAGB3_WRCLI4_BASE_IDX 0 |
912 | #define regDAGB3_WRCLI5 0x01b3 |
913 | #define regDAGB3_WRCLI5_BASE_IDX 0 |
914 | #define regDAGB3_WRCLI6 0x01b4 |
915 | #define regDAGB3_WRCLI6_BASE_IDX 0 |
916 | #define regDAGB3_WRCLI7 0x01b5 |
917 | #define regDAGB3_WRCLI7_BASE_IDX 0 |
918 | #define regDAGB3_WRCLI8 0x01b6 |
919 | #define regDAGB3_WRCLI8_BASE_IDX 0 |
920 | #define regDAGB3_WRCLI9 0x01b7 |
921 | #define regDAGB3_WRCLI9_BASE_IDX 0 |
922 | #define regDAGB3_WRCLI10 0x01b8 |
923 | #define regDAGB3_WRCLI10_BASE_IDX 0 |
924 | #define regDAGB3_WRCLI11 0x01b9 |
925 | #define regDAGB3_WRCLI11_BASE_IDX 0 |
926 | #define regDAGB3_WRCLI12 0x01ba |
927 | #define regDAGB3_WRCLI12_BASE_IDX 0 |
928 | #define regDAGB3_WRCLI13 0x01bb |
929 | #define regDAGB3_WRCLI13_BASE_IDX 0 |
930 | #define regDAGB3_WRCLI14 0x01bc |
931 | #define regDAGB3_WRCLI14_BASE_IDX 0 |
932 | #define regDAGB3_WRCLI15 0x01bd |
933 | #define regDAGB3_WRCLI15_BASE_IDX 0 |
934 | #define regDAGB3_WR_CNTL 0x01be |
935 | #define regDAGB3_WR_CNTL_BASE_IDX 0 |
936 | #define regDAGB3_WR_GMI_CNTL 0x01bf |
937 | #define regDAGB3_WR_GMI_CNTL_BASE_IDX 0 |
938 | #define regDAGB3_WR_ADDR_DAGB 0x01c0 |
939 | #define regDAGB3_WR_ADDR_DAGB_BASE_IDX 0 |
940 | #define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01c1 |
941 | #define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
942 | #define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c2 |
943 | #define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
944 | #define regDAGB3_WR_CGTT_CLK_CTRL 0x01c3 |
945 | #define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
946 | #define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c4 |
947 | #define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
948 | #define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c5 |
949 | #define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
950 | #define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c6 |
951 | #define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
952 | #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c7 |
953 | #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
954 | #define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c8 |
955 | #define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
956 | #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c9 |
957 | #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
958 | #define regDAGB3_WR_DATA_DAGB 0x01ca |
959 | #define regDAGB3_WR_DATA_DAGB_BASE_IDX 0 |
960 | #define regDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01cb |
961 | #define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
962 | #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01cc |
963 | #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
964 | #define regDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cd |
965 | #define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
966 | #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01ce |
967 | #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
968 | #define regDAGB3_WR_VC0_CNTL 0x01cf |
969 | #define regDAGB3_WR_VC0_CNTL_BASE_IDX 0 |
970 | #define regDAGB3_WR_VC1_CNTL 0x01d0 |
971 | #define regDAGB3_WR_VC1_CNTL_BASE_IDX 0 |
972 | #define regDAGB3_WR_VC2_CNTL 0x01d1 |
973 | #define regDAGB3_WR_VC2_CNTL_BASE_IDX 0 |
974 | #define regDAGB3_WR_VC3_CNTL 0x01d2 |
975 | #define regDAGB3_WR_VC3_CNTL_BASE_IDX 0 |
976 | #define regDAGB3_WR_VC4_CNTL 0x01d3 |
977 | #define regDAGB3_WR_VC4_CNTL_BASE_IDX 0 |
978 | #define regDAGB3_WR_VC5_CNTL 0x01d4 |
979 | #define regDAGB3_WR_VC5_CNTL_BASE_IDX 0 |
980 | #define regDAGB3_WR_VC6_CNTL 0x01d5 |
981 | #define regDAGB3_WR_VC6_CNTL_BASE_IDX 0 |
982 | #define regDAGB3_WR_VC7_CNTL 0x01d6 |
983 | #define regDAGB3_WR_VC7_CNTL_BASE_IDX 0 |
984 | #define regDAGB3_WR_CNTL_MISC 0x01d7 |
985 | #define regDAGB3_WR_CNTL_MISC_BASE_IDX 0 |
986 | #define regDAGB3_WR_TLB_CREDIT 0x01d8 |
987 | #define regDAGB3_WR_TLB_CREDIT_BASE_IDX 0 |
988 | #define regDAGB3_WR_DATA_CREDIT 0x01d9 |
989 | #define regDAGB3_WR_DATA_CREDIT_BASE_IDX 0 |
990 | #define regDAGB3_WR_MISC_CREDIT 0x01da |
991 | #define regDAGB3_WR_MISC_CREDIT_BASE_IDX 0 |
992 | #define regDAGB3_WR_OSD_CREDIT_CNTL1 0x01db |
993 | #define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
994 | #define regDAGB3_WR_OSD_CREDIT_CNTL2 0x01dc |
995 | #define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
996 | #define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x01dd |
997 | #define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
998 | #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01de |
999 | #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
1000 | #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01df |
1001 | #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
1002 | #define regDAGB3_WRCLI_ASK_PENDING 0x01e0 |
1003 | #define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX 0 |
1004 | #define regDAGB3_WRCLI_GO_PENDING 0x01e1 |
1005 | #define regDAGB3_WRCLI_GO_PENDING_BASE_IDX 0 |
1006 | #define regDAGB3_WRCLI_GBLSEND_PENDING 0x01e2 |
1007 | #define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
1008 | #define regDAGB3_WRCLI_TLB_PENDING 0x01e3 |
1009 | #define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX 0 |
1010 | #define regDAGB3_WRCLI_OARB_PENDING 0x01e4 |
1011 | #define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX 0 |
1012 | #define regDAGB3_WRCLI_OSD_PENDING 0x01e5 |
1013 | #define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX 0 |
1014 | #define regDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e6 |
1015 | #define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
1016 | #define regDAGB3_WRCLI_DBUS_GO_PENDING 0x01e7 |
1017 | #define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
1018 | #define regDAGB3_DAGB_DLY 0x01e8 |
1019 | #define regDAGB3_DAGB_DLY_BASE_IDX 0 |
1020 | #define regDAGB3_CNTL_MISC 0x01e9 |
1021 | #define regDAGB3_CNTL_MISC_BASE_IDX 0 |
1022 | #define regDAGB3_CNTL_MISC2 0x01ea |
1023 | #define regDAGB3_CNTL_MISC2_BASE_IDX 0 |
1024 | #define regDAGB3_FATAL_ERROR_CNTL 0x01eb |
1025 | #define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX 0 |
1026 | #define regDAGB3_FATAL_ERROR_CLEAR 0x01ec |
1027 | #define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX 0 |
1028 | #define regDAGB3_FATAL_ERROR_STATUS0 0x01ed |
1029 | #define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX 0 |
1030 | #define regDAGB3_FATAL_ERROR_STATUS1 0x01ee |
1031 | #define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX 0 |
1032 | #define regDAGB3_FATAL_ERROR_STATUS2 0x01ef |
1033 | #define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX 0 |
1034 | #define regDAGB3_FATAL_ERROR_STATUS3 0x01f0 |
1035 | #define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX 0 |
1036 | #define regDAGB3_FIFO_EMPTY 0x01f1 |
1037 | #define regDAGB3_FIFO_EMPTY_BASE_IDX 0 |
1038 | #define regDAGB3_FIFO_FULL 0x01f2 |
1039 | #define regDAGB3_FIFO_FULL_BASE_IDX 0 |
1040 | #define regDAGB3_WR_CREDITS_FULL 0x01f3 |
1041 | #define regDAGB3_WR_CREDITS_FULL_BASE_IDX 0 |
1042 | #define regDAGB3_RD_CREDITS_FULL 0x01f4 |
1043 | #define regDAGB3_RD_CREDITS_FULL_BASE_IDX 0 |
1044 | #define regDAGB3_PERFCOUNTER_LO 0x01f5 |
1045 | #define regDAGB3_PERFCOUNTER_LO_BASE_IDX 0 |
1046 | #define regDAGB3_PERFCOUNTER_HI 0x01f6 |
1047 | #define regDAGB3_PERFCOUNTER_HI_BASE_IDX 0 |
1048 | #define regDAGB3_PERFCOUNTER0_CFG 0x01f7 |
1049 | #define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX 0 |
1050 | #define regDAGB3_PERFCOUNTER1_CFG 0x01f8 |
1051 | #define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX 0 |
1052 | #define regDAGB3_PERFCOUNTER2_CFG 0x01f9 |
1053 | #define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX 0 |
1054 | #define regDAGB3_PERFCOUNTER_RSLT_CNTL 0x01fa |
1055 | #define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
1056 | #define regDAGB3_L1TLB_REG_RW 0x01fb |
1057 | #define regDAGB3_L1TLB_REG_RW_BASE_IDX 0 |
1058 | #define regDAGB3_RESERVE1 0x01fc |
1059 | #define regDAGB3_RESERVE1_BASE_IDX 0 |
1060 | #define regDAGB3_RESERVE2 0x01fd |
1061 | #define regDAGB3_RESERVE2_BASE_IDX 0 |
1062 | #define regDAGB3_RESERVE3 0x01fe |
1063 | #define regDAGB3_RESERVE3_BASE_IDX 0 |
1064 | #define regDAGB3_RESERVE4 0x01ff |
1065 | #define regDAGB3_RESERVE4_BASE_IDX 0 |
1066 | |
1067 | |
1068 | // addressBlock: mmhub_dagb_dagbdec4 |
1069 | // base address: 0x68800 |
1070 | #define regDAGB4_RDCLI0 0x0200 |
1071 | #define regDAGB4_RDCLI0_BASE_IDX 0 |
1072 | #define regDAGB4_RDCLI1 0x0201 |
1073 | #define regDAGB4_RDCLI1_BASE_IDX 0 |
1074 | #define regDAGB4_RDCLI2 0x0202 |
1075 | #define regDAGB4_RDCLI2_BASE_IDX 0 |
1076 | #define regDAGB4_RDCLI3 0x0203 |
1077 | #define regDAGB4_RDCLI3_BASE_IDX 0 |
1078 | #define regDAGB4_RDCLI4 0x0204 |
1079 | #define regDAGB4_RDCLI4_BASE_IDX 0 |
1080 | #define regDAGB4_RDCLI5 0x0205 |
1081 | #define regDAGB4_RDCLI5_BASE_IDX 0 |
1082 | #define regDAGB4_RDCLI6 0x0206 |
1083 | #define regDAGB4_RDCLI6_BASE_IDX 0 |
1084 | #define regDAGB4_RDCLI7 0x0207 |
1085 | #define regDAGB4_RDCLI7_BASE_IDX 0 |
1086 | #define regDAGB4_RDCLI8 0x0208 |
1087 | #define regDAGB4_RDCLI8_BASE_IDX 0 |
1088 | #define regDAGB4_RDCLI9 0x0209 |
1089 | #define regDAGB4_RDCLI9_BASE_IDX 0 |
1090 | #define regDAGB4_RDCLI10 0x020a |
1091 | #define regDAGB4_RDCLI10_BASE_IDX 0 |
1092 | #define regDAGB4_RDCLI11 0x020b |
1093 | #define regDAGB4_RDCLI11_BASE_IDX 0 |
1094 | #define regDAGB4_RDCLI12 0x020c |
1095 | #define regDAGB4_RDCLI12_BASE_IDX 0 |
1096 | #define regDAGB4_RDCLI13 0x020d |
1097 | #define regDAGB4_RDCLI13_BASE_IDX 0 |
1098 | #define regDAGB4_RDCLI14 0x020e |
1099 | #define regDAGB4_RDCLI14_BASE_IDX 0 |
1100 | #define regDAGB4_RDCLI15 0x020f |
1101 | #define regDAGB4_RDCLI15_BASE_IDX 0 |
1102 | #define regDAGB4_RD_CNTL 0x0210 |
1103 | #define regDAGB4_RD_CNTL_BASE_IDX 0 |
1104 | #define regDAGB4_RD_GMI_CNTL 0x0211 |
1105 | #define regDAGB4_RD_GMI_CNTL_BASE_IDX 0 |
1106 | #define regDAGB4_RD_ADDR_DAGB 0x0212 |
1107 | #define regDAGB4_RD_ADDR_DAGB_BASE_IDX 0 |
1108 | #define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 |
1109 | #define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
1110 | #define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 |
1111 | #define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
1112 | #define regDAGB4_RD_CGTT_CLK_CTRL 0x0215 |
1113 | #define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1114 | #define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 |
1115 | #define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1116 | #define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 |
1117 | #define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1118 | #define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 |
1119 | #define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
1120 | #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 |
1121 | #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1122 | #define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a |
1123 | #define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
1124 | #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b |
1125 | #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1126 | #define regDAGB4_RD_VC0_CNTL 0x021c |
1127 | #define regDAGB4_RD_VC0_CNTL_BASE_IDX 0 |
1128 | #define regDAGB4_RD_VC1_CNTL 0x021d |
1129 | #define regDAGB4_RD_VC1_CNTL_BASE_IDX 0 |
1130 | #define regDAGB4_RD_VC2_CNTL 0x021e |
1131 | #define regDAGB4_RD_VC2_CNTL_BASE_IDX 0 |
1132 | #define regDAGB4_RD_VC3_CNTL 0x021f |
1133 | #define regDAGB4_RD_VC3_CNTL_BASE_IDX 0 |
1134 | #define regDAGB4_RD_VC4_CNTL 0x0220 |
1135 | #define regDAGB4_RD_VC4_CNTL_BASE_IDX 0 |
1136 | #define regDAGB4_RD_VC5_CNTL 0x0221 |
1137 | #define regDAGB4_RD_VC5_CNTL_BASE_IDX 0 |
1138 | #define regDAGB4_RD_VC6_CNTL 0x0222 |
1139 | #define regDAGB4_RD_VC6_CNTL_BASE_IDX 0 |
1140 | #define regDAGB4_RD_VC7_CNTL 0x0223 |
1141 | #define regDAGB4_RD_VC7_CNTL_BASE_IDX 0 |
1142 | #define regDAGB4_RD_CNTL_MISC 0x0224 |
1143 | #define regDAGB4_RD_CNTL_MISC_BASE_IDX 0 |
1144 | #define regDAGB4_RD_TLB_CREDIT 0x0225 |
1145 | #define regDAGB4_RD_TLB_CREDIT_BASE_IDX 0 |
1146 | #define regDAGB4_RD_RDRET_CREDIT_CNTL 0x0226 |
1147 | #define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
1148 | #define regDAGB4_RD_RDRET_CREDIT_CNTL2 0x0227 |
1149 | #define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
1150 | #define regDAGB4_RDCLI_ASK_PENDING 0x0228 |
1151 | #define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX 0 |
1152 | #define regDAGB4_RDCLI_GO_PENDING 0x0229 |
1153 | #define regDAGB4_RDCLI_GO_PENDING_BASE_IDX 0 |
1154 | #define regDAGB4_RDCLI_GBLSEND_PENDING 0x022a |
1155 | #define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
1156 | #define regDAGB4_RDCLI_TLB_PENDING 0x022b |
1157 | #define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX 0 |
1158 | #define regDAGB4_RDCLI_OARB_PENDING 0x022c |
1159 | #define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX 0 |
1160 | #define regDAGB4_RDCLI_OSD_PENDING 0x022d |
1161 | #define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX 0 |
1162 | #define regDAGB4_WRCLI0 0x022e |
1163 | #define regDAGB4_WRCLI0_BASE_IDX 0 |
1164 | #define regDAGB4_WRCLI1 0x022f |
1165 | #define regDAGB4_WRCLI1_BASE_IDX 0 |
1166 | #define regDAGB4_WRCLI2 0x0230 |
1167 | #define regDAGB4_WRCLI2_BASE_IDX 0 |
1168 | #define regDAGB4_WRCLI3 0x0231 |
1169 | #define regDAGB4_WRCLI3_BASE_IDX 0 |
1170 | #define regDAGB4_WRCLI4 0x0232 |
1171 | #define regDAGB4_WRCLI4_BASE_IDX 0 |
1172 | #define regDAGB4_WRCLI5 0x0233 |
1173 | #define regDAGB4_WRCLI5_BASE_IDX 0 |
1174 | #define regDAGB4_WRCLI6 0x0234 |
1175 | #define regDAGB4_WRCLI6_BASE_IDX 0 |
1176 | #define regDAGB4_WRCLI7 0x0235 |
1177 | #define regDAGB4_WRCLI7_BASE_IDX 0 |
1178 | #define regDAGB4_WRCLI8 0x0236 |
1179 | #define regDAGB4_WRCLI8_BASE_IDX 0 |
1180 | #define regDAGB4_WRCLI9 0x0237 |
1181 | #define regDAGB4_WRCLI9_BASE_IDX 0 |
1182 | #define regDAGB4_WRCLI10 0x0238 |
1183 | #define regDAGB4_WRCLI10_BASE_IDX 0 |
1184 | #define regDAGB4_WRCLI11 0x0239 |
1185 | #define regDAGB4_WRCLI11_BASE_IDX 0 |
1186 | #define regDAGB4_WRCLI12 0x023a |
1187 | #define regDAGB4_WRCLI12_BASE_IDX 0 |
1188 | #define regDAGB4_WRCLI13 0x023b |
1189 | #define regDAGB4_WRCLI13_BASE_IDX 0 |
1190 | #define regDAGB4_WRCLI14 0x023c |
1191 | #define regDAGB4_WRCLI14_BASE_IDX 0 |
1192 | #define regDAGB4_WRCLI15 0x023d |
1193 | #define regDAGB4_WRCLI15_BASE_IDX 0 |
1194 | #define regDAGB4_WR_CNTL 0x023e |
1195 | #define regDAGB4_WR_CNTL_BASE_IDX 0 |
1196 | #define regDAGB4_WR_GMI_CNTL 0x023f |
1197 | #define regDAGB4_WR_GMI_CNTL_BASE_IDX 0 |
1198 | #define regDAGB4_WR_ADDR_DAGB 0x0240 |
1199 | #define regDAGB4_WR_ADDR_DAGB_BASE_IDX 0 |
1200 | #define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x0241 |
1201 | #define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
1202 | #define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0242 |
1203 | #define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
1204 | #define regDAGB4_WR_CGTT_CLK_CTRL 0x0243 |
1205 | #define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1206 | #define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0244 |
1207 | #define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1208 | #define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0245 |
1209 | #define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1210 | #define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0246 |
1211 | #define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
1212 | #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0247 |
1213 | #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1214 | #define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0248 |
1215 | #define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
1216 | #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0249 |
1217 | #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1218 | #define regDAGB4_WR_DATA_DAGB 0x024a |
1219 | #define regDAGB4_WR_DATA_DAGB_BASE_IDX 0 |
1220 | #define regDAGB4_WR_DATA_DAGB_MAX_BURST0 0x024b |
1221 | #define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
1222 | #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024c |
1223 | #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1224 | #define regDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024d |
1225 | #define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
1226 | #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024e |
1227 | #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1228 | #define regDAGB4_WR_VC0_CNTL 0x024f |
1229 | #define regDAGB4_WR_VC0_CNTL_BASE_IDX 0 |
1230 | #define regDAGB4_WR_VC1_CNTL 0x0250 |
1231 | #define regDAGB4_WR_VC1_CNTL_BASE_IDX 0 |
1232 | #define regDAGB4_WR_VC2_CNTL 0x0251 |
1233 | #define regDAGB4_WR_VC2_CNTL_BASE_IDX 0 |
1234 | #define regDAGB4_WR_VC3_CNTL 0x0252 |
1235 | #define regDAGB4_WR_VC3_CNTL_BASE_IDX 0 |
1236 | #define regDAGB4_WR_VC4_CNTL 0x0253 |
1237 | #define regDAGB4_WR_VC4_CNTL_BASE_IDX 0 |
1238 | #define regDAGB4_WR_VC5_CNTL 0x0254 |
1239 | #define regDAGB4_WR_VC5_CNTL_BASE_IDX 0 |
1240 | #define regDAGB4_WR_VC6_CNTL 0x0255 |
1241 | #define regDAGB4_WR_VC6_CNTL_BASE_IDX 0 |
1242 | #define regDAGB4_WR_VC7_CNTL 0x0256 |
1243 | #define regDAGB4_WR_VC7_CNTL_BASE_IDX 0 |
1244 | #define regDAGB4_WR_CNTL_MISC 0x0257 |
1245 | #define regDAGB4_WR_CNTL_MISC_BASE_IDX 0 |
1246 | #define regDAGB4_WR_TLB_CREDIT 0x0258 |
1247 | #define regDAGB4_WR_TLB_CREDIT_BASE_IDX 0 |
1248 | #define regDAGB4_WR_DATA_CREDIT 0x0259 |
1249 | #define regDAGB4_WR_DATA_CREDIT_BASE_IDX 0 |
1250 | #define regDAGB4_WR_MISC_CREDIT 0x025a |
1251 | #define regDAGB4_WR_MISC_CREDIT_BASE_IDX 0 |
1252 | #define regDAGB4_WR_OSD_CREDIT_CNTL1 0x025b |
1253 | #define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
1254 | #define regDAGB4_WR_OSD_CREDIT_CNTL2 0x025c |
1255 | #define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
1256 | #define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x025d |
1257 | #define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
1258 | #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025e |
1259 | #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
1260 | #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025f |
1261 | #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
1262 | #define regDAGB4_WRCLI_ASK_PENDING 0x0260 |
1263 | #define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX 0 |
1264 | #define regDAGB4_WRCLI_GO_PENDING 0x0261 |
1265 | #define regDAGB4_WRCLI_GO_PENDING_BASE_IDX 0 |
1266 | #define regDAGB4_WRCLI_GBLSEND_PENDING 0x0262 |
1267 | #define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
1268 | #define regDAGB4_WRCLI_TLB_PENDING 0x0263 |
1269 | #define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX 0 |
1270 | #define regDAGB4_WRCLI_OARB_PENDING 0x0264 |
1271 | #define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX 0 |
1272 | #define regDAGB4_WRCLI_OSD_PENDING 0x0265 |
1273 | #define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX 0 |
1274 | #define regDAGB4_WRCLI_DBUS_ASK_PENDING 0x0266 |
1275 | #define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
1276 | #define regDAGB4_WRCLI_DBUS_GO_PENDING 0x0267 |
1277 | #define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
1278 | #define regDAGB4_DAGB_DLY 0x0268 |
1279 | #define regDAGB4_DAGB_DLY_BASE_IDX 0 |
1280 | #define regDAGB4_CNTL_MISC 0x0269 |
1281 | #define regDAGB4_CNTL_MISC_BASE_IDX 0 |
1282 | #define regDAGB4_CNTL_MISC2 0x026a |
1283 | #define regDAGB4_CNTL_MISC2_BASE_IDX 0 |
1284 | #define regDAGB4_FATAL_ERROR_CNTL 0x026b |
1285 | #define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX 0 |
1286 | #define regDAGB4_FATAL_ERROR_CLEAR 0x026c |
1287 | #define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX 0 |
1288 | #define regDAGB4_FATAL_ERROR_STATUS0 0x026d |
1289 | #define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX 0 |
1290 | #define regDAGB4_FATAL_ERROR_STATUS1 0x026e |
1291 | #define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX 0 |
1292 | #define regDAGB4_FATAL_ERROR_STATUS2 0x026f |
1293 | #define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX 0 |
1294 | #define regDAGB4_FATAL_ERROR_STATUS3 0x0270 |
1295 | #define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX 0 |
1296 | #define regDAGB4_FIFO_EMPTY 0x0271 |
1297 | #define regDAGB4_FIFO_EMPTY_BASE_IDX 0 |
1298 | #define regDAGB4_FIFO_FULL 0x0272 |
1299 | #define regDAGB4_FIFO_FULL_BASE_IDX 0 |
1300 | #define regDAGB4_WR_CREDITS_FULL 0x0273 |
1301 | #define regDAGB4_WR_CREDITS_FULL_BASE_IDX 0 |
1302 | #define regDAGB4_RD_CREDITS_FULL 0x0274 |
1303 | #define regDAGB4_RD_CREDITS_FULL_BASE_IDX 0 |
1304 | #define regDAGB4_PERFCOUNTER_LO 0x0275 |
1305 | #define regDAGB4_PERFCOUNTER_LO_BASE_IDX 0 |
1306 | #define regDAGB4_PERFCOUNTER_HI 0x0276 |
1307 | #define regDAGB4_PERFCOUNTER_HI_BASE_IDX 0 |
1308 | #define regDAGB4_PERFCOUNTER0_CFG 0x0277 |
1309 | #define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX 0 |
1310 | #define regDAGB4_PERFCOUNTER1_CFG 0x0278 |
1311 | #define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX 0 |
1312 | #define regDAGB4_PERFCOUNTER2_CFG 0x0279 |
1313 | #define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX 0 |
1314 | #define regDAGB4_PERFCOUNTER_RSLT_CNTL 0x027a |
1315 | #define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
1316 | #define regDAGB4_L1TLB_REG_RW 0x027b |
1317 | #define regDAGB4_L1TLB_REG_RW_BASE_IDX 0 |
1318 | #define regDAGB4_RESERVE1 0x027c |
1319 | #define regDAGB4_RESERVE1_BASE_IDX 0 |
1320 | #define regDAGB4_RESERVE2 0x027d |
1321 | #define regDAGB4_RESERVE2_BASE_IDX 0 |
1322 | #define regDAGB4_RESERVE3 0x027e |
1323 | #define regDAGB4_RESERVE3_BASE_IDX 0 |
1324 | #define regDAGB4_RESERVE4 0x027f |
1325 | #define regDAGB4_RESERVE4_BASE_IDX 0 |
1326 | |
1327 | |
1328 | // addressBlock: mmhub_dagb_dagbdec5 |
1329 | // base address: 0x68a00 |
1330 | #define regDAGB5_RDCLI0 0x0280 |
1331 | #define regDAGB5_RDCLI0_BASE_IDX 0 |
1332 | #define regDAGB5_RDCLI1 0x0281 |
1333 | #define regDAGB5_RDCLI1_BASE_IDX 0 |
1334 | #define regDAGB5_RDCLI2 0x0282 |
1335 | #define regDAGB5_RDCLI2_BASE_IDX 0 |
1336 | #define regDAGB5_RDCLI3 0x0283 |
1337 | #define regDAGB5_RDCLI3_BASE_IDX 0 |
1338 | #define regDAGB5_RDCLI4 0x0284 |
1339 | #define regDAGB5_RDCLI4_BASE_IDX 0 |
1340 | #define regDAGB5_RDCLI5 0x0285 |
1341 | #define regDAGB5_RDCLI5_BASE_IDX 0 |
1342 | #define regDAGB5_RDCLI6 0x0286 |
1343 | #define regDAGB5_RDCLI6_BASE_IDX 0 |
1344 | #define regDAGB5_RDCLI7 0x0287 |
1345 | #define regDAGB5_RDCLI7_BASE_IDX 0 |
1346 | #define regDAGB5_RDCLI8 0x0288 |
1347 | #define regDAGB5_RDCLI8_BASE_IDX 0 |
1348 | #define regDAGB5_RDCLI9 0x0289 |
1349 | #define regDAGB5_RDCLI9_BASE_IDX 0 |
1350 | #define regDAGB5_RDCLI10 0x028a |
1351 | #define regDAGB5_RDCLI10_BASE_IDX 0 |
1352 | #define regDAGB5_RDCLI11 0x028b |
1353 | #define regDAGB5_RDCLI11_BASE_IDX 0 |
1354 | #define regDAGB5_RDCLI12 0x028c |
1355 | #define regDAGB5_RDCLI12_BASE_IDX 0 |
1356 | #define regDAGB5_RDCLI13 0x028d |
1357 | #define regDAGB5_RDCLI13_BASE_IDX 0 |
1358 | #define regDAGB5_RDCLI14 0x028e |
1359 | #define regDAGB5_RDCLI14_BASE_IDX 0 |
1360 | #define regDAGB5_RDCLI15 0x028f |
1361 | #define regDAGB5_RDCLI15_BASE_IDX 0 |
1362 | #define regDAGB5_RD_CNTL 0x0290 |
1363 | #define regDAGB5_RD_CNTL_BASE_IDX 0 |
1364 | #define regDAGB5_RD_GMI_CNTL 0x0291 |
1365 | #define regDAGB5_RD_GMI_CNTL_BASE_IDX 0 |
1366 | #define regDAGB5_RD_ADDR_DAGB 0x0292 |
1367 | #define regDAGB5_RD_ADDR_DAGB_BASE_IDX 0 |
1368 | #define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x0293 |
1369 | #define regDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
1370 | #define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x0294 |
1371 | #define regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
1372 | #define regDAGB5_RD_CGTT_CLK_CTRL 0x0295 |
1373 | #define regDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1374 | #define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x0296 |
1375 | #define regDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1376 | #define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x0297 |
1377 | #define regDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 |
1378 | #define regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x0298 |
1379 | #define regDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
1380 | #define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x0299 |
1381 | #define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1382 | #define regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x029a |
1383 | #define regDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
1384 | #define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x029b |
1385 | #define regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1386 | #define regDAGB5_RD_VC0_CNTL 0x029c |
1387 | #define regDAGB5_RD_VC0_CNTL_BASE_IDX 0 |
1388 | #define regDAGB5_RD_VC1_CNTL 0x029d |
1389 | #define regDAGB5_RD_VC1_CNTL_BASE_IDX 0 |
1390 | #define regDAGB5_RD_VC2_CNTL 0x029e |
1391 | #define regDAGB5_RD_VC2_CNTL_BASE_IDX 0 |
1392 | #define regDAGB5_RD_VC3_CNTL 0x029f |
1393 | #define regDAGB5_RD_VC3_CNTL_BASE_IDX 0 |
1394 | #define regDAGB5_RD_VC4_CNTL 0x02a0 |
1395 | #define regDAGB5_RD_VC4_CNTL_BASE_IDX 0 |
1396 | #define regDAGB5_RD_VC5_CNTL 0x02a1 |
1397 | #define regDAGB5_RD_VC5_CNTL_BASE_IDX 0 |
1398 | #define regDAGB5_RD_VC6_CNTL 0x02a2 |
1399 | #define regDAGB5_RD_VC6_CNTL_BASE_IDX 0 |
1400 | #define regDAGB5_RD_VC7_CNTL 0x02a3 |
1401 | #define regDAGB5_RD_VC7_CNTL_BASE_IDX 0 |
1402 | #define regDAGB5_RD_CNTL_MISC 0x02a4 |
1403 | #define regDAGB5_RD_CNTL_MISC_BASE_IDX 0 |
1404 | #define regDAGB5_RD_TLB_CREDIT 0x02a5 |
1405 | #define regDAGB5_RD_TLB_CREDIT_BASE_IDX 0 |
1406 | #define regDAGB5_RD_RDRET_CREDIT_CNTL 0x02a6 |
1407 | #define regDAGB5_RD_RDRET_CREDIT_CNTL_BASE_IDX 0 |
1408 | #define regDAGB5_RD_RDRET_CREDIT_CNTL2 0x02a7 |
1409 | #define regDAGB5_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0 |
1410 | #define regDAGB5_RDCLI_ASK_PENDING 0x02a8 |
1411 | #define regDAGB5_RDCLI_ASK_PENDING_BASE_IDX 0 |
1412 | #define regDAGB5_RDCLI_GO_PENDING 0x02a9 |
1413 | #define regDAGB5_RDCLI_GO_PENDING_BASE_IDX 0 |
1414 | #define regDAGB5_RDCLI_GBLSEND_PENDING 0x02aa |
1415 | #define regDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 0 |
1416 | #define regDAGB5_RDCLI_TLB_PENDING 0x02ab |
1417 | #define regDAGB5_RDCLI_TLB_PENDING_BASE_IDX 0 |
1418 | #define regDAGB5_RDCLI_OARB_PENDING 0x02ac |
1419 | #define regDAGB5_RDCLI_OARB_PENDING_BASE_IDX 0 |
1420 | #define regDAGB5_RDCLI_OSD_PENDING 0x02ad |
1421 | #define regDAGB5_RDCLI_OSD_PENDING_BASE_IDX 0 |
1422 | #define regDAGB5_WRCLI0 0x02ae |
1423 | #define regDAGB5_WRCLI0_BASE_IDX 0 |
1424 | #define regDAGB5_WRCLI1 0x02af |
1425 | #define regDAGB5_WRCLI1_BASE_IDX 0 |
1426 | #define regDAGB5_WRCLI2 0x02b0 |
1427 | #define regDAGB5_WRCLI2_BASE_IDX 0 |
1428 | #define regDAGB5_WRCLI3 0x02b1 |
1429 | #define regDAGB5_WRCLI3_BASE_IDX 0 |
1430 | #define regDAGB5_WRCLI4 0x02b2 |
1431 | #define regDAGB5_WRCLI4_BASE_IDX 0 |
1432 | #define regDAGB5_WRCLI5 0x02b3 |
1433 | #define regDAGB5_WRCLI5_BASE_IDX 0 |
1434 | #define regDAGB5_WRCLI6 0x02b4 |
1435 | #define regDAGB5_WRCLI6_BASE_IDX 0 |
1436 | #define regDAGB5_WRCLI7 0x02b5 |
1437 | #define regDAGB5_WRCLI7_BASE_IDX 0 |
1438 | #define regDAGB5_WRCLI8 0x02b6 |
1439 | #define regDAGB5_WRCLI8_BASE_IDX 0 |
1440 | #define regDAGB5_WRCLI9 0x02b7 |
1441 | #define regDAGB5_WRCLI9_BASE_IDX 0 |
1442 | #define regDAGB5_WRCLI10 0x02b8 |
1443 | #define regDAGB5_WRCLI10_BASE_IDX 0 |
1444 | #define regDAGB5_WRCLI11 0x02b9 |
1445 | #define regDAGB5_WRCLI11_BASE_IDX 0 |
1446 | #define regDAGB5_WRCLI12 0x02ba |
1447 | #define regDAGB5_WRCLI12_BASE_IDX 0 |
1448 | #define regDAGB5_WRCLI13 0x02bb |
1449 | #define regDAGB5_WRCLI13_BASE_IDX 0 |
1450 | #define regDAGB5_WRCLI14 0x02bc |
1451 | #define regDAGB5_WRCLI14_BASE_IDX 0 |
1452 | #define regDAGB5_WRCLI15 0x02bd |
1453 | #define regDAGB5_WRCLI15_BASE_IDX 0 |
1454 | #define regDAGB5_WR_CNTL 0x02be |
1455 | #define regDAGB5_WR_CNTL_BASE_IDX 0 |
1456 | #define regDAGB5_WR_GMI_CNTL 0x02bf |
1457 | #define regDAGB5_WR_GMI_CNTL_BASE_IDX 0 |
1458 | #define regDAGB5_WR_ADDR_DAGB 0x02c0 |
1459 | #define regDAGB5_WR_ADDR_DAGB_BASE_IDX 0 |
1460 | #define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x02c1 |
1461 | #define regDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 |
1462 | #define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x02c2 |
1463 | #define regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 |
1464 | #define regDAGB5_WR_CGTT_CLK_CTRL 0x02c3 |
1465 | #define regDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1466 | #define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x02c4 |
1467 | #define regDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1468 | #define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x02c5 |
1469 | #define regDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 |
1470 | #define regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x02c6 |
1471 | #define regDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 |
1472 | #define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x02c7 |
1473 | #define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1474 | #define regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x02c8 |
1475 | #define regDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 |
1476 | #define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x02c9 |
1477 | #define regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1478 | #define regDAGB5_WR_DATA_DAGB 0x02ca |
1479 | #define regDAGB5_WR_DATA_DAGB_BASE_IDX 0 |
1480 | #define regDAGB5_WR_DATA_DAGB_MAX_BURST0 0x02cb |
1481 | #define regDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 |
1482 | #define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x02cc |
1483 | #define regDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 |
1484 | #define regDAGB5_WR_DATA_DAGB_MAX_BURST1 0x02cd |
1485 | #define regDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 |
1486 | #define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x02ce |
1487 | #define regDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 |
1488 | #define regDAGB5_WR_VC0_CNTL 0x02cf |
1489 | #define regDAGB5_WR_VC0_CNTL_BASE_IDX 0 |
1490 | #define regDAGB5_WR_VC1_CNTL 0x02d0 |
1491 | #define regDAGB5_WR_VC1_CNTL_BASE_IDX 0 |
1492 | #define regDAGB5_WR_VC2_CNTL 0x02d1 |
1493 | #define regDAGB5_WR_VC2_CNTL_BASE_IDX 0 |
1494 | #define regDAGB5_WR_VC3_CNTL 0x02d2 |
1495 | #define regDAGB5_WR_VC3_CNTL_BASE_IDX 0 |
1496 | #define regDAGB5_WR_VC4_CNTL 0x02d3 |
1497 | #define regDAGB5_WR_VC4_CNTL_BASE_IDX 0 |
1498 | #define regDAGB5_WR_VC5_CNTL 0x02d4 |
1499 | #define regDAGB5_WR_VC5_CNTL_BASE_IDX 0 |
1500 | #define regDAGB5_WR_VC6_CNTL 0x02d5 |
1501 | #define regDAGB5_WR_VC6_CNTL_BASE_IDX 0 |
1502 | #define regDAGB5_WR_VC7_CNTL 0x02d6 |
1503 | #define regDAGB5_WR_VC7_CNTL_BASE_IDX 0 |
1504 | #define regDAGB5_WR_CNTL_MISC 0x02d7 |
1505 | #define regDAGB5_WR_CNTL_MISC_BASE_IDX 0 |
1506 | #define regDAGB5_WR_TLB_CREDIT 0x02d8 |
1507 | #define regDAGB5_WR_TLB_CREDIT_BASE_IDX 0 |
1508 | #define regDAGB5_WR_DATA_CREDIT 0x02d9 |
1509 | #define regDAGB5_WR_DATA_CREDIT_BASE_IDX 0 |
1510 | #define regDAGB5_WR_MISC_CREDIT 0x02da |
1511 | #define regDAGB5_WR_MISC_CREDIT_BASE_IDX 0 |
1512 | #define regDAGB5_WR_OSD_CREDIT_CNTL1 0x02db |
1513 | #define regDAGB5_WR_OSD_CREDIT_CNTL1_BASE_IDX 0 |
1514 | #define regDAGB5_WR_OSD_CREDIT_CNTL2 0x02dc |
1515 | #define regDAGB5_WR_OSD_CREDIT_CNTL2_BASE_IDX 0 |
1516 | #define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x02dd |
1517 | #define regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0 |
1518 | #define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x02de |
1519 | #define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 |
1520 | #define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x02df |
1521 | #define regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 |
1522 | #define regDAGB5_WRCLI_ASK_PENDING 0x02e0 |
1523 | #define regDAGB5_WRCLI_ASK_PENDING_BASE_IDX 0 |
1524 | #define regDAGB5_WRCLI_GO_PENDING 0x02e1 |
1525 | #define regDAGB5_WRCLI_GO_PENDING_BASE_IDX 0 |
1526 | #define regDAGB5_WRCLI_GBLSEND_PENDING 0x02e2 |
1527 | #define regDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 0 |
1528 | #define regDAGB5_WRCLI_TLB_PENDING 0x02e3 |
1529 | #define regDAGB5_WRCLI_TLB_PENDING_BASE_IDX 0 |
1530 | #define regDAGB5_WRCLI_OARB_PENDING 0x02e4 |
1531 | #define regDAGB5_WRCLI_OARB_PENDING_BASE_IDX 0 |
1532 | #define regDAGB5_WRCLI_OSD_PENDING 0x02e5 |
1533 | #define regDAGB5_WRCLI_OSD_PENDING_BASE_IDX 0 |
1534 | #define regDAGB5_WRCLI_DBUS_ASK_PENDING 0x02e6 |
1535 | #define regDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 |
1536 | #define regDAGB5_WRCLI_DBUS_GO_PENDING 0x02e7 |
1537 | #define regDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 |
1538 | #define regDAGB5_DAGB_DLY 0x02e8 |
1539 | #define regDAGB5_DAGB_DLY_BASE_IDX 0 |
1540 | #define regDAGB5_CNTL_MISC 0x02e9 |
1541 | #define regDAGB5_CNTL_MISC_BASE_IDX 0 |
1542 | #define regDAGB5_CNTL_MISC2 0x02ea |
1543 | #define regDAGB5_CNTL_MISC2_BASE_IDX 0 |
1544 | #define regDAGB5_FATAL_ERROR_CNTL 0x02eb |
1545 | #define regDAGB5_FATAL_ERROR_CNTL_BASE_IDX 0 |
1546 | #define regDAGB5_FATAL_ERROR_CLEAR 0x02ec |
1547 | #define regDAGB5_FATAL_ERROR_CLEAR_BASE_IDX 0 |
1548 | #define regDAGB5_FATAL_ERROR_STATUS0 0x02ed |
1549 | #define regDAGB5_FATAL_ERROR_STATUS0_BASE_IDX 0 |
1550 | #define regDAGB5_FATAL_ERROR_STATUS1 0x02ee |
1551 | #define regDAGB5_FATAL_ERROR_STATUS1_BASE_IDX 0 |
1552 | #define regDAGB5_FATAL_ERROR_STATUS2 0x02ef |
1553 | #define regDAGB5_FATAL_ERROR_STATUS2_BASE_IDX 0 |
1554 | #define regDAGB5_FATAL_ERROR_STATUS3 0x02f0 |
1555 | #define regDAGB5_FATAL_ERROR_STATUS3_BASE_IDX 0 |
1556 | #define regDAGB5_FIFO_EMPTY 0x02f1 |
1557 | #define regDAGB5_FIFO_EMPTY_BASE_IDX 0 |
1558 | #define regDAGB5_FIFO_FULL 0x02f2 |
1559 | #define regDAGB5_FIFO_FULL_BASE_IDX 0 |
1560 | #define regDAGB5_WR_CREDITS_FULL 0x02f3 |
1561 | #define regDAGB5_WR_CREDITS_FULL_BASE_IDX 0 |
1562 | #define regDAGB5_RD_CREDITS_FULL 0x02f4 |
1563 | #define regDAGB5_RD_CREDITS_FULL_BASE_IDX 0 |
1564 | #define regDAGB5_PERFCOUNTER_LO 0x02f5 |
1565 | #define regDAGB5_PERFCOUNTER_LO_BASE_IDX 0 |
1566 | #define regDAGB5_PERFCOUNTER_HI 0x02f6 |
1567 | #define regDAGB5_PERFCOUNTER_HI_BASE_IDX 0 |
1568 | #define regDAGB5_PERFCOUNTER0_CFG 0x02f7 |
1569 | #define regDAGB5_PERFCOUNTER0_CFG_BASE_IDX 0 |
1570 | #define regDAGB5_PERFCOUNTER1_CFG 0x02f8 |
1571 | #define regDAGB5_PERFCOUNTER1_CFG_BASE_IDX 0 |
1572 | #define regDAGB5_PERFCOUNTER2_CFG 0x02f9 |
1573 | #define regDAGB5_PERFCOUNTER2_CFG_BASE_IDX 0 |
1574 | #define regDAGB5_PERFCOUNTER_RSLT_CNTL 0x02fa |
1575 | #define regDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
1576 | #define regDAGB5_L1TLB_REG_RW 0x02fb |
1577 | #define regDAGB5_L1TLB_REG_RW_BASE_IDX 0 |
1578 | #define regDAGB5_RESERVE1 0x02fc |
1579 | #define regDAGB5_RESERVE1_BASE_IDX 0 |
1580 | #define regDAGB5_RESERVE2 0x02fd |
1581 | #define regDAGB5_RESERVE2_BASE_IDX 0 |
1582 | #define regDAGB5_RESERVE3 0x02fe |
1583 | #define regDAGB5_RESERVE3_BASE_IDX 0 |
1584 | #define regDAGB5_RESERVE4 0x02ff |
1585 | #define regDAGB5_RESERVE4_BASE_IDX 0 |
1586 | |
1587 | |
1588 | // addressBlock: mmhub_ea_mmeadec0 |
1589 | // base address: 0x68c00 |
1590 | #define regMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0300 |
1591 | #define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
1592 | #define regMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0301 |
1593 | #define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
1594 | #define regMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0302 |
1595 | #define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
1596 | #define regMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0303 |
1597 | #define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
1598 | #define regMMEA0_DRAM_RD_GRP2VC_MAP 0x0304 |
1599 | #define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
1600 | #define regMMEA0_DRAM_WR_GRP2VC_MAP 0x0305 |
1601 | #define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
1602 | #define regMMEA0_DRAM_RD_LAZY 0x0306 |
1603 | #define regMMEA0_DRAM_RD_LAZY_BASE_IDX 0 |
1604 | #define regMMEA0_DRAM_WR_LAZY 0x0307 |
1605 | #define regMMEA0_DRAM_WR_LAZY_BASE_IDX 0 |
1606 | #define regMMEA0_DRAM_RD_CAM_CNTL 0x0308 |
1607 | #define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
1608 | #define regMMEA0_DRAM_WR_CAM_CNTL 0x0309 |
1609 | #define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
1610 | #define regMMEA0_DRAM_PAGE_BURST 0x030a |
1611 | #define regMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 |
1612 | #define regMMEA0_DRAM_RD_PRI_AGE 0x030b |
1613 | #define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 |
1614 | #define regMMEA0_DRAM_WR_PRI_AGE 0x030c |
1615 | #define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 |
1616 | #define regMMEA0_DRAM_RD_PRI_QUEUING 0x030d |
1617 | #define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
1618 | #define regMMEA0_DRAM_WR_PRI_QUEUING 0x030e |
1619 | #define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
1620 | #define regMMEA0_DRAM_RD_PRI_FIXED 0x030f |
1621 | #define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
1622 | #define regMMEA0_DRAM_WR_PRI_FIXED 0x0310 |
1623 | #define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
1624 | #define regMMEA0_DRAM_RD_PRI_URGENCY 0x0311 |
1625 | #define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
1626 | #define regMMEA0_DRAM_WR_PRI_URGENCY 0x0312 |
1627 | #define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
1628 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0313 |
1629 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
1630 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0314 |
1631 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
1632 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0315 |
1633 | #define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
1634 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0316 |
1635 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
1636 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0317 |
1637 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
1638 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0318 |
1639 | #define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
1640 | #define regMMEA0_GMI_RD_CLI2GRP_MAP0 0x0319 |
1641 | #define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
1642 | #define regMMEA0_GMI_RD_CLI2GRP_MAP1 0x031a |
1643 | #define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
1644 | #define regMMEA0_GMI_WR_CLI2GRP_MAP0 0x031b |
1645 | #define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
1646 | #define regMMEA0_GMI_WR_CLI2GRP_MAP1 0x031c |
1647 | #define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
1648 | #define regMMEA0_GMI_RD_GRP2VC_MAP 0x031d |
1649 | #define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
1650 | #define regMMEA0_GMI_WR_GRP2VC_MAP 0x031e |
1651 | #define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
1652 | #define regMMEA0_GMI_RD_LAZY 0x031f |
1653 | #define regMMEA0_GMI_RD_LAZY_BASE_IDX 0 |
1654 | #define regMMEA0_GMI_WR_LAZY 0x0320 |
1655 | #define regMMEA0_GMI_WR_LAZY_BASE_IDX 0 |
1656 | #define regMMEA0_GMI_RD_CAM_CNTL 0x0321 |
1657 | #define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 0 |
1658 | #define regMMEA0_GMI_WR_CAM_CNTL 0x0322 |
1659 | #define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 0 |
1660 | #define regMMEA0_GMI_PAGE_BURST 0x0323 |
1661 | #define regMMEA0_GMI_PAGE_BURST_BASE_IDX 0 |
1662 | #define regMMEA0_GMI_RD_PRI_AGE 0x0324 |
1663 | #define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX 0 |
1664 | #define regMMEA0_GMI_WR_PRI_AGE 0x0325 |
1665 | #define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX 0 |
1666 | #define regMMEA0_GMI_RD_PRI_QUEUING 0x0326 |
1667 | #define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
1668 | #define regMMEA0_GMI_WR_PRI_QUEUING 0x0327 |
1669 | #define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
1670 | #define regMMEA0_GMI_RD_PRI_FIXED 0x0328 |
1671 | #define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 0 |
1672 | #define regMMEA0_GMI_WR_PRI_FIXED 0x0329 |
1673 | #define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 0 |
1674 | #define regMMEA0_GMI_RD_PRI_URGENCY 0x032a |
1675 | #define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
1676 | #define regMMEA0_GMI_WR_PRI_URGENCY 0x032b |
1677 | #define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
1678 | #define regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x032c |
1679 | #define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
1680 | #define regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x032d |
1681 | #define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
1682 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI1 0x032e |
1683 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
1684 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI2 0x032f |
1685 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
1686 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI3 0x0330 |
1687 | #define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
1688 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI1 0x0331 |
1689 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
1690 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI2 0x0332 |
1691 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
1692 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI3 0x0333 |
1693 | #define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
1694 | #define regMMEA0_ADDRNORM_BASE_ADDR0 0x0334 |
1695 | #define regMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
1696 | #define regMMEA0_ADDRNORM_LIMIT_ADDR0 0x0335 |
1697 | #define regMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
1698 | #define regMMEA0_ADDRNORM_BASE_ADDR1 0x0336 |
1699 | #define regMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
1700 | #define regMMEA0_ADDRNORM_LIMIT_ADDR1 0x0337 |
1701 | #define regMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
1702 | #define regMMEA0_ADDRNORM_OFFSET_ADDR1 0x0338 |
1703 | #define regMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
1704 | #define regMMEA0_ADDRNORM_BASE_ADDR2 0x0339 |
1705 | #define regMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
1706 | #define regMMEA0_ADDRNORM_LIMIT_ADDR2 0x033a |
1707 | #define regMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
1708 | #define regMMEA0_ADDRNORM_BASE_ADDR3 0x033b |
1709 | #define regMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
1710 | #define regMMEA0_ADDRNORM_LIMIT_ADDR3 0x033c |
1711 | #define regMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
1712 | #define regMMEA0_ADDRNORM_OFFSET_ADDR3 0x033d |
1713 | #define regMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
1714 | #define regMMEA0_ADDRNORM_MEGABASE_ADDR0 0x033e |
1715 | #define regMMEA0_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
1716 | #define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0x033f |
1717 | #define regMMEA0_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
1718 | #define regMMEA0_ADDRNORM_MEGABASE_ADDR1 0x0340 |
1719 | #define regMMEA0_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
1720 | #define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0x0341 |
1721 | #define regMMEA0_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
1722 | #define regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0343 |
1723 | #define regMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
1724 | #define regMMEA0_ADDRNORMGMI_HOLE_CNTL 0x0344 |
1725 | #define regMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
1726 | #define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0345 |
1727 | #define regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
1728 | #define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0346 |
1729 | #define regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
1730 | #define regMMEA0_ADDRDEC_BANK_CFG 0x0347 |
1731 | #define regMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 |
1732 | #define regMMEA0_ADDRDEC_MISC_CFG 0x0348 |
1733 | #define regMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 |
1734 | #define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0353 |
1735 | #define regMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
1736 | #define regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x035e |
1737 | #define regMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
1738 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x035f |
1739 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
1740 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0360 |
1741 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
1742 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0361 |
1743 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
1744 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0362 |
1745 | #define regMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
1746 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0363 |
1747 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
1748 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x0364 |
1749 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
1750 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x0365 |
1751 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
1752 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x0366 |
1753 | #define regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
1754 | #define regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x0367 |
1755 | #define regMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
1756 | #define regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x0368 |
1757 | #define regMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
1758 | #define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x0369 |
1759 | #define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
1760 | #define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x036a |
1761 | #define regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
1762 | #define regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x036b |
1763 | #define regMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
1764 | #define regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x036c |
1765 | #define regMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
1766 | #define regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x036d |
1767 | #define regMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
1768 | #define regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x036e |
1769 | #define regMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
1770 | #define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x036f |
1771 | #define regMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
1772 | #define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x0370 |
1773 | #define regMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
1774 | #define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0371 |
1775 | #define regMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
1776 | #define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0372 |
1777 | #define regMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
1778 | #define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0373 |
1779 | #define regMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
1780 | #define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0374 |
1781 | #define regMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
1782 | #define regMMEA0_ADDRDEC0_RM_SEL_CS01 0x0375 |
1783 | #define regMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
1784 | #define regMMEA0_ADDRDEC0_RM_SEL_CS23 0x0376 |
1785 | #define regMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
1786 | #define regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x0377 |
1787 | #define regMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
1788 | #define regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x0378 |
1789 | #define regMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
1790 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x0379 |
1791 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
1792 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x037a |
1793 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
1794 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x037b |
1795 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
1796 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x037c |
1797 | #define regMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
1798 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x037d |
1799 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
1800 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x037e |
1801 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
1802 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x037f |
1803 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
1804 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0380 |
1805 | #define regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
1806 | #define regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0381 |
1807 | #define regMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
1808 | #define regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0382 |
1809 | #define regMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
1810 | #define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0383 |
1811 | #define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
1812 | #define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0384 |
1813 | #define regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
1814 | #define regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0385 |
1815 | #define regMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
1816 | #define regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0386 |
1817 | #define regMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
1818 | #define regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0387 |
1819 | #define regMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
1820 | #define regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0388 |
1821 | #define regMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
1822 | #define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0389 |
1823 | #define regMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
1824 | #define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x038a |
1825 | #define regMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
1826 | #define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x038b |
1827 | #define regMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
1828 | #define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x038c |
1829 | #define regMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
1830 | #define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x038d |
1831 | #define regMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
1832 | #define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x038e |
1833 | #define regMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
1834 | #define regMMEA0_ADDRDEC1_RM_SEL_CS01 0x038f |
1835 | #define regMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
1836 | #define regMMEA0_ADDRDEC1_RM_SEL_CS23 0x0390 |
1837 | #define regMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
1838 | #define regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0391 |
1839 | #define regMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
1840 | #define regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0392 |
1841 | #define regMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
1842 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0393 |
1843 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
1844 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0394 |
1845 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
1846 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0395 |
1847 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
1848 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0396 |
1849 | #define regMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
1850 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0397 |
1851 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
1852 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0398 |
1853 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
1854 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0399 |
1855 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
1856 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x039a |
1857 | #define regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
1858 | #define regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x039b |
1859 | #define regMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
1860 | #define regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x039c |
1861 | #define regMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
1862 | #define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x039d |
1863 | #define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
1864 | #define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x039e |
1865 | #define regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
1866 | #define regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x039f |
1867 | #define regMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
1868 | #define regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x03a0 |
1869 | #define regMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
1870 | #define regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x03a1 |
1871 | #define regMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
1872 | #define regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x03a2 |
1873 | #define regMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
1874 | #define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x03a3 |
1875 | #define regMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
1876 | #define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x03a4 |
1877 | #define regMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
1878 | #define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x03a5 |
1879 | #define regMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
1880 | #define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x03a6 |
1881 | #define regMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
1882 | #define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x03a7 |
1883 | #define regMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
1884 | #define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x03a8 |
1885 | #define regMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
1886 | #define regMMEA0_ADDRDEC2_RM_SEL_CS01 0x03a9 |
1887 | #define regMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
1888 | #define regMMEA0_ADDRDEC2_RM_SEL_CS23 0x03aa |
1889 | #define regMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
1890 | #define regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x03ab |
1891 | #define regMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
1892 | #define regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x03ac |
1893 | #define regMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
1894 | #define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x03ad |
1895 | #define regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
1896 | #define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x03ae |
1897 | #define regMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
1898 | #define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0x03d1 |
1899 | #define regMMEA0_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
1900 | #define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0x03d2 |
1901 | #define regMMEA0_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
1902 | #define regMMEA0_ADDRNORMDRAM_MASKING 0x03d3 |
1903 | #define regMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
1904 | #define regMMEA0_ADDRNORMGMI_MASKING 0x03d4 |
1905 | #define regMMEA0_ADDRNORMGMI_MASKING_BASE_IDX 0 |
1906 | #define regMMEA0_IO_RD_CLI2GRP_MAP0 0x03d5 |
1907 | #define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
1908 | #define regMMEA0_IO_RD_CLI2GRP_MAP1 0x03d6 |
1909 | #define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
1910 | #define regMMEA0_IO_WR_CLI2GRP_MAP0 0x03d7 |
1911 | #define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
1912 | #define regMMEA0_IO_WR_CLI2GRP_MAP1 0x03d8 |
1913 | #define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
1914 | #define regMMEA0_IO_RD_COMBINE_FLUSH 0x03d9 |
1915 | #define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
1916 | #define regMMEA0_IO_WR_COMBINE_FLUSH 0x03da |
1917 | #define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
1918 | #define regMMEA0_IO_GROUP_BURST 0x03db |
1919 | #define regMMEA0_IO_GROUP_BURST_BASE_IDX 0 |
1920 | #define regMMEA0_IO_RD_PRI_AGE 0x03dc |
1921 | #define regMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 |
1922 | #define regMMEA0_IO_WR_PRI_AGE 0x03dd |
1923 | #define regMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 |
1924 | #define regMMEA0_IO_RD_PRI_QUEUING 0x03de |
1925 | #define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 |
1926 | #define regMMEA0_IO_WR_PRI_QUEUING 0x03df |
1927 | #define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 |
1928 | #define regMMEA0_IO_RD_PRI_FIXED 0x03e0 |
1929 | #define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 |
1930 | #define regMMEA0_IO_WR_PRI_FIXED 0x03e1 |
1931 | #define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 |
1932 | #define regMMEA0_IO_RD_PRI_URGENCY 0x03e2 |
1933 | #define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 |
1934 | #define regMMEA0_IO_WR_PRI_URGENCY 0x03e3 |
1935 | #define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 |
1936 | #define regMMEA0_IO_RD_PRI_URGENCY_MASKING 0x03e4 |
1937 | #define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
1938 | #define regMMEA0_IO_WR_PRI_URGENCY_MASKING 0x03e5 |
1939 | #define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
1940 | #define regMMEA0_IO_RD_PRI_QUANT_PRI1 0x03e6 |
1941 | #define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
1942 | #define regMMEA0_IO_RD_PRI_QUANT_PRI2 0x03e7 |
1943 | #define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
1944 | #define regMMEA0_IO_RD_PRI_QUANT_PRI3 0x03e8 |
1945 | #define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
1946 | #define regMMEA0_IO_WR_PRI_QUANT_PRI1 0x03e9 |
1947 | #define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
1948 | #define regMMEA0_IO_WR_PRI_QUANT_PRI2 0x03ea |
1949 | #define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
1950 | #define regMMEA0_IO_WR_PRI_QUANT_PRI3 0x03eb |
1951 | #define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
1952 | #define regMMEA0_SDP_ARB_DRAM 0x03ec |
1953 | #define regMMEA0_SDP_ARB_DRAM_BASE_IDX 0 |
1954 | #define regMMEA0_SDP_ARB_GMI 0x03ed |
1955 | #define regMMEA0_SDP_ARB_GMI_BASE_IDX 0 |
1956 | #define regMMEA0_SDP_ARB_FINAL 0x03ee |
1957 | #define regMMEA0_SDP_ARB_FINAL_BASE_IDX 0 |
1958 | #define regMMEA0_SDP_DRAM_PRIORITY 0x03ef |
1959 | #define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 |
1960 | #define regMMEA0_SDP_GMI_PRIORITY 0x03f0 |
1961 | #define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX 0 |
1962 | #define regMMEA0_SDP_IO_PRIORITY 0x03f1 |
1963 | #define regMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 |
1964 | #define regMMEA0_SDP_CREDITS 0x03f2 |
1965 | #define regMMEA0_SDP_CREDITS_BASE_IDX 0 |
1966 | #define regMMEA0_SDP_TAG_RESERVE0 0x03f3 |
1967 | #define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 |
1968 | #define regMMEA0_SDP_TAG_RESERVE1 0x03f4 |
1969 | #define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 |
1970 | #define regMMEA0_SDP_VCC_RESERVE0 0x03f5 |
1971 | #define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 |
1972 | #define regMMEA0_SDP_VCC_RESERVE1 0x03f6 |
1973 | #define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 |
1974 | #define regMMEA0_SDP_VCD_RESERVE0 0x03f7 |
1975 | #define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 |
1976 | #define regMMEA0_SDP_VCD_RESERVE1 0x03f8 |
1977 | #define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 |
1978 | #define regMMEA0_SDP_REQ_CNTL 0x03f9 |
1979 | #define regMMEA0_SDP_REQ_CNTL_BASE_IDX 0 |
1980 | #define regMMEA0_MISC 0x03fa |
1981 | #define regMMEA0_MISC_BASE_IDX 0 |
1982 | #define regMMEA0_LATENCY_SAMPLING 0x03fb |
1983 | #define regMMEA0_LATENCY_SAMPLING_BASE_IDX 0 |
1984 | #define regMMEA0_PERFCOUNTER_LO 0x03fc |
1985 | #define regMMEA0_PERFCOUNTER_LO_BASE_IDX 0 |
1986 | #define regMMEA0_PERFCOUNTER_HI 0x03fd |
1987 | #define regMMEA0_PERFCOUNTER_HI_BASE_IDX 0 |
1988 | #define regMMEA0_PERFCOUNTER0_CFG 0x03fe |
1989 | #define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 |
1990 | #define regMMEA0_PERFCOUNTER1_CFG 0x03ff |
1991 | #define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 |
1992 | #define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400 |
1993 | #define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
1994 | #define regMMEA0_EDC_CNT 0x0406 |
1995 | #define regMMEA0_EDC_CNT_BASE_IDX 0 |
1996 | #define regMMEA0_EDC_CNT2 0x0407 |
1997 | #define regMMEA0_EDC_CNT2_BASE_IDX 0 |
1998 | #define regMMEA0_DSM_CNTL 0x0408 |
1999 | #define regMMEA0_DSM_CNTL_BASE_IDX 0 |
2000 | #define regMMEA0_DSM_CNTLA 0x0409 |
2001 | #define regMMEA0_DSM_CNTLA_BASE_IDX 0 |
2002 | #define regMMEA0_DSM_CNTLB 0x040a |
2003 | #define regMMEA0_DSM_CNTLB_BASE_IDX 0 |
2004 | #define regMMEA0_DSM_CNTL2 0x040b |
2005 | #define regMMEA0_DSM_CNTL2_BASE_IDX 0 |
2006 | #define regMMEA0_DSM_CNTL2A 0x040c |
2007 | #define regMMEA0_DSM_CNTL2A_BASE_IDX 0 |
2008 | #define regMMEA0_DSM_CNTL2B 0x040d |
2009 | #define regMMEA0_DSM_CNTL2B_BASE_IDX 0 |
2010 | #define regMMEA0_CGTT_CLK_CTRL 0x040f |
2011 | #define regMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 |
2012 | #define regMMEA0_EDC_MODE 0x0410 |
2013 | #define regMMEA0_EDC_MODE_BASE_IDX 0 |
2014 | #define regMMEA0_ERR_STATUS 0x0411 |
2015 | #define regMMEA0_ERR_STATUS_BASE_IDX 0 |
2016 | #define regMMEA0_MISC2 0x0412 |
2017 | #define regMMEA0_MISC2_BASE_IDX 0 |
2018 | #define regMMEA0_ADDRDEC_SELECT 0x0413 |
2019 | #define regMMEA0_ADDRDEC_SELECT_BASE_IDX 0 |
2020 | #define regMMEA0_EDC_CNT3 0x0414 |
2021 | #define regMMEA0_EDC_CNT3_BASE_IDX 0 |
2022 | #define regMMEA0_MISC_AON 0x0415 |
2023 | #define regMMEA0_MISC_AON_BASE_IDX 0 |
2024 | |
2025 | |
2026 | // addressBlock: mmhub_ea_mmeadec1 |
2027 | // base address: 0x69100 |
2028 | #define regMMEA1_DRAM_RD_CLI2GRP_MAP0 0x0440 |
2029 | #define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2030 | #define regMMEA1_DRAM_RD_CLI2GRP_MAP1 0x0441 |
2031 | #define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2032 | #define regMMEA1_DRAM_WR_CLI2GRP_MAP0 0x0442 |
2033 | #define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2034 | #define regMMEA1_DRAM_WR_CLI2GRP_MAP1 0x0443 |
2035 | #define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2036 | #define regMMEA1_DRAM_RD_GRP2VC_MAP 0x0444 |
2037 | #define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
2038 | #define regMMEA1_DRAM_WR_GRP2VC_MAP 0x0445 |
2039 | #define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
2040 | #define regMMEA1_DRAM_RD_LAZY 0x0446 |
2041 | #define regMMEA1_DRAM_RD_LAZY_BASE_IDX 0 |
2042 | #define regMMEA1_DRAM_WR_LAZY 0x0447 |
2043 | #define regMMEA1_DRAM_WR_LAZY_BASE_IDX 0 |
2044 | #define regMMEA1_DRAM_RD_CAM_CNTL 0x0448 |
2045 | #define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
2046 | #define regMMEA1_DRAM_WR_CAM_CNTL 0x0449 |
2047 | #define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
2048 | #define regMMEA1_DRAM_PAGE_BURST 0x044a |
2049 | #define regMMEA1_DRAM_PAGE_BURST_BASE_IDX 0 |
2050 | #define regMMEA1_DRAM_RD_PRI_AGE 0x044b |
2051 | #define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 0 |
2052 | #define regMMEA1_DRAM_WR_PRI_AGE 0x044c |
2053 | #define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 0 |
2054 | #define regMMEA1_DRAM_RD_PRI_QUEUING 0x044d |
2055 | #define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
2056 | #define regMMEA1_DRAM_WR_PRI_QUEUING 0x044e |
2057 | #define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
2058 | #define regMMEA1_DRAM_RD_PRI_FIXED 0x044f |
2059 | #define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
2060 | #define regMMEA1_DRAM_WR_PRI_FIXED 0x0450 |
2061 | #define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
2062 | #define regMMEA1_DRAM_RD_PRI_URGENCY 0x0451 |
2063 | #define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
2064 | #define regMMEA1_DRAM_WR_PRI_URGENCY 0x0452 |
2065 | #define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
2066 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x0453 |
2067 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2068 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x0454 |
2069 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2070 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x0455 |
2071 | #define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2072 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x0456 |
2073 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2074 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x0457 |
2075 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2076 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x0458 |
2077 | #define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2078 | #define regMMEA1_GMI_RD_CLI2GRP_MAP0 0x0459 |
2079 | #define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2080 | #define regMMEA1_GMI_RD_CLI2GRP_MAP1 0x045a |
2081 | #define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2082 | #define regMMEA1_GMI_WR_CLI2GRP_MAP0 0x045b |
2083 | #define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2084 | #define regMMEA1_GMI_WR_CLI2GRP_MAP1 0x045c |
2085 | #define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2086 | #define regMMEA1_GMI_RD_GRP2VC_MAP 0x045d |
2087 | #define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
2088 | #define regMMEA1_GMI_WR_GRP2VC_MAP 0x045e |
2089 | #define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
2090 | #define regMMEA1_GMI_RD_LAZY 0x045f |
2091 | #define regMMEA1_GMI_RD_LAZY_BASE_IDX 0 |
2092 | #define regMMEA1_GMI_WR_LAZY 0x0460 |
2093 | #define regMMEA1_GMI_WR_LAZY_BASE_IDX 0 |
2094 | #define regMMEA1_GMI_RD_CAM_CNTL 0x0461 |
2095 | #define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 0 |
2096 | #define regMMEA1_GMI_WR_CAM_CNTL 0x0462 |
2097 | #define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 0 |
2098 | #define regMMEA1_GMI_PAGE_BURST 0x0463 |
2099 | #define regMMEA1_GMI_PAGE_BURST_BASE_IDX 0 |
2100 | #define regMMEA1_GMI_RD_PRI_AGE 0x0464 |
2101 | #define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX 0 |
2102 | #define regMMEA1_GMI_WR_PRI_AGE 0x0465 |
2103 | #define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX 0 |
2104 | #define regMMEA1_GMI_RD_PRI_QUEUING 0x0466 |
2105 | #define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
2106 | #define regMMEA1_GMI_WR_PRI_QUEUING 0x0467 |
2107 | #define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
2108 | #define regMMEA1_GMI_RD_PRI_FIXED 0x0468 |
2109 | #define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 0 |
2110 | #define regMMEA1_GMI_WR_PRI_FIXED 0x0469 |
2111 | #define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 0 |
2112 | #define regMMEA1_GMI_RD_PRI_URGENCY 0x046a |
2113 | #define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
2114 | #define regMMEA1_GMI_WR_PRI_URGENCY 0x046b |
2115 | #define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
2116 | #define regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x046c |
2117 | #define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
2118 | #define regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x046d |
2119 | #define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
2120 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI1 0x046e |
2121 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2122 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI2 0x046f |
2123 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2124 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI3 0x0470 |
2125 | #define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2126 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI1 0x0471 |
2127 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2128 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI2 0x0472 |
2129 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2130 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI3 0x0473 |
2131 | #define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2132 | #define regMMEA1_ADDRNORM_BASE_ADDR0 0x0474 |
2133 | #define regMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
2134 | #define regMMEA1_ADDRNORM_LIMIT_ADDR0 0x0475 |
2135 | #define regMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
2136 | #define regMMEA1_ADDRNORM_BASE_ADDR1 0x0476 |
2137 | #define regMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
2138 | #define regMMEA1_ADDRNORM_LIMIT_ADDR1 0x0477 |
2139 | #define regMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
2140 | #define regMMEA1_ADDRNORM_OFFSET_ADDR1 0x0478 |
2141 | #define regMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
2142 | #define regMMEA1_ADDRNORM_BASE_ADDR2 0x0479 |
2143 | #define regMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
2144 | #define regMMEA1_ADDRNORM_LIMIT_ADDR2 0x047a |
2145 | #define regMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
2146 | #define regMMEA1_ADDRNORM_BASE_ADDR3 0x047b |
2147 | #define regMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
2148 | #define regMMEA1_ADDRNORM_LIMIT_ADDR3 0x047c |
2149 | #define regMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
2150 | #define regMMEA1_ADDRNORM_OFFSET_ADDR3 0x047d |
2151 | #define regMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
2152 | #define regMMEA1_ADDRNORM_MEGABASE_ADDR0 0x047e |
2153 | #define regMMEA1_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
2154 | #define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0x047f |
2155 | #define regMMEA1_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
2156 | #define regMMEA1_ADDRNORM_MEGABASE_ADDR1 0x0480 |
2157 | #define regMMEA1_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
2158 | #define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0x0481 |
2159 | #define regMMEA1_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
2160 | #define regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0483 |
2161 | #define regMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
2162 | #define regMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0484 |
2163 | #define regMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
2164 | #define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0485 |
2165 | #define regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
2166 | #define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0486 |
2167 | #define regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
2168 | #define regMMEA1_ADDRDEC_BANK_CFG 0x0487 |
2169 | #define regMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 0 |
2170 | #define regMMEA1_ADDRDEC_MISC_CFG 0x0488 |
2171 | #define regMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 0 |
2172 | #define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0493 |
2173 | #define regMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
2174 | #define regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x049e |
2175 | #define regMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
2176 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x049f |
2177 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
2178 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x04a0 |
2179 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
2180 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x04a1 |
2181 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
2182 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x04a2 |
2183 | #define regMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
2184 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x04a3 |
2185 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
2186 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x04a4 |
2187 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
2188 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x04a5 |
2189 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
2190 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x04a6 |
2191 | #define regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
2192 | #define regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x04a7 |
2193 | #define regMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
2194 | #define regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x04a8 |
2195 | #define regMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
2196 | #define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x04a9 |
2197 | #define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
2198 | #define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x04aa |
2199 | #define regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
2200 | #define regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x04ab |
2201 | #define regMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
2202 | #define regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x04ac |
2203 | #define regMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
2204 | #define regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x04ad |
2205 | #define regMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
2206 | #define regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x04ae |
2207 | #define regMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
2208 | #define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x04af |
2209 | #define regMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
2210 | #define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x04b0 |
2211 | #define regMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
2212 | #define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x04b1 |
2213 | #define regMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
2214 | #define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x04b2 |
2215 | #define regMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
2216 | #define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x04b3 |
2217 | #define regMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
2218 | #define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x04b4 |
2219 | #define regMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
2220 | #define regMMEA1_ADDRDEC0_RM_SEL_CS01 0x04b5 |
2221 | #define regMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
2222 | #define regMMEA1_ADDRDEC0_RM_SEL_CS23 0x04b6 |
2223 | #define regMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
2224 | #define regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x04b7 |
2225 | #define regMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
2226 | #define regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x04b8 |
2227 | #define regMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
2228 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x04b9 |
2229 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
2230 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x04ba |
2231 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
2232 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x04bb |
2233 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
2234 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x04bc |
2235 | #define regMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
2236 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x04bd |
2237 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
2238 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x04be |
2239 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
2240 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x04bf |
2241 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
2242 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x04c0 |
2243 | #define regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
2244 | #define regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x04c1 |
2245 | #define regMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
2246 | #define regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x04c2 |
2247 | #define regMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
2248 | #define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x04c3 |
2249 | #define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
2250 | #define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x04c4 |
2251 | #define regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
2252 | #define regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x04c5 |
2253 | #define regMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
2254 | #define regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x04c6 |
2255 | #define regMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
2256 | #define regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x04c7 |
2257 | #define regMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
2258 | #define regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x04c8 |
2259 | #define regMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
2260 | #define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x04c9 |
2261 | #define regMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
2262 | #define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x04ca |
2263 | #define regMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
2264 | #define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x04cb |
2265 | #define regMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
2266 | #define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x04cc |
2267 | #define regMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
2268 | #define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x04cd |
2269 | #define regMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
2270 | #define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x04ce |
2271 | #define regMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
2272 | #define regMMEA1_ADDRDEC1_RM_SEL_CS01 0x04cf |
2273 | #define regMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
2274 | #define regMMEA1_ADDRDEC1_RM_SEL_CS23 0x04d0 |
2275 | #define regMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
2276 | #define regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x04d1 |
2277 | #define regMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
2278 | #define regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x04d2 |
2279 | #define regMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
2280 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x04d3 |
2281 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
2282 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x04d4 |
2283 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
2284 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x04d5 |
2285 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
2286 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x04d6 |
2287 | #define regMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
2288 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x04d7 |
2289 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
2290 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x04d8 |
2291 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
2292 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x04d9 |
2293 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
2294 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x04da |
2295 | #define regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
2296 | #define regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x04db |
2297 | #define regMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
2298 | #define regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x04dc |
2299 | #define regMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
2300 | #define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x04dd |
2301 | #define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
2302 | #define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x04de |
2303 | #define regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
2304 | #define regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x04df |
2305 | #define regMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
2306 | #define regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x04e0 |
2307 | #define regMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
2308 | #define regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x04e1 |
2309 | #define regMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
2310 | #define regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x04e2 |
2311 | #define regMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
2312 | #define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x04e3 |
2313 | #define regMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
2314 | #define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x04e4 |
2315 | #define regMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
2316 | #define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x04e5 |
2317 | #define regMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
2318 | #define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x04e6 |
2319 | #define regMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
2320 | #define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x04e7 |
2321 | #define regMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
2322 | #define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x04e8 |
2323 | #define regMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
2324 | #define regMMEA1_ADDRDEC2_RM_SEL_CS01 0x04e9 |
2325 | #define regMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
2326 | #define regMMEA1_ADDRDEC2_RM_SEL_CS23 0x04ea |
2327 | #define regMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
2328 | #define regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x04eb |
2329 | #define regMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
2330 | #define regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x04ec |
2331 | #define regMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
2332 | #define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x04ed |
2333 | #define regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
2334 | #define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x04ee |
2335 | #define regMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
2336 | #define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0x0511 |
2337 | #define regMMEA1_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
2338 | #define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0x0512 |
2339 | #define regMMEA1_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
2340 | #define regMMEA1_ADDRNORMDRAM_MASKING 0x0513 |
2341 | #define regMMEA1_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
2342 | #define regMMEA1_ADDRNORMGMI_MASKING 0x0514 |
2343 | #define regMMEA1_ADDRNORMGMI_MASKING_BASE_IDX 0 |
2344 | #define regMMEA1_IO_RD_CLI2GRP_MAP0 0x0515 |
2345 | #define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2346 | #define regMMEA1_IO_RD_CLI2GRP_MAP1 0x0516 |
2347 | #define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2348 | #define regMMEA1_IO_WR_CLI2GRP_MAP0 0x0517 |
2349 | #define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2350 | #define regMMEA1_IO_WR_CLI2GRP_MAP1 0x0518 |
2351 | #define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2352 | #define regMMEA1_IO_RD_COMBINE_FLUSH 0x0519 |
2353 | #define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
2354 | #define regMMEA1_IO_WR_COMBINE_FLUSH 0x051a |
2355 | #define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
2356 | #define regMMEA1_IO_GROUP_BURST 0x051b |
2357 | #define regMMEA1_IO_GROUP_BURST_BASE_IDX 0 |
2358 | #define regMMEA1_IO_RD_PRI_AGE 0x051c |
2359 | #define regMMEA1_IO_RD_PRI_AGE_BASE_IDX 0 |
2360 | #define regMMEA1_IO_WR_PRI_AGE 0x051d |
2361 | #define regMMEA1_IO_WR_PRI_AGE_BASE_IDX 0 |
2362 | #define regMMEA1_IO_RD_PRI_QUEUING 0x051e |
2363 | #define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 0 |
2364 | #define regMMEA1_IO_WR_PRI_QUEUING 0x051f |
2365 | #define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 0 |
2366 | #define regMMEA1_IO_RD_PRI_FIXED 0x0520 |
2367 | #define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX 0 |
2368 | #define regMMEA1_IO_WR_PRI_FIXED 0x0521 |
2369 | #define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX 0 |
2370 | #define regMMEA1_IO_RD_PRI_URGENCY 0x0522 |
2371 | #define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 0 |
2372 | #define regMMEA1_IO_WR_PRI_URGENCY 0x0523 |
2373 | #define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 0 |
2374 | #define regMMEA1_IO_RD_PRI_URGENCY_MASKING 0x0524 |
2375 | #define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
2376 | #define regMMEA1_IO_WR_PRI_URGENCY_MASKING 0x0525 |
2377 | #define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
2378 | #define regMMEA1_IO_RD_PRI_QUANT_PRI1 0x0526 |
2379 | #define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2380 | #define regMMEA1_IO_RD_PRI_QUANT_PRI2 0x0527 |
2381 | #define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2382 | #define regMMEA1_IO_RD_PRI_QUANT_PRI3 0x0528 |
2383 | #define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2384 | #define regMMEA1_IO_WR_PRI_QUANT_PRI1 0x0529 |
2385 | #define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2386 | #define regMMEA1_IO_WR_PRI_QUANT_PRI2 0x052a |
2387 | #define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2388 | #define regMMEA1_IO_WR_PRI_QUANT_PRI3 0x052b |
2389 | #define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2390 | #define regMMEA1_SDP_ARB_DRAM 0x052c |
2391 | #define regMMEA1_SDP_ARB_DRAM_BASE_IDX 0 |
2392 | #define regMMEA1_SDP_ARB_GMI 0x052d |
2393 | #define regMMEA1_SDP_ARB_GMI_BASE_IDX 0 |
2394 | #define regMMEA1_SDP_ARB_FINAL 0x052e |
2395 | #define regMMEA1_SDP_ARB_FINAL_BASE_IDX 0 |
2396 | #define regMMEA1_SDP_DRAM_PRIORITY 0x052f |
2397 | #define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 0 |
2398 | #define regMMEA1_SDP_GMI_PRIORITY 0x0530 |
2399 | #define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX 0 |
2400 | #define regMMEA1_SDP_IO_PRIORITY 0x0531 |
2401 | #define regMMEA1_SDP_IO_PRIORITY_BASE_IDX 0 |
2402 | #define regMMEA1_SDP_CREDITS 0x0532 |
2403 | #define regMMEA1_SDP_CREDITS_BASE_IDX 0 |
2404 | #define regMMEA1_SDP_TAG_RESERVE0 0x0533 |
2405 | #define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX 0 |
2406 | #define regMMEA1_SDP_TAG_RESERVE1 0x0534 |
2407 | #define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX 0 |
2408 | #define regMMEA1_SDP_VCC_RESERVE0 0x0535 |
2409 | #define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX 0 |
2410 | #define regMMEA1_SDP_VCC_RESERVE1 0x0536 |
2411 | #define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX 0 |
2412 | #define regMMEA1_SDP_VCD_RESERVE0 0x0537 |
2413 | #define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX 0 |
2414 | #define regMMEA1_SDP_VCD_RESERVE1 0x0538 |
2415 | #define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX 0 |
2416 | #define regMMEA1_SDP_REQ_CNTL 0x0539 |
2417 | #define regMMEA1_SDP_REQ_CNTL_BASE_IDX 0 |
2418 | #define regMMEA1_MISC 0x053a |
2419 | #define regMMEA1_MISC_BASE_IDX 0 |
2420 | #define regMMEA1_LATENCY_SAMPLING 0x053b |
2421 | #define regMMEA1_LATENCY_SAMPLING_BASE_IDX 0 |
2422 | #define regMMEA1_PERFCOUNTER_LO 0x053c |
2423 | #define regMMEA1_PERFCOUNTER_LO_BASE_IDX 0 |
2424 | #define regMMEA1_PERFCOUNTER_HI 0x053d |
2425 | #define regMMEA1_PERFCOUNTER_HI_BASE_IDX 0 |
2426 | #define regMMEA1_PERFCOUNTER0_CFG 0x053e |
2427 | #define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX 0 |
2428 | #define regMMEA1_PERFCOUNTER1_CFG 0x053f |
2429 | #define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 |
2430 | #define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540 |
2431 | #define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
2432 | #define regMMEA1_EDC_CNT 0x0546 |
2433 | #define regMMEA1_EDC_CNT_BASE_IDX 0 |
2434 | #define regMMEA1_EDC_CNT2 0x0547 |
2435 | #define regMMEA1_EDC_CNT2_BASE_IDX 0 |
2436 | #define regMMEA1_DSM_CNTL 0x0548 |
2437 | #define regMMEA1_DSM_CNTL_BASE_IDX 0 |
2438 | #define regMMEA1_DSM_CNTLA 0x0549 |
2439 | #define regMMEA1_DSM_CNTLA_BASE_IDX 0 |
2440 | #define regMMEA1_DSM_CNTLB 0x054a |
2441 | #define regMMEA1_DSM_CNTLB_BASE_IDX 0 |
2442 | #define regMMEA1_DSM_CNTL2 0x054b |
2443 | #define regMMEA1_DSM_CNTL2_BASE_IDX 0 |
2444 | #define regMMEA1_DSM_CNTL2A 0x054c |
2445 | #define regMMEA1_DSM_CNTL2A_BASE_IDX 0 |
2446 | #define regMMEA1_DSM_CNTL2B 0x054d |
2447 | #define regMMEA1_DSM_CNTL2B_BASE_IDX 0 |
2448 | #define regMMEA1_CGTT_CLK_CTRL 0x054f |
2449 | #define regMMEA1_CGTT_CLK_CTRL_BASE_IDX 0 |
2450 | #define regMMEA1_EDC_MODE 0x0550 |
2451 | #define regMMEA1_EDC_MODE_BASE_IDX 0 |
2452 | #define regMMEA1_ERR_STATUS 0x0551 |
2453 | #define regMMEA1_ERR_STATUS_BASE_IDX 0 |
2454 | #define regMMEA1_MISC2 0x0552 |
2455 | #define regMMEA1_MISC2_BASE_IDX 0 |
2456 | #define regMMEA1_ADDRDEC_SELECT 0x0553 |
2457 | #define regMMEA1_ADDRDEC_SELECT_BASE_IDX 0 |
2458 | #define regMMEA1_EDC_CNT3 0x0554 |
2459 | #define regMMEA1_EDC_CNT3_BASE_IDX 0 |
2460 | #define regMMEA1_MISC_AON 0x0555 |
2461 | #define regMMEA1_MISC_AON_BASE_IDX 0 |
2462 | |
2463 | |
2464 | // addressBlock: mmhub_ea_mmeadec2 |
2465 | // base address: 0x69600 |
2466 | #define regMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0580 |
2467 | #define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2468 | #define regMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0581 |
2469 | #define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2470 | #define regMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0582 |
2471 | #define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2472 | #define regMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0583 |
2473 | #define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2474 | #define regMMEA2_DRAM_RD_GRP2VC_MAP 0x0584 |
2475 | #define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
2476 | #define regMMEA2_DRAM_WR_GRP2VC_MAP 0x0585 |
2477 | #define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
2478 | #define regMMEA2_DRAM_RD_LAZY 0x0586 |
2479 | #define regMMEA2_DRAM_RD_LAZY_BASE_IDX 0 |
2480 | #define regMMEA2_DRAM_WR_LAZY 0x0587 |
2481 | #define regMMEA2_DRAM_WR_LAZY_BASE_IDX 0 |
2482 | #define regMMEA2_DRAM_RD_CAM_CNTL 0x0588 |
2483 | #define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
2484 | #define regMMEA2_DRAM_WR_CAM_CNTL 0x0589 |
2485 | #define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
2486 | #define regMMEA2_DRAM_PAGE_BURST 0x058a |
2487 | #define regMMEA2_DRAM_PAGE_BURST_BASE_IDX 0 |
2488 | #define regMMEA2_DRAM_RD_PRI_AGE 0x058b |
2489 | #define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 0 |
2490 | #define regMMEA2_DRAM_WR_PRI_AGE 0x058c |
2491 | #define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 0 |
2492 | #define regMMEA2_DRAM_RD_PRI_QUEUING 0x058d |
2493 | #define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
2494 | #define regMMEA2_DRAM_WR_PRI_QUEUING 0x058e |
2495 | #define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
2496 | #define regMMEA2_DRAM_RD_PRI_FIXED 0x058f |
2497 | #define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
2498 | #define regMMEA2_DRAM_WR_PRI_FIXED 0x0590 |
2499 | #define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
2500 | #define regMMEA2_DRAM_RD_PRI_URGENCY 0x0591 |
2501 | #define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
2502 | #define regMMEA2_DRAM_WR_PRI_URGENCY 0x0592 |
2503 | #define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
2504 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0593 |
2505 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2506 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0594 |
2507 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2508 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0595 |
2509 | #define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2510 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0596 |
2511 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2512 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0597 |
2513 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2514 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0598 |
2515 | #define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2516 | #define regMMEA2_GMI_RD_CLI2GRP_MAP0 0x0599 |
2517 | #define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2518 | #define regMMEA2_GMI_RD_CLI2GRP_MAP1 0x059a |
2519 | #define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2520 | #define regMMEA2_GMI_WR_CLI2GRP_MAP0 0x059b |
2521 | #define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2522 | #define regMMEA2_GMI_WR_CLI2GRP_MAP1 0x059c |
2523 | #define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2524 | #define regMMEA2_GMI_RD_GRP2VC_MAP 0x059d |
2525 | #define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
2526 | #define regMMEA2_GMI_WR_GRP2VC_MAP 0x059e |
2527 | #define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
2528 | #define regMMEA2_GMI_RD_LAZY 0x059f |
2529 | #define regMMEA2_GMI_RD_LAZY_BASE_IDX 0 |
2530 | #define regMMEA2_GMI_WR_LAZY 0x05a0 |
2531 | #define regMMEA2_GMI_WR_LAZY_BASE_IDX 0 |
2532 | #define regMMEA2_GMI_RD_CAM_CNTL 0x05a1 |
2533 | #define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 0 |
2534 | #define regMMEA2_GMI_WR_CAM_CNTL 0x05a2 |
2535 | #define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 0 |
2536 | #define regMMEA2_GMI_PAGE_BURST 0x05a3 |
2537 | #define regMMEA2_GMI_PAGE_BURST_BASE_IDX 0 |
2538 | #define regMMEA2_GMI_RD_PRI_AGE 0x05a4 |
2539 | #define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX 0 |
2540 | #define regMMEA2_GMI_WR_PRI_AGE 0x05a5 |
2541 | #define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX 0 |
2542 | #define regMMEA2_GMI_RD_PRI_QUEUING 0x05a6 |
2543 | #define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
2544 | #define regMMEA2_GMI_WR_PRI_QUEUING 0x05a7 |
2545 | #define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
2546 | #define regMMEA2_GMI_RD_PRI_FIXED 0x05a8 |
2547 | #define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 0 |
2548 | #define regMMEA2_GMI_WR_PRI_FIXED 0x05a9 |
2549 | #define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 0 |
2550 | #define regMMEA2_GMI_RD_PRI_URGENCY 0x05aa |
2551 | #define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
2552 | #define regMMEA2_GMI_WR_PRI_URGENCY 0x05ab |
2553 | #define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
2554 | #define regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x05ac |
2555 | #define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
2556 | #define regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x05ad |
2557 | #define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
2558 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI1 0x05ae |
2559 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2560 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI2 0x05af |
2561 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2562 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI3 0x05b0 |
2563 | #define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2564 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI1 0x05b1 |
2565 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2566 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI2 0x05b2 |
2567 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2568 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI3 0x05b3 |
2569 | #define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2570 | #define regMMEA2_ADDRNORM_BASE_ADDR0 0x05b4 |
2571 | #define regMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
2572 | #define regMMEA2_ADDRNORM_LIMIT_ADDR0 0x05b5 |
2573 | #define regMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
2574 | #define regMMEA2_ADDRNORM_BASE_ADDR1 0x05b6 |
2575 | #define regMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
2576 | #define regMMEA2_ADDRNORM_LIMIT_ADDR1 0x05b7 |
2577 | #define regMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
2578 | #define regMMEA2_ADDRNORM_OFFSET_ADDR1 0x05b8 |
2579 | #define regMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
2580 | #define regMMEA2_ADDRNORM_BASE_ADDR2 0x05b9 |
2581 | #define regMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
2582 | #define regMMEA2_ADDRNORM_LIMIT_ADDR2 0x05ba |
2583 | #define regMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
2584 | #define regMMEA2_ADDRNORM_BASE_ADDR3 0x05bb |
2585 | #define regMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
2586 | #define regMMEA2_ADDRNORM_LIMIT_ADDR3 0x05bc |
2587 | #define regMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
2588 | #define regMMEA2_ADDRNORM_OFFSET_ADDR3 0x05bd |
2589 | #define regMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
2590 | #define regMMEA2_ADDRNORM_MEGABASE_ADDR0 0x05be |
2591 | #define regMMEA2_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
2592 | #define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0 0x05bf |
2593 | #define regMMEA2_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
2594 | #define regMMEA2_ADDRNORM_MEGABASE_ADDR1 0x05c0 |
2595 | #define regMMEA2_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
2596 | #define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1 0x05c1 |
2597 | #define regMMEA2_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
2598 | #define regMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x05c3 |
2599 | #define regMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
2600 | #define regMMEA2_ADDRNORMGMI_HOLE_CNTL 0x05c4 |
2601 | #define regMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
2602 | #define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x05c5 |
2603 | #define regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
2604 | #define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x05c6 |
2605 | #define regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
2606 | #define regMMEA2_ADDRDEC_BANK_CFG 0x05c7 |
2607 | #define regMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 0 |
2608 | #define regMMEA2_ADDRDEC_MISC_CFG 0x05c8 |
2609 | #define regMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 0 |
2610 | #define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x05d3 |
2611 | #define regMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
2612 | #define regMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x05de |
2613 | #define regMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
2614 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x05df |
2615 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
2616 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x05e0 |
2617 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
2618 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x05e1 |
2619 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
2620 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x05e2 |
2621 | #define regMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
2622 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x05e3 |
2623 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
2624 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x05e4 |
2625 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
2626 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x05e5 |
2627 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
2628 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x05e6 |
2629 | #define regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
2630 | #define regMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x05e7 |
2631 | #define regMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
2632 | #define regMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x05e8 |
2633 | #define regMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
2634 | #define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x05e9 |
2635 | #define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
2636 | #define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x05ea |
2637 | #define regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
2638 | #define regMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x05eb |
2639 | #define regMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
2640 | #define regMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x05ec |
2641 | #define regMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
2642 | #define regMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x05ed |
2643 | #define regMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
2644 | #define regMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x05ee |
2645 | #define regMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
2646 | #define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x05ef |
2647 | #define regMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
2648 | #define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x05f0 |
2649 | #define regMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
2650 | #define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x05f1 |
2651 | #define regMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
2652 | #define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x05f2 |
2653 | #define regMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
2654 | #define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x05f3 |
2655 | #define regMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
2656 | #define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x05f4 |
2657 | #define regMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
2658 | #define regMMEA2_ADDRDEC0_RM_SEL_CS01 0x05f5 |
2659 | #define regMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
2660 | #define regMMEA2_ADDRDEC0_RM_SEL_CS23 0x05f6 |
2661 | #define regMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
2662 | #define regMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x05f7 |
2663 | #define regMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
2664 | #define regMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x05f8 |
2665 | #define regMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
2666 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x05f9 |
2667 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
2668 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x05fa |
2669 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
2670 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x05fb |
2671 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
2672 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x05fc |
2673 | #define regMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
2674 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x05fd |
2675 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
2676 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x05fe |
2677 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
2678 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x05ff |
2679 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
2680 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0600 |
2681 | #define regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
2682 | #define regMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0601 |
2683 | #define regMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
2684 | #define regMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0602 |
2685 | #define regMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
2686 | #define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0603 |
2687 | #define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
2688 | #define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0604 |
2689 | #define regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
2690 | #define regMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0605 |
2691 | #define regMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
2692 | #define regMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0606 |
2693 | #define regMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
2694 | #define regMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0607 |
2695 | #define regMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
2696 | #define regMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0608 |
2697 | #define regMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
2698 | #define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0609 |
2699 | #define regMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
2700 | #define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x060a |
2701 | #define regMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
2702 | #define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x060b |
2703 | #define regMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
2704 | #define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x060c |
2705 | #define regMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
2706 | #define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x060d |
2707 | #define regMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
2708 | #define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x060e |
2709 | #define regMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
2710 | #define regMMEA2_ADDRDEC1_RM_SEL_CS01 0x060f |
2711 | #define regMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
2712 | #define regMMEA2_ADDRDEC1_RM_SEL_CS23 0x0610 |
2713 | #define regMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
2714 | #define regMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0611 |
2715 | #define regMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
2716 | #define regMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0612 |
2717 | #define regMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
2718 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0613 |
2719 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
2720 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0614 |
2721 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
2722 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0615 |
2723 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
2724 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0616 |
2725 | #define regMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
2726 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0617 |
2727 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
2728 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0618 |
2729 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
2730 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0619 |
2731 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
2732 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x061a |
2733 | #define regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
2734 | #define regMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x061b |
2735 | #define regMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
2736 | #define regMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x061c |
2737 | #define regMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
2738 | #define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x061d |
2739 | #define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
2740 | #define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x061e |
2741 | #define regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
2742 | #define regMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x061f |
2743 | #define regMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
2744 | #define regMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x0620 |
2745 | #define regMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
2746 | #define regMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x0621 |
2747 | #define regMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
2748 | #define regMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x0622 |
2749 | #define regMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
2750 | #define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x0623 |
2751 | #define regMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
2752 | #define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x0624 |
2753 | #define regMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
2754 | #define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x0625 |
2755 | #define regMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
2756 | #define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x0626 |
2757 | #define regMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
2758 | #define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x0627 |
2759 | #define regMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
2760 | #define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x0628 |
2761 | #define regMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
2762 | #define regMMEA2_ADDRDEC2_RM_SEL_CS01 0x0629 |
2763 | #define regMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
2764 | #define regMMEA2_ADDRDEC2_RM_SEL_CS23 0x062a |
2765 | #define regMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
2766 | #define regMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x062b |
2767 | #define regMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
2768 | #define regMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x062c |
2769 | #define regMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
2770 | #define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x062d |
2771 | #define regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
2772 | #define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x062e |
2773 | #define regMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
2774 | #define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0 0x0651 |
2775 | #define regMMEA2_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
2776 | #define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1 0x0652 |
2777 | #define regMMEA2_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
2778 | #define regMMEA2_ADDRNORMDRAM_MASKING 0x0653 |
2779 | #define regMMEA2_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
2780 | #define regMMEA2_ADDRNORMGMI_MASKING 0x0654 |
2781 | #define regMMEA2_ADDRNORMGMI_MASKING_BASE_IDX 0 |
2782 | #define regMMEA2_IO_RD_CLI2GRP_MAP0 0x0655 |
2783 | #define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2784 | #define regMMEA2_IO_RD_CLI2GRP_MAP1 0x0656 |
2785 | #define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2786 | #define regMMEA2_IO_WR_CLI2GRP_MAP0 0x0657 |
2787 | #define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2788 | #define regMMEA2_IO_WR_CLI2GRP_MAP1 0x0658 |
2789 | #define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2790 | #define regMMEA2_IO_RD_COMBINE_FLUSH 0x0659 |
2791 | #define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
2792 | #define regMMEA2_IO_WR_COMBINE_FLUSH 0x065a |
2793 | #define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
2794 | #define regMMEA2_IO_GROUP_BURST 0x065b |
2795 | #define regMMEA2_IO_GROUP_BURST_BASE_IDX 0 |
2796 | #define regMMEA2_IO_RD_PRI_AGE 0x065c |
2797 | #define regMMEA2_IO_RD_PRI_AGE_BASE_IDX 0 |
2798 | #define regMMEA2_IO_WR_PRI_AGE 0x065d |
2799 | #define regMMEA2_IO_WR_PRI_AGE_BASE_IDX 0 |
2800 | #define regMMEA2_IO_RD_PRI_QUEUING 0x065e |
2801 | #define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 0 |
2802 | #define regMMEA2_IO_WR_PRI_QUEUING 0x065f |
2803 | #define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 0 |
2804 | #define regMMEA2_IO_RD_PRI_FIXED 0x0660 |
2805 | #define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX 0 |
2806 | #define regMMEA2_IO_WR_PRI_FIXED 0x0661 |
2807 | #define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX 0 |
2808 | #define regMMEA2_IO_RD_PRI_URGENCY 0x0662 |
2809 | #define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 0 |
2810 | #define regMMEA2_IO_WR_PRI_URGENCY 0x0663 |
2811 | #define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 0 |
2812 | #define regMMEA2_IO_RD_PRI_URGENCY_MASKING 0x0664 |
2813 | #define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
2814 | #define regMMEA2_IO_WR_PRI_URGENCY_MASKING 0x0665 |
2815 | #define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
2816 | #define regMMEA2_IO_RD_PRI_QUANT_PRI1 0x0666 |
2817 | #define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2818 | #define regMMEA2_IO_RD_PRI_QUANT_PRI2 0x0667 |
2819 | #define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2820 | #define regMMEA2_IO_RD_PRI_QUANT_PRI3 0x0668 |
2821 | #define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2822 | #define regMMEA2_IO_WR_PRI_QUANT_PRI1 0x0669 |
2823 | #define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2824 | #define regMMEA2_IO_WR_PRI_QUANT_PRI2 0x066a |
2825 | #define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2826 | #define regMMEA2_IO_WR_PRI_QUANT_PRI3 0x066b |
2827 | #define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2828 | #define regMMEA2_SDP_ARB_DRAM 0x066c |
2829 | #define regMMEA2_SDP_ARB_DRAM_BASE_IDX 0 |
2830 | #define regMMEA2_SDP_ARB_GMI 0x066d |
2831 | #define regMMEA2_SDP_ARB_GMI_BASE_IDX 0 |
2832 | #define regMMEA2_SDP_ARB_FINAL 0x066e |
2833 | #define regMMEA2_SDP_ARB_FINAL_BASE_IDX 0 |
2834 | #define regMMEA2_SDP_DRAM_PRIORITY 0x066f |
2835 | #define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 0 |
2836 | #define regMMEA2_SDP_GMI_PRIORITY 0x0670 |
2837 | #define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX 0 |
2838 | #define regMMEA2_SDP_IO_PRIORITY 0x0671 |
2839 | #define regMMEA2_SDP_IO_PRIORITY_BASE_IDX 0 |
2840 | #define regMMEA2_SDP_CREDITS 0x0672 |
2841 | #define regMMEA2_SDP_CREDITS_BASE_IDX 0 |
2842 | #define regMMEA2_SDP_TAG_RESERVE0 0x0673 |
2843 | #define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX 0 |
2844 | #define regMMEA2_SDP_TAG_RESERVE1 0x0674 |
2845 | #define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX 0 |
2846 | #define regMMEA2_SDP_VCC_RESERVE0 0x0675 |
2847 | #define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX 0 |
2848 | #define regMMEA2_SDP_VCC_RESERVE1 0x0676 |
2849 | #define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX 0 |
2850 | #define regMMEA2_SDP_VCD_RESERVE0 0x0677 |
2851 | #define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX 0 |
2852 | #define regMMEA2_SDP_VCD_RESERVE1 0x0678 |
2853 | #define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX 0 |
2854 | #define regMMEA2_SDP_REQ_CNTL 0x0679 |
2855 | #define regMMEA2_SDP_REQ_CNTL_BASE_IDX 0 |
2856 | #define regMMEA2_MISC 0x067a |
2857 | #define regMMEA2_MISC_BASE_IDX 0 |
2858 | #define regMMEA2_LATENCY_SAMPLING 0x067b |
2859 | #define regMMEA2_LATENCY_SAMPLING_BASE_IDX 0 |
2860 | #define regMMEA2_PERFCOUNTER_LO 0x067c |
2861 | #define regMMEA2_PERFCOUNTER_LO_BASE_IDX 0 |
2862 | #define regMMEA2_PERFCOUNTER_HI 0x067d |
2863 | #define regMMEA2_PERFCOUNTER_HI_BASE_IDX 0 |
2864 | #define regMMEA2_PERFCOUNTER0_CFG 0x067e |
2865 | #define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX 0 |
2866 | #define regMMEA2_PERFCOUNTER1_CFG 0x067f |
2867 | #define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0 |
2868 | #define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680 |
2869 | #define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
2870 | #define regMMEA2_EDC_CNT 0x0686 |
2871 | #define regMMEA2_EDC_CNT_BASE_IDX 0 |
2872 | #define regMMEA2_EDC_CNT2 0x0687 |
2873 | #define regMMEA2_EDC_CNT2_BASE_IDX 0 |
2874 | #define regMMEA2_DSM_CNTL 0x0688 |
2875 | #define regMMEA2_DSM_CNTL_BASE_IDX 0 |
2876 | #define regMMEA2_DSM_CNTLA 0x0689 |
2877 | #define regMMEA2_DSM_CNTLA_BASE_IDX 0 |
2878 | #define regMMEA2_DSM_CNTLB 0x068a |
2879 | #define regMMEA2_DSM_CNTLB_BASE_IDX 0 |
2880 | #define regMMEA2_DSM_CNTL2 0x068b |
2881 | #define regMMEA2_DSM_CNTL2_BASE_IDX 0 |
2882 | #define regMMEA2_DSM_CNTL2A 0x068c |
2883 | #define regMMEA2_DSM_CNTL2A_BASE_IDX 0 |
2884 | #define regMMEA2_DSM_CNTL2B 0x068d |
2885 | #define regMMEA2_DSM_CNTL2B_BASE_IDX 0 |
2886 | #define regMMEA2_CGTT_CLK_CTRL 0x068f |
2887 | #define regMMEA2_CGTT_CLK_CTRL_BASE_IDX 0 |
2888 | #define regMMEA2_EDC_MODE 0x0690 |
2889 | #define regMMEA2_EDC_MODE_BASE_IDX 0 |
2890 | #define regMMEA2_ERR_STATUS 0x0691 |
2891 | #define regMMEA2_ERR_STATUS_BASE_IDX 0 |
2892 | #define regMMEA2_MISC2 0x0692 |
2893 | #define regMMEA2_MISC2_BASE_IDX 0 |
2894 | #define regMMEA2_ADDRDEC_SELECT 0x0693 |
2895 | #define regMMEA2_ADDRDEC_SELECT_BASE_IDX 0 |
2896 | #define regMMEA2_EDC_CNT3 0x0694 |
2897 | #define regMMEA2_EDC_CNT3_BASE_IDX 0 |
2898 | #define regMMEA2_MISC_AON 0x0695 |
2899 | #define regMMEA2_MISC_AON_BASE_IDX 0 |
2900 | |
2901 | |
2902 | // addressBlock: mmhub_ea_mmeadec3 |
2903 | // base address: 0x69b00 |
2904 | #define regMMEA3_DRAM_RD_CLI2GRP_MAP0 0x06c0 |
2905 | #define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2906 | #define regMMEA3_DRAM_RD_CLI2GRP_MAP1 0x06c1 |
2907 | #define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2908 | #define regMMEA3_DRAM_WR_CLI2GRP_MAP0 0x06c2 |
2909 | #define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2910 | #define regMMEA3_DRAM_WR_CLI2GRP_MAP1 0x06c3 |
2911 | #define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2912 | #define regMMEA3_DRAM_RD_GRP2VC_MAP 0x06c4 |
2913 | #define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
2914 | #define regMMEA3_DRAM_WR_GRP2VC_MAP 0x06c5 |
2915 | #define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
2916 | #define regMMEA3_DRAM_RD_LAZY 0x06c6 |
2917 | #define regMMEA3_DRAM_RD_LAZY_BASE_IDX 0 |
2918 | #define regMMEA3_DRAM_WR_LAZY 0x06c7 |
2919 | #define regMMEA3_DRAM_WR_LAZY_BASE_IDX 0 |
2920 | #define regMMEA3_DRAM_RD_CAM_CNTL 0x06c8 |
2921 | #define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
2922 | #define regMMEA3_DRAM_WR_CAM_CNTL 0x06c9 |
2923 | #define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
2924 | #define regMMEA3_DRAM_PAGE_BURST 0x06ca |
2925 | #define regMMEA3_DRAM_PAGE_BURST_BASE_IDX 0 |
2926 | #define regMMEA3_DRAM_RD_PRI_AGE 0x06cb |
2927 | #define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 0 |
2928 | #define regMMEA3_DRAM_WR_PRI_AGE 0x06cc |
2929 | #define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 0 |
2930 | #define regMMEA3_DRAM_RD_PRI_QUEUING 0x06cd |
2931 | #define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
2932 | #define regMMEA3_DRAM_WR_PRI_QUEUING 0x06ce |
2933 | #define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
2934 | #define regMMEA3_DRAM_RD_PRI_FIXED 0x06cf |
2935 | #define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
2936 | #define regMMEA3_DRAM_WR_PRI_FIXED 0x06d0 |
2937 | #define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
2938 | #define regMMEA3_DRAM_RD_PRI_URGENCY 0x06d1 |
2939 | #define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
2940 | #define regMMEA3_DRAM_WR_PRI_URGENCY 0x06d2 |
2941 | #define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
2942 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x06d3 |
2943 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2944 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x06d4 |
2945 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
2946 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x06d5 |
2947 | #define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
2948 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x06d6 |
2949 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
2950 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x06d7 |
2951 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
2952 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x06d8 |
2953 | #define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
2954 | #define regMMEA3_GMI_RD_CLI2GRP_MAP0 0x06d9 |
2955 | #define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
2956 | #define regMMEA3_GMI_RD_CLI2GRP_MAP1 0x06da |
2957 | #define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
2958 | #define regMMEA3_GMI_WR_CLI2GRP_MAP0 0x06db |
2959 | #define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
2960 | #define regMMEA3_GMI_WR_CLI2GRP_MAP1 0x06dc |
2961 | #define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
2962 | #define regMMEA3_GMI_RD_GRP2VC_MAP 0x06dd |
2963 | #define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
2964 | #define regMMEA3_GMI_WR_GRP2VC_MAP 0x06de |
2965 | #define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
2966 | #define regMMEA3_GMI_RD_LAZY 0x06df |
2967 | #define regMMEA3_GMI_RD_LAZY_BASE_IDX 0 |
2968 | #define regMMEA3_GMI_WR_LAZY 0x06e0 |
2969 | #define regMMEA3_GMI_WR_LAZY_BASE_IDX 0 |
2970 | #define regMMEA3_GMI_RD_CAM_CNTL 0x06e1 |
2971 | #define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 0 |
2972 | #define regMMEA3_GMI_WR_CAM_CNTL 0x06e2 |
2973 | #define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 0 |
2974 | #define regMMEA3_GMI_PAGE_BURST 0x06e3 |
2975 | #define regMMEA3_GMI_PAGE_BURST_BASE_IDX 0 |
2976 | #define regMMEA3_GMI_RD_PRI_AGE 0x06e4 |
2977 | #define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX 0 |
2978 | #define regMMEA3_GMI_WR_PRI_AGE 0x06e5 |
2979 | #define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX 0 |
2980 | #define regMMEA3_GMI_RD_PRI_QUEUING 0x06e6 |
2981 | #define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
2982 | #define regMMEA3_GMI_WR_PRI_QUEUING 0x06e7 |
2983 | #define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
2984 | #define regMMEA3_GMI_RD_PRI_FIXED 0x06e8 |
2985 | #define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 0 |
2986 | #define regMMEA3_GMI_WR_PRI_FIXED 0x06e9 |
2987 | #define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 0 |
2988 | #define regMMEA3_GMI_RD_PRI_URGENCY 0x06ea |
2989 | #define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
2990 | #define regMMEA3_GMI_WR_PRI_URGENCY 0x06eb |
2991 | #define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
2992 | #define regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x06ec |
2993 | #define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
2994 | #define regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x06ed |
2995 | #define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
2996 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI1 0x06ee |
2997 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
2998 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI2 0x06ef |
2999 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3000 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI3 0x06f0 |
3001 | #define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3002 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI1 0x06f1 |
3003 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3004 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI2 0x06f2 |
3005 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3006 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI3 0x06f3 |
3007 | #define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3008 | #define regMMEA3_ADDRNORM_BASE_ADDR0 0x06f4 |
3009 | #define regMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
3010 | #define regMMEA3_ADDRNORM_LIMIT_ADDR0 0x06f5 |
3011 | #define regMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
3012 | #define regMMEA3_ADDRNORM_BASE_ADDR1 0x06f6 |
3013 | #define regMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
3014 | #define regMMEA3_ADDRNORM_LIMIT_ADDR1 0x06f7 |
3015 | #define regMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
3016 | #define regMMEA3_ADDRNORM_OFFSET_ADDR1 0x06f8 |
3017 | #define regMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
3018 | #define regMMEA3_ADDRNORM_BASE_ADDR2 0x06f9 |
3019 | #define regMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
3020 | #define regMMEA3_ADDRNORM_LIMIT_ADDR2 0x06fa |
3021 | #define regMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
3022 | #define regMMEA3_ADDRNORM_BASE_ADDR3 0x06fb |
3023 | #define regMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
3024 | #define regMMEA3_ADDRNORM_LIMIT_ADDR3 0x06fc |
3025 | #define regMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
3026 | #define regMMEA3_ADDRNORM_OFFSET_ADDR3 0x06fd |
3027 | #define regMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
3028 | #define regMMEA3_ADDRNORM_MEGABASE_ADDR0 0x06fe |
3029 | #define regMMEA3_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
3030 | #define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0 0x06ff |
3031 | #define regMMEA3_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
3032 | #define regMMEA3_ADDRNORM_MEGABASE_ADDR1 0x0700 |
3033 | #define regMMEA3_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
3034 | #define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1 0x0701 |
3035 | #define regMMEA3_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
3036 | #define regMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0703 |
3037 | #define regMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
3038 | #define regMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0704 |
3039 | #define regMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
3040 | #define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0705 |
3041 | #define regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
3042 | #define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0706 |
3043 | #define regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
3044 | #define regMMEA3_ADDRDEC_BANK_CFG 0x0707 |
3045 | #define regMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 0 |
3046 | #define regMMEA3_ADDRDEC_MISC_CFG 0x0708 |
3047 | #define regMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 0 |
3048 | #define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0713 |
3049 | #define regMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
3050 | #define regMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x071e |
3051 | #define regMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
3052 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x071f |
3053 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
3054 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x0720 |
3055 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
3056 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x0721 |
3057 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
3058 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x0722 |
3059 | #define regMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
3060 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x0723 |
3061 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
3062 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x0724 |
3063 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
3064 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x0725 |
3065 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
3066 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x0726 |
3067 | #define regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
3068 | #define regMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x0727 |
3069 | #define regMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
3070 | #define regMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x0728 |
3071 | #define regMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
3072 | #define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x0729 |
3073 | #define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
3074 | #define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x072a |
3075 | #define regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
3076 | #define regMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x072b |
3077 | #define regMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
3078 | #define regMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x072c |
3079 | #define regMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
3080 | #define regMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x072d |
3081 | #define regMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
3082 | #define regMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x072e |
3083 | #define regMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
3084 | #define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x072f |
3085 | #define regMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
3086 | #define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x0730 |
3087 | #define regMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
3088 | #define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x0731 |
3089 | #define regMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
3090 | #define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x0732 |
3091 | #define regMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
3092 | #define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x0733 |
3093 | #define regMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
3094 | #define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x0734 |
3095 | #define regMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
3096 | #define regMMEA3_ADDRDEC0_RM_SEL_CS01 0x0735 |
3097 | #define regMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
3098 | #define regMMEA3_ADDRDEC0_RM_SEL_CS23 0x0736 |
3099 | #define regMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
3100 | #define regMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x0737 |
3101 | #define regMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
3102 | #define regMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x0738 |
3103 | #define regMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
3104 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x0739 |
3105 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
3106 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x073a |
3107 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
3108 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x073b |
3109 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
3110 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x073c |
3111 | #define regMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
3112 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x073d |
3113 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
3114 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x073e |
3115 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
3116 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x073f |
3117 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
3118 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x0740 |
3119 | #define regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
3120 | #define regMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x0741 |
3121 | #define regMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
3122 | #define regMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x0742 |
3123 | #define regMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
3124 | #define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x0743 |
3125 | #define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
3126 | #define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x0744 |
3127 | #define regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
3128 | #define regMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x0745 |
3129 | #define regMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
3130 | #define regMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x0746 |
3131 | #define regMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
3132 | #define regMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x0747 |
3133 | #define regMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
3134 | #define regMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x0748 |
3135 | #define regMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
3136 | #define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x0749 |
3137 | #define regMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
3138 | #define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x074a |
3139 | #define regMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
3140 | #define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x074b |
3141 | #define regMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
3142 | #define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x074c |
3143 | #define regMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
3144 | #define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x074d |
3145 | #define regMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
3146 | #define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x074e |
3147 | #define regMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
3148 | #define regMMEA3_ADDRDEC1_RM_SEL_CS01 0x074f |
3149 | #define regMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
3150 | #define regMMEA3_ADDRDEC1_RM_SEL_CS23 0x0750 |
3151 | #define regMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
3152 | #define regMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x0751 |
3153 | #define regMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
3154 | #define regMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x0752 |
3155 | #define regMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
3156 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x0753 |
3157 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
3158 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x0754 |
3159 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
3160 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x0755 |
3161 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
3162 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x0756 |
3163 | #define regMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
3164 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x0757 |
3165 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
3166 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x0758 |
3167 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
3168 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x0759 |
3169 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
3170 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x075a |
3171 | #define regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
3172 | #define regMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x075b |
3173 | #define regMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
3174 | #define regMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x075c |
3175 | #define regMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
3176 | #define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x075d |
3177 | #define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
3178 | #define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x075e |
3179 | #define regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
3180 | #define regMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x075f |
3181 | #define regMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
3182 | #define regMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x0760 |
3183 | #define regMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
3184 | #define regMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x0761 |
3185 | #define regMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
3186 | #define regMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x0762 |
3187 | #define regMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
3188 | #define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x0763 |
3189 | #define regMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
3190 | #define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x0764 |
3191 | #define regMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
3192 | #define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x0765 |
3193 | #define regMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
3194 | #define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x0766 |
3195 | #define regMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
3196 | #define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x0767 |
3197 | #define regMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
3198 | #define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x0768 |
3199 | #define regMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
3200 | #define regMMEA3_ADDRDEC2_RM_SEL_CS01 0x0769 |
3201 | #define regMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
3202 | #define regMMEA3_ADDRDEC2_RM_SEL_CS23 0x076a |
3203 | #define regMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
3204 | #define regMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x076b |
3205 | #define regMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
3206 | #define regMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x076c |
3207 | #define regMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
3208 | #define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x076d |
3209 | #define regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
3210 | #define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x076e |
3211 | #define regMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
3212 | #define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0 0x0791 |
3213 | #define regMMEA3_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
3214 | #define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1 0x0792 |
3215 | #define regMMEA3_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
3216 | #define regMMEA3_ADDRNORMDRAM_MASKING 0x0793 |
3217 | #define regMMEA3_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
3218 | #define regMMEA3_ADDRNORMGMI_MASKING 0x0794 |
3219 | #define regMMEA3_ADDRNORMGMI_MASKING_BASE_IDX 0 |
3220 | #define regMMEA3_IO_RD_CLI2GRP_MAP0 0x0795 |
3221 | #define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3222 | #define regMMEA3_IO_RD_CLI2GRP_MAP1 0x0796 |
3223 | #define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3224 | #define regMMEA3_IO_WR_CLI2GRP_MAP0 0x0797 |
3225 | #define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3226 | #define regMMEA3_IO_WR_CLI2GRP_MAP1 0x0798 |
3227 | #define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3228 | #define regMMEA3_IO_RD_COMBINE_FLUSH 0x0799 |
3229 | #define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
3230 | #define regMMEA3_IO_WR_COMBINE_FLUSH 0x079a |
3231 | #define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
3232 | #define regMMEA3_IO_GROUP_BURST 0x079b |
3233 | #define regMMEA3_IO_GROUP_BURST_BASE_IDX 0 |
3234 | #define regMMEA3_IO_RD_PRI_AGE 0x079c |
3235 | #define regMMEA3_IO_RD_PRI_AGE_BASE_IDX 0 |
3236 | #define regMMEA3_IO_WR_PRI_AGE 0x079d |
3237 | #define regMMEA3_IO_WR_PRI_AGE_BASE_IDX 0 |
3238 | #define regMMEA3_IO_RD_PRI_QUEUING 0x079e |
3239 | #define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 0 |
3240 | #define regMMEA3_IO_WR_PRI_QUEUING 0x079f |
3241 | #define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 0 |
3242 | #define regMMEA3_IO_RD_PRI_FIXED 0x07a0 |
3243 | #define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX 0 |
3244 | #define regMMEA3_IO_WR_PRI_FIXED 0x07a1 |
3245 | #define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX 0 |
3246 | #define regMMEA3_IO_RD_PRI_URGENCY 0x07a2 |
3247 | #define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 0 |
3248 | #define regMMEA3_IO_WR_PRI_URGENCY 0x07a3 |
3249 | #define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 0 |
3250 | #define regMMEA3_IO_RD_PRI_URGENCY_MASKING 0x07a4 |
3251 | #define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
3252 | #define regMMEA3_IO_WR_PRI_URGENCY_MASKING 0x07a5 |
3253 | #define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
3254 | #define regMMEA3_IO_RD_PRI_QUANT_PRI1 0x07a6 |
3255 | #define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3256 | #define regMMEA3_IO_RD_PRI_QUANT_PRI2 0x07a7 |
3257 | #define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3258 | #define regMMEA3_IO_RD_PRI_QUANT_PRI3 0x07a8 |
3259 | #define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3260 | #define regMMEA3_IO_WR_PRI_QUANT_PRI1 0x07a9 |
3261 | #define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3262 | #define regMMEA3_IO_WR_PRI_QUANT_PRI2 0x07aa |
3263 | #define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3264 | #define regMMEA3_IO_WR_PRI_QUANT_PRI3 0x07ab |
3265 | #define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3266 | #define regMMEA3_SDP_ARB_DRAM 0x07ac |
3267 | #define regMMEA3_SDP_ARB_DRAM_BASE_IDX 0 |
3268 | #define regMMEA3_SDP_ARB_GMI 0x07ad |
3269 | #define regMMEA3_SDP_ARB_GMI_BASE_IDX 0 |
3270 | #define regMMEA3_SDP_ARB_FINAL 0x07ae |
3271 | #define regMMEA3_SDP_ARB_FINAL_BASE_IDX 0 |
3272 | #define regMMEA3_SDP_DRAM_PRIORITY 0x07af |
3273 | #define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 0 |
3274 | #define regMMEA3_SDP_GMI_PRIORITY 0x07b0 |
3275 | #define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX 0 |
3276 | #define regMMEA3_SDP_IO_PRIORITY 0x07b1 |
3277 | #define regMMEA3_SDP_IO_PRIORITY_BASE_IDX 0 |
3278 | #define regMMEA3_SDP_CREDITS 0x07b2 |
3279 | #define regMMEA3_SDP_CREDITS_BASE_IDX 0 |
3280 | #define regMMEA3_SDP_TAG_RESERVE0 0x07b3 |
3281 | #define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX 0 |
3282 | #define regMMEA3_SDP_TAG_RESERVE1 0x07b4 |
3283 | #define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX 0 |
3284 | #define regMMEA3_SDP_VCC_RESERVE0 0x07b5 |
3285 | #define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX 0 |
3286 | #define regMMEA3_SDP_VCC_RESERVE1 0x07b6 |
3287 | #define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX 0 |
3288 | #define regMMEA3_SDP_VCD_RESERVE0 0x07b7 |
3289 | #define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX 0 |
3290 | #define regMMEA3_SDP_VCD_RESERVE1 0x07b8 |
3291 | #define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX 0 |
3292 | #define regMMEA3_SDP_REQ_CNTL 0x07b9 |
3293 | #define regMMEA3_SDP_REQ_CNTL_BASE_IDX 0 |
3294 | #define regMMEA3_MISC 0x07ba |
3295 | #define regMMEA3_MISC_BASE_IDX 0 |
3296 | #define regMMEA3_LATENCY_SAMPLING 0x07bb |
3297 | #define regMMEA3_LATENCY_SAMPLING_BASE_IDX 0 |
3298 | #define regMMEA3_PERFCOUNTER_LO 0x07bc |
3299 | #define regMMEA3_PERFCOUNTER_LO_BASE_IDX 0 |
3300 | #define regMMEA3_PERFCOUNTER_HI 0x07bd |
3301 | #define regMMEA3_PERFCOUNTER_HI_BASE_IDX 0 |
3302 | #define regMMEA3_PERFCOUNTER0_CFG 0x07be |
3303 | #define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX 0 |
3304 | #define regMMEA3_PERFCOUNTER1_CFG 0x07bf |
3305 | #define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0 |
3306 | #define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0 |
3307 | #define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
3308 | #define regMMEA3_EDC_CNT 0x07c6 |
3309 | #define regMMEA3_EDC_CNT_BASE_IDX 0 |
3310 | #define regMMEA3_EDC_CNT2 0x07c7 |
3311 | #define regMMEA3_EDC_CNT2_BASE_IDX 0 |
3312 | #define regMMEA3_DSM_CNTL 0x07c8 |
3313 | #define regMMEA3_DSM_CNTL_BASE_IDX 0 |
3314 | #define regMMEA3_DSM_CNTLA 0x07c9 |
3315 | #define regMMEA3_DSM_CNTLA_BASE_IDX 0 |
3316 | #define regMMEA3_DSM_CNTLB 0x07ca |
3317 | #define regMMEA3_DSM_CNTLB_BASE_IDX 0 |
3318 | #define regMMEA3_DSM_CNTL2 0x07cb |
3319 | #define regMMEA3_DSM_CNTL2_BASE_IDX 0 |
3320 | #define regMMEA3_DSM_CNTL2A 0x07cc |
3321 | #define regMMEA3_DSM_CNTL2A_BASE_IDX 0 |
3322 | #define regMMEA3_DSM_CNTL2B 0x07cd |
3323 | #define regMMEA3_DSM_CNTL2B_BASE_IDX 0 |
3324 | #define regMMEA3_CGTT_CLK_CTRL 0x07cf |
3325 | #define regMMEA3_CGTT_CLK_CTRL_BASE_IDX 0 |
3326 | #define regMMEA3_EDC_MODE 0x07d0 |
3327 | #define regMMEA3_EDC_MODE_BASE_IDX 0 |
3328 | #define regMMEA3_ERR_STATUS 0x07d1 |
3329 | #define regMMEA3_ERR_STATUS_BASE_IDX 0 |
3330 | #define regMMEA3_MISC2 0x07d2 |
3331 | #define regMMEA3_MISC2_BASE_IDX 0 |
3332 | #define regMMEA3_ADDRDEC_SELECT 0x07d3 |
3333 | #define regMMEA3_ADDRDEC_SELECT_BASE_IDX 0 |
3334 | #define regMMEA3_EDC_CNT3 0x07d4 |
3335 | #define regMMEA3_EDC_CNT3_BASE_IDX 0 |
3336 | #define regMMEA3_MISC_AON 0x07d5 |
3337 | #define regMMEA3_MISC_AON_BASE_IDX 0 |
3338 | |
3339 | |
3340 | // addressBlock: mmhub_ea_mmeadec4 |
3341 | // base address: 0x6a000 |
3342 | #define regMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0800 |
3343 | #define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3344 | #define regMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0801 |
3345 | #define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3346 | #define regMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0802 |
3347 | #define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3348 | #define regMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0803 |
3349 | #define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3350 | #define regMMEA4_DRAM_RD_GRP2VC_MAP 0x0804 |
3351 | #define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
3352 | #define regMMEA4_DRAM_WR_GRP2VC_MAP 0x0805 |
3353 | #define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
3354 | #define regMMEA4_DRAM_RD_LAZY 0x0806 |
3355 | #define regMMEA4_DRAM_RD_LAZY_BASE_IDX 0 |
3356 | #define regMMEA4_DRAM_WR_LAZY 0x0807 |
3357 | #define regMMEA4_DRAM_WR_LAZY_BASE_IDX 0 |
3358 | #define regMMEA4_DRAM_RD_CAM_CNTL 0x0808 |
3359 | #define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
3360 | #define regMMEA4_DRAM_WR_CAM_CNTL 0x0809 |
3361 | #define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
3362 | #define regMMEA4_DRAM_PAGE_BURST 0x080a |
3363 | #define regMMEA4_DRAM_PAGE_BURST_BASE_IDX 0 |
3364 | #define regMMEA4_DRAM_RD_PRI_AGE 0x080b |
3365 | #define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 0 |
3366 | #define regMMEA4_DRAM_WR_PRI_AGE 0x080c |
3367 | #define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 0 |
3368 | #define regMMEA4_DRAM_RD_PRI_QUEUING 0x080d |
3369 | #define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
3370 | #define regMMEA4_DRAM_WR_PRI_QUEUING 0x080e |
3371 | #define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
3372 | #define regMMEA4_DRAM_RD_PRI_FIXED 0x080f |
3373 | #define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
3374 | #define regMMEA4_DRAM_WR_PRI_FIXED 0x0810 |
3375 | #define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
3376 | #define regMMEA4_DRAM_RD_PRI_URGENCY 0x0811 |
3377 | #define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
3378 | #define regMMEA4_DRAM_WR_PRI_URGENCY 0x0812 |
3379 | #define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
3380 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0813 |
3381 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3382 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0814 |
3383 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3384 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0815 |
3385 | #define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3386 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0816 |
3387 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3388 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0817 |
3389 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3390 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0818 |
3391 | #define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3392 | #define regMMEA4_GMI_RD_CLI2GRP_MAP0 0x0819 |
3393 | #define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3394 | #define regMMEA4_GMI_RD_CLI2GRP_MAP1 0x081a |
3395 | #define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3396 | #define regMMEA4_GMI_WR_CLI2GRP_MAP0 0x081b |
3397 | #define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3398 | #define regMMEA4_GMI_WR_CLI2GRP_MAP1 0x081c |
3399 | #define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3400 | #define regMMEA4_GMI_RD_GRP2VC_MAP 0x081d |
3401 | #define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
3402 | #define regMMEA4_GMI_WR_GRP2VC_MAP 0x081e |
3403 | #define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
3404 | #define regMMEA4_GMI_RD_LAZY 0x081f |
3405 | #define regMMEA4_GMI_RD_LAZY_BASE_IDX 0 |
3406 | #define regMMEA4_GMI_WR_LAZY 0x0820 |
3407 | #define regMMEA4_GMI_WR_LAZY_BASE_IDX 0 |
3408 | #define regMMEA4_GMI_RD_CAM_CNTL 0x0821 |
3409 | #define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 0 |
3410 | #define regMMEA4_GMI_WR_CAM_CNTL 0x0822 |
3411 | #define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 0 |
3412 | #define regMMEA4_GMI_PAGE_BURST 0x0823 |
3413 | #define regMMEA4_GMI_PAGE_BURST_BASE_IDX 0 |
3414 | #define regMMEA4_GMI_RD_PRI_AGE 0x0824 |
3415 | #define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX 0 |
3416 | #define regMMEA4_GMI_WR_PRI_AGE 0x0825 |
3417 | #define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX 0 |
3418 | #define regMMEA4_GMI_RD_PRI_QUEUING 0x0826 |
3419 | #define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
3420 | #define regMMEA4_GMI_WR_PRI_QUEUING 0x0827 |
3421 | #define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
3422 | #define regMMEA4_GMI_RD_PRI_FIXED 0x0828 |
3423 | #define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 0 |
3424 | #define regMMEA4_GMI_WR_PRI_FIXED 0x0829 |
3425 | #define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 0 |
3426 | #define regMMEA4_GMI_RD_PRI_URGENCY 0x082a |
3427 | #define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
3428 | #define regMMEA4_GMI_WR_PRI_URGENCY 0x082b |
3429 | #define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
3430 | #define regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x082c |
3431 | #define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
3432 | #define regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x082d |
3433 | #define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
3434 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI1 0x082e |
3435 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3436 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI2 0x082f |
3437 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3438 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI3 0x0830 |
3439 | #define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3440 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI1 0x0831 |
3441 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3442 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI2 0x0832 |
3443 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3444 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI3 0x0833 |
3445 | #define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3446 | #define regMMEA4_ADDRNORM_BASE_ADDR0 0x0834 |
3447 | #define regMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
3448 | #define regMMEA4_ADDRNORM_LIMIT_ADDR0 0x0835 |
3449 | #define regMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
3450 | #define regMMEA4_ADDRNORM_BASE_ADDR1 0x0836 |
3451 | #define regMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
3452 | #define regMMEA4_ADDRNORM_LIMIT_ADDR1 0x0837 |
3453 | #define regMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
3454 | #define regMMEA4_ADDRNORM_OFFSET_ADDR1 0x0838 |
3455 | #define regMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
3456 | #define regMMEA4_ADDRNORM_BASE_ADDR2 0x0839 |
3457 | #define regMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
3458 | #define regMMEA4_ADDRNORM_LIMIT_ADDR2 0x083a |
3459 | #define regMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
3460 | #define regMMEA4_ADDRNORM_BASE_ADDR3 0x083b |
3461 | #define regMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
3462 | #define regMMEA4_ADDRNORM_LIMIT_ADDR3 0x083c |
3463 | #define regMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
3464 | #define regMMEA4_ADDRNORM_OFFSET_ADDR3 0x083d |
3465 | #define regMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
3466 | #define regMMEA4_ADDRNORM_MEGABASE_ADDR0 0x083e |
3467 | #define regMMEA4_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
3468 | #define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0 0x083f |
3469 | #define regMMEA4_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
3470 | #define regMMEA4_ADDRNORM_MEGABASE_ADDR1 0x0840 |
3471 | #define regMMEA4_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
3472 | #define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1 0x0841 |
3473 | #define regMMEA4_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
3474 | #define regMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x0843 |
3475 | #define regMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
3476 | #define regMMEA4_ADDRNORMGMI_HOLE_CNTL 0x0844 |
3477 | #define regMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
3478 | #define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0845 |
3479 | #define regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
3480 | #define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0846 |
3481 | #define regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
3482 | #define regMMEA4_ADDRDEC_BANK_CFG 0x0847 |
3483 | #define regMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 0 |
3484 | #define regMMEA4_ADDRDEC_MISC_CFG 0x0848 |
3485 | #define regMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 0 |
3486 | #define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x0853 |
3487 | #define regMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
3488 | #define regMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x085e |
3489 | #define regMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
3490 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x085f |
3491 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
3492 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x0860 |
3493 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
3494 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x0861 |
3495 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
3496 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x0862 |
3497 | #define regMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
3498 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x0863 |
3499 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
3500 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x0864 |
3501 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
3502 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x0865 |
3503 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
3504 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x0866 |
3505 | #define regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
3506 | #define regMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x0867 |
3507 | #define regMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
3508 | #define regMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x0868 |
3509 | #define regMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
3510 | #define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x0869 |
3511 | #define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
3512 | #define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x086a |
3513 | #define regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
3514 | #define regMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x086b |
3515 | #define regMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
3516 | #define regMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x086c |
3517 | #define regMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
3518 | #define regMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x086d |
3519 | #define regMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
3520 | #define regMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x086e |
3521 | #define regMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
3522 | #define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x086f |
3523 | #define regMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
3524 | #define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x0870 |
3525 | #define regMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
3526 | #define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x0871 |
3527 | #define regMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
3528 | #define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x0872 |
3529 | #define regMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
3530 | #define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x0873 |
3531 | #define regMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
3532 | #define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x0874 |
3533 | #define regMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
3534 | #define regMMEA4_ADDRDEC0_RM_SEL_CS01 0x0875 |
3535 | #define regMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
3536 | #define regMMEA4_ADDRDEC0_RM_SEL_CS23 0x0876 |
3537 | #define regMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
3538 | #define regMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x0877 |
3539 | #define regMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
3540 | #define regMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x0878 |
3541 | #define regMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
3542 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x0879 |
3543 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
3544 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x087a |
3545 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
3546 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x087b |
3547 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
3548 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x087c |
3549 | #define regMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
3550 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x087d |
3551 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
3552 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x087e |
3553 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
3554 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x087f |
3555 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
3556 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0880 |
3557 | #define regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
3558 | #define regMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0881 |
3559 | #define regMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
3560 | #define regMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0882 |
3561 | #define regMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
3562 | #define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0883 |
3563 | #define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
3564 | #define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0884 |
3565 | #define regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
3566 | #define regMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0885 |
3567 | #define regMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
3568 | #define regMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0886 |
3569 | #define regMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
3570 | #define regMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0887 |
3571 | #define regMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
3572 | #define regMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0888 |
3573 | #define regMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
3574 | #define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0889 |
3575 | #define regMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
3576 | #define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x088a |
3577 | #define regMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
3578 | #define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x088b |
3579 | #define regMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
3580 | #define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x088c |
3581 | #define regMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
3582 | #define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x088d |
3583 | #define regMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
3584 | #define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x088e |
3585 | #define regMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
3586 | #define regMMEA4_ADDRDEC1_RM_SEL_CS01 0x088f |
3587 | #define regMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
3588 | #define regMMEA4_ADDRDEC1_RM_SEL_CS23 0x0890 |
3589 | #define regMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
3590 | #define regMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0891 |
3591 | #define regMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
3592 | #define regMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0892 |
3593 | #define regMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
3594 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0893 |
3595 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
3596 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0894 |
3597 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
3598 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0895 |
3599 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
3600 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0896 |
3601 | #define regMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
3602 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0897 |
3603 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
3604 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0898 |
3605 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
3606 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0899 |
3607 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
3608 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x089a |
3609 | #define regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
3610 | #define regMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x089b |
3611 | #define regMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
3612 | #define regMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x089c |
3613 | #define regMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
3614 | #define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x089d |
3615 | #define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
3616 | #define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x089e |
3617 | #define regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
3618 | #define regMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x089f |
3619 | #define regMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
3620 | #define regMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x08a0 |
3621 | #define regMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
3622 | #define regMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x08a1 |
3623 | #define regMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
3624 | #define regMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x08a2 |
3625 | #define regMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
3626 | #define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x08a3 |
3627 | #define regMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
3628 | #define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x08a4 |
3629 | #define regMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
3630 | #define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x08a5 |
3631 | #define regMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
3632 | #define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x08a6 |
3633 | #define regMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
3634 | #define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x08a7 |
3635 | #define regMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
3636 | #define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x08a8 |
3637 | #define regMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
3638 | #define regMMEA4_ADDRDEC2_RM_SEL_CS01 0x08a9 |
3639 | #define regMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
3640 | #define regMMEA4_ADDRDEC2_RM_SEL_CS23 0x08aa |
3641 | #define regMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
3642 | #define regMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x08ab |
3643 | #define regMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
3644 | #define regMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x08ac |
3645 | #define regMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
3646 | #define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x08ad |
3647 | #define regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
3648 | #define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x08ae |
3649 | #define regMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
3650 | #define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0 0x08d1 |
3651 | #define regMMEA4_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
3652 | #define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1 0x08d2 |
3653 | #define regMMEA4_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
3654 | #define regMMEA4_ADDRNORMDRAM_MASKING 0x08d3 |
3655 | #define regMMEA4_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
3656 | #define regMMEA4_ADDRNORMGMI_MASKING 0x08d4 |
3657 | #define regMMEA4_ADDRNORMGMI_MASKING_BASE_IDX 0 |
3658 | #define regMMEA4_IO_RD_CLI2GRP_MAP0 0x08d5 |
3659 | #define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3660 | #define regMMEA4_IO_RD_CLI2GRP_MAP1 0x08d6 |
3661 | #define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3662 | #define regMMEA4_IO_WR_CLI2GRP_MAP0 0x08d7 |
3663 | #define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3664 | #define regMMEA4_IO_WR_CLI2GRP_MAP1 0x08d8 |
3665 | #define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3666 | #define regMMEA4_IO_RD_COMBINE_FLUSH 0x08d9 |
3667 | #define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
3668 | #define regMMEA4_IO_WR_COMBINE_FLUSH 0x08da |
3669 | #define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
3670 | #define regMMEA4_IO_GROUP_BURST 0x08db |
3671 | #define regMMEA4_IO_GROUP_BURST_BASE_IDX 0 |
3672 | #define regMMEA4_IO_RD_PRI_AGE 0x08dc |
3673 | #define regMMEA4_IO_RD_PRI_AGE_BASE_IDX 0 |
3674 | #define regMMEA4_IO_WR_PRI_AGE 0x08dd |
3675 | #define regMMEA4_IO_WR_PRI_AGE_BASE_IDX 0 |
3676 | #define regMMEA4_IO_RD_PRI_QUEUING 0x08de |
3677 | #define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 0 |
3678 | #define regMMEA4_IO_WR_PRI_QUEUING 0x08df |
3679 | #define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 0 |
3680 | #define regMMEA4_IO_RD_PRI_FIXED 0x08e0 |
3681 | #define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX 0 |
3682 | #define regMMEA4_IO_WR_PRI_FIXED 0x08e1 |
3683 | #define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX 0 |
3684 | #define regMMEA4_IO_RD_PRI_URGENCY 0x08e2 |
3685 | #define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 0 |
3686 | #define regMMEA4_IO_WR_PRI_URGENCY 0x08e3 |
3687 | #define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 0 |
3688 | #define regMMEA4_IO_RD_PRI_URGENCY_MASKING 0x08e4 |
3689 | #define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
3690 | #define regMMEA4_IO_WR_PRI_URGENCY_MASKING 0x08e5 |
3691 | #define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
3692 | #define regMMEA4_IO_RD_PRI_QUANT_PRI1 0x08e6 |
3693 | #define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3694 | #define regMMEA4_IO_RD_PRI_QUANT_PRI2 0x08e7 |
3695 | #define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3696 | #define regMMEA4_IO_RD_PRI_QUANT_PRI3 0x08e8 |
3697 | #define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3698 | #define regMMEA4_IO_WR_PRI_QUANT_PRI1 0x08e9 |
3699 | #define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3700 | #define regMMEA4_IO_WR_PRI_QUANT_PRI2 0x08ea |
3701 | #define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3702 | #define regMMEA4_IO_WR_PRI_QUANT_PRI3 0x08eb |
3703 | #define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3704 | #define regMMEA4_SDP_ARB_DRAM 0x08ec |
3705 | #define regMMEA4_SDP_ARB_DRAM_BASE_IDX 0 |
3706 | #define regMMEA4_SDP_ARB_GMI 0x08ed |
3707 | #define regMMEA4_SDP_ARB_GMI_BASE_IDX 0 |
3708 | #define regMMEA4_SDP_ARB_FINAL 0x08ee |
3709 | #define regMMEA4_SDP_ARB_FINAL_BASE_IDX 0 |
3710 | #define regMMEA4_SDP_DRAM_PRIORITY 0x08ef |
3711 | #define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 0 |
3712 | #define regMMEA4_SDP_GMI_PRIORITY 0x08f0 |
3713 | #define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX 0 |
3714 | #define regMMEA4_SDP_IO_PRIORITY 0x08f1 |
3715 | #define regMMEA4_SDP_IO_PRIORITY_BASE_IDX 0 |
3716 | #define regMMEA4_SDP_CREDITS 0x08f2 |
3717 | #define regMMEA4_SDP_CREDITS_BASE_IDX 0 |
3718 | #define regMMEA4_SDP_TAG_RESERVE0 0x08f3 |
3719 | #define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX 0 |
3720 | #define regMMEA4_SDP_TAG_RESERVE1 0x08f4 |
3721 | #define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX 0 |
3722 | #define regMMEA4_SDP_VCC_RESERVE0 0x08f5 |
3723 | #define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX 0 |
3724 | #define regMMEA4_SDP_VCC_RESERVE1 0x08f6 |
3725 | #define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX 0 |
3726 | #define regMMEA4_SDP_VCD_RESERVE0 0x08f7 |
3727 | #define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX 0 |
3728 | #define regMMEA4_SDP_VCD_RESERVE1 0x08f8 |
3729 | #define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX 0 |
3730 | #define regMMEA4_SDP_REQ_CNTL 0x08f9 |
3731 | #define regMMEA4_SDP_REQ_CNTL_BASE_IDX 0 |
3732 | #define regMMEA4_MISC 0x08fa |
3733 | #define regMMEA4_MISC_BASE_IDX 0 |
3734 | #define regMMEA4_LATENCY_SAMPLING 0x08fb |
3735 | #define regMMEA4_LATENCY_SAMPLING_BASE_IDX 0 |
3736 | #define regMMEA4_PERFCOUNTER_LO 0x08fc |
3737 | #define regMMEA4_PERFCOUNTER_LO_BASE_IDX 0 |
3738 | #define regMMEA4_PERFCOUNTER_HI 0x08fd |
3739 | #define regMMEA4_PERFCOUNTER_HI_BASE_IDX 0 |
3740 | #define regMMEA4_PERFCOUNTER0_CFG 0x08fe |
3741 | #define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX 0 |
3742 | #define regMMEA4_PERFCOUNTER1_CFG 0x08ff |
3743 | #define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0 |
3744 | #define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900 |
3745 | #define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
3746 | #define regMMEA4_EDC_CNT 0x0906 |
3747 | #define regMMEA4_EDC_CNT_BASE_IDX 0 |
3748 | #define regMMEA4_EDC_CNT2 0x0907 |
3749 | #define regMMEA4_EDC_CNT2_BASE_IDX 0 |
3750 | #define regMMEA4_DSM_CNTL 0x0908 |
3751 | #define regMMEA4_DSM_CNTL_BASE_IDX 0 |
3752 | #define regMMEA4_DSM_CNTLA 0x0909 |
3753 | #define regMMEA4_DSM_CNTLA_BASE_IDX 0 |
3754 | #define regMMEA4_DSM_CNTLB 0x090a |
3755 | #define regMMEA4_DSM_CNTLB_BASE_IDX 0 |
3756 | #define regMMEA4_DSM_CNTL2 0x090b |
3757 | #define regMMEA4_DSM_CNTL2_BASE_IDX 0 |
3758 | #define regMMEA4_DSM_CNTL2A 0x090c |
3759 | #define regMMEA4_DSM_CNTL2A_BASE_IDX 0 |
3760 | #define regMMEA4_DSM_CNTL2B 0x090d |
3761 | #define regMMEA4_DSM_CNTL2B_BASE_IDX 0 |
3762 | #define regMMEA4_CGTT_CLK_CTRL 0x090f |
3763 | #define regMMEA4_CGTT_CLK_CTRL_BASE_IDX 0 |
3764 | #define regMMEA4_EDC_MODE 0x0910 |
3765 | #define regMMEA4_EDC_MODE_BASE_IDX 0 |
3766 | #define regMMEA4_ERR_STATUS 0x0911 |
3767 | #define regMMEA4_ERR_STATUS_BASE_IDX 0 |
3768 | #define regMMEA4_MISC2 0x0912 |
3769 | #define regMMEA4_MISC2_BASE_IDX 0 |
3770 | #define regMMEA4_ADDRDEC_SELECT 0x0913 |
3771 | #define regMMEA4_ADDRDEC_SELECT_BASE_IDX 0 |
3772 | #define regMMEA4_EDC_CNT3 0x0914 |
3773 | #define regMMEA4_EDC_CNT3_BASE_IDX 0 |
3774 | #define regMMEA4_MISC_AON 0x0915 |
3775 | #define regMMEA4_MISC_AON_BASE_IDX 0 |
3776 | |
3777 | |
3778 | // addressBlock: mmhub_ea_mmeadec5 |
3779 | // base address: 0x6a500 |
3780 | #define regMMEA5_DRAM_RD_CLI2GRP_MAP0 0x0940 |
3781 | #define regMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3782 | #define regMMEA5_DRAM_RD_CLI2GRP_MAP1 0x0941 |
3783 | #define regMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3784 | #define regMMEA5_DRAM_WR_CLI2GRP_MAP0 0x0942 |
3785 | #define regMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3786 | #define regMMEA5_DRAM_WR_CLI2GRP_MAP1 0x0943 |
3787 | #define regMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3788 | #define regMMEA5_DRAM_RD_GRP2VC_MAP 0x0944 |
3789 | #define regMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 |
3790 | #define regMMEA5_DRAM_WR_GRP2VC_MAP 0x0945 |
3791 | #define regMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 |
3792 | #define regMMEA5_DRAM_RD_LAZY 0x0946 |
3793 | #define regMMEA5_DRAM_RD_LAZY_BASE_IDX 0 |
3794 | #define regMMEA5_DRAM_WR_LAZY 0x0947 |
3795 | #define regMMEA5_DRAM_WR_LAZY_BASE_IDX 0 |
3796 | #define regMMEA5_DRAM_RD_CAM_CNTL 0x0948 |
3797 | #define regMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 0 |
3798 | #define regMMEA5_DRAM_WR_CAM_CNTL 0x0949 |
3799 | #define regMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 0 |
3800 | #define regMMEA5_DRAM_PAGE_BURST 0x094a |
3801 | #define regMMEA5_DRAM_PAGE_BURST_BASE_IDX 0 |
3802 | #define regMMEA5_DRAM_RD_PRI_AGE 0x094b |
3803 | #define regMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 0 |
3804 | #define regMMEA5_DRAM_WR_PRI_AGE 0x094c |
3805 | #define regMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 0 |
3806 | #define regMMEA5_DRAM_RD_PRI_QUEUING 0x094d |
3807 | #define regMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 0 |
3808 | #define regMMEA5_DRAM_WR_PRI_QUEUING 0x094e |
3809 | #define regMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 0 |
3810 | #define regMMEA5_DRAM_RD_PRI_FIXED 0x094f |
3811 | #define regMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 0 |
3812 | #define regMMEA5_DRAM_WR_PRI_FIXED 0x0950 |
3813 | #define regMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 0 |
3814 | #define regMMEA5_DRAM_RD_PRI_URGENCY 0x0951 |
3815 | #define regMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 0 |
3816 | #define regMMEA5_DRAM_WR_PRI_URGENCY 0x0952 |
3817 | #define regMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 0 |
3818 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x0953 |
3819 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3820 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x0954 |
3821 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3822 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x0955 |
3823 | #define regMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3824 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x0956 |
3825 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3826 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x0957 |
3827 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3828 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x0958 |
3829 | #define regMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3830 | #define regMMEA5_GMI_RD_CLI2GRP_MAP0 0x0959 |
3831 | #define regMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 0 |
3832 | #define regMMEA5_GMI_RD_CLI2GRP_MAP1 0x095a |
3833 | #define regMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 0 |
3834 | #define regMMEA5_GMI_WR_CLI2GRP_MAP0 0x095b |
3835 | #define regMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 0 |
3836 | #define regMMEA5_GMI_WR_CLI2GRP_MAP1 0x095c |
3837 | #define regMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 0 |
3838 | #define regMMEA5_GMI_RD_GRP2VC_MAP 0x095d |
3839 | #define regMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 0 |
3840 | #define regMMEA5_GMI_WR_GRP2VC_MAP 0x095e |
3841 | #define regMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 0 |
3842 | #define regMMEA5_GMI_RD_LAZY 0x095f |
3843 | #define regMMEA5_GMI_RD_LAZY_BASE_IDX 0 |
3844 | #define regMMEA5_GMI_WR_LAZY 0x0960 |
3845 | #define regMMEA5_GMI_WR_LAZY_BASE_IDX 0 |
3846 | #define regMMEA5_GMI_RD_CAM_CNTL 0x0961 |
3847 | #define regMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 0 |
3848 | #define regMMEA5_GMI_WR_CAM_CNTL 0x0962 |
3849 | #define regMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 0 |
3850 | #define regMMEA5_GMI_PAGE_BURST 0x0963 |
3851 | #define regMMEA5_GMI_PAGE_BURST_BASE_IDX 0 |
3852 | #define regMMEA5_GMI_RD_PRI_AGE 0x0964 |
3853 | #define regMMEA5_GMI_RD_PRI_AGE_BASE_IDX 0 |
3854 | #define regMMEA5_GMI_WR_PRI_AGE 0x0965 |
3855 | #define regMMEA5_GMI_WR_PRI_AGE_BASE_IDX 0 |
3856 | #define regMMEA5_GMI_RD_PRI_QUEUING 0x0966 |
3857 | #define regMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 0 |
3858 | #define regMMEA5_GMI_WR_PRI_QUEUING 0x0967 |
3859 | #define regMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 0 |
3860 | #define regMMEA5_GMI_RD_PRI_FIXED 0x0968 |
3861 | #define regMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 0 |
3862 | #define regMMEA5_GMI_WR_PRI_FIXED 0x0969 |
3863 | #define regMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 0 |
3864 | #define regMMEA5_GMI_RD_PRI_URGENCY 0x096a |
3865 | #define regMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 0 |
3866 | #define regMMEA5_GMI_WR_PRI_URGENCY 0x096b |
3867 | #define regMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 0 |
3868 | #define regMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x096c |
3869 | #define regMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
3870 | #define regMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x096d |
3871 | #define regMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
3872 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI1 0x096e |
3873 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
3874 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI2 0x096f |
3875 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
3876 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI3 0x0970 |
3877 | #define regMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
3878 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI1 0x0971 |
3879 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
3880 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI2 0x0972 |
3881 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
3882 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI3 0x0973 |
3883 | #define regMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
3884 | #define regMMEA5_ADDRNORM_BASE_ADDR0 0x0974 |
3885 | #define regMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 0 |
3886 | #define regMMEA5_ADDRNORM_LIMIT_ADDR0 0x0975 |
3887 | #define regMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 |
3888 | #define regMMEA5_ADDRNORM_BASE_ADDR1 0x0976 |
3889 | #define regMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 0 |
3890 | #define regMMEA5_ADDRNORM_LIMIT_ADDR1 0x0977 |
3891 | #define regMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 |
3892 | #define regMMEA5_ADDRNORM_OFFSET_ADDR1 0x0978 |
3893 | #define regMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 |
3894 | #define regMMEA5_ADDRNORM_BASE_ADDR2 0x0979 |
3895 | #define regMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 0 |
3896 | #define regMMEA5_ADDRNORM_LIMIT_ADDR2 0x097a |
3897 | #define regMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 |
3898 | #define regMMEA5_ADDRNORM_BASE_ADDR3 0x097b |
3899 | #define regMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 0 |
3900 | #define regMMEA5_ADDRNORM_LIMIT_ADDR3 0x097c |
3901 | #define regMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 |
3902 | #define regMMEA5_ADDRNORM_OFFSET_ADDR3 0x097d |
3903 | #define regMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 |
3904 | #define regMMEA5_ADDRNORM_MEGABASE_ADDR0 0x097e |
3905 | #define regMMEA5_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 |
3906 | #define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0 0x097f |
3907 | #define regMMEA5_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 |
3908 | #define regMMEA5_ADDRNORM_MEGABASE_ADDR1 0x0980 |
3909 | #define regMMEA5_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 |
3910 | #define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1 0x0981 |
3911 | #define regMMEA5_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 |
3912 | #define regMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x0983 |
3913 | #define regMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 |
3914 | #define regMMEA5_ADDRNORMGMI_HOLE_CNTL 0x0984 |
3915 | #define regMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 |
3916 | #define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0985 |
3917 | #define regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 |
3918 | #define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0986 |
3919 | #define regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 |
3920 | #define regMMEA5_ADDRDEC_BANK_CFG 0x0987 |
3921 | #define regMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 0 |
3922 | #define regMMEA5_ADDRDEC_MISC_CFG 0x0988 |
3923 | #define regMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 0 |
3924 | #define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x0993 |
3925 | #define regMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 |
3926 | #define regMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x099e |
3927 | #define regMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 |
3928 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x099f |
3929 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 |
3930 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x09a0 |
3931 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 |
3932 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x09a1 |
3933 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 |
3934 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x09a2 |
3935 | #define regMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 |
3936 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x09a3 |
3937 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 |
3938 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x09a4 |
3939 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 |
3940 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x09a5 |
3941 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 |
3942 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x09a6 |
3943 | #define regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 |
3944 | #define regMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x09a7 |
3945 | #define regMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 |
3946 | #define regMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x09a8 |
3947 | #define regMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 |
3948 | #define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x09a9 |
3949 | #define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 |
3950 | #define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x09aa |
3951 | #define regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 |
3952 | #define regMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x09ab |
3953 | #define regMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 |
3954 | #define regMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x09ac |
3955 | #define regMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 |
3956 | #define regMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x09ad |
3957 | #define regMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 |
3958 | #define regMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x09ae |
3959 | #define regMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 |
3960 | #define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x09af |
3961 | #define regMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 |
3962 | #define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x09b0 |
3963 | #define regMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 |
3964 | #define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x09b1 |
3965 | #define regMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 |
3966 | #define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x09b2 |
3967 | #define regMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 |
3968 | #define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x09b3 |
3969 | #define regMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 |
3970 | #define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x09b4 |
3971 | #define regMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 |
3972 | #define regMMEA5_ADDRDEC0_RM_SEL_CS01 0x09b5 |
3973 | #define regMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 |
3974 | #define regMMEA5_ADDRDEC0_RM_SEL_CS23 0x09b6 |
3975 | #define regMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 |
3976 | #define regMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x09b7 |
3977 | #define regMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 |
3978 | #define regMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x09b8 |
3979 | #define regMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 |
3980 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x09b9 |
3981 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 |
3982 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x09ba |
3983 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 |
3984 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x09bb |
3985 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 |
3986 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x09bc |
3987 | #define regMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 |
3988 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x09bd |
3989 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 |
3990 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x09be |
3991 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 |
3992 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x09bf |
3993 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 |
3994 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x09c0 |
3995 | #define regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 |
3996 | #define regMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x09c1 |
3997 | #define regMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 |
3998 | #define regMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x09c2 |
3999 | #define regMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 |
4000 | #define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x09c3 |
4001 | #define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 |
4002 | #define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x09c4 |
4003 | #define regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 |
4004 | #define regMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x09c5 |
4005 | #define regMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 |
4006 | #define regMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x09c6 |
4007 | #define regMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 |
4008 | #define regMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x09c7 |
4009 | #define regMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 |
4010 | #define regMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x09c8 |
4011 | #define regMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 |
4012 | #define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x09c9 |
4013 | #define regMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 |
4014 | #define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x09ca |
4015 | #define regMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 |
4016 | #define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x09cb |
4017 | #define regMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 |
4018 | #define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x09cc |
4019 | #define regMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 |
4020 | #define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x09cd |
4021 | #define regMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 |
4022 | #define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x09ce |
4023 | #define regMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 |
4024 | #define regMMEA5_ADDRDEC1_RM_SEL_CS01 0x09cf |
4025 | #define regMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 |
4026 | #define regMMEA5_ADDRDEC1_RM_SEL_CS23 0x09d0 |
4027 | #define regMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 |
4028 | #define regMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x09d1 |
4029 | #define regMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 |
4030 | #define regMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x09d2 |
4031 | #define regMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 |
4032 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x09d3 |
4033 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 |
4034 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x09d4 |
4035 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 |
4036 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x09d5 |
4037 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 |
4038 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x09d6 |
4039 | #define regMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 |
4040 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x09d7 |
4041 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 |
4042 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x09d8 |
4043 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 |
4044 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x09d9 |
4045 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 |
4046 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x09da |
4047 | #define regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 |
4048 | #define regMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x09db |
4049 | #define regMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 |
4050 | #define regMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x09dc |
4051 | #define regMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 |
4052 | #define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x09dd |
4053 | #define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 |
4054 | #define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x09de |
4055 | #define regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 |
4056 | #define regMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x09df |
4057 | #define regMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 |
4058 | #define regMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x09e0 |
4059 | #define regMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 |
4060 | #define regMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x09e1 |
4061 | #define regMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 |
4062 | #define regMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x09e2 |
4063 | #define regMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 |
4064 | #define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x09e3 |
4065 | #define regMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 |
4066 | #define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x09e4 |
4067 | #define regMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 |
4068 | #define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x09e5 |
4069 | #define regMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 |
4070 | #define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x09e6 |
4071 | #define regMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 |
4072 | #define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x09e7 |
4073 | #define regMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 |
4074 | #define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x09e8 |
4075 | #define regMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 |
4076 | #define regMMEA5_ADDRDEC2_RM_SEL_CS01 0x09e9 |
4077 | #define regMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 |
4078 | #define regMMEA5_ADDRDEC2_RM_SEL_CS23 0x09ea |
4079 | #define regMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 |
4080 | #define regMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x09eb |
4081 | #define regMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 |
4082 | #define regMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x09ec |
4083 | #define regMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 |
4084 | #define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x09ed |
4085 | #define regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 |
4086 | #define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x09ee |
4087 | #define regMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 |
4088 | #define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0 0x0a11 |
4089 | #define regMMEA5_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 |
4090 | #define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1 0x0a12 |
4091 | #define regMMEA5_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 |
4092 | #define regMMEA5_ADDRNORMDRAM_MASKING 0x0a13 |
4093 | #define regMMEA5_ADDRNORMDRAM_MASKING_BASE_IDX 0 |
4094 | #define regMMEA5_ADDRNORMGMI_MASKING 0x0a14 |
4095 | #define regMMEA5_ADDRNORMGMI_MASKING_BASE_IDX 0 |
4096 | #define regMMEA5_IO_RD_CLI2GRP_MAP0 0x0a15 |
4097 | #define regMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 |
4098 | #define regMMEA5_IO_RD_CLI2GRP_MAP1 0x0a16 |
4099 | #define regMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 |
4100 | #define regMMEA5_IO_WR_CLI2GRP_MAP0 0x0a17 |
4101 | #define regMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 |
4102 | #define regMMEA5_IO_WR_CLI2GRP_MAP1 0x0a18 |
4103 | #define regMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 |
4104 | #define regMMEA5_IO_RD_COMBINE_FLUSH 0x0a19 |
4105 | #define regMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 0 |
4106 | #define regMMEA5_IO_WR_COMBINE_FLUSH 0x0a1a |
4107 | #define regMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 0 |
4108 | #define regMMEA5_IO_GROUP_BURST 0x0a1b |
4109 | #define regMMEA5_IO_GROUP_BURST_BASE_IDX 0 |
4110 | #define regMMEA5_IO_RD_PRI_AGE 0x0a1c |
4111 | #define regMMEA5_IO_RD_PRI_AGE_BASE_IDX 0 |
4112 | #define regMMEA5_IO_WR_PRI_AGE 0x0a1d |
4113 | #define regMMEA5_IO_WR_PRI_AGE_BASE_IDX 0 |
4114 | #define regMMEA5_IO_RD_PRI_QUEUING 0x0a1e |
4115 | #define regMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 0 |
4116 | #define regMMEA5_IO_WR_PRI_QUEUING 0x0a1f |
4117 | #define regMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 0 |
4118 | #define regMMEA5_IO_RD_PRI_FIXED 0x0a20 |
4119 | #define regMMEA5_IO_RD_PRI_FIXED_BASE_IDX 0 |
4120 | #define regMMEA5_IO_WR_PRI_FIXED 0x0a21 |
4121 | #define regMMEA5_IO_WR_PRI_FIXED_BASE_IDX 0 |
4122 | #define regMMEA5_IO_RD_PRI_URGENCY 0x0a22 |
4123 | #define regMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 0 |
4124 | #define regMMEA5_IO_WR_PRI_URGENCY 0x0a23 |
4125 | #define regMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 0 |
4126 | #define regMMEA5_IO_RD_PRI_URGENCY_MASKING 0x0a24 |
4127 | #define regMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 |
4128 | #define regMMEA5_IO_WR_PRI_URGENCY_MASKING 0x0a25 |
4129 | #define regMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 |
4130 | #define regMMEA5_IO_RD_PRI_QUANT_PRI1 0x0a26 |
4131 | #define regMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 |
4132 | #define regMMEA5_IO_RD_PRI_QUANT_PRI2 0x0a27 |
4133 | #define regMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 |
4134 | #define regMMEA5_IO_RD_PRI_QUANT_PRI3 0x0a28 |
4135 | #define regMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 |
4136 | #define regMMEA5_IO_WR_PRI_QUANT_PRI1 0x0a29 |
4137 | #define regMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 |
4138 | #define regMMEA5_IO_WR_PRI_QUANT_PRI2 0x0a2a |
4139 | #define regMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 |
4140 | #define regMMEA5_IO_WR_PRI_QUANT_PRI3 0x0a2b |
4141 | #define regMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 |
4142 | #define regMMEA5_SDP_ARB_DRAM 0x0a2c |
4143 | #define regMMEA5_SDP_ARB_DRAM_BASE_IDX 0 |
4144 | #define regMMEA5_SDP_ARB_GMI 0x0a2d |
4145 | #define regMMEA5_SDP_ARB_GMI_BASE_IDX 0 |
4146 | #define regMMEA5_SDP_ARB_FINAL 0x0a2e |
4147 | #define regMMEA5_SDP_ARB_FINAL_BASE_IDX 0 |
4148 | #define regMMEA5_SDP_DRAM_PRIORITY 0x0a2f |
4149 | #define regMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 0 |
4150 | #define regMMEA5_SDP_GMI_PRIORITY 0x0a30 |
4151 | #define regMMEA5_SDP_GMI_PRIORITY_BASE_IDX 0 |
4152 | #define regMMEA5_SDP_IO_PRIORITY 0x0a31 |
4153 | #define regMMEA5_SDP_IO_PRIORITY_BASE_IDX 0 |
4154 | #define regMMEA5_SDP_CREDITS 0x0a32 |
4155 | #define regMMEA5_SDP_CREDITS_BASE_IDX 0 |
4156 | #define regMMEA5_SDP_TAG_RESERVE0 0x0a33 |
4157 | #define regMMEA5_SDP_TAG_RESERVE0_BASE_IDX 0 |
4158 | #define regMMEA5_SDP_TAG_RESERVE1 0x0a34 |
4159 | #define regMMEA5_SDP_TAG_RESERVE1_BASE_IDX 0 |
4160 | #define regMMEA5_SDP_VCC_RESERVE0 0x0a35 |
4161 | #define regMMEA5_SDP_VCC_RESERVE0_BASE_IDX 0 |
4162 | #define regMMEA5_SDP_VCC_RESERVE1 0x0a36 |
4163 | #define regMMEA5_SDP_VCC_RESERVE1_BASE_IDX 0 |
4164 | #define regMMEA5_SDP_VCD_RESERVE0 0x0a37 |
4165 | #define regMMEA5_SDP_VCD_RESERVE0_BASE_IDX 0 |
4166 | #define regMMEA5_SDP_VCD_RESERVE1 0x0a38 |
4167 | #define regMMEA5_SDP_VCD_RESERVE1_BASE_IDX 0 |
4168 | #define regMMEA5_SDP_REQ_CNTL 0x0a39 |
4169 | #define regMMEA5_SDP_REQ_CNTL_BASE_IDX 0 |
4170 | #define regMMEA5_MISC 0x0a3a |
4171 | #define regMMEA5_MISC_BASE_IDX 0 |
4172 | #define regMMEA5_LATENCY_SAMPLING 0x0a3b |
4173 | #define regMMEA5_LATENCY_SAMPLING_BASE_IDX 0 |
4174 | #define regMMEA5_PERFCOUNTER_LO 0x0a3c |
4175 | #define regMMEA5_PERFCOUNTER_LO_BASE_IDX 0 |
4176 | #define regMMEA5_PERFCOUNTER_HI 0x0a3d |
4177 | #define regMMEA5_PERFCOUNTER_HI_BASE_IDX 0 |
4178 | #define regMMEA5_PERFCOUNTER0_CFG 0x0a3e |
4179 | #define regMMEA5_PERFCOUNTER0_CFG_BASE_IDX 0 |
4180 | #define regMMEA5_PERFCOUNTER1_CFG 0x0a3f |
4181 | #define regMMEA5_PERFCOUNTER1_CFG_BASE_IDX 0 |
4182 | #define regMMEA5_PERFCOUNTER_RSLT_CNTL 0x0a40 |
4183 | #define regMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
4184 | #define regMMEA5_EDC_CNT 0x0a46 |
4185 | #define regMMEA5_EDC_CNT_BASE_IDX 0 |
4186 | #define regMMEA5_EDC_CNT2 0x0a47 |
4187 | #define regMMEA5_EDC_CNT2_BASE_IDX 0 |
4188 | #define regMMEA5_DSM_CNTL 0x0a48 |
4189 | #define regMMEA5_DSM_CNTL_BASE_IDX 0 |
4190 | #define regMMEA5_DSM_CNTLA 0x0a49 |
4191 | #define regMMEA5_DSM_CNTLA_BASE_IDX 0 |
4192 | #define regMMEA5_DSM_CNTLB 0x0a4a |
4193 | #define regMMEA5_DSM_CNTLB_BASE_IDX 0 |
4194 | #define regMMEA5_DSM_CNTL2 0x0a4b |
4195 | #define regMMEA5_DSM_CNTL2_BASE_IDX 0 |
4196 | #define regMMEA5_DSM_CNTL2A 0x0a4c |
4197 | #define regMMEA5_DSM_CNTL2A_BASE_IDX 0 |
4198 | #define regMMEA5_DSM_CNTL2B 0x0a4d |
4199 | #define regMMEA5_DSM_CNTL2B_BASE_IDX 0 |
4200 | #define regMMEA5_CGTT_CLK_CTRL 0x0a4f |
4201 | #define regMMEA5_CGTT_CLK_CTRL_BASE_IDX 0 |
4202 | #define regMMEA5_EDC_MODE 0x0a50 |
4203 | #define regMMEA5_EDC_MODE_BASE_IDX 0 |
4204 | #define regMMEA5_ERR_STATUS 0x0a51 |
4205 | #define regMMEA5_ERR_STATUS_BASE_IDX 0 |
4206 | #define regMMEA5_MISC2 0x0a52 |
4207 | #define regMMEA5_MISC2_BASE_IDX 0 |
4208 | #define regMMEA5_ADDRDEC_SELECT 0x0a53 |
4209 | #define regMMEA5_ADDRDEC_SELECT_BASE_IDX 0 |
4210 | #define regMMEA5_EDC_CNT3 0x0a54 |
4211 | #define regMMEA5_EDC_CNT3_BASE_IDX 0 |
4212 | #define regMMEA5_MISC_AON 0x0a55 |
4213 | #define regMMEA5_MISC_AON_BASE_IDX 0 |
4214 | |
4215 | |
4216 | // addressBlock: mmhub_l1tlb_vml1dec |
4217 | // base address: 0x6ac00 |
4218 | #define regMC_VM_MX_L1_TLB0_STATUS 0x0b08 |
4219 | #define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 |
4220 | #define regMC_VM_MX_L1_TLB1_STATUS 0x0b09 |
4221 | #define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 |
4222 | #define regMC_VM_MX_L1_TLB2_STATUS 0x0b0a |
4223 | #define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 |
4224 | #define regMC_VM_MX_L1_TLB3_STATUS 0x0b0b |
4225 | #define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 |
4226 | #define regMC_VM_MX_L1_TLB4_STATUS 0x0b0c |
4227 | #define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 |
4228 | #define regMC_VM_MX_L1_TLB5_STATUS 0x0b0d |
4229 | #define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 |
4230 | #define regMC_VM_MX_L1_TLB6_STATUS 0x0b0e |
4231 | #define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 |
4232 | #define regMC_VM_MX_L1_TLB7_STATUS 0x0b0f |
4233 | #define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 |
4234 | |
4235 | |
4236 | // addressBlock: mmhub_l1tlb_vml1pldec |
4237 | // base address: 0x6ac80 |
4238 | #define regMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0b20 |
4239 | #define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 |
4240 | #define regMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0b21 |
4241 | #define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 |
4242 | #define regMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0b22 |
4243 | #define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 |
4244 | #define regMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0b23 |
4245 | #define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 |
4246 | #define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0b24 |
4247 | #define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
4248 | |
4249 | |
4250 | // addressBlock: mmhub_l1tlb_vml1prdec |
4251 | // base address: 0x6acc0 |
4252 | #define regMC_VM_MX_L1_PERFCOUNTER_LO 0x0b30 |
4253 | #define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 |
4254 | #define regMC_VM_MX_L1_PERFCOUNTER_HI 0x0b31 |
4255 | #define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 |
4256 | |
4257 | |
4258 | // addressBlock: mmhub_pctldec0 |
4259 | // base address: 0x6aa00 |
4260 | #define regPCTL0_CTRL 0x0a80 |
4261 | #define regPCTL0_CTRL_BASE_IDX 0 |
4262 | #define regPCTL0_MMHUB_DEEPSLEEP_IB 0x0a81 |
4263 | #define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 0 |
4264 | #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x0a82 |
4265 | #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 |
4266 | #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0a83 |
4267 | #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 0 |
4268 | #define regPCTL0_PG_IGNORE_DEEPSLEEP 0x0a84 |
4269 | #define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 |
4270 | #define regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x0a85 |
4271 | #define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 0 |
4272 | #define regPCTL0_SLICE0_CFG_DAGB_BUSY 0x0a86 |
4273 | #define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 0 |
4274 | #define regPCTL0_SLICE0_CFG_DS_ALLOW 0x0a87 |
4275 | #define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 0 |
4276 | #define regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x0a88 |
4277 | #define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4278 | #define regPCTL0_SLICE1_CFG_DAGB_BUSY 0x0a89 |
4279 | #define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 0 |
4280 | #define regPCTL0_SLICE1_CFG_DS_ALLOW 0x0a8a |
4281 | #define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 0 |
4282 | #define regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x0a8b |
4283 | #define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4284 | #define regPCTL0_SLICE2_CFG_DAGB_BUSY 0x0a8c |
4285 | #define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 0 |
4286 | #define regPCTL0_SLICE2_CFG_DS_ALLOW 0x0a8d |
4287 | #define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 0 |
4288 | #define regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x0a8e |
4289 | #define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4290 | #define regPCTL0_SLICE3_CFG_DAGB_BUSY 0x0a8f |
4291 | #define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 0 |
4292 | #define regPCTL0_SLICE3_CFG_DS_ALLOW 0x0a90 |
4293 | #define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 0 |
4294 | #define regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x0a91 |
4295 | #define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4296 | #define regPCTL0_SLICE4_CFG_DAGB_BUSY 0x0a92 |
4297 | #define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 0 |
4298 | #define regPCTL0_SLICE4_CFG_DS_ALLOW 0x0a93 |
4299 | #define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 0 |
4300 | #define regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x0a94 |
4301 | #define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4302 | #define regPCTL0_SLICE5_CFG_DAGB_BUSY 0x0a95 |
4303 | #define regPCTL0_SLICE5_CFG_DAGB_BUSY_BASE_IDX 0 |
4304 | #define regPCTL0_SLICE5_CFG_DS_ALLOW 0x0a96 |
4305 | #define regPCTL0_SLICE5_CFG_DS_ALLOW_BASE_IDX 0 |
4306 | #define regPCTL0_SLICE5_CFG_DS_ALLOW_IB 0x0a97 |
4307 | #define regPCTL0_SLICE5_CFG_DS_ALLOW_IB_BASE_IDX 0 |
4308 | #define regPCTL0_UTCL2_MISC 0x0a98 |
4309 | #define regPCTL0_UTCL2_MISC_BASE_IDX 0 |
4310 | #define regPCTL0_SLICE0_MISC 0x0a99 |
4311 | #define regPCTL0_SLICE0_MISC_BASE_IDX 0 |
4312 | #define regPCTL0_SLICE1_MISC 0x0a9a |
4313 | #define regPCTL0_SLICE1_MISC_BASE_IDX 0 |
4314 | #define regPCTL0_SLICE2_MISC 0x0a9b |
4315 | #define regPCTL0_SLICE2_MISC_BASE_IDX 0 |
4316 | #define regPCTL0_SLICE3_MISC 0x0a9c |
4317 | #define regPCTL0_SLICE3_MISC_BASE_IDX 0 |
4318 | #define regPCTL0_SLICE4_MISC 0x0a9d |
4319 | #define regPCTL0_SLICE4_MISC_BASE_IDX 0 |
4320 | #define regPCTL0_SLICE5_MISC 0x0a9e |
4321 | #define regPCTL0_SLICE5_MISC_BASE_IDX 0 |
4322 | |
4323 | |
4324 | // addressBlock: mmhub_utcl2_atcl2dec |
4325 | // base address: 0x6ad00 |
4326 | #define regATC_L2_CNTL 0x0b40 |
4327 | #define regATC_L2_CNTL_BASE_IDX 0 |
4328 | #define regATC_L2_CNTL2 0x0b41 |
4329 | #define regATC_L2_CNTL2_BASE_IDX 0 |
4330 | #define regATC_L2_CACHE_DATA0 0x0b44 |
4331 | #define regATC_L2_CACHE_DATA0_BASE_IDX 0 |
4332 | #define regATC_L2_CACHE_DATA1 0x0b45 |
4333 | #define regATC_L2_CACHE_DATA1_BASE_IDX 0 |
4334 | #define regATC_L2_CACHE_DATA2 0x0b46 |
4335 | #define regATC_L2_CACHE_DATA2_BASE_IDX 0 |
4336 | #define regATC_L2_CACHE_DATA3 0x0b47 |
4337 | #define regATC_L2_CACHE_DATA3_BASE_IDX 0 |
4338 | #define regATC_L2_CNTL3 0x0b48 |
4339 | #define regATC_L2_CNTL3_BASE_IDX 0 |
4340 | #define regATC_L2_STATUS 0x0b49 |
4341 | #define regATC_L2_STATUS_BASE_IDX 0 |
4342 | #define regATC_L2_STATUS2 0x0b4a |
4343 | #define regATC_L2_STATUS2_BASE_IDX 0 |
4344 | #define regATC_L2_MISC_CG 0x0b4b |
4345 | #define regATC_L2_MISC_CG_BASE_IDX 0 |
4346 | #define regATC_L2_MEM_POWER_LS 0x0b4c |
4347 | #define regATC_L2_MEM_POWER_LS_BASE_IDX 0 |
4348 | #define regATC_L2_CGTT_CLK_CTRL 0x0b4d |
4349 | #define regATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 |
4350 | #define regATC_L2_CACHE_4K_DSM_INDEX 0x0b4e |
4351 | #define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 0 |
4352 | #define regATC_L2_CACHE_32K_DSM_INDEX 0x0b4f |
4353 | #define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX 0 |
4354 | #define regATC_L2_CACHE_2M_DSM_INDEX 0x0b50 |
4355 | #define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 0 |
4356 | #define regATC_L2_CACHE_4K_DSM_CNTL 0x0b51 |
4357 | #define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 0 |
4358 | #define regATC_L2_CACHE_32K_DSM_CNTL 0x0b52 |
4359 | #define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX 0 |
4360 | #define regATC_L2_CACHE_2M_DSM_CNTL 0x0b53 |
4361 | #define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 0 |
4362 | #define regATC_L2_CNTL4 0x0b54 |
4363 | #define regATC_L2_CNTL4_BASE_IDX 0 |
4364 | #define regATC_L2_MM_GROUP_RT_CLASSES 0x0b55 |
4365 | #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 |
4366 | |
4367 | |
4368 | // addressBlock: mmhub_utcl2_atcl2pfcntldec |
4369 | // base address: 0x6b4d0 |
4370 | #define regATC_L2_PERFCOUNTER0_CFG 0x0d34 |
4371 | #define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 |
4372 | #define regATC_L2_PERFCOUNTER1_CFG 0x0d35 |
4373 | #define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 |
4374 | #define regATC_L2_PERFCOUNTER_RSLT_CNTL 0x0d36 |
4375 | #define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
4376 | |
4377 | |
4378 | // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
4379 | // base address: 0x6b4c0 |
4380 | #define regATC_L2_PERFCOUNTER_LO 0x0d30 |
4381 | #define regATC_L2_PERFCOUNTER_LO_BASE_IDX 0 |
4382 | #define regATC_L2_PERFCOUNTER_HI 0x0d31 |
4383 | #define regATC_L2_PERFCOUNTER_HI_BASE_IDX 0 |
4384 | |
4385 | |
4386 | // addressBlock: mmhub_utcl2_l2tlbdec |
4387 | // base address: 0x6b580 |
4388 | #define regL2TLB_TLB0_STATUS 0x0d61 |
4389 | #define regL2TLB_TLB0_STATUS_BASE_IDX 0 |
4390 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0d63 |
4391 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 0 |
4392 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0d64 |
4393 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 0 |
4394 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0d65 |
4395 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 0 |
4396 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0d66 |
4397 | #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 0 |
4398 | |
4399 | |
4400 | // addressBlock: mmhub_utcl2_l2tlbpldec |
4401 | // base address: 0x6b5a0 |
4402 | #define regL2TLB_PERFCOUNTER0_CFG 0x0d68 |
4403 | #define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX 0 |
4404 | #define regL2TLB_PERFCOUNTER1_CFG 0x0d69 |
4405 | #define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX 0 |
4406 | #define regL2TLB_PERFCOUNTER2_CFG 0x0d6a |
4407 | #define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX 0 |
4408 | #define regL2TLB_PERFCOUNTER3_CFG 0x0d6b |
4409 | #define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX 0 |
4410 | #define regL2TLB_PERFCOUNTER_RSLT_CNTL 0x0d6c |
4411 | #define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
4412 | |
4413 | |
4414 | // addressBlock: mmhub_utcl2_l2tlbprdec |
4415 | // base address: 0x6b5c0 |
4416 | #define regL2TLB_PERFCOUNTER_LO 0x0d70 |
4417 | #define regL2TLB_PERFCOUNTER_LO_BASE_IDX 0 |
4418 | #define regL2TLB_PERFCOUNTER_HI 0x0d71 |
4419 | #define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0 |
4420 | |
4421 | |
4422 | // addressBlock: mmhub_utcl2_vml2pfdec |
4423 | // base address: 0x6ae00 |
4424 | #define regVM_L2_CNTL 0x0b80 |
4425 | #define regVM_L2_CNTL_BASE_IDX 0 |
4426 | #define regVM_L2_CNTL2 0x0b81 |
4427 | #define regVM_L2_CNTL2_BASE_IDX 0 |
4428 | #define regVM_L2_CNTL3 0x0b82 |
4429 | #define regVM_L2_CNTL3_BASE_IDX 0 |
4430 | #define regVM_L2_STATUS 0x0b83 |
4431 | #define regVM_L2_STATUS_BASE_IDX 0 |
4432 | #define regVM_DUMMY_PAGE_FAULT_CNTL 0x0b84 |
4433 | #define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 |
4434 | #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0b85 |
4435 | #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 |
4436 | #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0b86 |
4437 | #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 |
4438 | #define regVM_L2_PROTECTION_FAULT_CNTL 0x0b87 |
4439 | #define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 |
4440 | #define regVM_L2_PROTECTION_FAULT_CNTL2 0x0b88 |
4441 | #define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 |
4442 | #define regVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0b89 |
4443 | #define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 |
4444 | #define regVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0b8a |
4445 | #define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 |
4446 | #define regVM_L2_PROTECTION_FAULT_STATUS 0x0b8b |
4447 | #define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 |
4448 | #define regVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0b8c |
4449 | #define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 |
4450 | #define regVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0b8d |
4451 | #define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 |
4452 | #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0b8e |
4453 | #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 |
4454 | #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0b8f |
4455 | #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 |
4456 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0b91 |
4457 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 |
4458 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0b92 |
4459 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 |
4460 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0b93 |
4461 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 |
4462 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0b94 |
4463 | #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 |
4464 | #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0b95 |
4465 | #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 |
4466 | #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0b96 |
4467 | #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 |
4468 | #define regVM_L2_CNTL4 0x0b97 |
4469 | #define regVM_L2_CNTL4_BASE_IDX 0 |
4470 | #define regVM_L2_MM_GROUP_RT_CLASSES 0x0b98 |
4471 | #define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 |
4472 | #define regVM_L2_BANK_SELECT_RESERVED_CID 0x0b99 |
4473 | #define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 |
4474 | #define regVM_L2_BANK_SELECT_RESERVED_CID2 0x0b9a |
4475 | #define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 |
4476 | #define regVM_L2_CACHE_PARITY_CNTL 0x0b9b |
4477 | #define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 |
4478 | #define regVM_L2_CGTT_CLK_CTRL 0x0b9e |
4479 | #define regVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 |
4480 | #define regVM_L2_CGTT_BUSY_CTRL 0x0b9f |
4481 | #define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 |
4482 | #define regVML2_MEM_ECC_INDEX 0x0ba1 |
4483 | #define regVML2_MEM_ECC_INDEX_BASE_IDX 0 |
4484 | #define regVML2_WALKER_MEM_ECC_INDEX 0x0ba2 |
4485 | #define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX 0 |
4486 | #define regUTCL2_MEM_ECC_INDEX 0x0ba3 |
4487 | #define regUTCL2_MEM_ECC_INDEX_BASE_IDX 0 |
4488 | #define regVML2_MEM_ECC_CNTL 0x0ba4 |
4489 | #define regVML2_MEM_ECC_CNTL_BASE_IDX 0 |
4490 | #define regVML2_WALKER_MEM_ECC_CNTL 0x0ba5 |
4491 | #define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX 0 |
4492 | #define regUTCL2_MEM_ECC_CNTL 0x0ba6 |
4493 | #define regUTCL2_MEM_ECC_CNTL_BASE_IDX 0 |
4494 | #define regVML2_MEM_ECC_STATUS 0x0ba7 |
4495 | #define regVML2_MEM_ECC_STATUS_BASE_IDX 0 |
4496 | #define regVML2_WALKER_MEM_ECC_STATUS 0x0ba8 |
4497 | #define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX 0 |
4498 | #define regUTCL2_MEM_ECC_STATUS 0x0ba9 |
4499 | #define regUTCL2_MEM_ECC_STATUS_BASE_IDX 0 |
4500 | #define regUTCL2_EDC_MODE 0x0baa |
4501 | #define regUTCL2_EDC_MODE_BASE_IDX 0 |
4502 | #define regUTCL2_EDC_CONFIG 0x0bab |
4503 | #define regUTCL2_EDC_CONFIG_BASE_IDX 0 |
4504 | |
4505 | |
4506 | // addressBlock: mmhub_utcl2_vml2pldec |
4507 | // base address: 0x6b500 |
4508 | #define regMC_VM_L2_PERFCOUNTER0_CFG 0x0d40 |
4509 | #define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 |
4510 | #define regMC_VM_L2_PERFCOUNTER1_CFG 0x0d41 |
4511 | #define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 |
4512 | #define regMC_VM_L2_PERFCOUNTER2_CFG 0x0d42 |
4513 | #define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 |
4514 | #define regMC_VM_L2_PERFCOUNTER3_CFG 0x0d43 |
4515 | #define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 |
4516 | #define regMC_VM_L2_PERFCOUNTER4_CFG 0x0d44 |
4517 | #define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 |
4518 | #define regMC_VM_L2_PERFCOUNTER5_CFG 0x0d45 |
4519 | #define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 |
4520 | #define regMC_VM_L2_PERFCOUNTER6_CFG 0x0d46 |
4521 | #define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 |
4522 | #define regMC_VM_L2_PERFCOUNTER7_CFG 0x0d47 |
4523 | #define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 |
4524 | #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0d48 |
4525 | #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 |
4526 | |
4527 | |
4528 | // addressBlock: mmhub_utcl2_vml2prdec |
4529 | // base address: 0x6b540 |
4530 | #define regMC_VM_L2_PERFCOUNTER_LO 0x0d50 |
4531 | #define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 |
4532 | #define regMC_VM_L2_PERFCOUNTER_HI 0x0d51 |
4533 | #define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 |
4534 | |
4535 | |
4536 | // addressBlock: mmhub_utcl2_vml2vcdec |
4537 | // base address: 0x6af00 |
4538 | #define regVM_CONTEXT0_CNTL 0x0bc0 |
4539 | #define regVM_CONTEXT0_CNTL_BASE_IDX 0 |
4540 | #define regVM_CONTEXT1_CNTL 0x0bc1 |
4541 | #define regVM_CONTEXT1_CNTL_BASE_IDX 0 |
4542 | #define regVM_CONTEXT2_CNTL 0x0bc2 |
4543 | #define regVM_CONTEXT2_CNTL_BASE_IDX 0 |
4544 | #define regVM_CONTEXT3_CNTL 0x0bc3 |
4545 | #define regVM_CONTEXT3_CNTL_BASE_IDX 0 |
4546 | #define regVM_CONTEXT4_CNTL 0x0bc4 |
4547 | #define regVM_CONTEXT4_CNTL_BASE_IDX 0 |
4548 | #define regVM_CONTEXT5_CNTL 0x0bc5 |
4549 | #define regVM_CONTEXT5_CNTL_BASE_IDX 0 |
4550 | #define regVM_CONTEXT6_CNTL 0x0bc6 |
4551 | #define regVM_CONTEXT6_CNTL_BASE_IDX 0 |
4552 | #define regVM_CONTEXT7_CNTL 0x0bc7 |
4553 | #define regVM_CONTEXT7_CNTL_BASE_IDX 0 |
4554 | #define regVM_CONTEXT8_CNTL 0x0bc8 |
4555 | #define regVM_CONTEXT8_CNTL_BASE_IDX 0 |
4556 | #define regVM_CONTEXT9_CNTL 0x0bc9 |
4557 | #define regVM_CONTEXT9_CNTL_BASE_IDX 0 |
4558 | #define regVM_CONTEXT10_CNTL 0x0bca |
4559 | #define regVM_CONTEXT10_CNTL_BASE_IDX 0 |
4560 | #define regVM_CONTEXT11_CNTL 0x0bcb |
4561 | #define regVM_CONTEXT11_CNTL_BASE_IDX 0 |
4562 | #define regVM_CONTEXT12_CNTL 0x0bcc |
4563 | #define regVM_CONTEXT12_CNTL_BASE_IDX 0 |
4564 | #define regVM_CONTEXT13_CNTL 0x0bcd |
4565 | #define regVM_CONTEXT13_CNTL_BASE_IDX 0 |
4566 | #define regVM_CONTEXT14_CNTL 0x0bce |
4567 | #define regVM_CONTEXT14_CNTL_BASE_IDX 0 |
4568 | #define regVM_CONTEXT15_CNTL 0x0bcf |
4569 | #define regVM_CONTEXT15_CNTL_BASE_IDX 0 |
4570 | #define regVM_CONTEXTS_DISABLE 0x0bd0 |
4571 | #define regVM_CONTEXTS_DISABLE_BASE_IDX 0 |
4572 | #define regVM_INVALIDATE_ENG0_SEM 0x0bd1 |
4573 | #define regVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 |
4574 | #define regVM_INVALIDATE_ENG1_SEM 0x0bd2 |
4575 | #define regVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 |
4576 | #define regVM_INVALIDATE_ENG2_SEM 0x0bd3 |
4577 | #define regVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 |
4578 | #define regVM_INVALIDATE_ENG3_SEM 0x0bd4 |
4579 | #define regVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 |
4580 | #define regVM_INVALIDATE_ENG4_SEM 0x0bd5 |
4581 | #define regVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 |
4582 | #define regVM_INVALIDATE_ENG5_SEM 0x0bd6 |
4583 | #define regVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 |
4584 | #define regVM_INVALIDATE_ENG6_SEM 0x0bd7 |
4585 | #define regVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 |
4586 | #define regVM_INVALIDATE_ENG7_SEM 0x0bd8 |
4587 | #define regVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 |
4588 | #define regVM_INVALIDATE_ENG8_SEM 0x0bd9 |
4589 | #define regVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 |
4590 | #define regVM_INVALIDATE_ENG9_SEM 0x0bda |
4591 | #define regVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 |
4592 | #define regVM_INVALIDATE_ENG10_SEM 0x0bdb |
4593 | #define regVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 |
4594 | #define regVM_INVALIDATE_ENG11_SEM 0x0bdc |
4595 | #define regVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 |
4596 | #define regVM_INVALIDATE_ENG12_SEM 0x0bdd |
4597 | #define regVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 |
4598 | #define regVM_INVALIDATE_ENG13_SEM 0x0bde |
4599 | #define regVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 |
4600 | #define regVM_INVALIDATE_ENG14_SEM 0x0bdf |
4601 | #define regVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 |
4602 | #define regVM_INVALIDATE_ENG15_SEM 0x0be0 |
4603 | #define regVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 |
4604 | #define regVM_INVALIDATE_ENG16_SEM 0x0be1 |
4605 | #define regVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 |
4606 | #define regVM_INVALIDATE_ENG17_SEM 0x0be2 |
4607 | #define regVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 |
4608 | #define regVM_INVALIDATE_ENG0_REQ 0x0be3 |
4609 | #define regVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 |
4610 | #define regVM_INVALIDATE_ENG1_REQ 0x0be4 |
4611 | #define regVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 |
4612 | #define regVM_INVALIDATE_ENG2_REQ 0x0be5 |
4613 | #define regVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 |
4614 | #define regVM_INVALIDATE_ENG3_REQ 0x0be6 |
4615 | #define regVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 |
4616 | #define regVM_INVALIDATE_ENG4_REQ 0x0be7 |
4617 | #define regVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 |
4618 | #define regVM_INVALIDATE_ENG5_REQ 0x0be8 |
4619 | #define regVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 |
4620 | #define regVM_INVALIDATE_ENG6_REQ 0x0be9 |
4621 | #define regVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 |
4622 | #define regVM_INVALIDATE_ENG7_REQ 0x0bea |
4623 | #define regVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 |
4624 | #define regVM_INVALIDATE_ENG8_REQ 0x0beb |
4625 | #define regVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 |
4626 | #define regVM_INVALIDATE_ENG9_REQ 0x0bec |
4627 | #define regVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 |
4628 | #define regVM_INVALIDATE_ENG10_REQ 0x0bed |
4629 | #define regVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 |
4630 | #define regVM_INVALIDATE_ENG11_REQ 0x0bee |
4631 | #define regVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 |
4632 | #define regVM_INVALIDATE_ENG12_REQ 0x0bef |
4633 | #define regVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 |
4634 | #define regVM_INVALIDATE_ENG13_REQ 0x0bf0 |
4635 | #define regVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 |
4636 | #define regVM_INVALIDATE_ENG14_REQ 0x0bf1 |
4637 | #define regVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 |
4638 | #define regVM_INVALIDATE_ENG15_REQ 0x0bf2 |
4639 | #define regVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 |
4640 | #define regVM_INVALIDATE_ENG16_REQ 0x0bf3 |
4641 | #define regVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 |
4642 | #define regVM_INVALIDATE_ENG17_REQ 0x0bf4 |
4643 | #define regVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 |
4644 | #define regVM_INVALIDATE_ENG0_ACK 0x0bf5 |
4645 | #define regVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 |
4646 | #define regVM_INVALIDATE_ENG1_ACK 0x0bf6 |
4647 | #define regVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 |
4648 | #define regVM_INVALIDATE_ENG2_ACK 0x0bf7 |
4649 | #define regVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 |
4650 | #define regVM_INVALIDATE_ENG3_ACK 0x0bf8 |
4651 | #define regVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 |
4652 | #define regVM_INVALIDATE_ENG4_ACK 0x0bf9 |
4653 | #define regVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 |
4654 | #define regVM_INVALIDATE_ENG5_ACK 0x0bfa |
4655 | #define regVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 |
4656 | #define regVM_INVALIDATE_ENG6_ACK 0x0bfb |
4657 | #define regVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 |
4658 | #define regVM_INVALIDATE_ENG7_ACK 0x0bfc |
4659 | #define regVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 |
4660 | #define regVM_INVALIDATE_ENG8_ACK 0x0bfd |
4661 | #define regVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 |
4662 | #define regVM_INVALIDATE_ENG9_ACK 0x0bfe |
4663 | #define regVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 |
4664 | #define regVM_INVALIDATE_ENG10_ACK 0x0bff |
4665 | #define regVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 |
4666 | #define regVM_INVALIDATE_ENG11_ACK 0x0c00 |
4667 | #define regVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 |
4668 | #define regVM_INVALIDATE_ENG12_ACK 0x0c01 |
4669 | #define regVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 |
4670 | #define regVM_INVALIDATE_ENG13_ACK 0x0c02 |
4671 | #define regVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 |
4672 | #define regVM_INVALIDATE_ENG14_ACK 0x0c03 |
4673 | #define regVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 |
4674 | #define regVM_INVALIDATE_ENG15_ACK 0x0c04 |
4675 | #define regVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 |
4676 | #define regVM_INVALIDATE_ENG16_ACK 0x0c05 |
4677 | #define regVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 |
4678 | #define regVM_INVALIDATE_ENG17_ACK 0x0c06 |
4679 | #define regVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 |
4680 | #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0c07 |
4681 | #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 |
4682 | #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0c08 |
4683 | #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 |
4684 | #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0c09 |
4685 | #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 |
4686 | #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0c0a |
4687 | #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 |
4688 | #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0c0b |
4689 | #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 |
4690 | #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0c0c |
4691 | #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 |
4692 | #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0c0d |
4693 | #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 |
4694 | #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0c0e |
4695 | #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 |
4696 | #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0c0f |
4697 | #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 |
4698 | #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0c10 |
4699 | #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 |
4700 | #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0c11 |
4701 | #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 |
4702 | #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0c12 |
4703 | #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 |
4704 | #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0c13 |
4705 | #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 |
4706 | #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0c14 |
4707 | #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 |
4708 | #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0c15 |
4709 | #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 |
4710 | #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0c16 |
4711 | #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 |
4712 | #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0c17 |
4713 | #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 |
4714 | #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0c18 |
4715 | #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 |
4716 | #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0c19 |
4717 | #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 |
4718 | #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0c1a |
4719 | #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 |
4720 | #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0c1b |
4721 | #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 |
4722 | #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0c1c |
4723 | #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 |
4724 | #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0c1d |
4725 | #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 |
4726 | #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0c1e |
4727 | #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 |
4728 | #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0c1f |
4729 | #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 |
4730 | #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0c20 |
4731 | #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 |
4732 | #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0c21 |
4733 | #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 |
4734 | #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0c22 |
4735 | #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 |
4736 | #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0c23 |
4737 | #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 |
4738 | #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0c24 |
4739 | #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 |
4740 | #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0c25 |
4741 | #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 |
4742 | #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0c26 |
4743 | #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 |
4744 | #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0c27 |
4745 | #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 |
4746 | #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0c28 |
4747 | #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 |
4748 | #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0c29 |
4749 | #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 |
4750 | #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0c2a |
4751 | #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 |
4752 | #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0c2b |
4753 | #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4754 | #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0c2c |
4755 | #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4756 | #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0c2d |
4757 | #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4758 | #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0c2e |
4759 | #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4760 | #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0c2f |
4761 | #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4762 | #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0c30 |
4763 | #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4764 | #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0c31 |
4765 | #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4766 | #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0c32 |
4767 | #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4768 | #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0c33 |
4769 | #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4770 | #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0c34 |
4771 | #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4772 | #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0c35 |
4773 | #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4774 | #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0c36 |
4775 | #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4776 | #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0c37 |
4777 | #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4778 | #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0c38 |
4779 | #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4780 | #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0c39 |
4781 | #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4782 | #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0c3a |
4783 | #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4784 | #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0c3b |
4785 | #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4786 | #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0c3c |
4787 | #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4788 | #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0c3d |
4789 | #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4790 | #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0c3e |
4791 | #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4792 | #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0c3f |
4793 | #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4794 | #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0c40 |
4795 | #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4796 | #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0c41 |
4797 | #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4798 | #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0c42 |
4799 | #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4800 | #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0c43 |
4801 | #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4802 | #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0c44 |
4803 | #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4804 | #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0c45 |
4805 | #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4806 | #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0c46 |
4807 | #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4808 | #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0c47 |
4809 | #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4810 | #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0c48 |
4811 | #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4812 | #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0c49 |
4813 | #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 |
4814 | #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0c4a |
4815 | #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 |
4816 | #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0c4b |
4817 | #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4818 | #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0c4c |
4819 | #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4820 | #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0c4d |
4821 | #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4822 | #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0c4e |
4823 | #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4824 | #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0c4f |
4825 | #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4826 | #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0c50 |
4827 | #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4828 | #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0c51 |
4829 | #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4830 | #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0c52 |
4831 | #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4832 | #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0c53 |
4833 | #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4834 | #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0c54 |
4835 | #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4836 | #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0c55 |
4837 | #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4838 | #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0c56 |
4839 | #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4840 | #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0c57 |
4841 | #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4842 | #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0c58 |
4843 | #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4844 | #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0c59 |
4845 | #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4846 | #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0c5a |
4847 | #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4848 | #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0c5b |
4849 | #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4850 | #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0c5c |
4851 | #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4852 | #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0c5d |
4853 | #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4854 | #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0c5e |
4855 | #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4856 | #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0c5f |
4857 | #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4858 | #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0c60 |
4859 | #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4860 | #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0c61 |
4861 | #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4862 | #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0c62 |
4863 | #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4864 | #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0c63 |
4865 | #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4866 | #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0c64 |
4867 | #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4868 | #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0c65 |
4869 | #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4870 | #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0c66 |
4871 | #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4872 | #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0c67 |
4873 | #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4874 | #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0c68 |
4875 | #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4876 | #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0c69 |
4877 | #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 |
4878 | #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0c6a |
4879 | #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 |
4880 | #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0c6b |
4881 | #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4882 | #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0c6c |
4883 | #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4884 | #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0c6d |
4885 | #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4886 | #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0c6e |
4887 | #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4888 | #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0c6f |
4889 | #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4890 | #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0c70 |
4891 | #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4892 | #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0c71 |
4893 | #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4894 | #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0c72 |
4895 | #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4896 | #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0c73 |
4897 | #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4898 | #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0c74 |
4899 | #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4900 | #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0c75 |
4901 | #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4902 | #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0c76 |
4903 | #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4904 | #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0c77 |
4905 | #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4906 | #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0c78 |
4907 | #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4908 | #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0c79 |
4909 | #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4910 | #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0c7a |
4911 | #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4912 | #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0c7b |
4913 | #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4914 | #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0c7c |
4915 | #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4916 | #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0c7d |
4917 | #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4918 | #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0c7e |
4919 | #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4920 | #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0c7f |
4921 | #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4922 | #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0c80 |
4923 | #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4924 | #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0c81 |
4925 | #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4926 | #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0c82 |
4927 | #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4928 | #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0c83 |
4929 | #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4930 | #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0c84 |
4931 | #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4932 | #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0c85 |
4933 | #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4934 | #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0c86 |
4935 | #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4936 | #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0c87 |
4937 | #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4938 | #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0c88 |
4939 | #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4940 | #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0c89 |
4941 | #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 |
4942 | #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0c8a |
4943 | #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 |
4944 | |
4945 | |
4946 | // addressBlock: mmhub_utcl2_vmsharedhvdec |
4947 | // base address: 0x6b380 |
4948 | #define regMC_VM_FB_SIZE_OFFSET_VF0 0x0ce0 |
4949 | #define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 |
4950 | #define regMC_VM_FB_SIZE_OFFSET_VF1 0x0ce1 |
4951 | #define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 |
4952 | #define regMC_VM_FB_SIZE_OFFSET_VF2 0x0ce2 |
4953 | #define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 |
4954 | #define regMC_VM_FB_SIZE_OFFSET_VF3 0x0ce3 |
4955 | #define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 |
4956 | #define regMC_VM_FB_SIZE_OFFSET_VF4 0x0ce4 |
4957 | #define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 |
4958 | #define regMC_VM_FB_SIZE_OFFSET_VF5 0x0ce5 |
4959 | #define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 |
4960 | #define regMC_VM_FB_SIZE_OFFSET_VF6 0x0ce6 |
4961 | #define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 |
4962 | #define regMC_VM_FB_SIZE_OFFSET_VF7 0x0ce7 |
4963 | #define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 |
4964 | #define regMC_VM_FB_SIZE_OFFSET_VF8 0x0ce8 |
4965 | #define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 |
4966 | #define regMC_VM_FB_SIZE_OFFSET_VF9 0x0ce9 |
4967 | #define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 |
4968 | #define regMC_VM_FB_SIZE_OFFSET_VF10 0x0cea |
4969 | #define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 |
4970 | #define regMC_VM_FB_SIZE_OFFSET_VF11 0x0ceb |
4971 | #define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 |
4972 | #define regMC_VM_FB_SIZE_OFFSET_VF12 0x0cec |
4973 | #define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 |
4974 | #define regMC_VM_FB_SIZE_OFFSET_VF13 0x0ced |
4975 | #define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 |
4976 | #define regMC_VM_FB_SIZE_OFFSET_VF14 0x0cee |
4977 | #define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 |
4978 | #define regMC_VM_FB_SIZE_OFFSET_VF15 0x0cef |
4979 | #define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 |
4980 | #define regMC_VM_MARC_BASE_LO_0 0x0cf1 |
4981 | #define regMC_VM_MARC_BASE_LO_0_BASE_IDX 0 |
4982 | #define regMC_VM_MARC_BASE_LO_1 0x0cf2 |
4983 | #define regMC_VM_MARC_BASE_LO_1_BASE_IDX 0 |
4984 | #define regMC_VM_MARC_BASE_LO_2 0x0cf3 |
4985 | #define regMC_VM_MARC_BASE_LO_2_BASE_IDX 0 |
4986 | #define regMC_VM_MARC_BASE_LO_3 0x0cf4 |
4987 | #define regMC_VM_MARC_BASE_LO_3_BASE_IDX 0 |
4988 | #define regMC_VM_MARC_BASE_HI_0 0x0cf5 |
4989 | #define regMC_VM_MARC_BASE_HI_0_BASE_IDX 0 |
4990 | #define regMC_VM_MARC_BASE_HI_1 0x0cf6 |
4991 | #define regMC_VM_MARC_BASE_HI_1_BASE_IDX 0 |
4992 | #define regMC_VM_MARC_BASE_HI_2 0x0cf7 |
4993 | #define regMC_VM_MARC_BASE_HI_2_BASE_IDX 0 |
4994 | #define regMC_VM_MARC_BASE_HI_3 0x0cf8 |
4995 | #define regMC_VM_MARC_BASE_HI_3_BASE_IDX 0 |
4996 | #define regMC_VM_MARC_RELOC_LO_0 0x0cf9 |
4997 | #define regMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 |
4998 | #define regMC_VM_MARC_RELOC_LO_1 0x0cfa |
4999 | #define regMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 |
5000 | #define regMC_VM_MARC_RELOC_LO_2 0x0cfb |
5001 | #define regMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 |
5002 | #define regMC_VM_MARC_RELOC_LO_3 0x0cfc |
5003 | #define regMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 |
5004 | #define regMC_VM_MARC_RELOC_HI_0 0x0cfd |
5005 | #define regMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 |
5006 | #define regMC_VM_MARC_RELOC_HI_1 0x0cfe |
5007 | #define regMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 |
5008 | #define regMC_VM_MARC_RELOC_HI_2 0x0cff |
5009 | #define regMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 |
5010 | #define regMC_VM_MARC_RELOC_HI_3 0x0d00 |
5011 | #define regMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 |
5012 | #define regMC_VM_MARC_LEN_LO_0 0x0d01 |
5013 | #define regMC_VM_MARC_LEN_LO_0_BASE_IDX 0 |
5014 | #define regMC_VM_MARC_LEN_LO_1 0x0d02 |
5015 | #define regMC_VM_MARC_LEN_LO_1_BASE_IDX 0 |
5016 | #define regMC_VM_MARC_LEN_LO_2 0x0d03 |
5017 | #define regMC_VM_MARC_LEN_LO_2_BASE_IDX 0 |
5018 | #define regMC_VM_MARC_LEN_LO_3 0x0d04 |
5019 | #define regMC_VM_MARC_LEN_LO_3_BASE_IDX 0 |
5020 | #define regMC_VM_MARC_LEN_HI_0 0x0d05 |
5021 | #define regMC_VM_MARC_LEN_HI_0_BASE_IDX 0 |
5022 | #define regMC_VM_MARC_LEN_HI_1 0x0d06 |
5023 | #define regMC_VM_MARC_LEN_HI_1_BASE_IDX 0 |
5024 | #define regMC_VM_MARC_LEN_HI_2 0x0d07 |
5025 | #define regMC_VM_MARC_LEN_HI_2_BASE_IDX 0 |
5026 | #define regMC_VM_MARC_LEN_HI_3 0x0d08 |
5027 | #define regMC_VM_MARC_LEN_HI_3_BASE_IDX 0 |
5028 | #define regVM_PCIE_ATS_CNTL 0x0d0b |
5029 | #define regVM_PCIE_ATS_CNTL_BASE_IDX 0 |
5030 | #define regVM_PCIE_ATS_CNTL_VF_0 0x0d0c |
5031 | #define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 |
5032 | #define regVM_PCIE_ATS_CNTL_VF_1 0x0d0d |
5033 | #define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 |
5034 | #define regVM_PCIE_ATS_CNTL_VF_2 0x0d0e |
5035 | #define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 |
5036 | #define regVM_PCIE_ATS_CNTL_VF_3 0x0d0f |
5037 | #define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 |
5038 | #define regVM_PCIE_ATS_CNTL_VF_4 0x0d10 |
5039 | #define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 |
5040 | #define regVM_PCIE_ATS_CNTL_VF_5 0x0d11 |
5041 | #define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 |
5042 | #define regVM_PCIE_ATS_CNTL_VF_6 0x0d12 |
5043 | #define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 |
5044 | #define regVM_PCIE_ATS_CNTL_VF_7 0x0d13 |
5045 | #define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 |
5046 | #define regVM_PCIE_ATS_CNTL_VF_8 0x0d14 |
5047 | #define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 |
5048 | #define regVM_PCIE_ATS_CNTL_VF_9 0x0d15 |
5049 | #define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 |
5050 | #define regVM_PCIE_ATS_CNTL_VF_10 0x0d16 |
5051 | #define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 |
5052 | #define regVM_PCIE_ATS_CNTL_VF_11 0x0d17 |
5053 | #define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 |
5054 | #define regVM_PCIE_ATS_CNTL_VF_12 0x0d18 |
5055 | #define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 |
5056 | #define regVM_PCIE_ATS_CNTL_VF_13 0x0d19 |
5057 | #define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 |
5058 | #define regVM_PCIE_ATS_CNTL_VF_14 0x0d1a |
5059 | #define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 |
5060 | #define regVM_PCIE_ATS_CNTL_VF_15 0x0d1b |
5061 | #define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 |
5062 | #define regMC_SHARED_ACTIVE_FCN_ID 0x0d1c |
5063 | #define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 |
5064 | #define regMC_VM_XGMI_GPUIOV_ENABLE 0x0d1d |
5065 | #define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 0 |
5066 | |
5067 | |
5068 | // addressBlock: mmhub_utcl2_vmsharedpfdec |
5069 | // base address: 0x6b290 |
5070 | #define regMC_VM_FB_OFFSET 0x0cab |
5071 | #define regMC_VM_FB_OFFSET_BASE_IDX 0 |
5072 | #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0cac |
5073 | #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 |
5074 | #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0cad |
5075 | #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 |
5076 | #define regMC_VM_STEERING 0x0cae |
5077 | #define regMC_VM_STEERING_BASE_IDX 0 |
5078 | #define regMC_SHARED_VIRT_RESET_REQ 0x0caf |
5079 | #define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 |
5080 | #define regMC_MEM_POWER_LS 0x0cb0 |
5081 | #define regMC_MEM_POWER_LS_BASE_IDX 0 |
5082 | #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0cb1 |
5083 | #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 |
5084 | #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0cb2 |
5085 | #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 |
5086 | #define regMC_VM_APT_CNTL 0x0cb3 |
5087 | #define regMC_VM_APT_CNTL_BASE_IDX 0 |
5088 | #define regMC_VM_LOCAL_HBM_ADDRESS_START 0x0cb4 |
5089 | #define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 |
5090 | #define regMC_VM_LOCAL_HBM_ADDRESS_END 0x0cb5 |
5091 | #define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 |
5092 | #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0cb6 |
5093 | #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 |
5094 | #define regUTCL2_CGTT_CLK_CTRL 0x0cb7 |
5095 | #define regUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 |
5096 | #define regMC_VM_XGMI_LFB_CNTL 0x0cb8 |
5097 | #define regMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 |
5098 | #define regMC_VM_XGMI_LFB_SIZE 0x0cb9 |
5099 | #define regMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 |
5100 | #define regMC_VM_CACHEABLE_DRAM_CNTL 0x0cba |
5101 | #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 0 |
5102 | #define regMC_VM_HOST_MAPPING 0x0cbb |
5103 | #define regMC_VM_HOST_MAPPING_BASE_IDX 0 |
5104 | |
5105 | |
5106 | // addressBlock: mmhub_utcl2_vmsharedvcdec |
5107 | // base address: 0x6b300 |
5108 | #define regMC_VM_FB_LOCATION_BASE 0x0cc0 |
5109 | #define regMC_VM_FB_LOCATION_BASE_BASE_IDX 0 |
5110 | #define regMC_VM_FB_LOCATION_TOP 0x0cc1 |
5111 | #define regMC_VM_FB_LOCATION_TOP_BASE_IDX 0 |
5112 | #define regMC_VM_AGP_TOP 0x0cc2 |
5113 | #define regMC_VM_AGP_TOP_BASE_IDX 0 |
5114 | #define regMC_VM_AGP_BOT 0x0cc3 |
5115 | #define regMC_VM_AGP_BOT_BASE_IDX 0 |
5116 | #define regMC_VM_AGP_BASE 0x0cc4 |
5117 | #define regMC_VM_AGP_BASE_BASE_IDX 0 |
5118 | #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0cc5 |
5119 | #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 |
5120 | #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0cc6 |
5121 | #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 |
5122 | #define regMC_VM_MX_L1_TLB_CNTL 0x0cc7 |
5123 | #define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 |
5124 | |
5125 | #endif |
5126 | |